Copper interconnection electroplating process
By employing a segmented copper interconnect electroplating process and real-time additive monitoring, combined with laser annealing, the problems of insufficient plating smoothness and adhesion were solved, achieving high adhesion, low resistivity, and consistent electroplating results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-18
- Publication Date
- 2026-04-03
AI Technical Summary
Existing copper interconnect electroplating processes suffer from insufficient plating smoothness and reduced adhesion, making it difficult to meet the technical requirements of nodes below 10nm.
The electroplating process employs a segmented approach, including nucleation, accelerated filling, and leveling stages. Combined with real-time online monitoring of additive concentration and in-situ laser-assisted annealing, a dense and uniform copper nucleus is formed, improving adhesion and smoothness.
It achieves high adhesion, low resistivity and consistency of copper interconnects, reduces the burden of subsequent CMP, and improves electromigration lifetime and surface smoothness.
Abstract
Description
Technical Field
[0001] This invention relates to the field of electroplating technology, and in particular to a copper interconnect electroplating process. Background Technology
[0002] Metal interconnect technology is a core technology in integrated circuit manufacturing that interconnects independent components into complete circuits. It achieves electrical connections between devices by depositing a thin metal film on the chip surface and using photolithography to form wiring structures. Its core requirements include low resistivity, good contact performance, and adhesion to insulating layers. Early interconnect materials primarily used aluminum and its alloys due to their mature technology and low cost, but they suffered from electromigration effects and insufficient high-temperature stability. With increasing integration density, performance was improved by incorporating copper or silicon, or by introducing refractory metal silicide-barrier layer composite structures. After the 0.13-micron technology node, copper, with its lower resistivity, gradually replaced aluminum. Interconnects are manufactured using a dual damascene process (dielectric layer etching → copper filling → chemical mechanical polishing), requiring the deposition of a Ta / TaN barrier layer to prevent copper diffusion. Metal interconnect structures have evolved from single-layer to multi-layer stacking, combining physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes to achieve alternating construction of metal and insulating layers.
[0003] Before the 14nm node, DC electroplating combined with organic additives (accelerators, inhibitors, and leveling agents) could meet the requirements. However, as the node moves below 10nm, three major physical limits become apparent: quantum size effect: when the interconnect width is <20nm, electron surface scattering causes a surge in resistivity; high aspect ratio structure challenge: when the via aspect ratio is >10:1, diffusion mass transfer is limited, leading to "bow-knot voids"; interface failure: the discontinuity of the thin seed layer (<10nm) intensifies, the adhesion of the electroplated layer decreases, and thermomechanical mismatch induces delamination. Based on this, corresponding improvements should be made to address the problems of insufficient plating smoothness and decreased adhesion in existing copper interconnect electroplating processes. Summary of the Invention
[0004] Therefore, it is necessary to provide a copper interconnect electroplating process to address the technical problems of insufficient plating smoothness and adhesion of the coating obtained by existing copper interconnect electroplating processes.
[0005] A copper interconnect electroplating process includes the following steps:
[0006] S1. Substrate preparation: Silicon wafer cleaning, using SC1 solution, 0.5% HF solution and deionized water for sequential rinsing; Diffusion barrier layer deposition (TaN / Ta), using ALD to deposit a TaN / Ta double barrier layer; followed by ionization PVD to deposit a copper neutron layer;
[0007] S2. Pre-plating treatment: DIW rinse removes particulate contaminants from the silicon wafer surface; then, a mixture of 5% H2SO4 and 0.1% HCl is used to activate the silicon wafer surface, remove the oxide layer, and enhance wettability.
[0008] S3, Low-temperature high-density nucleation layer pre-deposition: In the pre-prepared plating solution, perform low-temperature, low-current-density DC electroplating for 30-60 seconds;
[0009] S4. Perform gradient-modulated pulse electroplating main deposition treatment on the silicon wafer, in the following order: ① Nucleation stage, with the forward pulse set to 5mA / cm 2 Current density and 5ms pulse width, reverse pulse set to -20mA / cm 2 ① Current density and 20ms pulse width, duty cycle set to 20%, total processing time 12s; ② Accelerated filling stage, forward current changed to gradient setting: initial current density 8mA / cm² 2 Then it linearly increased to 25 mA / cm 2 Slope: 0.14 mA / cm 2 / s, at this time the forward pulse width is set to 8ms, the reverse pulse width is set to 15ms, the duty cycle is set to 35%-62%, and the total processing time is 100s; ③ In the smoothing stage, the forward pulse is set to 10mA / cm 2 Current density and 20ms pulse width, reverse pulse set to -5mA / cm 2 The current density and 2ms pulse width (inserted once every 5 positive pulses), the duty cycle is set to 80%, and the total processing time is set to 18s;
[0010] S5. Post-processing: DIW spraying of silicon wafers; nitrogen spin drying;
[0011] S6. In-situ laser-assisted annealing: Under the protection of an inert atmosphere, the silicon wafer is subjected to infrared laser scanning treatment, which causes the copper film surface to melt and solidify rapidly. While promoting grain refinement and densification, stress is released and the surface is leveled.
[0012] S7. Subsequent processes: CMP; cleaning; testing.
[0013] In one embodiment, step S4 above includes the following steps:
[0014] S41. The silicon wafer is immersed in the main electroplating solution containing preset additives;
[0015] S42. Initiate in-situ additive concentration monitoring and closed-loop control;
[0016] S43. Electroplating is performed according to the three-stage modulation waveform of "nucleation, accelerated filling (gradient current increase / decrease accelerator), and leveling (decrease current / add micro-reverse pulse)" until the target thickness is reached.
[0017] In one embodiment, the additives incorporated into the main electroplating solution in step S41 above include a preset amount of accelerator, a preset amount of inhibitor, and a preset amount of leveling agent.
[0018] In one embodiment, the in-situ additive concentration detection and closed-loop control in step S42 above employs impedance spectroscopy (EIS), cyclic voltammetry (CVS), and related sensors. The concentrations of accelerators, inhibitors, and leveling agents are monitored in real time online via a PLC system, and the additive replenishment pump is dynamically adjusted to maintain the optimal concentration window for the additives.
[0019] In one embodiment, in step S43 above, the accelerator concentration in the nucleation stage is controlled at 6 ppm, the inhibitor concentration at 300 ppm, and the leveling agent concentration at 2 ppm, and the CVS detection frequency is once every 30 seconds; in the accelerated filling stage, the accelerator concentration is reduced to 2 ppm at a replenishment rate gradient of -0.04 ppm / s, the inhibitor concentration is controlled at 300 ppm, and the leveling agent concentration is controlled at 3 ppm; in the leveling stage, the accelerator concentration is controlled at 1 ppm, the inhibitor concentration is controlled at 400 ppm, and the leveling agent concentration is controlled at 6 ppm, and feedback on additive activity is implemented during EIS monitoring.
[0020] In one embodiment, in step S1 above, during the silicon wafer cleaning process, the SC1 solution cleaning temperature is 65°C and the cleaning time is 10 min, the 0.5% HF solution cleaning temperature is room temperature and the cleaning time is 15 s, and the DIW rinsing temperature is set to room temperature and the rinsing time is 5 min.
[0021] In one embodiment, in step S1 above, the diffusion barrier layer of the silicon wafer is deposited with a thickness of 2nm TaN layer + 3nm Ta layer, and the uniformity is controlled to ±0.1nm (3σ).
[0022] In one embodiment, in step S1 above, the copper neutron layer deposition thickness of the silicon wafer is 10-15 nm, the resistivity is controlled to be less than 4.0 μΩ·cm, and the sidewall coverage of the silicon wafer is controlled to be greater than 95%.
[0023] In one embodiment, in step S2 above, the DIW rinsing flow rate is set to 2L / min and the rinsing time is 30s.
[0024] In one embodiment, in step S2 above, the temperature is set to 25°C and the processing time is 10 seconds during the olefin activation process.
[0025] In one embodiment, in step S3 above, Cu in the pre-plating solution 2+The concentrations are 10 g / L, H2SO4 50 g / L, Cl- 50 ppm, PEG-8000 500 ppm, and SPS 1 ppm.
[0026] In one embodiment, in step S3 above, the electroplating temperature is set to 20℃±0.5℃, and the current density is 1.5mA / cm². 2 The electroplating time was 45s, and the deposition thickness was 8nm±1nm.
[0027] In one embodiment, in step S5 above, the DIW spray pressure is 1.5 bar, the spray time is 20 s, the nitrogen spin-drying speed is 2000 rpm, the spin-drying time is 30 s, and the nitrogen purity is ≥99.999%.
[0028] In one embodiment, in step S6 above, the laser type for in-situ laser-assisted annealing is set to a fiber-coupled semiconductor laser (wavelength 980nm), and the energy density is set to 0.8-1.2 J / cm². 2 The pulse width was set to 0.5ms, the scan speed to 500mm / s, the overlap rate to 90%, the atmosphere control to use N2 atmosphere (O2≤0.1ppm), and the peak temperature of the silicon wafer surface was controlled to 400℃ and cooled to 100℃ within 1ms.
[0029] The aforementioned copper interconnect electroplating process is subdivided into a "nucleation stage," an "accelerated filling stage," and a "planarization stage." The nucleation stage forms dense, uniform, fine-grained copper nuclei on the barrier / seed layer, improving adhesion and suppressing abnormal growth. The accelerated filling structure utilizes a bottom-acceleration effect to achieve overfilling, avoiding voids while controlling surface roughness. The planarization stage dissolves protrusions, achieving a highly planar surface and reducing the burden on subsequent CMP (Continuous Metal Plating). Simultaneously, by real-time online monitoring and dynamic adjustment of the content of various additives in the electroplating solution according to the needs of different stages, the optimal concentration of additives is maintained at all times, thereby stabilizing additive consumption and controlling by-product accumulation, thus improving the stability of the electroplating process and ensuring consistency between different batches of products. Furthermore, by immediately subjecting the electroplated silicon wafer to a low-energy-density, short-pulse infrared laser (such as an 808nm or 980nm diode laser) under an inert atmosphere, the copper film surface undergoes micro-melting and rapid solidification, achieving the goals of reducing resistivity, improving electromigration lifetime, reducing internal stress, and further smoothing the surface. Detailed Implementation
[0030] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described in detail below. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
[0031] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0032] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0033] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0034] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.
[0035] This invention discloses a copper interconnect electroplating process, which includes the following steps:
[0036] S1. Substrate preparation: Silicon wafer cleaning, using SC1 solution, 0.5% HF solution and deionized water for sequential rinsing; Diffusion barrier layer deposition (TaN / Ta), using ALD to deposit a TaN / Ta double barrier layer; followed by ionization PVD to deposit a copper neutron layer;
[0037] S2. Pre-plating treatment: DIW rinse removes particulate contaminants from the silicon wafer surface; then, a mixture of 5% H2SO4 and 0.1% HCl is used to activate the silicon wafer surface, remove the oxide layer, and enhance wettability.
[0038] S3, Low-temperature high-density nucleation layer pre-deposition: In the pre-prepared plating solution, perform low-temperature, low-current-density DC electroplating for 30-60 seconds;
[0039] S4. Perform gradient-modulated pulse electroplating main deposition treatment on the silicon wafer, in the following order: ① Nucleation stage, with the forward pulse set to 5mA / cm 2 Current density and 5ms pulse width, reverse pulse set to -20mA / cm 2 ① Current density and 20ms pulse width, duty cycle set to 20%, total processing time 12s; ② Accelerated filling stage, forward current changed to gradient setting: initial current density 8mA / cm² 2 Then it linearly increased to 25 mA / cm 2 Slope: 0.14 mA / cm 2 / s, at this time the forward pulse width is set to 8ms, the reverse pulse width is set to 15ms, the duty cycle is set to 35%-62%, and the total processing time is 100s; ③ In the smoothing stage, the forward pulse is set to 10mA / cm 2 Current density and 20ms pulse width, reverse pulse set to -5mA / cm 2 The current density and 2ms pulse width (inserted once every 5 positive pulses), the duty cycle is set to 80%, and the total processing time is set to 18s;
[0040] S5. Post-processing: DIW spraying of silicon wafers; nitrogen spin drying;
[0041] S6. In-situ laser-assisted annealing: Under the protection of an inert atmosphere, the silicon wafer is subjected to infrared laser scanning treatment, which causes the copper film surface to melt and solidify rapidly. While promoting grain refinement and densification, stress is released and the surface is leveled.
[0042] S7. Subsequent processes: CMP; cleaning; testing.
[0043] Furthermore, step S4 above includes the following steps:
[0044] S41. The silicon wafer is immersed in the main electroplating solution containing preset additives;
[0045] S42. Initiate in-situ additive concentration monitoring and closed-loop control;
[0046] S43. Electroplating is performed according to the three-stage modulation waveform of "nucleation, accelerated filling (gradient current increase / decrease accelerator), and leveling (decrease current / add micro-reverse pulse)" until the target thickness is reached.
[0047] Specifically, the additives incorporated into the main electroplating solution in step S41 include a preset amount of accelerator, a preset amount of inhibitor, and a preset amount of leveling agent.
[0048] Specifically, in step S42 above, the in-situ additive concentration detection and closed-loop control employ impedance spectroscopy (EIS), cyclic voltammetry (CVS), and related sensors. The concentrations of accelerators, inhibitors, and leveling agents are monitored in real time via a PLC system, and the additive replenishment pump is dynamically adjusted to maintain the optimal concentration window for the additives.
[0049] Based on the above settings, more specifically, in step S43, the accelerator concentration in the nucleation stage is controlled at 6 ppm, the inhibitor concentration at 300 ppm, and the leveling agent concentration at 2 ppm, and the CVS detection frequency is once every 30 seconds; in the accelerated filling stage, the accelerator concentration is reduced to 2 ppm at a replenishment rate gradient of -0.04 ppm / s, the inhibitor concentration is controlled at 300 ppm, and the leveling agent concentration is controlled at 3 ppm; in the leveling stage, the accelerator concentration is controlled at 1 ppm, the inhibitor concentration is controlled at 400 ppm, and the leveling agent concentration is controlled at 6 ppm, and feedback on additive activity is implemented during EIS monitoring.
[0050] Furthermore, in step S1 above, during the silicon wafer cleaning process, the cleaning temperature of SC1 solution is 65°C and the cleaning time is 10 min, the cleaning temperature of 0.5% HF solution is room temperature and the cleaning time is 15 s, and the DIW rinsing temperature is set to room temperature and the rinsing time is 5 min.
[0051] Furthermore, in step S1 above, the diffusion barrier layer of the silicon wafer is deposited with a TaN layer of thickness of 2nm + a Ta layer of thickness of 3nm, and the uniformity is controlled to ±0.1nm (3σ).
[0052] Furthermore, in step S1 above, the copper neutron layer deposition thickness of the silicon wafer is 10-15 nm, the resistivity is controlled to be less than 4.0 μΩ·cm, and the sidewall coverage of the silicon wafer is controlled to be greater than 95%.
[0053] Furthermore, in step S2 above, the DIW rinsing flow rate is set to 2L / min, and the rinsing time is 30s.
[0054] Furthermore, in step S2 above, the temperature is set to 25°C and the processing time is 10 seconds during the olefin activation process.
[0055] Furthermore, in step S3 above, the Cu in the pre-plating solution 2+ The concentrations are 10 g / L, H2SO4 50 g / L, Cl- 50 ppm, PEG-8000 500 ppm, and SPS 1 ppm.
[0056] Furthermore, in step S3 above, the electroplating temperature is set to 20℃±0.5℃, and the current density is 1.5mA / cm². 2 The electroplating time was 45s, and the deposition thickness was 8nm±1nm.
[0057] Furthermore, in step S5 above, the DIW spray pressure is 1.5 bar, the spray time is 20 s; the nitrogen spin-drying speed is 2000 rpm, the spin-drying time is 30 s, and the nitrogen purity is ≥99.999%.
[0058] Furthermore, in step S6 above, the laser type for in-situ laser-assisted annealing is set to a fiber-coupled semiconductor laser (wavelength 980nm), and the energy density is set to 0.8-1.2 J / cm². 2 The pulse width was set to 0.5ms, the scan speed to 500mm / s, the overlap rate to 90%, the atmosphere control to use N2 atmosphere (O2≤0.1ppm), and the peak temperature of the silicon wafer surface was controlled to 400℃ and cooled to 100℃ within 1ms.
[0059] In summary, the copper interconnect electroplating process disclosed in this invention subdivides the electroplating process into a "nucleation stage," an "accelerated filling stage," and a "planarization stage." The nucleation stage forms dense, uniform, fine-grained copper nuclei on the barrier / seed layer, improving adhesion and suppressing abnormal growth. The accelerated filling structure utilizes a bottom-acceleration effect to achieve overfilling, avoiding voids while controlling surface roughness. The planarization stage dissolves protrusions, achieving a highly planar surface and reducing the burden on subsequent CMP. Simultaneously, by real-time online monitoring and dynamic adjustment of the content of various additives in the electroplating solution according to the needs of different stages, the optimal concentration of additives is maintained at all times, thereby stabilizing additive consumption and controlling by-product accumulation, thus improving the stability of the electroplating process and ensuring consistency between different batches of products. Furthermore, by immediately subjecting the electroplated silicon wafer to low-energy-density, short-pulse infrared laser (such as an 808nm or 980nm diode laser) scanning under an inert atmosphere, the copper film surface layer micro-melts and rapidly solidifies, achieving the goals of reducing resistivity, improving electromigration lifetime, reducing internal stress, and further smoothing the surface.
[0060] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0061] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.
Claims
1. A copper interconnect electroplating process, characterized in that, Includes the following steps: S1. Substrate preparation: Silicon wafer cleaning, using SC1 solution, 0.5% HF solution and deionized water for sequential rinsing; Diffusion barrier layer deposition (TaN / Ta), using ALD to deposit a TaN / Ta double barrier layer; followed by ionization PVD to deposit a copper neutron layer; S2. Pre-plating treatment: DIW rinse removes particulate contaminants from the silicon wafer surface; then, a mixture of 5% H2SO4 and 0.1% HCl is used to activate the silicon wafer surface, remove the oxide layer, and enhance wettability. S3, Low-temperature high-density nucleation layer pre-deposition: In the pre-prepared plating solution, perform low-temperature, low-current-density DC electroplating for 30-60 seconds; S4. Perform gradient-modulated pulse electroplating main deposition treatment on the silicon wafer, in the following order: ① Nucleation stage, with the forward pulse set to 5mA / cm 2 Current density and 5ms pulse width, reverse pulse set to -20mA / cm 2 ① Current density and 20ms pulse width, duty cycle set to 20%, total processing time 12s; ② Accelerated filling stage, forward current changed to gradient setting: initial current density 8mA / cm² 2 Then it linearly increased to 25 mA / cm 2 Slope: 0.14 mA / cm 2 / s, at this time the forward pulse width is set to 8ms, the reverse pulse width is set to 15ms, the duty cycle is set to 35%-62%, and the total processing time is 100s; ③ In the smoothing stage, the forward pulse is set to 10mA / cm 2 Current density and 20ms pulse width, reverse pulse set to -5mA / cm 2 The current density and 2ms pulse width (inserted once every 5 positive pulses), the duty cycle is set to 80%, and the total processing time is set to 18s; S5. Post-processing: DIW spraying of silicon wafers; nitrogen spin drying; S6. In-situ laser-assisted annealing: Under the protection of an inert atmosphere, the silicon wafer is subjected to infrared laser scanning treatment, which causes the copper film surface to melt and solidify rapidly. While promoting grain refinement and densification, stress is released and the surface is leveled. S7. Subsequent processes: CMP; cleaning; testing.
2. The copper interconnect electroplating process according to claim 1, characterized in that, Step S4 includes the following steps: S41. The silicon wafer is immersed in the main electroplating solution containing preset additives; S42. Initiate in-situ additive concentration monitoring and closed-loop control; S43. Electroplating is performed according to the three-stage modulation waveform of "nucleation, accelerated filling (gradient current increase / decrease accelerator), and leveling (decrease current / add micro-reverse pulse)" until the target thickness is reached.
3. The copper interconnect electroplating process according to claim 2, characterized in that, The additives incorporated into the main electroplating solution in step S41 include a preset amount of accelerator, a preset amount of inhibitor, and a preset amount of leveling agent.
4. The copper interconnect electroplating process according to claim 2, characterized in that, In step S42, the in-situ additive concentration detection and closed-loop control employ impedance spectroscopy (EIS), cyclic voltammetry (CVS), and related sensors. The concentrations of accelerators, inhibitors, and leveling agents are monitored in real time via a PLC system, and the additive replenishment pump is dynamically adjusted to maintain the optimal concentration window for the additives.
5. The copper interconnect electroplating process according to claim 2, characterized in that, In step S43, the accelerator concentration in the nucleation stage is controlled at 6 ppm, the inhibitor concentration at 300 ppm, and the leveling agent concentration at 2 ppm, and the CVS detection frequency is once every 30 seconds; in the accelerated filling stage, the accelerator concentration is reduced to 2 ppm at a replenishment rate gradient of -0.04 ppm / s, the inhibitor concentration is controlled at 300 ppm, and the leveling agent concentration is controlled at 3 ppm; in the leveling stage, the accelerator concentration is controlled at 1 ppm, the inhibitor concentration is controlled at 400 ppm, and the leveling agent concentration is controlled at 6 ppm, and feedback on additive activity is implemented during EIS monitoring.
6. The copper interconnect electroplating process according to claim 1, characterized in that, In step S1, during the silicon wafer cleaning process, the cleaning temperature of SC1 solution is 65℃ and the cleaning time is 10min, the cleaning temperature of 0.5% HF solution is room temperature and the cleaning time is 15s, and the DIW rinsing temperature is set to room temperature and the rinsing time is 5min.
7. The copper interconnect electroplating process according to claim 1, characterized in that, In step S1, the diffusion barrier layer of the silicon wafer is deposited with a thickness of 2nm TaN layer + 3nm Ta layer, and the uniformity is controlled to ±0.1nm (3σ).
8. The copper interconnect electroplating process according to claim 1, characterized in that, In step S1, the copper neutron layer deposition thickness of the silicon wafer is 10-15 nm, the resistivity is controlled to be less than 4.0 μΩ·cm, and the sidewall coverage of the silicon wafer is controlled to be greater than 95%.
9. The copper interconnect electroplating process according to claim 1, characterized in that, In step S5, the DIW spray pressure is 1.5 bar and the spray time is 20 s; the nitrogen spin dryer speed is 2000 rpm and the spin dryer time is 30 s; the nitrogen purity is ≥99.999%.
10. The copper interconnect electroplating process according to claim 1, characterized in that, In step S6, the laser type for in-situ laser-assisted annealing is set to a fiber-coupled semiconductor laser (wavelength 980nm), and the energy density is set to 0.8-1.2 J / cm². 2 The pulse width was set to 0.5ms, the scan speed to 500mm / s, the overlap rate to 90%, the atmosphere control to use N2 atmosphere (O2≤0.1ppm), and the peak temperature of the silicon wafer surface was controlled to 400℃ and cooled to 100℃ within 1ms.