Epitaxial defect inspection die and method
By designing an epitaxial defect inspection mold and method, and using a layout mold and wafer mold in conjunction with a microscope and a high-resolution non-contact imaging system, the precise location and screening of epitaxial defects were achieved. This solved the problems of high false negative rate and high cost in the existing technology, and improved the reliability screening effect of semiconductor laser chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-23
- Publication Date
- 2026-04-03
AI Technical Summary
Existing epitaxial defect detection methods suffer from high false negative rates and high costs, making it difficult to effectively screen out defective semiconductor laser chips in large-scale mass production.
An epitaxial defect inspection mold was designed, including a sheet-like layout mold and a wafer mold. By using a microscope in conjunction with a high-resolution non-contact imaging system, the epitaxial defects can be accurately located by aligning the mold with the epitaxial wafer, thereby reducing the false negative rate.
It reduced the overall missed detection rate of epitaxial defects by approximately 26.7%, effectively improving the reliability screening effect of semiconductor laser chips and reducing costs.
Smart Images
Figure CN121784015A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor chip wafer fabrication inspection technology, specifically relating to an epitaxial defect inspection mold and method. Background Technology
[0002] As semiconductor laser chips play an increasingly important role in people's lives, their reliability faces new challenges. Currently, semiconductor laser chips are generally screened for reliability through aging verification. However, in actual production, performing 100% aging on a massive number of chips is undoubtedly inefficient. Therefore, there is an urgent need to integrate multiple screening methods. Epitaxial defects, as one of the main causes of failure in high-power semiconductor laser chips, are easily covered by metal layers during actual production due to various processes such as gold evaporation and electrodeposition. This results in a very high rate of missed detection during the visual inspection of finished semiconductor laser chips. This significantly increases the risk of failure during use and poses a severe challenge to device reliability. If epitaxial defects can be accurately located and recorded before wafer fabrication and screened out during finished product visual inspection, the rate of missed detection can be effectively reduced, improving device reliability. Therefore, an inspection mold capable of accurately locating epitaxial defects is particularly important for the reliability screening of semiconductor laser chips.
[0003] Currently, existing epitaxial defect detection methods mainly rely on high-resolution non-contact imaging systems based on photoluminescence or cathodoluminescence principles. These systems analyze the distribution of epitaxial defects across the entire wafer to determine whether the wafer should proceed to the next processing step. However, for chips that have already undergone processing, their functionality is insufficient to screen out defective bars or individual transistors. Furthermore, these testing systems are extremely expensive. While indispensable in high-end R&D and product development, their use in mass production would undoubtedly represent a huge investment. Therefore, it is essential to design a low-cost inspection mold that can be used both in conjunction with a high-resolution non-contact imaging system and independently to screen out defective products and ensure device reliability. Summary of the Invention
[0004] To overcome the high rate of missed defects in semiconductor chip fabrication inspection, this invention proposes an epitaxial defect inspection mold and method.
[0005] The technical solution adopted by this invention to solve its technical problem is: An epitaxial defect inspection mold includes a sheet-like pattern mold and a fixing mold.
[0006] The fixed mold is used to fix the pattern mold and the epitaxial sheet. It is a rectangular plate with a through hole inside. The size of the through hole matches the outline size of the pattern mold. The pattern mold is located inside the through hole of the fixed mold.
[0007] The layout mold outline is consistent with the epitaxial wafer outline. During inspection, the epitaxial wafer is inspected on the layout mold. The layout mold is provided with layout vias, the positions of which correspond to the positions of individual transistors on the chip fabricated from the epitaxial wafer, and the shapes of the layout vias are consistent with the shapes of individual transistors on the chip fabricated from the epitaxial wafer.
[0008] The pattern mold is used to locate the positions of the bar strips and single tubes.
[0009] The materials of the aforementioned epitaxial defect inspection mold, layout mold, and fixing mold are all acrylic substrates.
[0010] The aforementioned epitaxial defect inspection mold uses a sheet-like wafer mold instead of a layout mold.
[0011] The wafer mold outline dimensions match the through-hole dimensions of the fixed mold, and the wafer mold is located inside the through-hole of the fixed mold.
[0012] The wafer mold outline is consistent with the epitaxial wafer outline. During inspection, the epitaxial wafer is located on the wafer mold.
[0013] The wafer mold is provided with wafer through-holes, and the positions of the wafer through-holes correspond to the positions of the effective areas of the epitaxial wafer.
[0014] Wafer molds are used to position the effective area of the wafer.
[0015] The aforementioned epitaxial defect inspection molds also include sheet-shaped wafer molds.
[0016] Wafer molds are used to position the effective area of a wafer.
[0017] The wafer mold outline is consistent with the layout mold outline.
[0018] The wafer mold is provided with wafer through-holes, and the positions of the wafer through-holes correspond to the positions of the effective areas of the epitaxial wafer.
[0019] Epitaxial wafers, wafer molds, and layout molds are placed sequentially from top to bottom and inserted into the through holes of the fixed mold.
[0020] The aforementioned epitaxial defect inspection mold uses an acrylic substrate as its wafer mold material.
[0021] An epitaxial defect inspection method includes the following steps: The epitaxial wafer, pattern die, and fixing die are placed on the microscope inspection table.
[0022] Microscopic recording of epitaxial section images.
[0023] By analyzing the epitaxial wafer image, the defect locations in the epitaxial wafer image are compared with the locations of the bars and single tubes of the chip fabricated from the epitaxial wafer to obtain the corresponding positions of each defect location in the bars and single tubes.
[0024] An epitaxial defect inspection method includes the following steps: The epitaxial wafer, wafer mold, and fixing mold are placed together on the microscope inspection table.
[0025] Microscopic recording of epitaxial section images.
[0026] Analyze epitaxial wafer images and record the location and number of defects in the effective region of the wafer fabricated from the epitaxial wafer.
[0027] An epitaxial defect inspection method includes the following steps: Epitaxial wafers, layout molds, wafer molds, and fixing molds are placed together on a microscope inspection table; Microscopic recording of epitaxial section images.
[0028] By analyzing the epitaxial wafer image, the defect locations in the epitaxial wafer image are compared with the locations of the bars and single tubes of the chip in the effective area of the wafer to obtain the corresponding positions of each defect location in the bars and single tubes of the chip in the effective area of the wafer.
[0029] The beneficial effects of this invention are: An epitaxial defect inspection mold comprises a wafer mold and a layout mold. The wafer mold is used to quickly locate the size and density of epitaxial defects in the effective area of the wafer to determine whether it is necessary to proceed to the next process. The layout mold can record the location of defects in bars or even individual tubes, which can be used to remove invisible defective products covered by metal layers after the wafer fabrication is completed.
[0030] An epitaxial defect inspection method is proposed for screening defective semiconductor chips and epitaxial wafers. Experimental results show that before using a mold, the missed detection rate for large epitaxial defects is approximately 20%, and the missed detection rate for small defects is approximately 40%. After adding the mold, the overall missed detection rate for P-side inspection is reduced by approximately 26.7%, which is of significant importance in screening chip reliability. Attached Figure Description
[0031] Figure 1 This is a schematic diagram of the epitaxial defect inspection mold according to Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the distribution of the effective region, ineffective region, and epitaxial defects in a wafer according to Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the position of the single tube corresponding to the position of the epitaxial defect in Embodiment 1 of the present invention.
[0032] The attached figures are labeled as follows: 1. Layout mold, 2. Wafer mold, 3. Fixing mold, 4. Epitaxial wafer; 5. Valid area, 6. Invalid area, 7. Defect. Detailed Implementation
[0033] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0034] Example 1 An epitaxial defect inspection method and mold, the basic structure of the device is as follows: Figure 1 As shown, there are no special requirements for the materials of each component; inexpensive acrylic substrates can be used.
[0035] Layout mold 1 is used to position the bar strip and single tube.
[0036] Wafer mold 2 is used to position the effective area of the wafer.
[0037] The fixed mold 3 serves to fix the mold in place.
[0038] Independent use: Place the epitaxial wafer 4, wafer mold 2, and layout mold 1 into the fixed mold 3 from top to bottom, and observe and record under a microscope.
[0039] When used in conjunction with a high-resolution non-contact imaging system, the layout mold 1 and wafer mold 2 can be imaged and imported into the testing system for comparison and recording with the result image; or the results from the analysis system can be exported, aligned with the layout mold 1 and wafer mold 2, and then compared and recorded.
[0040] The method and wafer mold 2 provided by this invention can quickly pinpoint the size and density of epitaxial defects in the effective area of the wafer, eliminate the influence of ineffective areas, and assist in determining whether a further process is necessary, such as... Figure 2 As shown. Valid area 5: The area where the chip is fabricated; Invalid area 6: The corner area excluding the chip fabrication area.
[0041] The method and mold 1 provided by this invention can record the location of defects in the strip, or even the location of a single tube, such as... Figure 3 As shown. Used to remove products with invisible defects covered by the metal layer after the wafer fabrication is completed.
[0042] According to experimental statistics, the overall missed detection rate of P-side inspection decreased by approximately 26.7% after using this method and mold.
[0043] This invention can be used in conjunction with a high-resolution non-contact imaging system or independently. It not only has extremely low manufacturing costs but also greatly reduces the reliability risks of the device, which is of great significance in screening chip reliability.
[0044] Example 2 An epitaxial defect inspection mold includes a sheet-like pattern mold 1 and a fixing mold 3; The fixed mold 3 is used to fix the pattern mold 1 and the epitaxial sheet 4. It is a rectangular plate with through holes inside. The size of the through holes matches the outline size of the pattern mold 1. The pattern mold 1 is located inside the through holes of the fixed mold 3.
[0045] The outline of the layout mold 1 is consistent with the outline of the epitaxial wafer 4. During inspection, the layout mold 1 is located on the epitaxial wafer 4. The layout mold 1 is provided with layout vias, the positions of which correspond to the positions of the single tubes of the chip fabricated by the epitaxial wafer 4, and the shapes of the layout vias are consistent with the shapes of the single tubes of the chip fabricated by the epitaxial wafer 4.
[0046] The pattern mold 1 is used to position the bar strip and the single tube.
[0047] Both the layout mold 1 and the fixed mold 3 are made of acrylic substrate.
[0048] An epitaxial defect inspection method includes the following steps: Epitaxial wafer 4, pattern die 1, and fixing die 3 are placed together on the microscope inspection table; Microscopic recording of image 4 of epitaxial section.
[0049] Analyze the image of epitaxial wafer 4, and compare the position of defect 7 in the image of epitaxial wafer 4 with the position of bar and single tube of the chip made from epitaxial wafer 4 to obtain the corresponding position of each defect 7 in bar and single tube.
[0050] Example 3 An epitaxial defect inspection mold includes a sheet-shaped wafer mold 2 and a fixing mold 3.
[0051] The outline dimensions of the wafer mold 2 match the through-hole dimensions of the fixed mold 3, and the wafer mold 2 is located inside the through-hole of the fixed mold 3.
[0052] The outline of the wafer mold 2 is consistent with the outline of the epitaxial wafer 4. During inspection, the wafer mold 2 is located on the epitaxial wafer 4 to be inspected.
[0053] The wafer mold 2 is provided with wafer through holes, and the positions of the wafer through holes correspond to the positions of the effective areas 5 of the wafer fabricated by the epitaxial wafer 4.
[0054] The wafer mold 2 is used to position the effective area 5 of the wafer.
[0055] The wafer mold 2 is made of an acrylic substrate.
[0056] An epitaxial defect inspection method includes the following steps: Epitaxial wafer 4, wafer mold 2, and fixing mold 3 are placed together on the microscope inspection table.
[0057] Microscopic recording of image 4 of epitaxial section.
[0058] Analyze the image of epitaxial wafer 4 and record the location and number of defects 7 in the effective region 5 of the wafer fabricated by epitaxial wafer 4 corresponding to defects 7 in the image of epitaxial wafer 4.
[0059] Example 4 An epitaxial defect inspection mold includes a sheet-shaped layout mold 1, a wafer mold 2, and a fixing mold 3.
[0060] Epitaxial wafer 4, wafer mold 2, and layout mold 1 are placed sequentially from top to bottom and inserted into the through hole of the fixing mold 3.
[0061] An epitaxial defect inspection method includes the following steps: Epitaxial wafer 4, layout mold 1, wafer mold 2, and fixing mold 3 are placed together on the microscope inspection table.
[0062] Microscopic recording of image 4 of epitaxial section.
[0063] Analyze the image of epitaxial wafer 4, and compare the position of defect 7 in the image of epitaxial wafer 4 with the position of the bar and single tube of the chip in the effective region 5 of the wafer to obtain the corresponding position of each defect 7 in the bar and single tube of the chip in the effective region 5 of the wafer.
Claims
1. A mold for inspecting epitaxial defects, characterized in that, Includes sheet-like pattern mold (1) and fixed mold (3); The fixed mold (3) is used to fix the pattern mold (1) and the epitaxial sheet (4). It is a rectangular plate with through holes inside. The size of the through holes matches the outline size of the pattern mold (1). The pattern mold (1) is located inside the through hole of the fixed mold (3). The outline of the layout mold (1) is consistent with the outline of the epitaxial wafer (4). During inspection, the layout mold (1) is placed on the epitaxial wafer (4). The layout mold (1) is provided with layout through holes. The position of the layout through holes corresponds to the position of the single tube of the chip made by the epitaxial wafer (4). The shape of the layout through holes is consistent with the shape of the single tube of the chip made by the epitaxial wafer (4). The pattern mold (1) is used to position the bar and single tube.
2. The epitaxial defect inspection mold according to claim 1, characterized in that, A sheet-like wafer mold (2) replaces the layout mold (1); The outline dimensions of the wafer mold (2) match the through-hole dimensions of the fixed mold (3), and the wafer mold (2) is located inside the through-hole of the fixed mold (3); The outline of the wafer mold (2) is consistent with the outline of the epitaxial wafer (4). During inspection, the wafer mold (2) is placed on the epitaxial wafer (4). The wafer mold (2) is provided with wafer through holes, and the position of the wafer through holes corresponds to the position of the effective area (5) of the wafer made by the epitaxial wafer (4); The wafer mold (2) is used to position the effective area of the wafer (5).
3. The epitaxial defect inspection mold according to claim 1, characterized in that, It also includes sheet-like wafer molds (2); The wafer mold (2) is used to position the effective area (5) of the wafer; The outline of the wafer mold (2) is consistent with the outline of the layout mold (1); The wafer mold (2) is provided with wafer through holes, and the position of the wafer through holes corresponds to the position of the effective area (5) of the wafer made by the epitaxial wafer (4); Epitaxial wafer (4), wafer mold (2), and layout mold (1) are placed sequentially from top to bottom and inserted into the through hole of the fixing mold (3).
4. The epitaxial defect inspection mold according to claim 1, characterized in that, The materials of the layout mold (1) and the fixed mold (3) are both acrylic substrates.
5. The epitaxial defect inspection mold according to claim 2, characterized in that, The wafer mold (2) is made of acrylic substrate.
6. A method for inspecting epitaxial defects, using the epitaxial defect inspection mold as described in claim 1 or 4, characterized in that, Includes the following processes: The epitaxial wafer (4), the pattern die (1), and the fixing die (3) are placed on the microscope inspection table; Microscopic recording of images of the epitaxial section (4); Analyze the image of the epitaxial wafer (4), and compare the position of the defect (7) in the image of the epitaxial wafer (4) with the position of the bar and single tube of the chip made by the epitaxial wafer (4) to obtain the corresponding position of each defect (7) in the bar and single tube.
7. A method for inspecting epitaxial defects, using the epitaxial defect inspection mold as described in claim 2 or 5, characterized in that, Includes the following processes: The epitaxial wafer (4), wafer mold (2), and fixing mold (3) are placed together on the microscope inspection table; Microscopic recording of images of the epitaxial section (4); Analyze the image of the epitaxial wafer (4) and record the location and number of defects (7) in the effective region (5) of the wafer fabricated by the epitaxial wafer (4) corresponding to the defects (7) in the image of the epitaxial wafer (4).
8. A method for inspecting epitaxial defects, using the epitaxial defect inspection mold as described in claim 3, characterized in that, Includes the following processes: The epitaxial wafer (4), the layout mold (1), the wafer mold (2), and the fixing mold (3) are placed together on the microscope inspection table; Microscopic recording of images of the epitaxial section (4); Analyze the image of the epitaxial wafer (4), and compare the position of the defect (7) in the image of the epitaxial wafer (4) with the position of the bar and single tube of the chip in the effective area (5) of the wafer to obtain the corresponding position of each defect (7) in the bar and single tube of the chip in the effective area (5) of the wafer.