Method and system for on-line junction temperature monitoring of power semiconductor based on miller platform voltage

Abstract

This invention provides a method and system for online junction temperature monitoring of power semiconductors based on Miller plateau voltage. The online junction temperature monitoring method for power semiconductors includes: Step S1: Calculating the Miller plateau voltage difference Δ during the current switching cycle using the following formula. V MP Δ V MP = V MP,on - V MP,off ;in, V MP,on This is the Miller plateau voltage measurement value of the power semiconductor in the on-state during the current switching cycle. V MP,off The Miller plateau voltage is the measured value of the power semiconductor in the off state during the current switching cycle; Step S2: Based on the relationship between the Miller plateau voltage difference and the junction temperature of the power semiconductor, the current Miller plateau voltage difference Δ V MP The junction temperature of the power semiconductor in the current switching cycle is obtained; wherein, in the relationship between the Miller plateau voltage difference and the junction temperature of the power semiconductor, the Miller plateau voltage difference and the junction temperature of the power semiconductor are linearly related.

Description

Technical Field

[0001] This invention belongs to the field of online monitoring of power semiconductor junction temperature, specifically relating to a method and system for online monitoring of power semiconductor junction temperature based on Miller plateau voltage. Background Technology

[0002] With the widespread application of silicon carbide metal-oxide-semiconductor field-effect transistors (SiC-MOSFETs) in high-performance power electronic systems, accurate junction temperature monitoring has become a crucial foundation for ensuring their reliable operation. SiC-MOSFETs, due to their high switching frequency, high power density, and excellent thermal performance, are widely used in new energy vehicles, renewable energy systems, and aerospace. However, under prolonged operation and high power density environments, the junction temperature of SiC-MOSFETs is prone to rise, accelerating device aging, causing electrical parameter drift, and potentially leading to thermally dependent failures. Therefore, accurate junction temperature estimation is critical for the reliability and thermal management optimization of SiC-MOSFETs.

[0003] Currently, methods based on temperature-sensitive electrical parameters (TSEP) are widely used in online junction temperature monitoring of SiC-MOSFETs due to their non-invasiveness, real-time nature, and ease of integration. In existing technologies, commonly used temperature-sensitive electrical parameters for junction temperature estimation include source-drain on-resistance, switching delay time, threshold voltage, and Miller plateau voltage during the on-state (or off-state) of the switching cycle. However, applying traditional temperature-sensitive electrical parameters for junction temperature estimation in practical applications still faces several challenges. First, these methods are significantly affected by device aging, making it difficult to stably estimate junction temperature over long periods. Second, the nonlinear mapping between temperature and electrical parameters limits the accuracy of junction temperature estimation. Finally, changes in load current, bus voltage, and other operating conditions reduce the robustness of the method, affecting its accuracy under complex operating conditions. Summary of the Invention

[0004] The present invention aims to solve the problems of insufficient accuracy and significant susceptibility to changes in operating conditions and device aging when using temperature-sensitive electrical parameters for junction temperature estimation in the prior art, and provides a method for online junction temperature monitoring of power semiconductors based on Miller plateau voltage.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a method for online junction temperature monitoring of power semiconductors based on Miller plateau voltage, comprising:

[0006] Step S1: Calculate the Miller plateau voltage difference Δ during the current switching cycle using the following formula. V MP :

[0007] Δ V MP = V MP,on - V MP,off ;

[0008] in, V MP,on This is the Miller plateau voltage measurement value of the power semiconductor in the on-state during the current switching cycle. V MP,off This is the Miller plateau voltage measurement of the power semiconductor in the off state during the current switching cycle;

[0009] Step S2: Based on the relationship between the Miller plateau voltage difference and the power semiconductor junction temperature, and the current Miller plateau voltage difference Δ... V MP This yields the junction temperature of the power semiconductor during the current switching cycle.

[0010] In the formula relating the Miller plateau voltage difference to the power semiconductor junction temperature, the Miller plateau voltage difference and the power semiconductor junction temperature are linearly related.

[0011] According to the same inventive concept, the present invention also provides a power semiconductor online junction temperature monitoring system based on Miller plateau voltage, comprising:

[0012] A trigger unit is used to detect the current drain-source voltage of the power semiconductor and determine whether a first condition and a second condition are met. The first condition is that the current drain-source voltage of the power semiconductor is less than a preset reference voltage, and the second condition is that the current drain-source voltage of the power semiconductor is greater than the preset reference voltage. The preset reference voltage has a value range of [0.4 × 10⁻⁶]. V ds,max 0.6× V ds,max ], V ds,max This represents the maximum drain-source voltage of the power semiconductor under the current operating conditions.

[0013] The detection unit outputs a valid signal at its first output terminal if the first condition is met at the current time and it is determined that the current time is the on state of the current switching cycle; and outputs a valid signal at its second output terminal if the second condition is met at the current time and it is determined that the current time is the off state of the current switching cycle.

[0014] The first sample-and-hold circuit has its input terminal, output terminal, and enable terminal electrically connected to the power semiconductor gate-source voltage acquisition terminal, the first input terminal of the signal processor, and the first output terminal of the detection unit, respectively.

[0015] The second sample-and-hold circuit has its input, output, and enable terminals electrically connected to the power semiconductor gate-source voltage acquisition terminal, the second input terminal of the signal processor, and the second output terminal of the detection unit, respectively.

[0016] A signal processor is used to execute the steps of the above-described online junction temperature monitoring method for power semiconductors.

[0017] This invention proposes a method based on the on / off Miller plateau voltage difference Δ V MP A method for online estimation of SiC-MOSFET junction temperature using temperature-sensitive electrical parameters. Simultaneously, an online measurement circuit for synchronous extraction of dual Miller plateau voltage was designed to obtain Δ in real time. V MP This overcomes the problem of traditional TSEP methods being affected by changes in operating conditions and device aging.

[0018] Compared with the prior art, the present invention has the following advantages:

[0019] (1) The proposed Δ V MP It has high temperature sensitivity, approximately 4.67 mV / °C, and exhibits a good linear relationship with junction temperature, ensuring high accuracy in online junction temperature estimation;

[0020] (2) This method is not sensitive to factors such as load current, bus voltage fluctuation and device aging, and can maintain high-precision measurement effect under various actual working conditions, ensuring the stability and reliability of online junction temperature estimation;

[0021] (3) Using the difference form Δ V MP It can effectively suppress common-mode offset and measurement noise, thereby improving the robustness and reliability of junction temperature estimation. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the voltage waveforms during the turn-on and turn-off transients of a SiC-MOSFET according to an embodiment of the present invention.

[0024] Figure 2 This is a gate equivalent circuit diagram during the Miller platform phase of the turn-on process in an embodiment of the present invention;

[0025] Figure 3 This is a gate equivalent circuit diagram during the Miller plateau phase of the turn-off process in an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the circuit structure connecting the power semiconductor online junction temperature monitoring system, the dual-pulse test circuit, and the power semiconductor when the power semiconductor is in the first connection state, according to an embodiment of the present invention.

[0027] Figure 5 for Figure 4 The timing diagram corresponding to the circuit structure;

[0028] Figure 6 This is a schematic diagram of the circuit connection of the drain, source, and gate of the power semiconductor when it is in the second connection state according to an embodiment of the present invention, wherein the online junction temperature monitoring system of the power semiconductor is omitted.

[0029] Figure 7 Δ is extracted at different preset temperatures in embodiments of the present invention. V MP .

[0030] In the above attached figures:

[0031] 1. Trigger unit; 11. First voltage divider circuit; 12. Buffer amplifier; 13. Comparator; 14. Inverter;

[0032] 2. Detection unit; 21. Second voltage divider circuit; 221. First monostable multivibrator; 222. Second monostable multivibrator; 231. First AND gate circuit; 232. Second AND gate circuit;

[0033] 3. Sample and hold unit; 31. Third voltage divider circuit; 321. First voltage follower; 322. Second voltage follower; 323. Third voltage follower; 324. Fourth voltage follower; 331. First sample and hold circuit; 332. Second sample and hold circuit;

[0034] 4. Data processing unit; 41. First signal isolator; 42. Analog-to-digital converter; 43. Signal processor; 44. Second signal isolator;

[0035] 50. Power semiconductors; 51. Gate drive circuits;

[0036] 60. Actual working circuit. Detailed Implementation

[0037] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0038] Figure 1 The transient waveforms of a SiC-MOSFET during turn-on and turn-off are shown, reflecting the voltage and current changes during these processes. During the Miller plateau phase, the turn-on and turn-off processes correspond to the drain-source voltage... V ds The rapid decrease and increase, and the turn-on Miller plateau voltage during the same pulse process. V MP,on Always higher than the turn-off Miller plateau voltage V MP,off It exhibits obvious asymmetry. Figure 1 middle, V g This represents the output signal of the gate drive circuit 51. In the ON state, V g = V g,on When in the off state, V g = V g,off . Figure 1 This demonstrates the output signal of the gate drive circuit 51 during the turn-on and turn-off processes of the SiC-MOSFET. V g Gate-source voltage V gs Drain current I d Drain-source voltage V ds A waveform diagram. Figure 1 middle, V th Indicates the threshold voltage. V bus Bus voltage I L For load current, V ds,on This represents the voltage of the power semiconductor in the on-state.

[0039] Figure 2 , Figure 3 The gate equivalent circuit of SiC-MOSFET during the Miller plateau phase of the turn-on and turn-off process is shown. Figure 2In the diagram, the shaded area represents the equivalent circuit model of a power semiconductor, which includes the equivalent gate resistance. R g,int (Also known as internal gate resistance), equivalent capacitance C gd (i.e., Miller capacitance), equivalent capacitance C ds Equivalent capacitance C gs . I sat This represents the drain current of a power semiconductor in its saturation operating region. Figure 2 Corresponding activation process, Figure 3 This corresponds to the turn-off process. During this stage, the gate circuit can be equivalently represented by the drive voltage... V g,on or V g,off External gate resistor R g,ext Equivalent gate resistance inside power semiconductors R g,int and input capacitance C iss A series network is formed. Due to the drain-source voltage... V ds Rapid changes in gate current I g Mainly used for Miller capacitors C gd Charging or discharging, while the gate-source voltage V gs This process remains constant, forming a Miller plateau. The Miller plateau voltage can be expressed as shown in Formula 1 below.

[0040] Formula 1:

[0041] ;

[0042] in, V th It is the threshold voltage. I d It is the drain current. L ch It is the channel length. Z It is the channel width. C ox It is the gate oxide capacitance density. μ This represents the mobility of charge carriers in the power semiconductor channel.

[0043] However, in practical applications, due to the internal gate resistance of SiC-MOSFETs... R g,int An unavoidable occurrence is that the gate voltage is typically sampled at...R g,ext and R g,int Instead of sampling directly from the chip's gate, the current is sampled from nodes between them. I g exist R g,int The voltage drop across the plateau causes the Miller plateau voltage to turn on and off ( V MP,on and V MP,off The measured value and the actual value V mil There are deviations between them, and these deviations are asymmetrical.

[0044] Specifically, during the turn-on process, the driving voltage V g,on Gate current during turn-on phase I g,on pass R g,ext and R g,int Forward flow, thus affecting the Miller capacitance C gd Charging is in progress. According to... Figure 2 Gate current during turn-on phase I g,on Corresponding Miller plateau voltage measurement value V MP,on It satisfies the following formula 2.

[0045] Formula 2:

[0046] ; ;

[0047] Formula 2 shows that, R g,int The forward voltage drop on the plateau causes the measured Miller plateau voltage to turn on. V MP,on Higher than the actual value V mil .in, RR g,int Internal gate resistor R g,int The resistance value, RR g,ext External gate resistor R g,ext The resistance value.

[0048] Conversely, during the turn-off phase, the drive voltage drops to... V g,off The gate current direction is reversed, and the gate current during the turn-off phase is... Ig,off pass R g,ext and R g,int Backflow to the driver source, for C gd Discharge complete. According to... Figure 3 Gate current during the turn-off phase I g,off With Miller platform voltage measurement value V MP,off It satisfies the following formula 3.

[0049] Formula 3:

[0050] ; ;

[0051] at this time, R g,int A reverse voltage drop is generated, causing the Miller plateau voltage measurement to be turned off. V MP,off Lower than the actual value V mil .

[0052] Combining Equation 2 and Equation 3, we can obtain the relationship between the measured value and the actual value of the Miller platform voltage, as shown in Equation 4.

[0053] Formula 4:

[0054]

[0055] Further calculation of the difference between the two yields the measured Miller plateau voltage difference Δ between the on and off states. V MP The analytical expression is shown in Formula 5.

[0056] Formula 5:

[0057] ;

[0058] Formula 5 shows that Δ V MP Originating from internal gate resistance R g,int The voltage drops generated in opposite directions during the charging and discharging paths have magnitudes that depend on the internal gate resistance. R g,int The percentage of total gate impedance. Δ V MP The expression only contains the internal gate resistance R g,int Temperature-related, junction temperature changes cause R g,int The change in Δ affectsV MP .because R g,int The temperature characteristics are unaffected by factors such as load current, bus voltage, gate oxide degradation, and package degradation; therefore, these factors have little impact on Δ. V MP The impact is also relatively small. Therefore, Δ V MP It exhibits good temperature dependence, making it an effective temperature-sensitive electrical parameter that can be used for online estimation of junction temperature. Here, the bus voltage represents the DC voltage supplying energy in the power conversion circuit where the power semiconductor is located. RR g,ext This is the default value.

[0059] This invention provides a method for online junction temperature monitoring of power semiconductors based on Miller plateau voltage, comprising:

[0060] Step S1: Calculate the Miller plateau voltage difference Δ during the current switching cycle using the following formula. V MP :

[0061] Δ V MP = V MP,on - V MP,off ;

[0062] in, V MP,on This is the Miller plateau voltage measurement value of power semiconductor 50 in the on-state during the current switching cycle. V MP,off This is the Miller plateau voltage measurement of power semiconductor 50 in the off state during the current switching cycle;

[0063] Step S2: Based on the relationship between the Miller plateau voltage difference and the junction temperature of the power semiconductor 50, the current Miller plateau voltage difference Δ V MP This yields the junction temperature of the power semiconductor 50 during the current switching cycle.

[0064] In the formula relating the Miller platform voltage difference to the junction temperature of the power semiconductor 50, the Miller platform voltage difference and the junction temperature of the power semiconductor 50 are linearly related.

[0065] According to the above-described configuration of the present invention, by measuring the Miller plateau voltage of the power semiconductor 50 in the on-state and the off-state during the current switching cycle online, the Miller plateau voltage difference Δ during the current switching cycle can be obtained. V MPThe junction temperature of the power semiconductor 50 in the current switching cycle is thus obtained. This invention, through theoretical derivation, discovers a linear relationship between the Miller plateau voltage difference and the junction temperature; this linear relationship allows for better junction temperature estimation accuracy. Based on the above theoretical derivation, the Miller plateau voltage difference in this application is only related to… R g,int Relatedly, compared with the existing technology that uses temperature-sensitive electrical parameters such as source-drain on-resistance, switching delay time, threshold voltage, and Miller plateau voltage during the on-state (or off-state) of the switching cycle to estimate junction temperature, the advantages of this application include: (1) due to the influence of device aging on junction temperature estimation... R g,int The impact of the aging of the device is relatively small, and the junction temperature monitoring method of this application is less affected by the aging of the device, and can stably estimate the junction temperature over a long period of time; (2) Since the junction temperature and the Miller plateau voltage difference are linearly related, the junction temperature estimation accuracy is better; (3) Since the changes in load current, bus voltage and other operating conditions have a relatively small impact on the junction temperature estimation accuracy, the method can accurately estimate the junction temperature over a long period of time. R g,int The impact of load current changes and bus voltage changes is relatively small, thus minimizing the influence of these operating conditions on the junction temperature monitoring method of this application. Even if the load current or bus voltage changes, there is no need to refit the relationship between the junction temperature and the Miller plateau voltage difference. This results in good robustness of the method, obtaining robust fitting coefficients, eliminating measurement errors and random noise, and maintaining superior accuracy even under complex operating conditions.

[0066] Additionally, if an internal gate resistor is used R g,int The traditional direct measurement method, which involves inputting a high-frequency AC signal to the gate of the power semiconductor and measuring the internal gate resistance by analyzing the signal response, suffers from the risk of electromagnetic interference from high-frequency signal injection and places high demands on the bandwidth of the measurement circuit. In contrast, this method eliminates the need for high-frequency signal injection. Instead, it measures the Miller plateau voltage difference to correlate the Miller plateau voltage difference with the internal gate resistance. R g,int The correlation allows for the effective utilization of the internal gate resistance. R g,int It has the advantage of a good linear relationship with junction temperature, utilizing the internal gate resistance. R g,int It has the advantage of being less affected by factors such as load current, bus voltage, gate oxide degradation and package degradation, and also avoids electromagnetic interference problems that may be caused by high-frequency signal injection.

[0067] Furthermore, the method for determining the relationship between the Miller plateau voltage difference and the junction temperature of the power semiconductor 50 includes:

[0068] Step SA1: Heat the power semiconductor 50 at multiple preset temperatures within the operating temperature range of the power semiconductor 50. When thermal equilibrium is reached each time the power semiconductor 50 is heated, determine the Miller plateau voltage difference corresponding to each preset temperature.

[0069] Step SA2: Based on each preset temperature and the Miller plateau voltage difference corresponding to the preset temperature, fit the relationship between the Miller plateau voltage difference and the junction temperature of the power semiconductor 50.

[0070] In this invention, the power semiconductor can be a power switching device, such as a SiC-MOSFET or an IGBT. Multiple preset temperatures are multiple temperatures obtained by taking values ​​at intervals within the 50°C operating temperature range of the power semiconductor. The meaning of multiple preset temperatures is that the number of preset temperatures is not less than 2, preferably not less than 6. For example, the multiple preset temperatures include 25°C, 50°C, 75°C, 100°C, 125°C, and 150°C. Under each preset temperature condition, the power semiconductor is heated and held for a predetermined time until it reaches a thermal equilibrium state. In the thermal equilibrium state, the preset temperature can be equivalently regarded as the junction temperature of the power semiconductor. In this state, the Miller plateau voltage difference corresponding to each preset temperature condition is obtained, and a mapping relationship between the Miller plateau voltage difference and the junction temperature is established accordingly. In step SA2, the proportional coefficient and constant in the linear relationship between the Miller plateau voltage difference and the junction temperature can be obtained through an existing fitting method (e.g., the least squares method).

[0071] According to the same inventive concept, the present invention also provides a power semiconductor online junction temperature monitoring system based on Miller plateau voltage, comprising:

[0072] Trigger unit 1 is used to detect the current drain-source voltage of power semiconductor 50 and determine whether a first condition and a second condition are met. The first condition is that the current drain-source voltage of power semiconductor 50 is less than a preset reference voltage, and the second condition is that the current drain-source voltage of power semiconductor 50 is greater than a preset reference voltage. The preset reference voltage has a value range of [0.4 × 10⁻⁶]. V ds,max 0.6× V ds,max ], V ds,max This represents the maximum drain-source voltage of the power semiconductor 50 under current operating conditions; the preset reference voltage is preferably 0.5 × V ds,max ;

[0073] Detection unit 2: If the first condition is met at the current time and it is determined that the current time is the on state of the current switching cycle, the first output terminal of detection unit 2 outputs a valid signal; if the second condition is met at the current time and it is determined that the current time is the off state of the current switching cycle, the second output terminal of detection unit 2 outputs a valid signal; the valid signal is used to enable the corresponding sample-and-hold circuit.

[0074] The first sample-and-hold circuit 331 has its input terminal, output terminal, and enable terminal electrically connected to the gate-source voltage acquisition terminal of the power semiconductor 50, the first input terminal of the signal processor 43, and the first output terminal of the detection unit 2, respectively.

[0075] The second sample-and-hold circuit 332 has its input terminal, output terminal, and enable terminal electrically connected to the gate-source voltage acquisition terminal of the power semiconductor 50, the second input terminal of the signal processor 43, and the second output terminal of the detection unit 2, respectively.

[0076] The signal processor 43 is used to execute the steps of the online junction temperature monitoring method for power semiconductors.

[0077] During the research, it was discovered that within the Miller plateau phase corresponding to the on-state and off-state of the power semiconductor, its drain-source voltage exhibits a rapid change characteristic from high to low or from low to high, respectively. Therefore, by comparing the drain-source voltage of the power semiconductor with a preset reference voltage, it is possible to determine whether the current moment is within the Miller plateau phase. Combined with the determination that the current switching transient is a turn-on or turn-off process, it is possible to determine whether the current moment is within the turn-on Miller plateau phase or the turn-off Miller plateau phase, thus using the gate-source voltage corresponding to that moment as the corresponding Miller plateau voltage measurement value. In this invention, a trigger unit is used to compare the drain-source voltage with the preset reference voltage in real time and determine whether the time interval corresponding to the Miller plateau voltage has been entered; a detection unit is used to determine whether the current switching transient is a turn-on or turn-off process. When the trigger unit determines that the current moment is within the Miller plateau phase, and the detection unit determines that the current moment is a turn-on process, the current moment is determined to be within the turn-on Miller plateau phase; when the trigger unit determines that the current moment is within the Miller plateau phase, and the detection unit determines that the current moment is a turn-off process, the current moment is determined to be within the turn-off Miller plateau phase. The first and second sample-and-hold circuits are used to acquire the gate-source voltage, respectively. When the detection unit determines that the current state is the Miller plateau phase, the first output signal of the detection unit 2 enables the first sample-and-hold circuit, causing the first sample-and-hold circuit to hold the input signal (i.e., the Miller plateau voltage measurement value in the on-state) for a set time and continuously output the signal to the first input terminal of the signal processor. When the detection unit determines that the current state is the Miller plateau phase, the second output signal of the detection unit 2 enables the second sample-and-hold circuit, causing the second sample-and-hold circuit to hold the input signal (i.e., the Miller plateau voltage measurement value in the off-state) for a set time and continuously output the signal to the second input terminal of the signal processor. The signal processor obtains the Miller plateau voltage difference within the current switching cycle by performing a difference calculation on the signals at the first and second input terminals.

[0078] Furthermore, the power semiconductor online junction temperature monitoring system also includes a dual-pulse test circuit and a heating device. The dual-pulse test circuit includes an inductor. L ce ,capacitance C ce ;

[0079] The power semiconductor 50 has a first connection state and a second connection state;

[0080] When the power semiconductor 50 is in the first connection state, the drain and source of the power semiconductor 50 are electrically connected to the dual-pulse test circuit.

[0081] When the power semiconductor 50 is in the second connection state, the drain and source of the power semiconductor 50 are electrically connected to the actual working circuit 60 corresponding to the online junction temperature monitoring.

[0082] The heating device is used to heat the power semiconductor 50 at multiple preset temperatures within the operating temperature range of the power semiconductor 50 when the power semiconductor 50 is in the first connected state.

[0083] The signal processor 43 is further configured to: when the power semiconductor 50 is in a first connection state and the power semiconductor 50 is heated to a thermal equilibrium state, determine the Miller plateau voltage difference corresponding to each preset temperature, and fit the relationship between the Miller plateau voltage difference and the junction temperature of the power semiconductor 50 according to each preset temperature and the Miller plateau voltage difference corresponding to the preset temperature; wherein, in the relationship between the Miller plateau voltage difference and the junction temperature of the power semiconductor 50, the Miller plateau voltage difference and the junction temperature of the power semiconductor 50 are linearly correlated; when the power semiconductor 50 is in a second connection state, execute steps S1 and S2.

[0084] In this embodiment, when the power semiconductor 50 is in the first connection state, its drain and source are connected to a dual-pulse test circuit including a bus capacitance and a load inductance. The dual-pulse test circuit includes an inductor. L ce ,capacitance C ce Preferably, the dual-pulse test circuit further includes an inductor. L ce parallel diodes D ce This is used to provide a freewheeling path. In this embodiment, the source of the power semiconductor 50 shares a common ground with the reference ground of the dual-pulse test circuit, and the drain of the power semiconductor 50 is connected in sequence through an inductor. L ce and capacitor C ce Connected to a reference ground. The dual-pulse test circuit of this invention is not limited to... Figure 4 The circuit structure shown can be used as the dual-pulse test circuit in this invention by any circuit structure capable of providing a dual-pulse signal as the driving signal. To visually demonstrate the timing relationship and triggering logic between the main signals, Figure 5 Given Figure 4 The timing diagram corresponding to the circuit structure.

[0085] In the first connection state, by applying a dual-pulse drive signal to the power semiconductor and heating it under multiple preset temperature conditions to achieve thermal equilibrium, the corresponding Miller plateau voltage difference is obtained, which is then used to establish a linear relationship between the junction temperature and the Miller plateau voltage difference.

[0086] like Figure 6As shown, when the power semiconductor 50 is in the second connection state, its drain and source are connected to the actual working circuit 60 corresponding to online junction temperature monitoring to perform power conversion function. The second connection state corresponds to the working state of the power semiconductor in actual application scenarios, such as operation in power conversion circuits in new energy vehicles, renewable energy systems, or aerospace applications. In the second connection state, the gate receives a pulse width modulation (PWM) signal to achieve power conversion.

[0087] In the first connection state and the second connection state, the gate of the power semiconductor 50 is connected through an external gate resistor. R g,ext The gate drive circuit 51 is electrically connected to the output terminal of the gate drive circuit 51; the input terminal of the gate drive circuit 51 is electrically connected to the signal processor 43. Preferably, the two can be electrically isolated by a second signal isolator 44, so that the signal processor 43 provides a drive signal to the power semiconductor.

[0088] In both the first and second connection states, the Miller plateau voltage difference is calculated by acquiring the corresponding signals from the power semiconductors. That is, trigger unit 1, detection unit 2, first sample-and-hold circuit 331, second sample-and-hold circuit 332, and signal processor 43 are all in operation. To simplify the circuit, in... Figure 6 The second connection state shown omits the corresponding circuit structure of the power semiconductor online junction temperature monitoring system, specifically omitting the trigger unit 1, detection unit 2, sample and hold unit 3, data processing unit 4, and second signal isolator 44. For Figure 6 The second connection state shown can be referred to by those skilled in the art. Figure 4 The corresponding circuit structure.

[0089] In the actual working circuit 60 corresponding to online junction temperature monitoring, when the power semiconductor 50 is used as a low-side switching device, its source is connected to the reference potential; when the power semiconductor 50 is used as a high-side switching device, its source is at a floating potential that changes with the circuit's operating state.

[0090] Further, the trigger unit 1 includes a comparator 13 and an inverter 14 electrically connected to the output of the comparator 13; the non-inverting input and inverting input of the comparator 13 are electrically connected to the drain-source voltage acquisition terminal and the first reference voltage terminal of the power semiconductor 50, respectively; the output of the inverter 14 forms the first output of the trigger unit 1, and the output of the comparator 13 forms the second output of the trigger unit 1; the voltage of the first reference voltage terminal is kc1× V ref ; V ref The preset reference voltage;

[0091] Among them, the signal of the drain-source voltage acquisition terminal V ds The signal at the non-inverting input of the comparator 13 The relation is kc1 is the voltage signal scaling factor.

[0092] Through the above technical solution, comparator 13 is used to compare the drain-source voltage signal of power semiconductor 50 with a preset reference voltage to determine whether the drain-source voltage meets the preset conditions.

[0093] Furthermore, the triggering unit 1 also includes a first voltage divider circuit 11 and a buffer amplifier 12; the signal at the input terminal and the signal at the output terminal of the first voltage divider circuit 11 are linearly correlated.

[0094] The drain-source voltage acquisition terminal of the power semiconductor 50 is electrically connected to the non-inverting input terminal of the buffer amplifier 12 through the first voltage divider circuit 11. The inverting input terminal and the output terminal of the buffer amplifier 12 are both electrically connected to the non-inverting input terminal of the comparator 13.

[0095] By setting up a first voltage divider circuit, the drain-source voltage of the power semiconductor 50 can be divided into a signal range suitable for the comparator input. The first voltage divider circuit may include a first resistor, a second resistor, a first capacitor, and a second capacitor. One end of the first resistor, one end of the second resistor, one end of the first capacitor, and one end of the second capacitor are all electrically connected to the non-inverting input terminal of the buffer amplifier 12. The other ends of the first resistor and the first capacitor are electrically connected to each other to form the input terminal of the first voltage divider circuit, thereby electrically connecting to the drain-source voltage acquisition terminal of the power semiconductor 50. The other ends of the second resistor and the second capacitor are both grounded.

[0096] Furthermore, the detection unit 2 includes a first monostable multivibrator 221, a second monostable multivibrator 222, a first AND gate circuit 231, and a second AND gate circuit 232;

[0097] The rising edge-activated trigger input of the first monostable multivibrator 221 and the falling edge-activated trigger input of the second monostable multivibrator 222 are both electrically connected to the output of the gate drive circuit 51 (i.e., the gate drive signal acquisition terminal of the power semiconductor 50).

[0098] The output of the gate drive circuit 51 and the gate resistor R g,ext One end is electrically connected, gate resistor R g,ext The other end is electrically connected to the gate of the power semiconductor 50; the gate drive signal of the power semiconductor 50 V p This is the voltage at the output terminal of the gate drive circuit 51;

[0099] The first output terminal of the trigger unit 1 and the non-inverting output terminal of the first monostable multivibrator 221 are respectively electrically connected to the two input terminals of the first logic AND gate 231; the second output terminal of the trigger unit 1 and the non-inverting output terminal of the second monostable multivibrator 222 are respectively electrically connected to the two input terminals of the second logic AND gate 232.

[0100] The output terminals of the first AND gate 231 and the second AND gate 232 respectively form the first output terminal and the second output terminal of the detection unit 2.

[0101] Furthermore, the rising edge-activated trigger input of the first monostable multivibrator 221 and the falling edge-activated trigger input of the second monostable multivibrator 222 are electrically connected to the output of the gate drive circuit 51 through the second voltage divider circuit 21; the signals at the input and output of the second voltage divider circuit 21 are linearly correlated.

[0102] Specifically, the input terminal of the second voltage divider circuit 21 is electrically connected to the output terminal of the gate drive circuit 51, and the trigger input terminal of the first monostable multivibrator 221 (effective on the rising edge) and the trigger input terminal of the second monostable multivibrator 222 (effective on the falling edge) are both electrically connected to the output terminal of the second voltage divider circuit 21.

[0103] The first monostable multivibrator 221 and the second monostable multivibrator 222 are used to detect the rising edge and falling edge of the gate drive signal, respectively. Their input terminals that are not involved in the trigger determination can be set to a fixed level state, and their unused output terminals can be excluded from subsequent logic processing.

[0104] A second voltage divider circuit is configured to scale the gate drive signal proportionally to obtain a voltage signal range suitable for the inputs of the first monostable multivibrator 221 and the second monostable multivibrator 222. The second voltage divider circuit includes a third resistor, a fourth resistor, and a fifth resistor. One end of the third resistor, one end of the fourth resistor, and one end of the fifth resistor are electrically connected to each other to form the output terminal of the second voltage divider circuit 21. The other end of the third resistor is electrically connected to a second reference voltage terminal (e.g., 5V), the other end of the fourth resistor forms the input terminal of the second voltage divider circuit 21, and the other end of the fifth resistor is electrically connected to a reference potential.

[0105] Furthermore, the power semiconductor online junction temperature monitoring system also includes a third voltage divider circuit 31; the signal at the input terminal and the signal at the output terminal of the third voltage divider circuit 31 are linearly correlated.

[0106] The input terminal of the third voltage divider circuit 31 is electrically connected to the gate-source voltage acquisition terminal of the power semiconductor 50, and the input terminals of the first sample-and-hold circuit 331 and the second sample-and-hold circuit 332 are both electrically connected to the output terminal of the third voltage divider circuit 31.

[0107] The signal at the gate-source voltage acquisition terminal V gs The signal at the first input terminal of the signal processor 43 V in,1 The relation is V in,1 =kp1× V gs +cp1;

[0108] The signal at the gate-source voltage acquisition terminal V gs The signal at the second input terminal of the signal processor 43 V in,2 The relation is V in,2 =kp2× V gs +cp2;

[0109] kp1 and cp1 are the first preset proportional coefficient and the first preset constant, respectively; kp2 and cp2 are the second preset proportional coefficient and the second preset constant, respectively.

[0110] Determined according to the following formula V MP,on value, V MP,off Value:

[0111] V MP,on =( V in,1 -cp1) / kp1; V MP,off =( V in,2 -cp2) / kp2.

[0112] A third voltage divider circuit 31 is used to perform voltage division on the gate-source voltage of the power semiconductor 50 to obtain a signal range suitable for subsequent signal processing circuit input. The third voltage divider circuit 31 includes a sixth resistor, a seventh resistor, and an eighth resistor. One end of the sixth resistor, one end of the seventh resistor, and one end of the eighth resistor are electrically connected to each other to form the output terminal of the third voltage divider circuit 31. The other end of the seventh resistor is electrically connected to a reference potential, the other end of the eighth resistor forms the input terminal of the third voltage divider circuit 31, and the other end of the sixth resistor is electrically connected to a second reference voltage terminal. kp1, cp1, kp2, and cp2 are jointly determined by the circuit parameters between the third voltage divider circuit 31 and the signal processor 43.

[0113] Furthermore, the power semiconductor online junction temperature monitoring system also includes a first signal isolator 41, an analog-to-digital converter 42, a first voltage follower 321, a second voltage follower 322, a third voltage follower 323, and a fourth voltage follower 324;

[0114] The input terminal of the first sample-and-hold circuit 331 is electrically connected to the output terminal of the third voltage divider circuit 31 through the first voltage follower 321;

[0115] The input terminal of the second sample-and-hold circuit 332 is electrically connected to the output terminal of the third voltage divider circuit 31 through the second voltage follower 322; the output terminal of the first sample-and-hold circuit 331 is electrically connected to the first input terminal of the signal processor 43 in sequence through the third voltage follower 323, the first signal isolator 41, and the analog-to-digital converter 42.

[0116] The output of the second sample-and-hold circuit 332 is electrically connected to the second input of the signal processor 43 via the fourth voltage follower 324, the first signal isolator 41, and the analog-to-digital converter 42.

[0117] Specifically, the first voltage follower 321 is configured to follow voltages, with its input terminal electrically connected to the output terminal of the third voltage divider circuit 31, its output terminal electrically connected to the inverting input terminal, and electrically connected to the input terminal of the first sample-and-hold circuit 331.

[0118] Specifically, the second voltage follower 322 is configured to follow voltages, with its input terminal electrically connected to the output terminal of the third voltage divider circuit 31, its output terminal electrically connected to the inverting input terminal, and electrically connected to the input terminal of the second sample-and-hold circuit 332.

[0119] The output of the first sample-and-hold circuit 331 is buffered by the third voltage follower 323 and then electrically connected to the first input of the first signal isolator 41. The first input and first output of the first signal isolator 41 are correspondingly configured. The first output of the first signal isolator 41 is electrically connected to the first input of the signal processor 43 via the analog-to-digital converter 42. Specifically, the output of the first sample-and-hold circuit 331 is electrically connected to the non-inverting input of the third voltage follower 323, and the output of the third voltage follower 323 is fed back to its inverting input to form a voltage follower structure. The output of the third voltage follower 323 is electrically connected to the first input of the first signal isolator 41.

[0120] The output of the second sample-and-hold circuit 332 is buffered by the fourth voltage follower 324 and then electrically connected to the second input of the first signal isolator 41. The second input and second output of the first signal isolator 41 are correspondingly configured. The second output of the first signal isolator 41 is electrically connected to the second input of the signal processor 43 via the analog-to-digital converter 42. Specifically, the output of the second sample-and-hold circuit 332 is electrically connected to the non-inverting input of the fourth voltage follower 324, and the output of the fourth voltage follower 324 is fed back to its inverting input to form a voltage follower structure. The output of the fourth voltage follower 324 is electrically connected to the second input of the first signal isolator 41. The circuit structures between the first input and first output of the first signal isolator 41 and between the second input and second output are independently configured.

[0121] This invention provides a method and online measurement circuit for SiC-MOSFET junction temperature based on Miller plateau voltage asymmetry during turn-on / turn-off, to solve the problems of existing online junction temperature measurement accuracy being easily affected by operating conditions and aging, as well as the complexity of the measurement circuit. The invention is further described in detail below.

[0122] This invention provides an online monitoring method for the junction temperature of SiC-MOSFETs based on the asymmetry of the turn-on / turn-off Miller plateau voltage. This method synchronously extracts the turn-on Miller plateau voltage within the same switching pulse. V MP,on With the turn-off Miller plateau voltage V MP,off And construct a new temperature-sensitive electrical parameter Δ based on the difference between the two. V MP = V MP,on - V MP,off .

[0123] As another aspect of the present invention, an online measurement circuit for synchronously extracting dual Miller plateau voltages is provided. This circuit employs the aforementioned online monitoring method for SiC-MOSFET junction temperature based on the asymmetry of the turn-on / turn-off Miller plateau voltage. The online junction temperature measurement circuit is as follows: Figure 6 As shown. Figure 4 , Figure 6 middle, V gs This represents the gate-source voltage of a power semiconductor. V ds This represents the drain-source voltage of a power semiconductor. V p This indicates the gate drive signal output by the gate drive circuit 51.

[0124] like Figure 5 As shown, during the switching process, the signal after being divided by the gate drive signal... The rising or falling edge triggers the monostable circuit to generate a pulse. V os,1 and V os,2 At the same time, voltage Rapidly drops / rises and falls below / rises above the preset reference voltage. V ref The output signal of inverter 14 / Output signal of comparator 13 V comp Inversion. When the output signals of the first monostable multivibrator and the inverter are both at a high level, a trigger pulse is generated. V sh,1 When the output signals of the second monostable multivibrator and the comparator are both at a high level, a trigger pulse is generated. V sh,2 Each of these circuits enables its corresponding sample-and-hold circuit, and the corresponding sample-and-hold circuit can hold the corresponding data. Voltage. At this time, the output of the sample-and-hold unit. V out,1 or V out,2 Maintain the corresponding Miller plateau voltages within the red and blue shaded regions, respectively. V MP,on and V MP,off Preset reference voltage V ref Typically set to V dsA preset ratio for the amplitude, preferably 0.4 to 0.6. By using a reference voltage proportional to the drain-source voltage amplitude, stable determination of the drain-source voltage variation process can be achieved in different switching cycles, thereby ensuring reliable identification of the Miller plateau stage.

[0125] To clearly describe the implementation of this measurement circuit, the following will introduce its four main functional units: the circuit includes a trigger unit 1, a detection unit 2, a sample-and-hold unit 3, and a data processing unit 4. The specific implementation is as follows:

[0126] Trigger unit 1 can also be called a threshold trigger unit. The function of trigger unit 1 is to detect the drain-source voltage in real time. V ds Whether the preset reference voltage related to the Miller platform determination has been reached V ref This triggers the gate-source voltage. V gs Measurement of drain-source voltage. V ds First, the voltage is scaled proportionally by the first voltage divider circuit 11 (which can be a resistor-capacitor voltage divider network), and then output by the buffer amplifier 12 (which can be a high-speed buffer amplifier). This reduces the impact of the source impedance on the input of subsequent comparators. (The buffered input...) With preset reference voltage V ref The positive and negative terminals of comparator 13 (a high-speed comparator can be used) are compared respectively. The output of comparator 13 is also connected to an inverter 14. When When the change exceeds a threshold (e.g., increases to a value exceeding the threshold or decreases to a value less than the threshold), comparator 13 outputs a first comparison signal. V comp Inverter 14 outputs an inverted signal corresponding to the first comparison signal. The first comparison signal and its inverted signal are used as logical input signals for subsequent trigger determination.

[0127] Detection unit 2 can also be called an edge detection unit. Detection unit 2 captures the gate drive signal. V p The rising and falling edges are used to effectively distinguish between the turn-on and turn-off phases. The gate driver output... V p The signal is close to a rectangular wave, and after passing through the second voltage divider circuit 21 (a resistor voltage divider network can be used), it becomes... This is to satisfy the input voltage range of the monostable multivibrator. Subsequently, The rising and falling edges are respectively fed into the first monostable multivibrator 221 and the second monostable multivibrator 222, which are used to generate gating pulses for turn-on detection.V os,1 and gating pulses used for shutdown detection V os,2 Next, the outputs of comparator 13 and inverter 14 are respectively ANDed with the corresponding gate pulses, where... and V os,1 These two inputs, respectively, are used as the two inputs of the first logic AND gate 231, and a logical AND operation is performed to generate the sampling trigger pulse for turning on the Miller platform. V sh,1 ,and V comp and V os,2 These two inputs, respectively, are used as the two inputs to the second logic AND gate 232, where a logical AND operation is performed to generate the sampling trigger pulse for turning off the Miller platform. V sh,2 .

[0128] Sample and hold unit 3 is used to quickly capture the gate-source voltage at the appropriate trigger time. V gs The transient value is recorded and held for a period of time for subsequent junction temperature estimation. V gs The voltage is scaled proportionally by the third voltage divider circuit 31 (which may be a resistor voltage divider network). The data is fed into the input terminals of the first sample-and-hold circuit 331 and the second sample-and-hold circuit 332. When the enable terminal of the first sample-and-hold circuit 331 receives... V sh,1 When the rising edge trigger pulse is received, it switches to hold state and outputs the value. V out,1 Keep it in this moment C h1 The voltage on the circuit corresponds to the Miller plateau voltage. When the enable pin of the second sample-and-hold circuit 332 receives... V sh,2 When the rising edge trigger pulse is received, it switches to hold state and outputs the value. V out,2 Keep it in this moment C h2The voltage on the circuit corresponds to the Miller plateau voltage. Specifically, the output of the third voltage divider circuit 31 and the input of the first sample-and-hold circuit 331 can be electrically connected via a first voltage follower 321; the output of the third voltage divider circuit 31 and the input of the second sample-and-hold circuit 332 can be electrically connected via a second voltage follower 322; the output of the first sample-and-hold circuit 331 and the first input of the first signal isolator 41 can be electrically connected via a third voltage follower 323; and the output of the second sample-and-hold circuit 332 and the second input of the first signal isolator 41 can be electrically connected via a fourth voltage follower 324.

[0129] Data processing unit 4 will sample the V out,1 and V out,2 The signal is linearly amplified by the first signal isolator 41, increasing the signal strength at the input of the analog-to-digital converter 42. V OUT,1 and V OUT,2 This increases the amplitude of the signal, thereby improving the signal acquired by the signal processor 43 (which may be a digital signal processor DSP). V MP,on and V MP,off The resolution of the signal. Then, the DSP calculates the difference between the two signals to obtain Δ. V MP In each switching cycle, Δ V MP It is sent to the DSP, and the Δ is stored in the DSP. V MP - T j The model is based on the measured Δ V MP return T j information.

[0130] To verify the feasibility of the proposed online junction temperature monitoring method, this embodiment employs a double-pulse switch test to validate the designed measurement circuit. The device under test (DUT) is a SiC-MOSFET, model C3M0016120K, with an internal gate resistor... R g,int The external gate resistor is 2.6Ω. R g,ext 10Ω, input voltage V IN 200V, load current I L It is 4A.

[0131] In the experiment, the device under test (DUT) was heated to 25°C, 50°C, 75°C, 100°C, 125°C, and 150°C using a temperature controller. At each preset temperature, the power semiconductor under test was kept heated to thermal equilibrium before testing, ensuring the junction temperature of the power semiconductor remained stable within the corresponding preset temperature range, thus avoiding the influence of junction temperature fluctuations on the measurement results. In this thermal equilibrium state, the preset temperature can be considered as the junction temperature of the power semiconductor, used to determine the Miller plateau voltage difference corresponding to that preset temperature. At each temperature, the load current... I L It is controlled as 4A.

[0132] Figure 7 The Miller plateau voltage difference Δ is shown during the turn-on and turn-off processes of SiC-MOSFETs under different junction temperatures. V MP Temperature dependence. Through the study of... Figure 7 The Δ is obtained by differential processing of the data in the middle. V MP This effectively suppresses common-mode offset, thereby improving measurement accuracy. When the junction temperature increases from 25°C to 150°C, Δ... V MP It shows a clear upward trend and a good linear relationship with the junction temperature, and the temperature sensitivity coefficient... S T The value is approximately 4.67 mV / °C. Therefore, it can be seen that when the junction temperature changes, the Miller plateau voltage difference Δ measured using this method... V MP The corresponding change indicates that the Miller plateau voltage difference is temperature-sensitive to the junction temperature. Experimental results verify that the proposed measurement circuit can accurately measure Δ. V MP Based on this, the junction temperature of SiC-MOSFETs can be derived. T j Among them, temperature sensitivity parameters S T It is the voltage difference Δ V MP The ratio between the voltage change and the junction temperature change ΔT represents the voltage difference corresponding to each unit temperature change. Specifically, S T =Δ V MP / ΔT.

[0133] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0134] The embodiments of the present invention have been described in detail above, but the content described is only a preferred embodiment of the present invention and should not be considered as limiting the scope of the present invention. All equivalent changes and modifications made within the scope of the present invention should still fall within the scope of the present invention. After reading this invention, modifications of various equivalent forms of the present invention by those skilled in the art fall within the scope defined by this application. Unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

Claims

1. A power semiconductor on-line junction temperature monitoring system based on Miller platform voltage, characterized by, include: The trigger unit (1) is used to detect the current drain-source voltage of the power semiconductor (50) and determine whether the first condition and the second condition are met. The first condition is that the current drain-source voltage of the power semiconductor (50) is less than a preset reference voltage, and the second condition is that the current drain-source voltage of the power semiconductor (50) is greater than the preset reference voltage. The preset reference voltage has a value range of [0.4 × 1000 kJ / m²]. V ds,max 0.6× V ds,max ], V ds,max This represents the maximum drain-source voltage of the power semiconductor (50) under the current operating conditions; Detection unit (2): If the first condition is met at the current time and it is determined that the current time is the on state of the current switching cycle, the first output terminal of the detection unit (2) outputs a valid signal; if the second condition is met at the current time and it is determined that the current time is the off state of the current switching cycle, the second output terminal of the detection unit (2) outputs a valid signal. The first sample-and-hold circuit (331) has its input, output and enable terminals electrically connected to the gate-source voltage acquisition terminal of the power semiconductor (50), the first input terminal of the signal processor (43), and the first output terminal of the detection unit (2), respectively. The second sample-and-hold circuit (332) has its input, output, and enable terminals electrically connected to the gate-source voltage acquisition terminal of the power semiconductor (50), the second input terminal of the signal processor (43), and the second output terminal of the detection unit (2), respectively. Signal processor (43) is used to perform the steps of the online junction temperature monitoring method for power semiconductors; The online junction temperature monitoring method for power semiconductors includes: Step S1: Calculate the Miller plateau voltage difference Δ during the current switching cycle using the following formula. V MP : D V MP = V MP,on − V MP,off ; in, V MP,on The Miller plateau voltage measurement value of the power semiconductor (50) in the on-state during the current switching cycle. V MP,off The Miller plateau voltage measurement of the power semiconductor (50) in the off state during the current switching cycle; Step S2: Based on the relationship between the Miller plateau voltage difference and the junction temperature of the power semiconductor (50), the current Miller plateau voltage difference Δ V MP The junction temperature of the power semiconductor (50) in the current switching cycle is obtained; In the formula relating the Miller plateau voltage difference to the junction temperature of the power semiconductor (50), the Miller plateau voltage difference and the junction temperature of the power semiconductor (50) are linearly related.

2. The power semiconductor online junction temperature monitoring system according to claim 1, characterized in that, The method for determining the relationship between the Miller plateau voltage difference and the junction temperature of the power semiconductor (50) includes: Step SA1: Heat the power semiconductor (50) at multiple preset temperatures within the operating temperature range of the power semiconductor (50). When thermal equilibrium is reached each time the power semiconductor (50) is heated, determine the Miller plateau voltage difference corresponding to each preset temperature. Step SA2: Based on each preset temperature and the Miller plateau voltage difference corresponding to the preset temperature, fit the relationship between the Miller plateau voltage difference and the junction temperature of the power semiconductor (50).

3. The power semiconductor online junction temperature monitoring system according to claim 1, characterized in that, The gate of the power semiconductor (50) is electrically connected to the gate drive circuit (51) through a gate resistor; The power semiconductor online junction temperature monitoring system also includes a dual-pulse test circuit and a heating device; The power semiconductor (50) has a first connection state and a second connection state; When the power semiconductor (50) is in the first connection state, the drain and source of the power semiconductor (50) are electrically connected to the double pulse test circuit; When the power semiconductor (50) is in the second connection state, the drain and source of the power semiconductor (50) are electrically connected to the actual working circuit (60) corresponding to the online junction temperature monitoring. The heating device is used to heat the power semiconductor (50) at multiple preset temperatures within the operating temperature range of the power semiconductor (50) when the power semiconductor (50) is in the first connected state. The signal processor (43) is further configured to: when the power semiconductor (50) is in a first connection state and the power semiconductor (50) is heated to a thermal equilibrium state, determine the Miller plateau voltage difference corresponding to each preset temperature, and fit the Miller plateau voltage difference with the junction temperature of the power semiconductor (50) according to each preset temperature and the Miller plateau voltage difference corresponding to the preset temperature; and execute steps S1 and S2 when the power semiconductor (50) is in a second connection state.

4. The power semiconductor online junction temperature monitoring system according to claim 1 or 3, characterized in that, The trigger unit (1) includes a comparator (13) and an inverter (14) electrically connected to the output of the comparator (13); the non-inverting input and the inverting input of the comparator (13) are electrically connected to the drain-source voltage acquisition terminal and the first reference voltage terminal of the power semiconductor (50), respectively; the output of the inverter (14) forms the first output of the trigger unit (1), and the output of the comparator (13) forms the second output of the trigger unit (1); the voltage of the first reference voltage terminal is kc1× V ref ; V ref The preset reference voltage; Among them, the signal of the drain-source voltage acquisition terminal V ds The signal at the non-inverting input of the comparator (13) The relation is kc1 is the voltage signal scaling factor.

5. The power semiconductor online junction temperature monitoring system according to claim 4, characterized in that, The trigger unit (1) further includes a first voltage divider circuit (11) and a buffer amplifier (12); the signal at the input end and the signal at the output end of the first voltage divider circuit (11) are linearly correlated; The drain-source voltage acquisition terminal of the power semiconductor (50) is electrically connected to the non-inverting input terminal of the buffer amplifier (12) through the first voltage divider circuit (11), and the inverting input terminal and output terminal of the buffer amplifier (12) are both electrically connected to the non-inverting input terminal of the comparator (13).

6. The power semiconductor online junction temperature monitoring system according to claim 4, characterized in that, The detection unit (2) includes a first monostable multivibrator (221), a second monostable multivibrator (222), a first logic AND gate (231), and a second logic AND gate (232). The rising edge-activated trigger input of the first monostable multivibrator (221) and the falling edge-activated trigger input of the second monostable multivibrator (222) are both electrically connected to the output of the gate drive circuit (51); The output of the gate drive circuit (51) is electrically connected to one end of the gate resistor, and the other end of the gate resistor is electrically connected to the gate of the power semiconductor (50). The first output terminal of the trigger unit (1) and the non-inverting output terminal of the first monostable multivibrator (221) are electrically connected to the two input terminals of the first logic AND gate (231), respectively; the second output terminal of the trigger unit (1) and the non-inverting output terminal of the second monostable multivibrator (222) are electrically connected to the two input terminals of the second logic AND gate (232), respectively. The output of the first logic AND gate (231) and the output of the second logic AND gate (232) form the first output of the detection unit (2) and the second output of the detection unit (2), respectively.

7. The power semiconductor online junction temperature monitoring system according to claim 6, characterized in that, The rising edge-activated trigger input of the first monostable multivibrator (221) and the falling edge-activated trigger input of the second monostable multivibrator (222) are electrically connected to the output of the gate drive circuit (51) through the second voltage divider circuit (21); the signals at the input and output of the second voltage divider circuit (21) are linearly correlated.

8. The power semiconductor online junction temperature monitoring system according to claim 1 or 3, characterized in that, It also includes a third voltage divider circuit (31); the signals at the input and output of the third voltage divider circuit (31) are linearly correlated. The input terminal of the third voltage divider circuit (31) is electrically connected to the gate-source voltage acquisition terminal of the power semiconductor (50), and the input terminals of the first sample-and-hold circuit (331) and the second sample-and-hold circuit (332) are both electrically connected to the output terminal of the third voltage divider circuit (31). The signal at the gate-source voltage acquisition terminal V gs The signal at the first input terminal of the signal processor (43) V in,1 The relation is V in,1 =kp1× V gs +cp1; The signal at the gate-source voltage acquisition terminal V gs The signal at the second input terminal of the signal processor (43) V in,2 The relation is V in,2 =kp2× V gs +cp2; kp1 and cp1 are the first preset proportional coefficient and the first preset constant, respectively; kp2 and cp2 are the second preset proportional coefficient and the second preset constant, respectively. Determined according to the following formula V MP,on value, V MP,off Value: V MP,on =( V in,1 -cp1) / kp1; V MP,off =( V in,2 -cp2) / kp2。 9. The power semiconductor online junction temperature monitoring system according to claim 8, characterized in that, It also includes a first signal isolator (41), an analog-to-digital converter (42), a first voltage follower (321), a second voltage follower (322), a third voltage follower (323), and a fourth voltage follower (324). The input terminal of the first sample-and-hold circuit (331) is electrically connected to the output terminal of the third voltage divider circuit (31) through the first voltage follower (321); The input terminal of the second sample-and-hold circuit (332) is electrically connected to the output terminal of the third voltage divider circuit (31) through the second voltage follower (322); The output of the first sample-and-hold circuit (331) is electrically connected to the first input of the signal processor (43) in sequence through the third voltage follower (323), the first signal isolator (41), and the analog-to-digital converter (42); The output of the second sample-and-hold circuit (332) is electrically connected to the second input of the signal processor (43) in sequence through the fourth voltage follower (324), the first signal isolator (41), and the analog-to-digital converter (42).

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