High-precision time information synchronization system
By introducing a high-precision time information synchronization system into the GNSS receiver and utilizing parallel processing of high-speed ADC and DAC, the problem of insufficient time information accuracy under high signal-to-noise ratio environments was solved, and high-precision time synchronization of 2ps was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-29
- Publication Date
- 2026-04-03
AI Technical Summary
Existing GNSS receivers lack sufficient time information accuracy in high signal-to-noise ratio environments, failing to meet the requirements of high-precision applications.
A high-precision time information synchronization system is adopted, including a reference clock module, digital logic chips (FPGA or ASIC), high-speed ADC and DAC. Through parallel processing and correlator calculation, the signal-to-noise ratio and baseband sampling rate are improved to achieve high-precision time information synchronization.
In high signal-to-noise ratio environments, the receiver output time accuracy is improved to 2ps, which is four orders of magnitude higher than that of traditional GNSS receivers.
Smart Images
Figure CN121784774A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of navigation systems, and in particular to a high-precision time information synchronization system. Background Technology
[0002] A Global Navigation Satellite System (GNSS) is a space-based radio navigation and positioning system that provides users with all-weather 3D coordinates, velocity, and time information at any location on the Earth's surface or in near-Earth space. It is a general term for satellite navigation systems that can achieve global coverage.
[0003] High-precision global positioning technology uses the high autocorrelation of pseudo-random (PRN) codes to enable the local receiver to recover accurate time information, thereby calculating the distance between the satellite and the receiver. This excellent correlation allows the receiver to recover the time relatively accurately from signals with extremely low signal-to-noise ratio and power (approximately -150 dBW) at a relatively low sampling rate (typically around 20 to 30 Msps) and a relatively low sampling bit width (2 bits to 4 bits), with an accuracy of approximately tens of nanoseconds.
[0004] This level of time precision is sufficient for some application scenarios. However, in certain specialized scenarios where extremely high-precision time information is required, it may not meet the application needs.
[0005] In the future, with the development of mobile communication and network technology, communication speeds will become increasingly higher, and the demand for the accuracy of time references will also increase.
[0006] A new way is needed to provide more accurate latency information. Summary of the Invention
[0007] The technical problem to be solved by the present invention is to overcome the defect of low accuracy of timing function in the prior art, and to provide a high-precision time information synchronization system in which the time accuracy of receiver output can be stably improved in a high signal-to-noise ratio environment.
[0008] The present invention solves the above-mentioned technical problems through the following technical solution:
[0009] A high-precision time synchronization system for a GNSS receiver is characterized in that the system includes a reference clock module, a digital logic chip, a high-speed ADC, and a high-speed DAC, wherein the digital logic chip is an FPGA or an ASIC.
[0010] The digital logic chip is used to generate pseudo-random codes based on the reference clock module;
[0011] The digital logic chip is used to convert pseudo-random codes into converted data according to the bit width of the high-speed DAC, and after parallel processing of the converted data, send continuous sampled data to the high-speed DAC.
[0012] The high-speed DAC is used to transmit sampled data;
[0013] The high-speed ADC is used to receive sampled data;
[0014] The digital logic chip is used to input the received sampled data into the FIFO module, and the data input into the FIFO module is grouped according to the sampling rate of the high-speed ADC;
[0015] The digital logic chip is used to input the grouped data of the FIFO module into the correlator. The correlator is used to input the calculated data into the synthesis accumulator. The synthesis accumulator inputs the accumulated data into the tracker to obtain tracking data. The number of correlators is the same as the number of groups.
[0016] The high-precision time information synchronization system of this application can be used in time synchronization scientific research platforms and equipment, such as satellite time synchronization functions.
[0017] Preferably, the reference clock module is connected to a digital logic chip, a high-speed ADC, and a high-speed DAC, respectively, and the digital logic chip is connected to the high-speed ADC and the high-speed DAC, respectively.
[0018] Preferably, the high-precision time information synchronization system is connected to another high-precision time information synchronization system through a transmission medium, and the high-speed ADC transmitter of one high-precision time information synchronization system is connected to the high-speed DAC receiver of the other high-precision time information synchronization system.
[0019] Preferably, the high-precision time information synchronization system is used to obtain parameters of the high-speed ADC and high-speed DAC using the thermal noise error of the GNSS receiver, wherein the formula for the thermal noise error is: ,in For bilateral front-end bandwidth, For code tracking loop noise bandwidth, For chip width, Carrier-to-noise ratio, This is the pre-detection integration time.
[0020] Preferably, for the target thermal noise error, the high-precision time information synchronization system acquires the parameters of the high-speed ADC and high-speed DAC with a sampling rate of not less than 2Gsps and a bit width of not less than 8 bits.
[0021] Preferably, the digital logic chip is used to perform 8-channel parallel processing on the converted data and then send 8 consecutive sampled data to the high-speed DAC at one time.
[0022] Preferably, the high-precision time information synchronization system includes a system state machine, and the digital logic chip is used for:
[0023] The received sampled data is input into the FIFO module in 250Msps, 8-channel parallel mode. When the system state machine receives the read signal, 16 sets of data are read out in one clock cycle. The 16 sets of data output by the FIFO are sent to 16 correlators respectively, and correlation operations are performed with their respective local codes.
[0024] Preferably, two adjacent correlators process two temporally consecutive sampling points, the local codes generated by the correlators are phase-continuous, and the local codes generated by the same correlator in the previous and next sampling points have a fixed phase difference.
[0025] Preferably, after all correlators have synchronously completed the calculation of 16 sets of sampling points, the system state machine is used to control the FIFO to stop outputting data, and the synthesis accumulator is used to add the 16 results to obtain the correlation result of a complete cycle;
[0026] The tracker is used to calculate loop parameters using the correlation results. The updated code phase and code rate are then fed back into the 16 correlators for the next round of calculation.
[0027] After the tracker captures the signal, it switches to fine tracking mode. The system calculates the time delay difference between the signal sent to the receiver based on information such as code phase and code rate, and outputs the result.
[0028] This application also provides a GNSS receiver, characterized in that the GNSS receiver includes the high-precision time information synchronization system described above.
[0029] Based on common knowledge in the field, the above-mentioned preferred conditions can be combined arbitrarily to obtain various preferred embodiments of the present invention.
[0030] The positive and progressive effects of this invention are as follows:
[0031] This application utilizes the high autocorrelation of PRN codes, enabling the receiver output time accuracy to remain stable at 2 ps in environments with high signal-to-noise ratios and high sampling rates, which is four orders of magnitude higher than the typical timing accuracy of approximately 40 ns for traditional GNSS receivers. Attached Figure Description
[0032] Figure 1 This is a schematic diagram of the high-precision time information synchronization system of Embodiment 1 of the present invention.
[0033] Figure 2 This is another structural schematic diagram of the high-precision time information synchronization system of Embodiment 1 of the present invention.
[0034] Figure 3 This is another structural schematic diagram of the high-precision time information synchronization system of Embodiment 1 of the present invention.
[0035] Figure 4 This is a schematic diagram illustrating the effect of the high-precision time information synchronization system in Embodiment 1 of the present invention. Detailed Implementation
[0036] The present invention will be further illustrated by way of embodiments below, but the present invention is not limited to the scope of the embodiments described herein.
[0037] Example 1
[0038] This embodiment provides a high-precision time information synchronization system. This system can be used as an experimental platform for receiver time information recovery, and as a time synchronization research platform and equipment, such as for satellite time synchronization function research.
[0039] The high-precision time information synchronization system includes a reference clock module, a digital logic chip, a high-speed ADC, and a high-speed DAC. The digital logic chip is an FPGA or an ASIC. In this embodiment, the digital logic chip is an FPGA.
[0040] The digital logic chip is used to generate pseudo-random codes based on the reference clock module;
[0041] The digital logic chip is used to convert pseudo-random codes into converted data according to the bit width of the high-speed DAC, and after parallel processing of the converted data, send continuous sampled data to the high-speed DAC.
[0042] The high-speed DAC is used to transmit sampled data;
[0043] The high-speed ADC is used to receive sampled data;
[0044] The digital logic chip is used to input the received sampled data into the FIFO module, and the data input into the FIFO module is grouped according to the sampling rate of the high-speed ADC;
[0045] The digital logic chip is used to input the grouped data of the FIFO module into the correlator. The correlator is used to input the calculated data into the synthesis accumulator. The synthesis accumulator inputs the accumulated data into the tracker to obtain tracking data. The number of correlators is the same as the number of groups.
[0046] Specifically, the reference clock module is connected to the digital logic chip, the high-speed ADC, and the high-speed DAC, respectively, and the digital logic chip is connected to the high-speed ADC and the high-speed DAC, respectively.
[0047] The high-precision time information synchronization system is connected to another high-precision time information synchronization system through a transmission medium. The high-speed ADC transmitter of one high-precision time information synchronization system is connected to the high-speed DAC receiver of the other high-precision time information synchronization system.
[0048] The high-precision time information synchronization system is connected to another high-precision time information synchronization system through a transmission medium that can guarantee the signal-to-noise ratio.
[0049] This embodiment provides two systems for implementing components of the transmitting end program and the receiving end program to calculate the receiver code tracking loop ranging error.
[0050] See Figure 1 System 1 and System 2 implement the transmission and reception of pseudo-random codes, as shown in the figure.
[0051] To address the limited time delay information or timing accuracy of GNSS receivers, and considering the limitations of the overall GNSS system design, it is difficult to improve timing accuracy simply by increasing signal power or improving the signal-to-noise ratio (SNR). This embodiment presents a method easily implemented in FPGAs or ASICs. Utilizing a high-precision time information transmission device and leveraging the high autocorrelation of PRN codes, the receiver can remotely achieve very high timing accuracy by improving the SNR, baseband sampling rate, and sampling bit width. Verification shows a system error of less than 2 ps.
[0052] To achieve high tracking accuracy, the main system parameters are determined based on the following equations:
[0053] The receiver's parameters should be designed based on theoretical analysis values. The main analysis is as follows:
[0054] The main source of ranging error in the receiver code tracking loop is thermal noise error. The high-precision time information synchronization system is used to obtain the parameters of the high-speed ADC and high-speed DAC using the thermal noise error of the GNSS receiver. The formula is as follows: .
[0055] in For bilateral front-end bandwidth, For code tracking loop noise bandwidth, For chip width, Carrier-to-noise ratio, This is the pre-detection integration time.
[0056] Specifically:
[0057] The value is 75dB, which represents the signal-to-noise ratio of the received laser signal.
[0058] The value is 1 / 250MHz, which means the ranging code width, and is the reciprocal of the ranging code rate. The ranging code rate is 500MHz.
[0059] The value is 2GHz, which means the corresponding AD sampling rate.
[0060] The value of D is 2, which means the number of lead and lag chips in the tracking loop.
[0061] The value is 1 / T, which means taking the reciprocal of the pre-detection integration time.
[0062] Based on the above conditions, the relationship between thermal noise error and pre-detection integration time can be obtained as follows: Figure 4 As shown.
[0063] Considering a certain noise margin, when the pre-detection integration time is ≥30ms, the thermal noise error can be less than 1ps.
[0064] Based on the above experimental results, this embodiment designs a high-precision time information synchronization system, which can realize a data processing scheme using high-speed ADC and high-speed DAC.
[0065] For the target thermal noise error value, the high-precision time information synchronization system acquires the parameters of the high-speed ADC and high-speed DAC with a sampling rate of not less than 2Gsps and a bit width of not less than 8 bits. That is, in this application, the high-speed ADC and high-speed DAC refer to ADCs and DACs with a sampling rate of not less than 2Gsps and a bit width of not less than 8 bits.
[0066] The digital logic chip is used to perform 8-channel parallel processing on the converted data and then send 8 consecutive sampled data to the high-speed DAC at one time.
[0067] The high-precision time information synchronization system includes a system state machine, and the digital logic chip is used for:
[0068] The received sampled data is input into the FIFO module in 250Msps, 8-channel parallel mode. When the system state machine receives the read signal, 16 sets of data are read out in one clock cycle. The 16 sets of data output by the FIFO are sent to 16 correlators respectively, and correlation operations are performed with their respective local codes.
[0069] Two adjacent correlators process two temporally consecutive sampling points. The local codes generated by the correlators are phase-continuous. The local code generated by the same correlator in the previous step has a fixed phase difference with the local code generated in the next step.
[0070] After all correlators have synchronously completed the calculation of 16 sets of sampling points, the system state machine is used to control the FIFO to stop outputting data, and the synthesis accumulator is used to add the 16 results to obtain the complete correlation result of one cycle.
[0071] The tracker is used to calculate loop parameters using the correlation results. The updated code phase and code rate are then fed back into the 16 correlators for the next round of calculation.
[0072] After the tracker captures the signal, it switches to fine tracking mode. The system calculates the time delay difference between the signal sent to the receiver based on information such as code phase and code rate, and outputs the result.
[0073] In this embodiment, the reference clock module needs to use a precision clock source, such as an atomic clock. The clock accuracy of the reference clock source is one of the key factors determining whether the system can achieve the expected ps or even fs level performance.
[0074] The FPGA primarily handles data processing and algorithm implementation. Speed and DSP resources must be sufficient to meet the requirements of algorithm implementation.
[0075] Both ADC and DAC require high-speed devices with a sampling rate of no less than 2Gsps and a bit width of no less than 8 bits.
[0076] The workflow of this embodiment mainly consists of two parts: the transmitting end program and the receiving end program. Both the transmitting end and the receiving end can be implemented using an FPGA.
[0077] The transmitting end (actually done by the DAC) mainly sends pseudo-random codes at fixed time intervals. Each chip lasts for the same duration.
[0078] In this embodiment, each chip is set to last for one FPGA system clock cycle.
[0079] Since the actual signal transmission is handled by the DAC, the FPGA needs to convert the pseudo-random code containing only 0s and 1s into data that conforms to the DAC's bit width. For example, if the DAC is 8-bit, 0s and 1s can be converted to 0 / 200, -100 / +100, depending on the DAC model and the voltage conversion formula.
[0080] Meanwhile, the DAC operates at frequencies above 2Gsps, and the FPGA master clock cannot run at such a high frequency. Therefore, the data interface between the FPGA and the DAC needs to be parallelized, such as 8-channel parallel processing, which sends 8 consecutive sampled data to the DAC at one time.
[0081] The receiving end primarily receives the sampled data from the high-speed ADC output in a multi-channel parallel manner, and then performs parallel tracking processing based on the code phase difference between data points. Parallel processing is employed because the sampling rate is as high as 2Gsps, which FPGAs or other devices cannot directly process in a serial manner at such a high rate. Furthermore, parallel processing allows the data to run at a lower system speed within the FPGA, significantly reducing the difficulty of algorithm implementation and lowering power consumption.
[0082] See Figure 2 , Figure 3 The specific processing method is as follows: The ADC sampling rate is set to 2GHz, and the data is first fed into a FIFO in 8 parallel channels at 250Msps. After receiving the signal from the system state machine, 16 sets of data are output per clock cycle, resulting in 16 sets of data and a total of 256 sampling points. In this way, the system can operate at a frequency of 250MHz, which is one-eighth of the ADC sampling rate, significantly reducing the implementation difficulty.
[0083] The data output from the FIFO is fed into 16 correlators, which perform correlation operations with their respective local codes. Adjacent correlators process two temporally consecutive sampling points, resulting in phase continuity between the local codes generated by the correlators. However, the local code generated by the same correlator in one sampling point has a fixed phase difference from the local code generated in the next sampling point, equal to the phase difference of the 16 sampling points.
[0084] This process essentially involves dividing a complete cycle of data into 16 equal parts and processing each part separately by 16 correlators.
[0085] Once all correlators have synchronously completed the calculation of 16 sets of sampling points, the system state machine will control the FIFO to stop outputting data. Then, the synthesis accumulator will add the 16 results together to finally obtain the correlation result for a complete cycle.
[0086] The results are then fed into the tracker to calculate the loop parameters. The updated code phase and code rate are then fed back into the 16 correlators for the next round of calculations.
[0087] Once the tracker captures a signal, it switches to fine-tracking mode. After tracking for several cycles, the parameters gradually converge. Actual on-platform testing has shown that the output eventually stabilizes within 2 ps.
[0088] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but all such changes and modifications fall within the scope of protection of the present invention.
Claims
1. A high-precision time information synchronization system, characterized in that, The high-precision time synchronization system includes a reference clock module, a digital logic chip, a high-speed ADC, and a high-speed DAC. The digital logic chip is either an FPGA or an ASIC. The digital logic chip is used to generate pseudo-random codes based on the reference clock module; The digital logic chip is used to convert pseudo-random codes into converted data according to the bit width of the high-speed DAC, and after parallel processing of the converted data, send continuous sampled data to the high-speed DAC. The high-speed DAC is used to transmit sampled data; The high-speed ADC is used to receive sampled data; The digital logic chip is used to input the received sampled data into the FIFO module, and the data input into the FIFO module is grouped according to the sampling rate of the high-speed ADC; The digital logic chip is used to input the grouped data of the FIFO module into the correlator. The correlator is used to input the calculated data into the synthesis accumulator. The synthesis accumulator inputs the accumulated data into the tracker to obtain tracking data. The number of correlators is the same as the number of groups.
2. The high-precision time information synchronization system as described in claim 1, characterized in that, The reference clock module is connected to the digital logic chip, the high-speed ADC, and the high-speed DAC, respectively. The digital logic chip is connected to the high-speed ADC and the high-speed DAC, respectively.
3. The high-precision time information synchronization system as described in claim 2, characterized in that, The high-precision time information synchronization system is connected to another high-precision time information synchronization system through a transmission medium. The high-speed ADC transmitter of one high-precision time information synchronization system is connected to the high-speed DAC receiver of the other high-precision time information synchronization system.
4. The high-precision time information synchronization system as described in claim 1, characterized in that, The high-precision time synchronization system is used to obtain parameters of the high-speed ADC and high-speed DAC by utilizing the thermal noise error of the GNSS receiver, wherein the formula for the thermal noise error is: ,in For bilateral front-end bandwidth, For code tracking loop noise bandwidth, For chip width, Carrier-to-noise ratio, This is the pre-detection integration time.
5. The high-precision time information synchronization system as described in claim 4, characterized in that, For the target thermal noise error value, the high-precision time information synchronization system acquires the parameters of the high-speed ADC and high-speed DAC with a sampling rate of not less than 2Gsps and a bit width of not less than 8 bits.
6. The high-precision time information synchronization system as described in claim 5, characterized in that, The digital logic chip is used to perform 8-channel parallel processing on the converted data and then send 8 consecutive sampled data to the high-speed DAC at one time.
7. The high-precision time information synchronization system as described in claim 6, characterized in that, The high-precision time information synchronization system includes a system state machine, and the digital logic chip is used for: The received sampled data is input into the FIFO module in 250Msps, 8-channel parallel mode. When the system state machine receives the read signal, 16 sets of data are read out in one clock cycle. The 16 sets of data output by the FIFO are sent to 16 correlators respectively, and correlation operations are performed with their respective local codes.
8. The high-precision time information synchronization system as described in claim 7, characterized in that, Two adjacent correlators process two temporally consecutive sampling points. The local codes generated by the correlators are phase-continuous, and there is a fixed phase difference between the local codes generated by the same correlator in the previous and next sampling periods.
9. The high-precision time information synchronization system as described in claim 7, characterized in that, After all correlators have synchronously completed the calculation of 16 sets of sampling points, the system state machine is used to control the FIFO to stop outputting data, and the synthesis accumulator is used to add the 16 results to obtain the complete correlation result of one cycle. The tracker is used to calculate loop parameters using the correlation results. The updated code phase and code rate are then fed back into the 16 correlators for the next round of calculation. After the tracker captures the signal, it switches to fine tracking mode. The system calculates the time delay difference between the signal and the receiver based on information such as code phase and code rate, and outputs the result.
10. A GNSS receiver, characterized in that, The GNSS receiver includes a high-precision time information synchronization system as described in any one of claims 1 to 9.