Copackage-based apparatus and system and method for copackage

Abstract

A co-packaging-based apparatus and system and a method for co-packaging are provided. The apparatus may include a substrate having a first attachment location within which a first photonic integrated circuit may be mounted and a second attachment location within which a bridge may be mounted. The first computing device may be mounted on the substrate and at least partially above the first attachment location and the second attachment location.

Description

Technical Field

[0001] The subject matter disclosed herein relates to packaging. More specifically, the subject matter disclosed herein relates to techniques for making electrical connections between electronic integrated circuits (EICs) and photonic integrated circuits (PICs). Background Technology

[0002] Semiconductor devices can be connected to additional devices and circuit systems on different substrates. Forming connections between substrates can provide increased computing power. However, forming connections between substrates can present challenges. Packaging describes a general approach for connecting and integrating multiple computing components together in an integrated cell, and can involve multiple different types of integrated circuits on multiple substrates that can be combined into a single cell. Packaging can also describe a method for protecting multiple computing components within a single cell by using various techniques for providing thermal, physical, and electrical protection. It should also be noted that the background art concepts discussed herein are for informational purposes only and are not intended to limit this disclosure. Neither the background art nor the fields described herein should be intended to limit the disclosure herein to any particular purpose or concept. Summary of the Invention

[0003] A co-packaged device disclosed herein may include a substrate having a first attachment location and a second attachment location, a first photonic integrated circuit (PIC) may be mounted within the first attachment location, and a bridge may be mounted within the second attachment location. A first computing device may be mounted on the substrate and at least partially above the first and second attachment locations. In some embodiments, a second computing device may be mounted on the substrate at least partially above the second attachment location, and the second computing device may be electrically connected to the first computing device via the bridge. In some embodiments, the first computing device may include at least one of a memory device and a processing device. In some embodiments, a redistribution layer may be present between the first photonic integrated circuit and the first computing device, and an optical fiber connection may extend between the surface of the substrate and the first photonic integrated circuit. In some embodiments, the substrate may include glass or silicon. In some embodiments, the first photonic integrated circuit may include a plug-in connector for a bidirectional optical fiber capable of transmitting an incoming optical signal to the first photonic integrated circuit and transmitting an outgoing optical signal from the first photonic integrated circuit. In some embodiments, a fluid cooling channel may be formed within the substrate, and a thermal via may be formed between the first attachment location and the surface of the substrate. In some embodiments, the thermal via may thermally couple the first photonic integrated circuit to the fluid cooling channel. In some embodiments, the bridge is a second photonic integrated circuit.

[0004] A co-package-based system disclosed herein may include: a substrate having a first side and a second side opposite to the first side. The first side may have a first attachment location and a second attachment location. A photonic integrated circuit may be at least partially located within the first attachment location, and a bridge may be at least partially located within the second attachment location. A first computing device may be mounted on the first side of the substrate. A first thermal via may be located within the substrate and may extend from the second side to the first attachment location. In some embodiments, a second computing device may be mounted on the first side of the substrate and may be coupled to the first computing device via a bridge at least partially located within the second attachment location. In some embodiments, an attachment film may be located between the thermal via and the photonic integrated circuit. In some embodiments, a second thermal via within the substrate may extend from the second side to the second attachment location, and an attachment film may be located between the second thermal via and the bridge. In some embodiments, a fluid cooling channel may be located within the substrate and thermally coupled to the first thermal via. In some embodiments, a redistribution layer may be located between the photonic integrated circuit and the first computing device; and an optical fiber connection may extend between a surface of the first side of the substrate and a surface of the photonic integrated circuit parallel to the first side. In some embodiments, the first computing device may be at least partially mounted above the first attachment location and the second attachment location.

[0005] A method for co-packaging may include: fabricating a substrate; forming a first attachment site and a second attachment site within a first side of the substrate; mounting a photonic integrated circuit (IC) at least partially within the first attachment site; mounting a bridge at least partially within the second attachment site; forming a redistribution layer on the first side of the substrate; and forming an opening region in the redistribution layer above the photonic IC. In some embodiments, a first computing device may be mounted on the redistribution layer and electrically connected to the photonic IC and the bridge. In some embodiments, a second computing device may be mounted on the redistribution layer and electrically connected to the first computing device via the bridge. In some embodiments, an optical fiber may be connected to the photonic IC via the opening region in the redistribution layer. In some embodiments, the step of fabricating the substrate may include forming at least one of forming a thermal via, forming a fluid cooling channel, and forming a through-substrate via. In some embodiments, the optical fiber may be connected to a surface of the photonic IC parallel to the first side of the substrate. In some embodiments, the first computing device may include a first device and a second device, which may include a processing device and a memory device. In some embodiments, the step of forming the first attachment site and the second attachment site within the first side of the substrate may include laser milling the glass substrate. Attached Figure Description

[0006] In the following sections, aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the accompanying drawings.

[0007] Figure 1Cross-sectional views are depicted of example embodiments of hybrid electronic integrated circuits and photonic integrated circuit systems according to various embodiments of the subject matter disclosed herein.

[0008] Figure 2 A plan view depicting an example embodiment of a hybrid electronic integrated circuit and photonic integrated circuit system according to various embodiments of the subject matter disclosed herein.

[0009] Figure 3 Cross-sectional views are depicted of example embodiments of hybrid electronic integrated circuits and photonic integrated circuit systems according to various embodiments of the subject matter disclosed herein.

[0010] Figure 4 Cross-sectional views are depicted of example embodiments of hybrid electronic integrated circuits and photonic integrated circuit systems according to various embodiments of the subject matter disclosed herein.

[0011] Figure 5A A first-time cross-sectional view of an example embodiment of a hybrid electronic integrated circuit and photonic integrated circuit system according to various embodiments of the subject matter disclosed herein is depicted.

[0012] Figure 5B An example embodiment of a hybrid electronic integrated circuit and photonic integrated circuit system according to various embodiments of the subject matter disclosed herein is depicted in a cross-sectional view at a second time.

[0013] Figure 5C A cross-sectional view at a third time depicts an example embodiment of a hybrid electronic integrated circuit and photonic integrated circuit system according to various embodiments of the subject matter disclosed herein.

[0014] Figure 5D A cross-sectional view at a fourth time is depicted of an example embodiment of a hybrid electronic integrated circuit and photonic integrated circuit system according to various embodiments of the subject matter disclosed herein.

[0015] Figure 5E A cross-sectional view at a fifth time is depicted of an example embodiment of a hybrid electronic integrated circuit and photonic integrated circuit system according to various embodiments of the subject matter disclosed herein.

[0016] Figure 5F A cross-sectional view at a sixth time is depicted of an example embodiment of a hybrid electronic integrated circuit and photonic integrated circuit system according to various embodiments of the subject matter disclosed herein.

[0017] Figure 5G A cross-sectional view at the seventh time depicts an example embodiment of a hybrid electronic integrated circuit and photonic integrated circuit system according to various embodiments of the subject matter disclosed herein.

[0018] Figure 5HAn example embodiment of a hybrid electronic integrated circuit and photonic integrated circuit system according to various embodiments of the subject matter disclosed herein is depicted in a cross-sectional view at an eighth time.

[0019] Figure 6 Example embodiments of methods based on various embodiments of the subject matter disclosed herein are described.

[0020] Figure 7 Cross-sectional views are depicted of example embodiments of hybrid electronic integrated circuits and photonic integrated circuit systems according to various embodiments of the subject matter disclosed herein.

[0021] Figure 8 Cross-sectional views are depicted of example embodiments of hybrid electronic integrated circuits and photonic integrated circuit systems according to various embodiments of the subject matter disclosed herein. Detailed Implementation

[0022] In the following detailed description, numerous specific details are set forth to provide a thorough understanding of this disclosure. However, those skilled in the art will understand that aspects of the disclosure may be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits have not been described in detail so as not to obscure the subject matter of this disclosure.

[0023] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment," "in an embodiment," or "according to an embodiment" (or other phrases with similar meanings) appearing in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not to be construed as necessarily preferred or advantageous over other embodiments. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Additionally, depending on the context of the discussion herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional", "pre-determined", etc.) may occasionally be used interchangeably with their corresponding non-hyphenated versions (e.g., "two-dimensional", "pre-determined", etc.), and uppercase entries (e.g., "integrated chip", "first substrate", "PIC", etc.) may be used interchangeably with their corresponding non-uppercase versions (e.g., "integrated chip", "first substrate", "pic", etc.). Such occasional interchangeability should not be considered inconsistent with each other.

[0024] Furthermore, depending on the context of the discussion herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It should also be noted that the various figures shown and discussed herein (including component diagrams) are for illustrative purposes only and are not drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Additionally, reference numerals are repeated throughout the figures to indicate corresponding and / or similar elements, where deemed appropriate.

[0025] The terminology used herein is for the purpose of describing some exemplary embodiments only and is not intended to be limiting of the claimed subject matter. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” indicate the presence of the stated features, integers (in whole), steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers (in whole), steps, operations, elements, components, and / or groups thereof.

[0026] It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to," or "bonded to" another element or layer, it may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be intermediate elements or layers present. In contrast, when an element is referred to as being "directly on" another element or layer, "directly connected to," or "directly bonded to" another element or layer, there are no intermediate elements or layers present. The same reference numerals always denote the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] As used herein, the terms “first,” “second,” etc., serve as labels for nouns that follow them and do not imply any kind of order (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Furthermore, the same reference numerals may be used across two or more figures to denote parts, components, blocks, circuits, units, or modules having the same or similar functions. However, such use is solely for simplification and ease of discussion; it does not imply that the construction or architectural details of such components or units are identical across all embodiments, or that such commonly referenced parts / modules are the only way to implement some of the exemplary embodiments disclosed herein.

[0028] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject pertains. It will also be understood that terms (such as those defined in general dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless clearly defined herein.

[0029] Various devices, structures, and methods for forming optical interconnects between devices comprising both electronic integrated circuits (EICs) and photonic integrated circuits (PICs) are disclosed herein. In some embodiments, a hybrid transceiver may use a combination of EICs and PICs to transmit and receive optical signals between devices. In some embodiments, a first hybrid transceiver may use an optical interconnect to communicate bidirectionally with a second hybrid transceiver.

[0030] As used herein, EIC refers to a wide variety of integrated circuits using electrical components. In some embodiments, an EIC may include a combination of various electrical components, such as transistors, resistors, inductors, and capacitors, which are combined on a substrate to form an electronic circuit. In some embodiments, an EIC may include a central processing unit (CPU), logic chips, memories (such as static random access memory (SRAM), dynamic random access memory (DRAM)), application processors (APs), graphics processing units (GPUs), artificial intelligence (AI) chips, high-bandwidth memory (HBM) interfaces, and other application-specific integrated circuits (ASICs). In some embodiments, the combination of circuits may exist on a substrate. In some embodiments, an EIC may be referred to using terms such as microchip, microcontroller, or silicon chip.

[0031] As used herein, PIC refers to a wide variety of integrated circuits that utilize photonic components. In some embodiments, a PIC may include a combination of various photonic components, such as waveguides, filters, gratings, lenses, mirrors, and optical ring resonators. In some embodiments, a PIC may include electrical components, such as photodiodes, light-emitting diodes, and laser diodes. In some embodiments, a PIC may be referred to using terms such as integrated optical circuits and planar optical wave circuits.

[0032] As used herein, the substrate may be composed of one or more of various materials and structures, including wafers using silicon, wafers using silicon-on-insulator (SOI) (such as glass), wafers using other semiconductor materials (such as germanium), and wafers using other semiconductor materials on insulators. In some embodiments, the substrate may include organic materials. In some embodiments, the substrate may be referred to individually or in combination as a wafer, die, and chip. In some embodiments, the substrate used in a PIC may be referred to as a waveguide. Thus, in some embodiments, bonding (attaching) the substrates together may be referred to as die-to-die (D2D) bonding, wafer-to-wafer (W2W) bonding, or die-to-wafer (D2W) bonding. In some embodiments, the packaged chip may comprise multiple substrates and may include a PIC substrate, an EIC substrate, or a combination of PIC and EIC substrates. In some embodiments, circuits may be bonded directly facing each other, while in other embodiments, flip-chip bonding may be used. In some embodiments, interconnections may be made between substrates on the front side or circuit side of the substrate. In other embodiments, interconnections may be made on the rear or back side of the substrate opposite to the circuit structure. In some embodiments, interconnects may include through-silicon vias (or through-silicon vias, TSVs) or other forms of through-chip vias, in which case one or more substrates may be connected using vias that travel through an intermediary (such as another substrate or chip). In some embodiments, interconnects may be formed using connections (such as pads) on the surface of the substrate, and additional materials (such as solder) may be used between the pads to form the interconnects.

[0033] In some embodiments, bonding between substrates may involve bonding between metals (or metal-to-metal bonding). In some embodiments, bonding between substrates may involve bonding between dielectric materials (or dielectric-to-dielectric bonding). In some embodiments, bonding between substrates may involve both metal-to-metal bonding and dielectric-to-dielectric bonding (referred to as hybrid bonding). Hybrid bonding techniques can be used to provide additional connections between opposing surfaces, thereby allowing both dielectric and conductive surfaces to bond, and increasing the mechanical strength of the resulting structure. As used herein, hybrid bonding can be defined as bonding conductive parts to conductive parts (such as metal-to-metal bonding) and bonding dielectric parts to dielectric parts (such as dielectric-to-dielectric bonding).

[0034] As used herein, multiplexing can refer to various techniques used for multiplexing optical signals. In some embodiments, multiplexing can refer to wavelength division multiplexing (WDM). In some embodiments, multiplexing can refer to polarization-based multiplexing. In some embodiments, multiplexing can refer to fiber mode-based polarization. In some embodiments, multiplexing can be a combination of one or more of WDM, polarization, and fiber mode polarization.

[0035] As used herein, polarization can refer to both linear polarization and circular polarization. Linear polarization modes can be referred to as S-polarization and P-polarization, or transverse magnetic (TM) polarization and transverse electric (TE) polarization. Circular polarization can be referred to as right-handed polarization (RCP) or left-handed polarization (LCP).

[0036] As used herein, conductor can refer to various conductive materials, including those that can be used alone or in combination with other materials (such as in the form of alloys). In some embodiments, the conductor is copper (Cu). In some embodiments, copper (Cu) can be in the form of Cu(II), Cu(III), or other forms of copper, alone or in combination with additional elements, including cobalt (Co) and ruthenium (Ru) . This enumeration of elements is not intended to be exhaustive, and in other embodiments, any other known types of conductive materials may be used.

[0037] As used herein, a device stack or a stack of devices can represent a combination of memory and supporting circuitry architectures (e.g., chiplets and dies containing individual memory elements, supporting processing units, input / output (I / O) circuitry systems, and other forms of integrated chips). As used herein, a chiplet can represent an integrated circuit (such as a microprocessor, memory device, etc.) with well-defined functions or other computational capabilities; chiplets allow for modular designs that enable multiple chiplets to share a substrate or intermediary in combination with larger packages to form a larger device. A core can represent a single unit in a multi-core device, in which multiple devices form a larger device, each capable of operating independently to allow multiple operational flows. In some embodiments, a core may take the form of a chiplet, or a chiplet may take the form of a core. However, in other embodiments, a chiplet may take the form of any other suitable integrated circuit.

[0038] As used herein, a bridge (bridging element) refers to a substrate, die, or other material having one or more conductive paths capable of forming a connection between one or more semiconductor devices and a substrate, interposer, or other package structure. A bridge may include one or more conductive traces that form a connection path along the bridge between one or more devices to which the bridge is attached. An embedded bridge, as used herein, may refer to a bridge within a layer of a semiconductor package and may be used interchangeably with bridge. An active bridge may refer to a bridge characterized by additional features beyond the connection (such as transistors, vias, and other circuit components).

[0039] As used herein, attachment location refers to a position where a die, substrate, computing device, interposer, or other device can be attached to a substrate. In some embodiments, attachment location may take the form of a cavity, recess, hole, opening, depression, pit, orifice pocket, hollow, space, slot, gap, or a combination thereof. As used herein, attachment location may be used interchangeably with cavity. In some embodiments, attachment location may take the form of a surface mount (attachment) constructed on a flat surface of the substrate, a surface structure constructed on the substrate, or a combination having a cavity.

[0040] Various embodiments of systems, methods, and apparatuses using co-packaged EICs and PICs on a substrate are disclosed herein. For example, various embodiments of systems, methods, and apparatuses for co-packaged optics architectures are disclosed herein. In various embodiments, the substrate may be a glass core substrate, a silicon substrate, or a substrate formed of any other suitable semiconductor material. In the various embodiments disclosed herein, the PIC may be at least partially embedded within a cavity of the substrate. In some embodiments, the EIC may also be at least partially embedded within a cavity of the substrate. In some embodiments, a process such as milling may create a cavity within the substrate for mounting at least one EIC and PIC. A redistribution layer may be at least partially mounted on the EIC or PIC at least partially embedded within the cavity of the substrate. The redistribution layer may support and be coupled to one or more additional devices (such as memory devices, processing devices, ASICs, and stacks including combinations such as HBM). Fiber optic attachment units (FAUs) may be directly connected to the PIC at least partially embedded within the cavity of the substrate via openings in the redistribution layer. Signals may be received by the FAU and transmitted to the PIC at least partially embedded within the cavity of the substrate before being transmitted via the redistribution layer to one or more additional devices.

[0041] In some embodiments, the substrate may have thermal features (such as vias, heat sinks, and fluid cooling channels). In some embodiments, the thermal features provide heat transfer for PICs, EICs, and any additional devices mounted to the substrate. In some embodiments, the thermal features may be formed on the substrate prior to forming a cavity for placing the EIC or PIC. In some embodiments, one or more through-vias may be formed on the substrate prior to forming a cavity for placing the EIC or PIC. In some embodiments, the one or more through-vias may be through-glass vias (TGVs) in a glass substrate, through-silicon vias (TSVs) in a silicon substrate, or any other suitable vias in any other substrate.

[0042] Figure 1 Exemplary embodiments of an architecture for forming a device packaging architecture 100 on a substrate 101 are disclosed. For example, Figure 1 A co-packaged device or system is disclosed. In some embodiments, substrate 101 includes one or more devices (also referred to herein as "computing devices") mounted thereon. Figure 1 In an exemplary embodiment, the first device 102 and the second device 104 are mounted on a substrate 101. In some embodiments, the substrate 101 may include a glass substrate, a glass core substrate, a silicon substrate, or another suitable substrate. In some embodiments, the means of the first device 102 and the second device 104 may be various forms of means (such as memory (including DRAM, SRAM, and other forms of memory); processors (including CPUs, XPUs, GPUs); and additional suitable circuitry (including ASICs)) or combinations thereof. In some embodiments, the first device 102 and the second device 104 may each include a stack of one or more component means. In some embodiments, the stack of component means may include one or more memory means, core means, and combinations thereof. In some embodiments, the core means may include, for example, a processor, a processing means, or other form of microcontroller to function as a controller. Although Figure 1 The exemplary embodiments depict only the first device 102 and the second device 104, but the device packaging architecture 100 may include additional devices (e.g., as described below for...). Figure 2 (Discussed).

[0043] The substrate 101 may be mounted with the first device 102 and the second device 104 in various ways and may include, individually or in combination, pads, bumps, microbumps, pillars, balls, ball grids, microsphere arrays, and other forms (such as controlled-collapse chip connection (C4) bumps). As used herein, a C4 bump refers to the form of a solder bump placed on a pad on the top surface of the substrate prior to flipping the substrate for the purpose of forming a flip chip. The mounting method may also include a dielectric material, which may include materials capable of forming connections other than conductive connections (such as adhesives, resins, or elastomers). In some embodiments, a combination of conductive and dielectric connections may form a hybrid bonding.

[0044] In some embodiments, substrate 101 may also include one or more integrated circuits embedded within the surface of substrate 101. Figure 1In an exemplary embodiment, a first PIC 110 is embedded within a cavity formed on the surface of a substrate 101. In some embodiments, the first PIC 110 may be mounted on an attachment film 109 located between the first PIC 110 and the substrate 101. In some embodiments, the attachment film 109 may be formed of an adhesive material (such as resin or epoxy), a metal layer, a dielectric material, or any other suitable material to form one or more layers, thereby allowing the first PIC 110 or the embedded bridge 108 to be mounted on the substrate 101. In some embodiments, the embedded bridge 108 may be embedded within the surface of the substrate 101, and in some embodiments, the attachment film 109 between the embedded bridge 108 and the substrate 101 may be included. In some embodiments, the embedded bridge 108 may be a PIC, while in other embodiments, the embedded bridge 108 may be an EIC, a die, a passive bridge, or some other suitable element used alone or in combination to form a connection between two circuits. In some embodiments, the first device 102 may be at least partially located above a first attachment location (e.g., a cavity in which the first PIC 110 is disposed) and a second attachment location (e.g., a cavity in which the embedded bridge 108 is disposed). In some embodiments, the second device 104 may be at least partially located above the second attachment location (e.g., a cavity in which the embedded bridge 108 is disposed). In some embodiments, the second device 104 may be electrically connected to the first device 102 via the embedded bridge 108.

[0045] In some embodiments, a first optical connection 106 may be connected to a first PIC 110. In some embodiments, the first optical connection 106 may extend between a surface of substrate 101 and the first PIC 110 (e.g., between a surface on the front side of substrate 101 and a surface of the first PIC 110 parallel to the front side of substrate 101). In some embodiments, the first optical connection 106 may be an optical fiber, an optical connector, a FAU, a pluggable optical connector, a plug-in connector, a V-groove, and combinations thereof and various arrays thereof. In some embodiments, the optical fiber may be unidirectional, allowing only transmission or reception, while in other embodiments, the optical fiber may be bidirectional. In some embodiments, the first PIC 110 may include a plug-in connector configured to receive bidirectional optical fibers. In some embodiments, additional optical elements (such as polarizers, gratings, antireflective coatings, filters, refractive index matching coatings, lenses, and any other suitable optical components) may be placed individually or in combination between the first optical connection 106 and the first PIC 110. In some embodiments, the first optical connection 106 may allow the device packaging architecture 100 to transmit optical signals, receive optical signals, or both receive and transmit optical signals. In some embodiments, the first optical connection 106 may include multiple optical connections (including a receiving optical connection for receiving incoming signals and a transmitting optical connection for transmitting outgoing signals). In some embodiments, the multiple optical connections may include one or more discrete optical connections corresponding to one or more multiplexing methods (e.g., wavelength-based multiplexing, fiber-mode-based multiplexing, polarization-based multiplexing, and combinations thereof). In some embodiments, the first optical connection 106 may provide optical coupling for optical signals to one or more additional systems (including additional computing systems, networks, remote computers, and any other suitable optical devices).

[0046] In some embodiments, a first redistribution layer (RDL) 112 may be formed on the back side of substrate 101, while a second RDL 116 may be formed on the front side of substrate 101. As used herein, the surface of substrate 101 in which the first PIC 110 is embedded is referred to as the front side, and the surface of substrate 101 opposite to the front side is referred to as the back side. In some embodiments, one or more through-vias (or through-substrate vias) 114 may extend from the back side to the front side through substrate 101. One or more through-vias 114 may combine the first RDL 112 to the second RDL 116 and provide routing for electrical and data signals between the first RDL 112 and the second RDL 116.

[0047] The first RDL 112 can provide for redistributing electrical signals from connections on the back side of substrate 101 to one or more layers (including a series of pads, bumps, vias, through-vias, traces, and other forms of connectivity) of one or more through-vias 114. The second RDL 116 can, in turn, provide for redistributing signals from connections on the front side of substrate 101 to one or more layers (including a series of pads, bumps, vias, through-vias, traces, and other forms of connectivity) of one or more through-vias 114, the first PIC 110, the embedded bridge 108, the first device 102, and the second device 104.

[0048] exist Figure 1 In an exemplary embodiment, the first device 102 and the second device 104 may be mounted on the second RDL 116 using one or more conductive connections 118 and one or more dielectric bonds 120. The one or more conductive connections 118 may individually or in combination include pads, bumps, microbumps, pillars, balls, ball grids, microsphere arrays, and other forms (such as C4 bumps). The one or more dielectric bonds 120 may include a dielectric material or adhesive (such as epoxy, resin, or other suitable material) between the first device 102 and the second RDL 116. In some embodiments, the one or more dielectric bonds 120 may be formed using an underfill technique and disposed between the first device 102 and the second RDL 116 and around the one or more conductive connections 118. In some embodiments, the one or more conductive connections 118 and the one or more dielectric bonds 120 may be combined to form a hybrid bond between the first device 102 and the substrate 101.

[0049] In some embodiments, substrate 101 may have substrate interconnects 122 formed on a first RDL 112. The substrate interconnects 122 electrically connect substrate 101 to a support substrate 130 (such as an interposer, an additional substrate, a card, a plate, or combinations thereof). In some embodiments, substrate interconnects 122 may include conductive connections, dielectric connections, or hybrid connections. In some embodiments, conductive connections may individually or in combination include pads, bumps, microbumps, pillars, balls, ball grids, microsphere arrays, and other forms (such as C4 bumps). In some embodiments, dielectric connections may individually or in combination include dielectric materials (such as silica, resins, adhesives, and epoxy resins). In some embodiments, the dielectric material may be in the form of an underfill and introduced between substrate 101 and support substrate 130 in conjunction with conductive connections, and may form hybrid connections between substrate 101 and support substrate 130 in conjunction with conductive connections.

[0050] In some embodiments, the first device 102 may provide driving electronics for the first PIC 110, and the first device 102 may provide heater control circuitry, a heater driver, a modulator driver, and a serializer to modify optical signals within the first PIC 110. For example, if the first PIC 110 includes one or more microring resonators, the heater may be integrated with one or more microring resonators to provide control over the resonant frequencies of one or more microring resonators by changing the physical characteristics of the one or more microring resonators. While portions of the heater may be formed within the first PIC 110, the electronics for controlling and regulating the heater are located in the first device 102, separate from the first PIC 110. Furthermore, the first PIC 110 may include one or more photodetectors to receive optical signals that may be transmitted to the first device 102 for further signal processing (including amplification, analog-to-digital conversion, rectification, or any other suitable signal processing techniques). In some embodiments, such as for Figure 4 Further discussion suggests that some or all of the drive electronics used in the first PIC 110 may be transferred from the first device 102 to another device (such as the second device 104), either alone or in combination with an additional driver EIC.

[0051] Figure 2 A plan view of a device packaging architecture 100 according to an exemplary embodiment is depicted. Figure 2 Provided with Figure 1 The plan view of the component corresponding to the first row 230. Figure 1 Show along Figure 2 The cross-sectional view of the dashed line A-A'. Figure 2 An exemplary embodiment provides elements of a second row 240 formed parallel to the first row 230. Additional elements of the second row 240 may be formed as discussed above with respect to the elements of the first row 230. Although Figure 2 The exemplary embodiment depicts only the first row 230 and the second row 240, but in some embodiments, additional rows (e.g., the third row, the fourth row, etc.) may be inserted.

[0052] In some embodiments, a second optical connection 206 may provide an optical connection to a second PIC 210. In some embodiments, the second optical connection 206 may be an optical connector, optical fiber, FAU, pluggable optical connector, plug-in connector, V-groove, and combinations thereof and various arrays thereof. In some embodiments, additional optical elements (such as polarizers, gratings, anti-reflective coatings, filters, refractive index matching coatings, lenses, and any other suitable optical components) may be placed individually or in combination between the second optical connection 206 and the second PIC 210. In some embodiments, the second optical connection 206 may allow the device packaging architecture 100 to transmit optical signals, receive optical signals, or both receive and transmit optical signals. In some embodiments, the second optical connection 206 may include multiple optical connections (including a receiving optical connection for receiving incoming signals and a transmitting optical connection for transmitting outgoing signals). In some embodiments, the multiple optical connections may include one or more separate optical connections corresponding to one or more multiplexing methods (e.g., wavelength-based multiplexing, fiber-mode-based multiplexing, polarization-based multiplexing, and combinations thereof). In some embodiments, the second optical connection 206 can provide optical coupling for optical signals to one or more additional systems, including additional computing systems, networks, remote computers, and any other suitable optical devices. In some embodiments, the first optical connection 106 and the second optical connection 206 can be independent of each other, while in some embodiments, the first optical connection 106 and the second optical connection 206 can enable one to act as a transmitter and the other as a receiver. In some embodiments, the first optical connection 106 and the second optical connection 206 can be optically coupled and can be combined directly or via one or more intermediate devices, systems, or networks.

[0053] In some embodiments, the second PIC 210 may be connected directly or via the second embedded bridge 208 to the third device 202 and the fourth device 204. The second PIC 210, the third device 202, the fourth device 204, and the second embedded bridge 208 may take the same form as the first PIC 110, the first device 102, the second device 104, and the embedded bridge 108 discussed above. In some embodiments, the interrow bridge 220 may connect the first row 230 and the second row 240, and provide signal and power wiring between the first row 230 and the second row 240. In some embodiments, the interrow bridge 220 may be a PIC, while in other embodiments, the interrow bridge 220 may be an EIC, die, passive bridge, or some other suitable element, used alone or in combination, to form a connection between two circuits. In some embodiments, one or more additional interrow bridges may be used to connect between rows when adding elements to one or more additional rows, while in other embodiments, a single interrow bridge may be used. In some embodiments, the interrow bridge 220 may be one or more bridges embedded within the substrate 101 and may be formed in series or parallel between rows of elements.

[0054] Figure 3 An illustrative embodiment of the second device packaging architecture 300 is depicted. For example, Figure 3 A device or system based on co-packaging is described. Figure 3 The second device packaging architecture 300 and Figure 1 The device packaging architecture 100 differs in that it includes one or more additional thermal features embedded within the substrate 101. In some embodiments, the additional thermal features may include one or more thermal vias 302, one or more fluid cooling channels 304, and combinations thereof.

[0055] In some embodiments, one or more thermal vias 302 may be formed in the back side of the substrate 101 and extend from a cavity containing the first PIC 110 or embedded bridge 108. In some embodiments, the thermal via 302 may be one or more through-holes (such as TSV or TGV) depending on the material of the substrate 101. In some embodiments, one or more thermal vias 302 may include a thermally conductive material (such as a metal (e.g., copper, silver, or aluminum) within the through-hole and additional materials suitable for use with semiconductor processes (such as aluminum nitride, silicon carbide, or any other suitable thermally conductive material (e.g., diamond)) and combinations thereof. In some embodiments, one or more thermal vias 302 may be incorporated into additional structures for regulating heat (such as thermoelectric devices, heat sinks, cooling pads, or other suitable structures). Furthermore, in some embodiments, one or more thermal vias 302 may be incorporated into one or more fluid cooling channels 304 (e.g., thermal coupling). In some embodiments, one or more thermal vias 302 may contact the first PIC 110 or the embedded bridge 108, while in other embodiments, the attachment membrane 109 may be between one or more thermal vias 302 and the first PIC 110 or the embedded bridge 108.

[0056] In some embodiments, substrate 101 may include one or more fluid cooling channels 304. In some embodiments, the one or more fluid cooling channels 304 may include channels formed within substrate 101 for fluid passage. In some embodiments, the fluid used within the one or more fluid cooling channels 304 may be a gas (such as air, nitrogen, argon, or other gases suitable for use within a semiconductor substrate). In some embodiments, the fluid used within the one or more fluid cooling channels 304 may be a liquid (such as water, aqueous solutions, alcohols, glycols, and combinations thereof). In some embodiments, the one or more fluid cooling channels 304 may be formed directly in substrate 101, while in other embodiments, the one or more fluid cooling channels 304 may include one or more layers between substrate 101 and the fluid within the one or more fluid cooling channels 304. In some embodiments, the one or more layers may include a material such as a metal, ceramic, or other material for providing a thermally conductive path between the fluid and substrate 101. In some embodiments, the one or more layers may include materials for providing encapsulation and protection against corrosion or other damage from the fluid.

[0057] In some embodiments, one or more thermal vias 302 may conduct heat into the fluid of one or more fluid cooling channels 304, and the heat may be transferred away from the one or more thermal vias 302 using convective heat transfer, conductive heat transfer, or a combination thereof. In some embodiments, mechanical devices (such as pumps or fans) or any other suitable fluid transport method may be used to actively deliver fluid to drive its flow, while in other embodiments, the fluid path may be shaped to allow passive flow of fluid, or any other mechanism for passive transport may be used (e.g., using fluids undergoing a phase change). In some embodiments, one or more fluid cooling channels 304 may be part of a closed-loop cooling system, while in other embodiments, one or more fluid cooling channels 304 may be part of an open-loop system, and in still other embodiments, one or more fluid cooling channels 304 may transfer between an open-loop system and a closed-loop system. In some embodiments, radiators, heat exchangers, expanders, compressors, cooling pads, thermal coolers, or any other suitable form of cooling, and combinations thereof, may be incorporated into one or more fluid cooling channels 304 to provide cooling to the fluid of one or more fluid cooling channels 304. In some embodiments, heat transferred via one or more fluid cooling channels 304 may be transferred to another fluid or conducted to another surface. In some embodiments, the heat dissipation structure may be used to provide cooling using a combination of radiative heat transfer, conductive heat transfer, and convective heat transfer. In some embodiments, a single fluid cooling channel in one or more fluid cooling channels 304 may provide cooling for all components embedded within the substrate 101, while in other embodiments, each component may have a separate fluid cooling channel in one or more fluid cooling channels 304. In some embodiments, such as Figure 2 One of the second device packaging architectures 300 shown includes an embodiment with an additional row of components, and one or more fluid cooling channels 304 may allow one of the fluid cooling channels 304 to be integrated into all components embedded within the substrate 101, while in other embodiments, each component embedded within the substrate 101 may have a separate fluid cooling channel among one or more fluid cooling channels 304 to provide relief.

[0058] Figure 4 An exemplary embodiment of a third device packaging architecture 400 is depicted. For example, Figure 4 A device or system based on co-package is described. The third device packaging architecture 400 and... Figure 3 The second device packaging architecture 300 and Figure 1The difference in the device packaging architecture 100 is that a surface PIC 410 mounted on the surface of substrate 101 is used instead of a first PIC 110 embedded within substrate 101. In some embodiments, the surface PIC 410 may be mounted on a second RDL 116, and a driver EIC 412 may be mounted on the surface PIC 410. The surface PIC 410 provides the optical components required to receive or transmit signals via the first optical connection 106. In some embodiments, the driver EIC 412 provides drive electronics (including heater control circuitry, heater driver, modulator driver, and serializer) for driving the surface PIC 410 to modify the optical signals within the surface PIC 410. For example, if the surface PIC 410 includes one or more microring resonators, the heater may be integrated with one or more microring resonators to provide control over the resonant frequencies of one or more microring resonators by changing the physical characteristics of the one or more microring resonators. While portions of the heater may be formed within the surface PIC 410, the electronics for controlling and regulating the heater are located within a first device 102 separate from the surface PIC 410. Furthermore, the surface PIC 410 may include one or more photodetectors to receive optical signals, which may be sent to the driver EIC 412 for further signal processing (including amplification, analog-to-digital conversion, rectification, or any other suitable signal processing techniques). In some embodiments, some or all of the driving electronics for the surface PIC 410 may be transferred from the driver EIC 412 to another device (such as the first device 102), either individually or in combination with the driver EIC 412. In some embodiments, the driver EIC 412 may be connected to a second RDL 116 via one or more vias 414 through the surface PIC 410. In some embodiments, a 3D stack of the surface PIC 410 and the driver EIC 412 may be formed prior to mounting the surface PIC 410 onto the substrate 101. In some embodiments, the surface PIC 410 and the driver EIC 412 may be mounted in a flip-chip configuration, with the driver EIC 412 in contact with the substrate 101 and the surface PIC 410 mounted on the driver EIC 412; in other embodiments, different configurations may be used. The driver EIC 412 can be mounted to the surface PIC 410, alone or in combination, using conductive connections, including pads, bumps, microbumps, pillars, balls, ball grids, microsphere arrays, and other forms (such as C4 bumps). In some embodiments, a dielectric connection may be included between the driver EIC 412 and the surface PIC 410, and may take the form of an underfill, adhesive, resin, epoxy, or other dielectric material.The surface PIC 410 may be mounted to the substrate 101, alone or in combination, using conductive connections, including pads, bumps, microbumps, pillars, balls, ball grids, microsphere arrays, and other forms (such as C4 bumps). In some embodiments, a dielectric connection may be included between the surface PIC 410 and the substrate 101, and may take the form of an underfill, adhesive, resin, epoxy, or other dielectric material.

[0059] Figures 5A to 5H Illustrative embodiments of the process for forming a device package architecture (such as device package architecture 100 or any other device package architecture shown herein) are described. For example, Figures 5A to 5H An illustrative embodiment of a method for co-packaging is described. Figure 6 Depicting and Figures 5A to 5H The illustrative embodiments correspond to example embodiments of process 600 for forming a device package assembly. For example, Figure 6 Depicting and Figures 5A to 5H The illustrative embodiments correspond to example embodiments of the method for co-encapsulation.

[0060] Figure 5A It describes, in Figure 6 In step S610, substrate 101 is prepared. Substrate 101 may be formed of glass or semiconductor (such as silicon) or combinations thereof. In some embodiments, substrate 101 may have one or more through-holes 114 formed within substrate 101, the one or more through-holes 114 extending between a first side and a second side of substrate 101. In some embodiments, drilling, laser milling, etching, or any other suitable process and combinations thereof may be used to form one or more through-holes 114. In some embodiments, one or more through-holes 114 may include a conductive material (such as a metal plug) formed within one or more through-holes 114, and may include materials such as copper, aluminum, titanium, tungsten, and combinations thereof. In some embodiments, the conductive material may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electrowetting, electroplating, or any other suitable technique. In some embodiments, one or more materials may be deposited to form a liner layer prior to bulk deposition (volume deposition), while in other embodiments, conductors may be deposited directly on substrate 101.

[0061] In some embodiments, during S610, one or more thermal vias 302, one or more fluid cooling channels 304, or combinations thereof may be formed in the substrate 101. In some embodiments, one or more thermal vias 302, one or more fluid cooling channels 304, or combinations thereof may be formed by first forming one or more openings within the substrate 101, which may be formed using drilling, laser milling, etching, or any other suitable process and combination thereof. In some embodiments, one or more thermal vias 302, one or more fluid cooling channels 304, or combinations thereof may subsequently be partially or completely filled using a thermally conductive material, such as one or more layers of metal, carbide, or nitride. In some embodiments, one or more fluid cooling channels 304 may be partially formed within the substrate 101 and may include one or more portions formed on the substrate 101. For example, an open channel may be formed within the substrate 101, and a cap may be mounted on the substrate 101 to cover the open channel. In other embodiments, any suitable technique may be used to form one or more fluid cooling channels 304 within the substrate 101. In some embodiments, one or more thermal vias 302 may be formed within the substrate 101 to a specific depth for engagement with an embedded device, while in other embodiments, the depth may be greater or less. In some embodiments, one or more thermal vias 302 and one or more fluid cooling channels 304 may be formed within the same layer of the substrate 101. In other embodiments, one or more fluid cooling channels 304 may be formed above or below one or more thermal vias 302.

[0062] Figure 5B It describes, in Figure 6 In step S620, one or more cavities 402 are formed in the substrate 101. In some embodiments, various techniques (such as laser milling, drilling, etching, or any other suitable process) may be used individually or in combination to form one or more cavities 402. In some embodiments, one or more cavities 402 may be formed to a depth intersecting with one or more thermal vias 302, while in other embodiments, the depth may be greater or less. In some embodiments, one or more cavities 402 may be formed to a uniform depth, while in other embodiments, one or more cavities 402 may vary in depth within each cavity, between cavities, or within and between cavities. In some embodiments, one or more cavities 402 may be formed to a depth such that a first PIC 110 or an embedded bridge 108 can be mounted in a corresponding cavity such that the surface of the first PIC 110 or the embedded bridge 108 is coplanar with the surface of the substrate 101, while in other embodiments, the surface of the first PIC 110 or the surface of the embedded bridge 108 may be above or below the corresponding surface of the substrate 101.

[0063] Figure 5C It describes, in Figure 6 In step S630, an attachment film 109 is deposited within one or more cavities 402. In some embodiments, the attachment film 109 may be formed of an adhesive material (such as resin or epoxy), a metal layer, a dielectric material, and any other suitable material to form one or more layers, thereby allowing the first PIC 110 or embedded bridge 108 to attach to the substrate 101. In some embodiments, the attachment film 109 may be formed using processes such as CVD, PVD, ALD, or any other suitable process. In some embodiments, the attachment film 109 may be the same material in each of the one or more cavities 402, while in other embodiments, the material of the attachment film 109 may vary between the one or more cavities 402. In some embodiments, the attachment film 109 may be formed to a consistent depth in each of the one or more cavities 402, while in some embodiments, the depth may vary within each of the one or more cavities 402, or the depth may vary between the various cavities 402.

[0064] Figure 5D It describes, in Figure 6 In step S640, a first PIC 110 and an embedded bridge 108 are mounted on an attachment film 109 within one or more cavities 402. In some embodiments, the first PIC 110 and the embedded bridge 108 may be mounted such that the surface of the first PIC 110 or the embedded bridge 108 is coplanar with the surface of the substrate 101, while in other embodiments, the surface of the first PIC 110 or the surface of the embedded bridge 108 may be above or below the corresponding surface of the substrate 101. In some embodiments, the embedded bridge 108 may include a second PIC, while in other embodiments, the embedded bridge may be formed using a semiconductor substrate (such as a silicon die). In some embodiments, the first PIC 110 or the embedded bridge 108 may cause the attachment film 109 to form a bond between the first PIC 110 or the embedded bridge 108 and the substrate 101. In some embodiments, further processing may be performed on the substrate 101 to bond the first PIC 110 or the embedded bridge 108 to the substrate 101, and may include using thermal or radiative energy to form the bond (such as by curing epoxy or resin within the attachment film 109).

[0065] Figure 5E It describes, in Figure 6In step S650, a first RDL 112 and a second RDL 116 are formed on the substrate 101. The first RDL 112 and the second RDL 116 may include one or more layers (including a series of pads, bumps, vias, through-vias, traces, and other forms of connectivity) for signal redistribution. In some embodiments, the first RDL 112 and the second RDL 116 may be formed directly on the surface of the substrate 101, while in some embodiments, one or more build-up layers may be formed to create a planar (flat) surface on which the first RDL 112 and the second RDL 116 may be formed. In some embodiments, the build-up layers may include one or more materials (including molding compounds, resins, epoxy resins, dielectric materials, and other materials suitable for use with the substrate 101). In some embodiments, the second RDL 116 may be formed over one or more cavities 402 and may be incorporated into the first PIC 110 and the embedded bridge 108. In some embodiments, the first RDL 112 and the second RDL 116 may be formed using various techniques for forming and patterning conductive layers, including depositing one or more materials using PVD, CVD, ALD, or other suitable techniques. Techniques such as photolithography, etching, polishing, milling, and ablation may be used to selectively remove portions of the material to further pattern it, while in other embodiments, techniques such as using a photoresist mask may be used to selectively deposit the material. In some embodiments, the material may include conductive materials (such as metals) and dielectric materials (such as nitrides and oxides). In some embodiments, the first RDL 112 and the second RDL 116 may be formed in parallel, while in other embodiments, the first RDL 112 and the second RDL 116 may be formed sequentially, or in a combination of parallel and sequential steps.

[0066] Figure 5F It describes, in Figure 6In step S660, an open space (or opening region) 404 may be formed in the second RDL 116 above the first PIC 110. In some embodiments, the open space 404 may be formed using methods such as photolithography, etching, milling, or any other suitable method to remove a portion of the material in the second RDL 116. In some embodiments, the open space 404 may be formed during the formation of the second RDL 116 in step S650, while in other embodiments, the open space 404 may be formed after the formation of the second RDL 116. In some embodiments, the open space 404 may expose the top surface of the first PIC 110, while in other embodiments, the open space 404 may expose the side or bottom surface of the first PIC 110. In some embodiments, the open space 404 may be formed to expose one or more additional optical elements (e.g., thin optical films, filters, or waveguides incorporated into the first PIC 110) embedded in the substrate 101.

[0067] Furthermore, in S660, a substrate interconnect 122 may be formed on the first RDL 112. In some embodiments, the substrate interconnect 122 may include conductive interconnects, dielectric interconnects, or hybrid interconnects. In some embodiments, conductive interconnects may include pads, bumps, microbumps, pillars, balls, ball grids, microsphere arrays, and other forms (such as C4 bumps), individually or in combination. In some embodiments, dielectric interconnects may include dielectric materials (such as silicon dioxide, resins, adhesives, and epoxy resins), individually or in combination. In some embodiments, the dielectric material may be in the form of an underfill and introduced between the substrate 101 and the support substrate 130 in conjunction with the conductive interconnects, and a hybrid connection may be formed between the substrate 101 and the support substrate 130. In some embodiments, the substrate interconnect 122 may electrically connect the substrate 101 to the support substrate 130 (such as an intermediary, an additional substrate, a card, a plate, or some combination thereof). In some embodiments, the substrate interconnect 122 may be fully formed in S660 to mount the substrate 101 on the support substrate 130, while in other embodiments, the substrate interconnect 122 may be only partially formed in S660 (e.g., forming a conductive ball grid array suitable for later mounting the substrate 101 on the support substrate 130).

[0068] Figure 5G It describes, in Figure 6In step S670, the first device 102 and the second device 104 can be mounted on the substrate 101 (on the second RDL 116). In some embodiments, the first device 102 and the second device 104 can be mounted on the second RDL 116 using one or more conductive connections 118 and one or more dielectric bonds 120. The one or more conductive connections 118 may individually or in combination include pads, bumps, microbumps, pillars, balls, ball grids, microsphere arrays, and other forms (such as C4 bumps). The one or more dielectric bonds 120 may include a dielectric material or adhesive (such as epoxy, resin, or other suitable material) between the first device 102 and the second RDL 116. In some embodiments, the one or more dielectric bonds 120 may be formed using an underfill technique and interposed between the first device 102 and the second RDL 116 and around the one or more conductive connections 118. In some embodiments, the one or more conductive connections 118 and the one or more dielectric bonds 120 may be combined to form a hybrid bond between the first device 102 and the substrate 101.

[0069] Figure 5H It describes, in Figure 6 In S680, the first optical connection 106 is coupled to the first PIC 110 using the open space 404 within the second RDL 116. In some embodiments, the first optical connection 106 may take the form of an optical connector, FAU, pluggable optical connector, plug-in connector, V-groove, and combinations thereof and various arrays thereof. In some embodiments, additional optical elements (such as polarizers, gratings, anti-reflective coatings, filters, refractive index matching coatings, lenses, and any other suitable optical components) may be placed individually or in combination between the first optical connection 106 and the first PIC 110. In some embodiments, the first optical connection 106 may be permanently attached to the first PIC 110, while in other embodiments, the first optical connection 106 may be removably attached to the first PIC 110.

[0070] Figure 7 An exemplary embodiment of a fourth device packaging architecture 700 is depicted. For example, Figure 7 A device or system based on co-package is described. The fourth device packaging architecture 700 and... Figure 1 Device packaging architecture 100 and Figure 3The second device packaging architecture 300 differs in that it features an embedded PIC 710 mounted on an embedded EIC 712. The embedded PIC 710 can be connected to the first optical connection 106 via an opening region in the second RDL 116. In some embodiments, the embedded EIC 712 can be mounted on an attachment film 109 and thermally coupled to one or more thermal vias 302 and one or more fluid cooling channels 304. In some embodiments, the embedded PIC 710 can be mounted on the embedded EIC 712 using one or more embedded interconnects 714. In some embodiments, the one or more embedded interconnects 714 can include conductive interconnects, dielectric interconnects, or hybrid interconnects. In some embodiments, conductive interconnects can individually or in combination include pads, bumps, microbumps, pillars, balls, ball grids, microsphere arrays, and other forms (such as C4 bumps). In some embodiments, dielectric interconnects can individually or in combination include dielectric materials (such as silica, resins, adhesives, and epoxy resins). In some embodiments, the dielectric material may be in the form of an underfill and introduced between the embedded EIC 712 and the embedded PIC 710 in conjunction with conductive interconnects, and a hybrid connection may be formed between the embedded EIC 712 and the embedded PIC 710. In some embodiments, the placement of the embedded EIC 712 may reduce the distance signals travel between the embedded EIC 712 and the embedded PIC 710, and thus improve efficiency and latency. In some embodiments, one or more trans-PIC vias 716 may extend through the embedded PIC 710, and an electrical connection may be formed between the embedded EIC 712 and the second RDL 116. In some embodiments, the embedded EIC 712 may use additional bonding methods (such as routing around the embedded PIC 710, or routing using vias to connect to a first RDL 112 that is subsequently routed to the second RDL 116).

[0071] Figure 8 An exemplary embodiment of a fifth device packaging architecture 800 is depicted. For example, Figure 8 A device or system based on co-package is described. The fifth device packaging architecture 800 and... Figure 1 Device packaging architecture 100 and Figure 3The second device packaging architecture 300 differs in that it is characterized by a first device stack 802 and a second device stack 804 replacing the first device 102 and the second device 104. In some embodiments, the first device stack 802 and the second device stack 804 may each include a stack of one or more component devices. In some embodiments, the stack of component devices may include memory devices, core devices, and combinations thereof. In some embodiments, the device may include a core device (e.g., a processor, processing device, or other form of microcontroller) serving as a controller. In some embodiments, the first device stack 802 and the second device stack 804 may include HBM and may include one or more memory devices stacked on top of each other and on top of a base die providing the core processor. In some embodiments, one or more trans-stack vias may connect the devices within the device stack together. Although Figure 8 The exemplary embodiments depict only the first device stack 802 and the second device stack 804, but the device packaging architecture may include additional devices (e.g., as described above for...). Figure 2 (Discussed).

[0072] While this specification may contain numerous details of specific implementation, these details should not be construed as limiting the scope of any claimed subject matter, but rather as descriptions of features specific to particular embodiments. Some features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in some combination, or even initially claimed in this way, one or more features from a claimed combination may be removed from that combination in some cases, and the claimed combination may involve sub-combinations or variations thereof.

[0073] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring the operations to be performed in the specific order shown or in a sequential order, or requiring all of the operations shown, in order to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0074] Therefore, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the actions set forth in the claims can be performed in a different order and still achieve the desired result. Furthermore, the processes (techniques) depicted in the drawings do not necessarily require the specific order or sequence shown to achieve the desired result. In some embodiments, multitasking and parallel processing can be advantageous.

[0075] As those skilled in the art will recognize, the innovative concepts described herein can be modified and varied across a wide range of applications. Therefore, the scope of the claimed subject matter should not be limited to any of the specific exemplary teachings discussed above, but rather is instead defined by the appended claims.

Claims

1. A device based on co-packaging, comprising: The substrate has a first attachment position and a second attachment position; The first photonic integrated circuit is installed in the first attachment position; The bridge is installed in the second attachment position; as well as A first computing device is mounted on a substrate and is at least partially above a first attachment position and a second attachment position.

2. The apparatus according to claim 1, further comprising: A second computing device is mounted on the substrate and at least partially above the second attachment location, wherein the second computing device is connected to the first computing device via a bridge circuit.

3. The apparatus according to claim 1, wherein, The first computing device includes at least one selected from the group consisting of a memory device and a processing device.

4. The apparatus according to claim 1, wherein, The redistribution layer is disposed between the first photonic integrated circuit and the first computing device, wherein an optical fiber is connected between the surface of the substrate and the first photonic integrated circuit.

5. The apparatus according to claim 1, wherein, The substrate includes at least one selected from the group consisting of glass and silicon.

6. The apparatus according to claim 1, wherein, The first photonic integrated circuit includes a plug-in connector configured to receive bidirectional optical fibers. The bidirectional optical fiber is configured to transmit the incoming optical signal to the first photonic integrated circuit, and The bidirectional optical fiber is configured to transmit outgoing optical signals from the first photonic integrated circuit.

7. The apparatus according to claim 1, further comprising: Fluid cooling channels are formed within the substrate; as well as A thermal via is formed between the first attachment location and the surface of the substrate. Among them, the thermal via thermally couples the first photonic integrated circuit to the fluid cooling channel.

8. The apparatus according to claim 1, wherein, The bridge is a second photonic integrated circuit.

9. A system based on co-packaging, comprising: The base has a first side and a second side opposite to the first side, the first side having a first attachment position and a second attachment position; Photonic integrated circuit, at least partially within the first attachment location; The bridge, at least partially within the second attachment location; A first computing device is mounted on a first side of the base; as well as A first thermal via is located within the substrate and extends from the second side to the first attachment location.

10. The system according to claim 9, further comprising: The second computing device is mounted on the first side of the base. The second computing device is connected to the first computing device via a bridge.

11. The system according to claim 9, further comprising: An attachment film is placed between the first thermal via and the photonic integrated circuit.

12. The system according to claim 9, further comprising: A second thermal via, within the substrate, wherein the second thermal via extends from a second side to a second attachment location; and An attachment membrane is placed between the second thermal via and the bridge.

13. The system according to claim 9, further comprising: A fluid cooling channel is located within the substrate and is thermally coupled to a first thermal via.

14. The system according to claim 9, further comprising: A redistribution layer is arranged between the photonic integrated circuit and the first computing device; as well as The optical fiber connection extends between the surface of the first side of the substrate and the surface of the photonic integrated circuit that is parallel to the first side.

15. The system according to claim 9, wherein, The first computing device is at least partially mounted above the first attachment position and the second attachment position.

16. A method for co-packaging, comprising: Preparation of substrate; A first attachment position and a second attachment position are formed on the first side of the substrate; The photonic integrated circuit is at least partially mounted in the first attachment location; The bridge shall be installed at least partially within the second attachment location; A redistribution layer is formed on the first side of the substrate; An opening region is formed in the redistribution layer above the photonic integrated circuit; A first computing device is mounted on the redistribution layer, and the first computing device is electrically connected to a photonic integrated circuit and a bridge. The second computing device is mounted on the redistribution layer and is connected to the first computing device via a bridge circuit. as well as Optical fibers are connected to photonic integrated circuits via openings in the redistribution layer.

17. The method according to claim 16, wherein, The steps for preparing the substrate include forming at least one of forming thermal vias, forming fluid cooling channels, and forming through-substrate vias.

18. The method according to claim 16, wherein, The optical fiber is connected to the surface of the photonic integrated circuit that is parallel to the first side of the substrate.

19. The method of claim 16, wherein, The first computing device includes at least one first device and at least one second device, wherein the first device and the second device each include at least one of a processing device and a memory device.

20. The method of claim 16, wherein, The steps of forming a first attachment position and a second attachment position within a first side of the substrate include laser milling the glass substrate.

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