Dark current elimination circuit of photoelectric chip

Abstract

The invention discloses a dark current elimination circuit of a photoelectric chip, and belongs to the technical field of photoelectric detectors and analog integrated circuits. The circuit comprises a capacitance voltage-dividing network (4), a self-adaptive bias module (5) and a differential amplification module (6), the capacitance voltage-dividing network (4) filters a direct current component corresponding to a dark current in the light current by utilizing the direct current blocking and alternating current passing characteristics of a capacitor; the self-adaptive bias module (5) comprises a bias lifting module and a reference bias module, a source follower structure is adopted to be matched with a bias current source, a stable quiescent working point is provided for the processed alternating current signal, a potential is lifted, and a reference bias matched with the lifting potential is generated through a symmetrical structure; and the differential amplification module (6) carries out differential operation on the signal after bias lifting and reference bias, inhibits a common-mode direct-current component and only amplifies an alternating-current signal. The invention has the advantages of obvious dark current elimination effect, high signal integrity, stable quiescent working point, simple structure and low cost, and can be widely applied to electronic equipment containing photoelectric chips, such as photoelectric sensors, photoelectric detection modules and the like.

Description

Technical Field

[0001] This invention relates to the field of photodetectors and analog integrated circuit technology, specifically to a method for eliminating the influence of dark current in photodiodes on signal detection in photodetector chips or modules. Background Technology

[0002] The photoelectric chip is the core component of a photoelectric detection system. Its internal photodiode (PD) converts light signals into electrical signals, achieving precise light-to-electrical signal conversion. However, in practical operation, even in the absence of light, the PD generates a weak leakage current, or dark current, due to factors such as the thermal motion of charge carriers. Under illumination, this dark current is superimposed on the current signal excited by the light signal, forming an approximately DC offset component. When detecting weak photoelectric signals, the dark current becomes a significant interference source, causing an approximately constant offset drift in the PD's output electrical signal. In traditional photoelectric detection front-end circuits, the transimpedance amplifier (TIA) converts the PD's photocurrent into voltage. The dark current is transmitted to the TIA along with the effective photocurrent for conversion. During subsequent amplification, the presence of the dark current severely encroaches on the dynamic range of the subsequent circuits, easily causing the amplifying devices to enter the saturation region, resulting in distortion of the effective light signal, severely reducing the accuracy and sensitivity of photoelectric detection, and making it impossible to effectively extract weak AC light signals.

[0003] Existing dark current elimination techniques can be mainly divided into three categories: The first category uses avalanche photodiodes (APDs) or PIN-PDs with extremely low dark current, but these are expensive; the second category uses digital calibration algorithms to eliminate dark current, which requires a digital-to-analog converter for sampling and processing, resulting in high circuit complexity and susceptibility to noise interference; the third category uses a single-capacitor DC blocking circuit to block dark current. Although this solution is inexpensive, the alternating light signal after DC blocking has no static operating point, and direct input to the amplifier circuit is prone to cutoff distortion. Furthermore, the signal amplitude cannot be pre-adjusted, resulting in limited dark current suppression.

[0004] Therefore, existing technologies suffer from severe signal distortion, incomplete dark current elimination, and difficulty in balancing cost and performance. There is an urgent need for a simple, low-cost, effective dark current elimination circuit for optoelectronic chips that can ensure signal integrity. Summary of the Invention

[0005] The purpose of this invention is to overcome the problems of high cost, unstable static operating point, and large residual dark current in existing dark current elimination schemes for optoelectronic chips, and to provide a dark current elimination circuit for optoelectronic chips that achieves complete elimination of dark current and stable amplification of alternating light signals.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A dark current elimination circuit for an optoelectronic chip mainly includes a capacitor voltage divider network (4), an adaptive bias module (5), and a differential proportional amplifier module (6). The front-end transimpedance amplifier (2) first converts the current signal generated by the PD photodiode (1) into a voltage signal and sends it to the capacitor voltage divider network (4) to block the DC component corresponding to the dark current in the photocurrent. The adaptive bias module (5) provides a static operating point for the processed AC signal and realizes potential rise. The symmetrical gate-grounded PMOS transistor (13) can generate a matching reference bias voltage. The differential amplifier module (6) completes the differential proportional operation and suppresses the common-mode DC component. The input terminal of the capacitor voltage divider network (4) is connected to a voltage signal with dark current influence. Utilizing the DC blocking and AC passing characteristics of the capacitor, only the alternating voltage signal excited by the optical signal is transmitted. The amplitude of the alternating signal is pre-adjusted by adjusting the voltage divider ratio. The output terminal is connected to the input terminal of the adaptive bias module. The adaptive bias module (5) adopts a PMOS source follower structure (12) to achieve voltage boosting. The bias current source (14) generated by the external bias voltage VBP provides a stable bias point for the PMOS transistor, ensuring that the PMOS transistor works in the saturation region, thereby boosting the AC signal potential output by the capacitor voltage divider by a fixed gate voltage Vgs1. At the same time, the PMOS device M2 (13) with a symmetrical structure is self-biased, matching the parameters in the PMOS source follower structure (12). Its gate is grounded, and an external bias current source with the same parameters connected to the source follower (12) is connected to output a reference bias voltage Vgs2 with the same potential amplitude as the PMOS bias boosting module, i.e., Vgs1 = Vgs2; The differential proportional amplifier module (6) is used to perform differential operation on the AC signal after the source follower (12) voltage is boosted and the reference bias voltage output by the symmetrical PMOS reference module, which effectively suppresses the common-mode DC component, only proportionally amplifies the alternating voltage signal, and finally outputs a stable voltage signal without dark level interference.

[0007] Preferably, the selection of coupling capacitors C1 (1) and C2 (2) in the capacitor voltage divider network (4) must meet two conditions: First, low-frequency conduction condition: C1 ≥ 1 / (2πf_min × Z_eq), C2 ≥ 1 / (2πf_min × Z_eq), where f_min is the lowest operating frequency of the AC signal to be processed, and Z_eq is the equivalent impedance of the capacitor voltage divider DC blocking module Z_eq = 1 / (2πf_min × (C1 / / C2)), ensuring that the AC signal in the frequency band of the signal to be processed has no significant attenuation; Second, voltage division ratio adjustment condition: capacitor voltage division ratio k = C2 / (C1 + C2), the capacitance ratio of C1 and C2 can be flexibly adjusted according to the amplitude of the AC signal to be processed and the subsequent amplification requirements.

[0008] Preferably, the adaptive bias boosting module in the circuit structure is a "source follower + external constant current bias" structure. It utilizes the high input impedance characteristics of the source follower to avoid the loading effect on the AC coupling network. At the same time, together with the symmetrical reference structure, it provides a stable and matched DC operating point for the subsequent differential amplifier, reducing the additional offset risk introduced by the single-ended to differential process.

[0009] Preferably, the circuit structure is an open-loop feedforward structure, which does not require complex feedback loop design, clock signal or digital calibration logic, and has the advantages of low power consumption, high stability and easy integration.

[0010] Preferably, the differential amplifier structure included in the circuit structure itself has a suppressive effect on the interference common to both input terminals, such as power supply noise and temperature drift at the bias point, which further improves the purity of the output signal.

[0011] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: Compared with the traditional single-capacitor DC blocking scheme, it can not only completely eliminate dark current interference, but also achieve pre-adjustment of alternating signal amplitude by adjusting the voltage division ratio, reducing the amplification pressure of subsequent amplification circuits, reducing signal distortion, and reducing the risk of residual dark current caused by leakage current of a single capacitor; Through the bias boosting design of "PMOS source follower + external bias current source", a stable static operating point is provided for the processed AC signal, avoiding the cutoff distortion of amplification devices caused by no bias signal; The overall circuit is constructed with conventional discrete components, without the need for digital processing units, high-frequency clocks or complex feedback control loops, with simple structure and low cost, and the temperature stability and power supply anti-interference capability are improved through parameter matching design, making it suitable for medium and high frequency signal scenarios and with a wide range of applications. Attached Figure Description

[0012] Figure 1 This is an overall block diagram of the circuit structure of an embodiment of the present invention. The block diagram mainly consists of a front-end photodetector transimpedance amplifier TIA (2) and a dark current elimination circuit (3), wherein the dark current elimination circuit consists of a capacitor voltage divider network (4), an adaptive bias module (5), and a differential amplifier module (6).

[0013] Figure 2This is a specific implementation circuit of the present invention based on CMOS technology. The capacitor voltage divider network (4) is composed of coupling capacitor C1 (7) and coupling capacitor C2 (8) connected in series. The input signal Vin after being processed by TIA (2) is applied to one end of C1 (7), and the other end of C2 (8) is grounded. The common connection point of the two capacitors is connected to the PMOS source follower structure (12) of the external bias current source, and together with the symmetrical PMOS self-biased transistor M2 (13), it is connected to the differential amplifier module (6). The differential amplifier module (6) is composed of operational amplifier U1 (20), input resistors R1 (16), R2 (17), R3 (18), feedback resistor Rf (19), and bias voltage Vref (21). Detailed Implementation

[0014] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0015] The present invention provides a dark current elimination circuit for an optoelectronic chip, comprising a capacitor voltage divider network (4), an adaptive bias module (5), and a differential proportional amplifier module (6). The specific composition and parameter design points of each module are as follows: The capacitor voltage divider network (4) is composed of coupling capacitors C1 (7) and C2 (8). Its function is to prevent any DC component of the input signal Vin from entering the subsequent circuit, and only allow the AC signal to pass through. The capacitor voltage division ratio k = C1 / (C1 + C2). One end of C1 (7) is used as the input terminal of the signal to be processed, and is connected to the mixed voltage signal Vin containing the DC component Vin_dark corresponding to the dark current and the AC signal Vin_ac. The series node of C1 (7) and C2 (8) is used as the output terminal and is connected to the input terminal of the PMOS bias boosting module. The other end of C2 (8) is grounded. The equivalent impedance Z_eq = 1 / (2πf_min × (C1 / / C2)) is calculated according to the lowest frequency fmin of the signal to be processed. The capacitance values ​​of C1 (7) and C2 (8) must both satisfy C ≥ The requirement of 1 / (2πf_min × Z_eq) ensures that the required alternating signal passes smoothly without significant attenuation, and the DC component corresponding to the dark current is completely blocked. The source follower (12) in the adaptive bias module (5) uses PMOS transistor M1 (11) as a buffer. Its gate receives the AC signal processed by the coupling capacitor, and its source is the output. At this time, the source output signal of M1 (11) is the superposition of the AC signal after capacitor voltage division and |Vgs1|. The constant current source Ibias1 provides a stable static operating current for M1. The reference module of the symmetrical PMOS consists of the second PMOS transistor M2 (13) and the bias current source Ibias2 (15). M2 (13) is selected with the same model as M1 (11) and its bias conditions and channel width-to-length ratio (W / L) are consistent with M1 (11), and the threshold voltage deviation does not exceed 2%. The gate of M2 (13) is directly grounded and is consistent with the static potential of the gate of M1 (12). The source of M2 (13) is used as the output terminal and is matched with the DC component in the output signal of the source of M1 (11) and sent to the input terminal of the differential proportional amplifier module.The differential amplifier (6) consists of an operational amplifier U1 (20), a feedback resistor Rf (19), and input resistors R1 (16), R2 (17), and R3 (18). The common-mode rejection ratio (CMRR) of the operational amplifier U1 (20) is ≥ 120dB. It has high input impedance and low noise, making it suitable for amplifying weak signals. R1 (16), R2 (17), R3 (18), and Rf (19) are all high-precision metal resistors with a resistance deviation of no more than 0.5%. The non-inverting input of U1 (20) is connected to the source of M2 (13) through R2 (17) and connected to the reference voltage Vref (21) through an external resistor R3 (18). The inverting input is connected to the PMOS source output with the gate grounded through R1 (16). The inverting input of U1 (20) is also connected to its own output through Rf (19). The output of the operational amplifier U1 (20) serves as the output of the entire circuit, and the output signal Vout = (Rf / R1) * Vin +Vref; that is, only the AC signal is amplified, completely eliminating the DC component Vin_dark brought by the original dark current.

[0016] In summary, this invention, through its ingenious circuit architecture, completely eliminates dark current, ensuring the integrity of the alternating optical signal while guaranteeing the accuracy of signal gain and the robustness of the circuit.

[0017] The above description is merely an implementation of the technical solution of the present invention, and is not intended to limit the patent scope of this application. Any equivalent structural or procedural exchanges made using the content of the specification and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A dark current elimination circuit for an optoelectronic chip, characterized in that, The circuit structure includes: a transimpedance amplifier (2) for converting the photocurrent signal generated by the PD photodiode (1) into a voltage signal, which contains a DC offset component caused by dark current; a capacitor voltage divider network (4) whose input is connected to the output of the PD photodiode (1) of the optoelectronic chip, to filter out the DC offset component in the voltage signal and output an alternating voltage signal; an adaptive bias module (5) whose input is connected to the output of the capacitor voltage divider network, and adopts a PMOS source follower structure (12) with an external bias current source to provide a stable static operating point for the AC signal after DC blocking and to raise the fixed potential, while generating a reference bias that matches the raised potential through a symmetrical PMOS structure (13) with the gate grounded, to provide a DC operating point bias for the signal after the DC component is filtered out and to generate a reference voltage; and a differential amplifier module (6) whose two inputs are respectively connected to the two outputs of the adaptive bias module, to amplify the difference between the two input voltages proportionally.

2. The circuit structure according to claim 1, characterized in that, The capacitor voltage divider network (4) includes C1 (7) and C2 (8) connected in series. The common connection point of the two capacitors is the output signal node after capacitor voltage division, which is used to output the AC signal after filtering out the DC component.

3. The circuit structure according to claim 1, characterized in that, The adaptive bias boosting module includes a first PMOS transistor M1 (11) and a first constant current source Ibias1 (14); the gate of the first PMOS transistor M1 (11) is connected to the output terminal of the capacitor voltage divider network, and its source serves as the output terminal of the source follower buffer stage, and is connected to the power supply through the first constant current source Ibias1 (14).

4. The circuit structure according to claim 1, characterized in that, The adaptive bias module (5) further includes a second PMOS transistor M2 (13) and a second constant current source Ibias2 (15); the second PMOS transistor M2 (13) and the first PMOS transistor M1 (11) are a matched pair, with their gates grounded or fixed bias voltages, and their sources outputting the adaptive reference voltage, which is connected to the power supply through the second constant current source Ibias2 (15); the second constant current source Ibias2 (15) and the first constant current source Ibias1 (14) are matched current sources.

5. The circuit structure according to claim 1, characterized in that, The differential amplifier module (6) includes an operational amplifier U1 (20), a feedback resistor Rf (19), and input resistors R1 (16), R2 (17), and R3 (18). The non-inverting input terminal of the operational amplifier U1 (20) is connected to the output terminal of the first source follower (12) through the input resistor R1 (16), and the inverting input terminal is connected to the output terminal of the gate-grounded self-biased PMOS transistor M2 (13) through the input resistor R2 (17). The inverting input terminal of the operational amplifier U1 (20) is connected to the output terminal through the feedback resistor Rf (19), and the non-inverting terminal is connected to the common-mode voltage Vref (21) through R3 (18).

6. The circuit structure according to claim 5, characterized in that, The input resistors R1(16) and R2(17), Rf(19) and R3(18) have equal resistance values ​​and the deviation does not exceed 1%; the output signal of the differential amplifier module is Vout = Vref + (Rf / R1) * Vin.

7. The dark current elimination circuit according to any one of claims 1 to 6, characterized in that, The circuit described is used in a photoelectric detection front-end amplifier and can be integrated into a photoelectric sensing chip or module.

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