Semiconductor processing event analysis method and system

Abstract

The invention discloses a semiconductor processing event analysis method and system, and relates to the technical field of event analysis methods, and the method comprises the steps: determining a semiconductor processing sequence according to the node positions of a plurality of semiconductor processing nodes and a preset semiconductor processing demand; according to the semiconductor processing sequence, the semiconductor processing task corresponding to each semiconductor processing node and the node state, the corresponding processing context information is predicted, and the accuracy of the processing context information is improved. Therefore, the corresponding semiconductor processing executor is matched based on the semiconductor processing event, and the execution condition of the sub-processing events is determined according to the semiconductor processing executor, each sub-processing event and the node state corresponding to each semiconductor processing node. And the analysis result of the semiconductor processing event is determined based on the execution conditions of the plurality of sub-processing events, the corresponding execution priorities and the processing progress of the semiconductor processing event, so that the accuracy of the analysis result of the semiconductor processing event is improved.

Description

Technical Field

[0001] This invention relates to the technical field of event analysis methods, and more particularly to a method and system for analyzing semiconductor processing events. Background Technology

[0002] With the development of technology, semiconductor processing equipment has been gradually applied to the industrial field to process semiconductors and form corresponding semiconductor processing events. In the existing technology, semiconductor processing events are collected and corresponding semiconductor processing nodes are determined based on the identification of semiconductor processing events. However, the overall consideration of the semiconductor processing tasks and node states corresponding to each semiconductor processing node is ignored, which affects the accuracy of processing context information and leads to low accuracy of semiconductor processing event analysis results. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a method and system for analyzing semiconductor processing events.

[0004] This invention provides a method for analyzing semiconductor processing events, including: Step S1: Collect semiconductor processing events and determine the corresponding semiconductor processing statements based on the analysis of the semiconductor processing events; Step S2: Determine the corresponding directed acyclic graph based on the semiconductor processing statement and the corresponding semiconductor processing planner; determine multiple semiconductor processing nodes based on the identification of the directed acyclic graph, and match each semiconductor processing node with the corresponding semiconductor processing task; Step S3: Determine the semiconductor processing sequence based on the node positions of multiple semiconductor processing nodes and the preset semiconductor processing requirements; predict the corresponding processing context information based on the semiconductor processing sequence, the semiconductor processing tasks corresponding to each semiconductor processing node, and the node status. Step S4: Based on the identification of processing context information, determine multiple sub-processing information, and determine the corresponding sub-processing event according to the multiple sub-processing information, the corresponding semiconductor processing node, and the semiconductor processing event; Step S5: Match the corresponding semiconductor processing actuator based on the semiconductor processing event, determine the execution status of the sub-processing event according to the semiconductor processing actuator, each sub-processing event and the node status corresponding to each semiconductor processing node, and determine the analysis result of the semiconductor processing event based on the execution status of multiple sub-processing events, the corresponding execution priority and the processing progress of the semiconductor processing event.

[0005] Optionally, step S1 includes: Step S11: Monitor the semiconductor processing in real time and collect multiple processing data of the semiconductor. Determine the processing content of the semiconductor based on the multiple processing data and the corresponding processing technology. At the same time, collect the processing route of the semiconductor and determine the semiconductor processing event based on the semiconductor processing route, the semiconductor processing content and the corresponding position. Step S12: Based on the detection of semiconductor processing events, determine multiple sub-semiconductor processing events, and determine the corresponding semiconductor processing statement according to the processing content of the multiple sub-semiconductor processing events, the semiconductor processing area, and the corresponding semiconductor processing equipment.

[0006] Optionally, step S2 includes: Step S21: Collect the semiconductor processing statement, and determine multiple sub-processing segments of different dimensions based on the detection of the semiconductor processing statement. Each sub-processing segment presents the processing content of the corresponding dimension; determine the corresponding key processing content based on the identification of multiple sub-processing segments. Step S22: Collect the semiconductor processing planner corresponding to the semiconductor processing event, and determine the corresponding directed acyclic graph based on each key processing content, the corresponding sub-processing segment and the corresponding semiconductor processing planner; Step S23: Determine multiple semiconductor processing nodes based on the identification of the directed acyclic graph, and mark the node position of each semiconductor processing node; match the corresponding semiconductor processing task based on the detection of each semiconductor processing node.

[0007] Optionally, step S3 includes: Step S31: Collect multiple semiconductor processing nodes and present the corresponding semiconductor processing tasks. Determine the semiconductor processing sequence based on the semiconductor processing tasks, node positions, and preset semiconductor processing requirements of the multiple semiconductor processing nodes, and dynamically adjust the node positions of the multiple semiconductor processing nodes.

[0008] Optionally, step S3 further includes: Step S32: After the node positions of multiple semiconductor processing nodes are adjusted, the first semiconductor processing information is determined based on the semiconductor processing sequence and the semiconductor processing task corresponding to each semiconductor processing node. Step S33: Collect the current processing history of each semiconductor processing node, determine the node status of each semiconductor processing node based on the current processing history of each semiconductor processing node and the real-time processing image of the semiconductor, determine the second semiconductor processing information based on the semiconductor processing sequence and the node status of each semiconductor processing node, and predict the corresponding processing context information based on the first semiconductor processing information and the second semiconductor processing information.

[0009] Optionally, step S4 includes: Step S41: Collect processing context information, determine multiple sub-processing information based on the processing context information and corresponding information tags, and determine the first sub-processing information combination based on the multiple sub-processing information and corresponding semiconductor processing nodes.

[0010] Optionally, step S4 further includes: Step S42: Collect semiconductor processing events, determine the corresponding semiconductor processing area based on the semiconductor processing events and multiple sub-processing information, determine the second sub-processing information combination based on the semiconductor processing area and the corresponding semiconductor processing node, and determine the corresponding sub-processing event based on the first sub-processing information combination and the second sub-processing information combination.

[0011] Optionally, step S5 includes: Step S51: Based on the analysis of semiconductor processing events, determine multiple processing factors, match the corresponding semiconductor processing actuators according to the multiple processing factors, the overall shape of the semiconductor and the semiconductor database, and determine the first execution parameters of the sub-processing events according to the semiconductor processing actuators and each sub-processing event; Step S52: Determine the second execution parameters of the sub-processing event based on the node status corresponding to the semiconductor processing actuator and each semiconductor processing node; determine the execution status of the sub-processing event based on the mapping relationship between the first execution parameters, the second execution parameters and the execution status corresponding to the sub-processing event.

[0012] Optionally, step S5 further includes: Step S53: Determine the corresponding execution priority based on the detection of multiple sub-processing events; determine the execution content status of the semiconductor processing event based on the execution status of multiple sub-processing events and their corresponding execution priorities; determine the processing progress status of the semiconductor processing event based on the execution status of multiple sub-processing events and the processing progress of the semiconductor processing event; and determine the analysis result of the semiconductor processing event based on the semiconductor processing event, its execution content status, and its processing progress status.

[0013] This invention provides a semiconductor processing event analysis system, which is applied to the above-described semiconductor processing event analysis method. The semiconductor processing event analysis system includes: The semiconductor processing statement module is used to collect semiconductor processing events and determine the corresponding semiconductor processing statements based on the analysis of these events. The semiconductor processing task module is used to determine the corresponding directed acyclic graph based on the semiconductor processing statement and the corresponding semiconductor processing planner; based on the identification of the directed acyclic graph, multiple semiconductor processing nodes are determined, and each semiconductor processing node is matched with a corresponding semiconductor processing task; The processing context information module is used to determine the semiconductor processing sequence based on the node positions of multiple semiconductor processing nodes and preset semiconductor processing requirements; and to predict the corresponding processing context information based on the semiconductor processing sequence, the semiconductor processing tasks corresponding to each semiconductor processing node, and the node status. The subprocessing event module is used to determine multiple subprocessing information based on the identification of processing context information, and to determine the corresponding subprocessing event based on the multiple subprocessing information, the corresponding semiconductor processing node, and the semiconductor processing event. The analysis results module is used to match the corresponding semiconductor processing actuators based on semiconductor processing events, determine the execution status of sub-processing events based on the semiconductor processing actuators, each sub-processing event, and the node status corresponding to each semiconductor processing node, and determine the analysis results of semiconductor processing events based on the execution status of multiple sub-processing events, their corresponding execution priorities, and the processing progress of semiconductor processing events.

[0014] Compared with the prior art, the beneficial effects of the present invention are: First, the semiconductor processing sequence is determined based on the node positions of multiple semiconductor processing nodes and the preset semiconductor processing requirements. Based on the semiconductor processing sequence, the semiconductor processing tasks corresponding to each semiconductor processing node, and the node status, the corresponding processing context information is predicted. A semiconductor processing planner and semiconductor processing statements are introduced, and the directed acyclic graph is further controlled.

[0015] Secondly, it takes into account the overall consideration of the semiconductor processing sequence, the semiconductor processing tasks corresponding to each semiconductor processing node, and the node status, thereby improving the accuracy of the processing context information.

[0016] Third, multiple sub-processing information is determined based on the identification of processing context information. The corresponding sub-processing events are determined based on the multiple sub-processing information, the corresponding semiconductor processing nodes, and the semiconductor processing events. The corresponding semiconductor processing actuators are matched based on the semiconductor processing events. The semiconductor processing actuators are introduced and managed, which improves the subsequent processing capability of semiconductor processing events.

[0017] Fourth, the execution status of sub-processing events is determined based on the semiconductor processing actuator, each sub-processing event, and the node status corresponding to each semiconductor processing node, thereby achieving further control over the execution status of sub-processing events.

[0018] Fifth, the analysis results of semiconductor processing events are determined based on the execution status of multiple sub-processing events, their corresponding execution priorities, and the processing progress of semiconductor processing events. The execution status of sub-processing events is output, realizing a holistic consideration of the execution status of multiple sub-processing events, their corresponding execution priorities, and the processing progress of semiconductor processing events, thereby improving the accuracy of the analysis results of semiconductor processing events. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating the semiconductor processing event analysis method in an embodiment of the present invention; Figure 2 This is a flowchart illustrating step S1 in the semiconductor processing event analysis method of this embodiment of the invention. Figure 3 This is a flowchart illustrating step S2 in the semiconductor processing event analysis method of this embodiment of the invention. Figure 4 This is a flowchart illustrating step S3 in the semiconductor processing event analysis method of this embodiment of the invention. Figure 5 This is a flowchart illustrating step S4 in the semiconductor processing event analysis method of this embodiment of the invention. Figure 6 This is a flowchart illustrating step S5 in the semiconductor processing event analysis method of this embodiment of the invention. Figure 7 This is a schematic diagram of the structural composition of the semiconductor processing event analysis system in an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0021] Please see Figures 1 to 7 A method for analyzing semiconductor processing events, applied to event analysis scenarios; the method for analyzing semiconductor processing events includes: Step S1: Collect semiconductor processing events and determine the corresponding semiconductor processing statements based on the analysis of the semiconductor processing events; Step S2: Determine the corresponding directed acyclic graph based on the semiconductor processing statement and the corresponding semiconductor processing planner; determine multiple semiconductor processing nodes based on the identification of the directed acyclic graph, and match each semiconductor processing node with the corresponding semiconductor processing task; Step S3: Determine the semiconductor processing sequence based on the node positions of multiple semiconductor processing nodes and the preset semiconductor processing requirements; predict the corresponding processing context information based on the semiconductor processing sequence, the semiconductor processing tasks corresponding to each semiconductor processing node, and the node status. Step S4: Based on the identification of processing context information, determine multiple sub-processing information, and determine the corresponding sub-processing event according to the multiple sub-processing information, the corresponding semiconductor processing node, and the semiconductor processing event; Step S5: Match the corresponding semiconductor processing actuator based on the semiconductor processing event, determine the execution status of the sub-processing event according to the semiconductor processing actuator, each sub-processing event and the node status corresponding to each semiconductor processing node, and determine the analysis result of the semiconductor processing event based on the execution status of multiple sub-processing events, the corresponding execution priority and the processing progress of the semiconductor processing event.

[0022] refer to Figure 2 In step S1, the specific steps are as follows: S11: Monitor the semiconductor processing in real time and collect multiple processing data of the semiconductor. Determine the processing content of the semiconductor based on the multiple processing data and the corresponding processing technology. At the same time, collect the processing route of the semiconductor and determine the semiconductor processing event based on the processing route, the processing content of the semiconductor, and the corresponding location. S12: Based on the detection of semiconductor processing events, determine multiple sub-semiconductor processing events, and determine the corresponding semiconductor processing statement according to the processing content of the multiple sub-semiconductor processing events, the processing area of ​​the semiconductor, and the corresponding semiconductor processing equipment.

[0023] In the embodiments of this application, a multi-dimensional data acquisition network covering the entire process was established. The monitored objects not only include the core process equipment itself, but also extend to material conveying systems (such as OHT overhead cranes and RGV railcars), measuring equipment, and even environmental control systems. The collected data can be mainly divided into three categories: Time-series data: This type of data is continuously generated by various sensors at extremely high frequencies (usually milliseconds), accurately recording the dynamic evolution of the process; for example, temperature, pressure, gas flow rate, radio frequency power, vacuum level, etc. in the reaction chamber; they are key to understanding how the process "changes".

[0024] Event / log data: This type of data is discrete and is generated by the equipment controller or manufacturing execution system (MES) when specific actions or state changes occur; they are like "milestones" in the process, marking the occurrence of key nodes, such as the equipment state switching from "idle" to "processing", wafer loading / unloading events, alarm triggering, and start / end markers of recipe execution, etc.

[0025] Trajectory data, primarily from the material handling system, records the real-time location coordinates and movement paths of wafers within the factory, providing a foundation for material flow and traceability. The system identifies the currently executing physical or chemical process by matching the real-time acquired multidimensional data stream with a pre-defined "process knowledge base," which predefines typical parameter ranges, timing characteristics, and key event markers for each process.

[0026] Matching algorithms typically employ a hybrid approach combining rule-based and model-based methods: Rule-based matching: This is a direct and efficient method that uses explicit logical conditions for judgment; for example, IF (pressure < 10 Pa AND RF power > 500 WANDF4 flow rate > 50 sccm) THEN processing content = 'plasma etching'; Model-based matching: For more complex dynamic processes, machine learning models (such as LSTM and CNN) can be used to extract deep features from time-series data, thereby identifying dynamic patterns that are difficult to describe with simple rules and correspond to specific processes (such as etching, deposition, and diffusion).

[0027] By deeply integrating with the factory's Manufacturing Execution System (MES) and Equipment Automation System (EAP), the system obtains the complete processing history and future plans for each production unit (such as wafer batches or individual wafers). The processing route typically exists as an ordered list of processes, such as [Batch A] > [Photolithography] > [Etching] > [Photoresist Removal] > [Cleaning] > [Metrology]. The system not only records the current process but also obtains its preceding processes and subsequent planned processes, which is crucial for understanding the causal relationships of events.

[0028] The outputs of the first three sub-steps—processing content, processing route, and physical location—are fused to generate a high-order, semantically complete "processing event." This event is a structured data object that typically contains the following core attributes: Event_ID: A unique identifier for the event; Object: The body of the event (e.g., Wafer_ID, Lot_ID); Process_Content: The specific content of the event (e.g., Poly-SiPlasmaEtch); Equipment: The equipment where the event occurred (e.g., ETCHER-01); Location: A more precise location (e.g., Chamber-01); Timestamp: The key time point of the event (e.g., start time, end time); Contextual_Info: Associated contextual information (e.g., information about preceding processes, recipe version number).

[0029] Furthermore, the system will perform a detailed analysis of the identified semiconductor processing events (such as "polysilicon plasma etching"). This analysis can be based on a preset process flow template, or it can be achieved by parsing the sequence of steps in the equipment recipe file, or by identifying different stage patterns in the timing data. The goal is to identify all the key sub-steps or sub-operations that constitute the event.

[0030] Once these sub-steps are detected, the system defines each independent operation as a "sub-semiconductor processing event." To ensure the accuracy of subsequent tracking and analysis, each sub-event is assigned a unique identifier, thus forming an ordered event chain.

[0031] For each sub-event identified in the previous step, a structured, machine-readable "processing statement" is generated. This statement is like a precise instruction given to the equipment, and it must contain all the key information required to execute the operation. The generation of the statement is mainly based on the following three dimensions of information: Processing content: clearly defining what each sub-event specifically "does," including core process details such as material type (e.g., photoresist type, etching gas) and process parameters (e.g., time, power, temperature, flow rate); Processing area: precisely locating "where" the operation occurs, which can be a specific layer on the wafer (e.g., layer 2, polysilicon layer) or a specific chamber inside the equipment (e.g., etching machine A chamber); Semiconductor processing equipment: specifying "who will do the operation"; that is, the specific name or model of the equipment that executes the sub-event (e.g., lithography machine A, developing machine B). The system combines these three dimensions of information in a structured way to finally generate a complete semiconductor processing statement.

[0032] refer to Figure 3 In step S2, the specific steps are as follows: S21: Collect the semiconductor processing statement, and determine multiple sub-processing segments of different dimensions based on the detection of the semiconductor processing statement. Each sub-processing segment presents the processing content of the corresponding dimension. Determine the corresponding key processing content based on the identification of multiple sub-processing segments. S22: Collect the semiconductor processing planner corresponding to the semiconductor processing event, and determine the corresponding directed acyclic graph based on each key processing content, the corresponding sub-processing segment and the corresponding semiconductor processing planner; S23: Identify multiple semiconductor processing nodes based on the recognition of the directed acyclic graph and mark the node position of each semiconductor processing node; match the corresponding semiconductor processing task based on the detection of each semiconductor processing node.

[0033] In the embodiments of this application, after receiving a complete processing statement, the system uses a pre-trained domain-specific language model or a rule-based entity recognition engine to perform multi-dimensional analysis. This process is far more than simple word segmentation; it requires a deep understanding of the precise meaning and role of each word or phrase in the context of semiconductor technology. The dimensions of analysis typically include: Operation dimension: identifying the core process actions to be performed, such as ETCH, DEPOSIT, ANNEAL, and CLEAN; Object dimension: identifying the entity being processed and its hierarchical attributes, such as WAFER, DIE, POLY_SI_LAYER, METAL_1_LAYER, and PHOTO_RESIST; Equipment dimension: identifying the hardware involved and its components, such as ETCHER-01, CHAMBER_A, and LOAD_LOCK.

[0034] Parameter dimension: Identifies specific process conditions and setpoints, such as PRESSURE: 5Pa (pressure), TIME: 300s (time), TEMPERATURE: 80°C (temperature), GAS_FLOW: CF 450sccm, O2 10sccm (gas flow rate); Target / Constraint dimension: Identifies desired process indicators or limiting conditions, such as TARGET_DEPTH: 500nm (target depth), SELECTIVITY: >10:1 (selectivity ratio), UNIFORMITY: <2% (uniformity); Control / Detection dimension: Identifies methods used for process control or endpoint detection, such as OPTICAL_EMISSION_SPECTROSCOPY (spectroscopy) and LASER_INTERFEROMETRY (laser interferometry). Through this multi-dimensional analysis, a linear statement is broken down into a structured information matrix, where each "sub-processing segment" is a value in the matrix, containing the "dimension-content" correspondence.

[0035] Specifically, in the semiconductor etching scenario, the input processing statement is: "In CHAMBER_A of ETCHER-01, perform plasma etching on POLY_SI_LAYER of Wafer#W789 using a CF4 / O2 mixed gas, with a target etching depth of 500nm, endpoint detection triggered by optical emission spectroscopy, and a process temperature of 80°C." After multi-dimensional analysis, the system will generate the following sub-processing segments: Operation dimension: Plasma etching; Object dimension: Wafer#W789, POLY_SI_LAYER; Device dimension: ETCHER-01, CHAMBER_A.

[0036] Parameter dimensions: GAS_MIX:CF4 / O2, TEMPERATURE:80°C.

[0037] Target / Constraint Dimension: TARGET_DEPTH: 500nm; Control / Detection Dimension: ENDPOINT_DETECTION: OPTICAL_EMISSION_SPECTROSCOPY.

[0038] After obtaining comprehensive sub-processed segments, the system needs to determine which information is the "key content" driving the entire analysis process. This is not a simple screening, but rather based on an "analysis importance assessment model" that comprehensively considers the following factors: Analysis goal-driven: Is this content directly related to the core objective of the analysis? For example, if the analysis objective is "to determine whether the etching depth is acceptable", then TARGET_DEPTH is the key content. Logical dependency: Is this content a necessary prerequisite for deriving other information? For example, POLY_SI_LAYER is key because all analyses revolve around this layer.

[0039] Process control criticality: Is this content a core control point affecting the process outcome? For example, the ENDPOINT_DETECTION method is critical because it directly determines the accuracy of etching. Anomaly diagnostic value: When anomalies occur, is this content the primary focus of investigation? For example, GAS_MIX and TEMPERATURE are critical because their drift is a common cause of process deviations. Based on these factors, the system calculates an "importance weight" for each sub-processing segment and sets a threshold. Segments exceeding the threshold are marked as "critical processing content."

[0040] Specifically, the system assesses the importance of the above sub-processing segments: Plasma Etching (Operation): Critical; defines the nature of the entire event; Wafer#W789 (Object): Important, but as an identifier, its importance is lower than the processing layer; POLY_SI_LAYER (Object): Critical; defines the specific target layer of the analysis; ETCHER-01, CHAMBER_A (Equipment): Important, used for data traceability, but not the core of the analysis logic; GAS_MIX:CF4 / O2,TEMPERATURE:80°C (Parameters): Critical; are the core variables affecting the etching rate and selectivity, and are used for diagnosing problems. Key; TARGET_DEPTH: 500nm (Target): Key; It is the benchmark for evaluating whether the results meet the standards; ENDPOINT_DETECTION: OPTICAL_EMISSION_SPECTROSCOPY (Control / Detection): Key; It is the core basis for judging whether the etching process has stopped precisely; The key processing content determined by the system is: Operation: Plasma Etching; Object: POLY_SI_LAYER; Parameters: GAS_MIX, TEMPERATURE; Target: TARGET_DEPTH; Control: ENDPOINT_DETECTION.

[0041] Furthermore, the "Semiconductor Processing Planner" is not a physical device, but an intelligent reasoning engine or expert system encapsulating profound knowledge in the semiconductor field. It functions like an experienced process engineer, containing: a process knowledge base storing the physicochemical principles, typical process windows, common failure modes, and related factors for various semiconductor processes (such as etching, deposition, and photolithography); analysis logic templates predefined standardized analysis processes for different analysis objectives; for example, for "film thickness analysis," the template includes fixed logic nodes such as "obtain previous value," "obtain subsequent value," "calculate difference," and "compare with target"; and a causal reasoning model capable of inferring intermediate hypotheses and dependencies that need to be verified based on key input content; for example, the model knows that "abnormal etching depth" is caused by "abnormal etching rate" or "endpoint detection failure," and that "abnormal etching rate" is related to "unstable gas flow" or "power drift." Therefore, the process of "collecting" the planner essentially instantiates or calls the most suitable planner instance from the model library based on the type of the current processing event (such as etching).

[0042] Specifically, the system recognizes the current event as "polysilicon layer plasma etching," so it calls a planner instance specifically for "plasma etching process analysis." This particular planner has built-in expertise on plasma physics, gas chemical reactions, endpoint detection principles, and other related knowledge, enabling it to accurately understand all analytical needs related to etching.

[0043] The planner receives the key processing content and complete sub-processing segments output by S121 as input and performs the following reasoning process: The planner first identifies the highest-order analysis objective; for example, from TARGET_DEPTH:500nm, it infers that the core objective is "verifying whether the actual etching depth meets the standard"; around the core objective, the planner uses its knowledge base to perform reverse deduction and forward expansion to construct a complete logical analysis chain; what is needed to verify the depth; the actual etching depth is needed; what is needed to obtain the actual etching depth; the film thickness after etching and the film thickness before etching are needed; which factors affect the actual etching depth; etching rate and etching time; which factors affect the etching rate; process parameters (gas, temperature, pressure) and equipment status; how to determine whether etching stops at the correct time; endpoint detection signal.

[0044] The planner maps each "proposition that needs to be verified" or "computation that needs to be performed" in the logic chain to a node in the DAG, and maps the causal or data dependencies between them to directed edges, thus forming a structured, acyclic analysis plan graph.

[0045] Specifically, after receiving the key information from S121, the planner begins to construct a Directed Acyclic Graph (DAG): Input: Operation: Plasma Etching, Object: POLY_SI_LAYER, Parameters: GAS_MIX, TEMPERATURE, Goal: TARGET_DEPTH, Control: ENDPOINT_DETECTION; Inference process: The core objective is to determine whether TARGET_DEPTH has been achieved, which requires calculating ACTUAL_DEPTH, thus requiring PRE_ETCH_THICKNESS (film thickness before etching) and POST_ETCH_THICKNESS (film thickness after etching), forming three nodes, and the calculation nodes depend on two data acquisition nodes; For in-depth analysis, the reliability of ENDPOINT_DETECTION needs to be verified, which requires analyzing OES_SIGNAL (spectral signal); To diagnose potential problems, the stability of key PARAMETERS (such as GAS_MIX, TEMPERATURE) during the process needs to be verified, which requires analyzing the corresponding time-series data.

[0046] The generated DAG structure is as follows: Node 1: Data Acquisition: Query the film thickness measurement value of Wafer#W789 before etching in POLY_SI_LAYER; Node 2: Data Acquisition: Query the film thickness measurement value of Wafer#W789 after etching in POLY_SI_LAYER; Node 3: Data Analysis: Calculate the statistical offset and standard deviation of key process parameters (CF4 / O2 flow rate, temperature) during the etching process; Node 4: Signal Analysis: Analyze the OES signal, identify the endpoint inflection point, and calculate its signal-to-noise ratio and waveform characteristics; Node 5: Data Calculation: Calculate the actual etching depth based on the results of Node 1 and Node 2; Node 6: Logical Judgment: Compare the calculation results of Node 5 with the target depth of 500nm and output preliminary conclusions; Node 7: Comprehensive Diagnosis: Integrate the results of Node 3, Node 4, and Node 6 to give a final analysis report (e.g., depth meets target, but there is a 2% drift in etching rate, it is recommended to check the gas mass flow controller); Dependencies: Node 5 depends on Node 1 and Node 2; Node 6 depends on Node 5; Node 7 depends on Node 3, Node 4, and Node 6.

[0047] Therefore, multiple semiconductor processing nodes are identified based on the recognition of directed acyclic graphs, and the node positions of each semiconductor processing node are marked; the corresponding semiconductor processing tasks are matched based on the detection of each semiconductor processing node, which is compatible with the overall consideration of the recognition of directed acyclic graphs and ensures the accuracy of multiple semiconductor processing nodes.

[0048] At this point, the system will traverse each node in the DAG and assign it a clear identity and execution attributes, transforming it from an abstract logical concept into a manageable concrete object; the system will assign a globally unique identifier to each node (such as Node_ID:DAG_001_N5) and record its descriptive name (such as "Calculate the actual etching depth").

[0049] The system categorizes and labels each node based on the DAG topology. This "position" is not a physical location, but rather its role and responsibility in the execution logic flow. Common position labels include: Input nodes: No prerequisites, the starting point of the entire analysis process, typically responsible for obtaining raw data from external data sources (such as databases or data lakes); Intermediate processing nodes: At least one prerequisite, responsible for calculating, transforming, or analyzing the output data of the preceding nodes; Parallel nodes: A group of independent intermediate nodes that can be executed simultaneously by the scheduler to improve efficiency; Convergence nodes: Multiple prerequisites, responsible for summarizing, merging, or comparing the results of multiple parallel or serial branches; Output nodes: No post-delays, the endpoint of the entire analysis process, responsible for generating the final analysis report, conclusions, or alerts.

[0050] Specifically, the system processes the etching analysis DAG generated by S22, identifying and labeling each node: Node1: Query film thickness before etching > Labeled as: Input node; Node2: Query film thickness after etching > Labeled as: Input node; Node3: Analyze process parameter stability > Labeled as: Intermediate processing node; Node4: Analyze OES signal > Labeled as: Intermediate processing node; Node5: Calculate actual etching depth > Labeled as: Convergence node (because it depends on Node1 and Node2); Node6: Determine if the depth meets the standard > Labeled as: Intermediate processing node; Node7: Generate comprehensive diagnostic report > Labeled as: Output node. Simultaneously, by analyzing dependencies, the system identifies that Node1 and Node2 can be executed in parallel, and Node3 and Node4 can also be executed in parallel, providing a basis for subsequent optimization of execution efficiency.

[0051] The system transforms the "descriptive intent" of each node in the DAG into an "executable instruction." Based on the node's description and location, the system matches and binds a specific "semiconductor processing task" from a predefined "task library." The task library is a collection of various atomic operation modules, such as: data connectors for connecting different types of databases (e.g., time-series database InfluxDB, relational database MySQL); data query templates: predefined SQL or NoSQL query scripts for extracting specific data; algorithm model library: encapsulated data analysis algorithms, such as time series stationarity tests, signal peak detection, and statistical process control (SPC) calculations; a logic judgment engine for executing rule judgments, such as IF value > threshold THEN...; and a report generator for formatting analysis results into HTML, PDF, or JSON reports. The matching process involves the system associating node descriptions with modules in the task library through semantic matching or rule mapping.

[0052] Specifically, the system matches a specific execution task and configuration for each marked node: Node1 (input node): Matching task: Execute data query task; Specific configuration: Connect to Metrology-DB; Execute SQL: SELECTthicknessFROMfilm_thicknessWHEREwafer_id='W789'ANDlayer='POLY_SI'ANDstep='PRE_ETCH'.

[0053] Node3 (Intermediate Processing Node): Matching Task: Calls the time series analysis algorithm; Specific Configuration: Algorithm: AugmentedDickey-FullerTest; Input Data: CF4 / O2 flow and temperature time series data of the etching equipment within a specified time window; Output: p-value, stability conclusion.

[0054] Node5 (Gathering Node): Matching Task: Performs basic arithmetic operations; Specific Configuration: Operation: (Node_2.output) - (Node_1.output); Output: actual_etch_depth; Node7 (Output Node): Matching Task: Calls the report generator; Specific Configuration: Template: Etch_Analysis_Report_Template.html; Input Data: Output results of Node3, Node4, and Node6; Output Format: PDF.

[0055] refer to Figure 4 In step S3, the specific steps are as follows: S31: Collect multiple semiconductor processing nodes and present the corresponding semiconductor processing tasks. Determine the semiconductor processing sequence based on the semiconductor processing tasks, node positions, and preset semiconductor processing requirements of the multiple semiconductor processing nodes, and dynamically adjust the node positions of the multiple semiconductor processing nodes. S32: After the node positions of multiple semiconductor processing nodes are adjusted, the first semiconductor processing information is determined based on the semiconductor processing sequence and the semiconductor processing task corresponding to each semiconductor processing node. S33: Collect the current processing history of each semiconductor processing node, determine the node status of each semiconductor processing node based on the current processing history of each semiconductor processing node and the real-time processing image of the semiconductor, determine the second semiconductor processing information based on the semiconductor processing sequence and the node status of each semiconductor processing node, and predict the corresponding processing context information based on the first semiconductor processing information and the second semiconductor processing information.

[0056] In the embodiments of this application, a technically feasible and conflict-free execution sequence is generated based on the logical dependencies of the DAG. This ensures the logical correctness of the analysis process and is the foundation for all subsequent optimizations. The system mainly performs the following operations: The scheduler executes a topology sorting algorithm on the DAG generated in S123. This algorithm ensures that each node (task) in the graph is scheduled for execution only after all its predecessor dependent nodes have been executed. This is the mathematical basis for ensuring the correctness of the analysis logic. During the topology sorting process, the scheduler identifies all sets of nodes that have no mutual dependencies. These nodes constitute a "parallel execution layer" and can be simultaneously distributed by the scheduler to different executors (or threads) for processing, thereby maximizing the utilization of computing resources and shortening the total analysis time. The scheduler generates an ordered list containing multiple execution layers. For example, [Layer1:{NodeA,NodeB},Layer2:{NodeC},Layer3:{NodeD,NodeE}], this list is the basic processing order.

[0057] Specifically, the scheduler obtains the DAG for etching analysis, which contains 7 nodes. Through topology sorting, it identifies the following execution layers: Layer 1 (input layer): Node 1 (querying film thickness before etching) and Node 2 (querying film thickness after etching) are independent and can be executed in parallel; Layer 2 (intermediate analysis layer): Node 3 (analyzing process parameter stability) and Node 4 (analyzing OES signals) are independent, but both depend on the data readiness of Layer 1; Layer 3 (calculation layer): Node 5 (calculating actual etching depth) depends on the results of Node 1 and Node 2; Layer 4 (judgment layer): Node 6 (judging whether the depth meets the standard) depends on the result of Node 5; Layer 5 (output layer): Node 7 (generating a comprehensive diagnostic report) depends on the results of Node 3, Node 4, and Node 6. Therefore, the basic processing order is determined as: {Node 1, Node 2} > {Node 3, Node 4} > {Node 5} > {Node 6} > {Node 7}.

[0058] The system introduces "preset semiconductor processing requirements" to optimize the basic sequence, making it more in line with actual production needs; the system checks whether each node task is associated with a specific business requirement tag; for example, a task may be marked as CRITICAL_PATH, REAL_TIME_ALERT, or POST_PROCESS_ANALYSIS; the scheduler will increase the execution weight of high-priority tasks and all their predecessor tasks.

[0059] The scheduler assesses the type (e.g., CPU-intensive, GPU-accelerated, large-scale memory-intensive) and quantity of resources required for each task; it fine-tunes the execution order based on the current cluster's resource availability; for example, if a GPU task is queued while CPU resources are idle, the scheduler will choose to execute a CPU analysis branch that does not depend on that GPU task first; at the same time, for analysis tasks with clear time requirements (e.g., those that must be completed within 15 minutes), the scheduler will reserve resources for them and delay the execution of some non-urgent background analysis tasks.

[0060] Specifically, the preset processing requirement is "prioritize diagnosing the stability of process parameters because the equipment has a recent maintenance record"; the scheduler finds that Node3 (analyzing process parameter stability) is marked as HIGH_PRIORITY; therefore, the scheduler optimizes the basic sequence: although Node3 and Node4 are at the same level, the executor will be assigned to Node3 first; at the same time, it will ensure that all the preceding tasks of Node3 (i.e., Node1 and Node2) are processed as quickly as possible; the optimized processing intent becomes: complete {Node1, Node2} as soon as possible, then execute Node3 immediately, and Node4 can be parallelized later; The scheduler continuously monitors the entire analysis process throughout its lifecycle and adjusts based on real-time feedback to ensure system robustness. The scheduler listens to the execution status of each node in real time, including QUEUED, RUNNING, SUCCESS, FAILED, and TIMEOUT.

[0061] If a node fails, the scheduler will respond according to preset strategies. These strategies include retrying the node, skipping the node (if it is a non-critical path), or activating a backup fault diagnosis sub-DAG. If a node's execution time significantly exceeds expectations, the scheduler can dynamically adjust resource allocation for subsequent nodes or send performance bottleneck alerts to the system administrator. In extreme cases, if a critical data source node fails, the scheduler can dynamically modify the DAG, marking all downstream branches that depend on that node as SKIPPED or FAILED_WITH_CAUSE, and directly generating a final report containing the reason for the failure, avoiding unnecessary waiting.

[0062] Specifically, the analysis process begins, and Node1 and Node2 are successfully executed; the scheduler activates Node3 and Node4, and Node3 (high priority) is executed immediately; while Node4 (analyzing OES signals) is executing, it discovers that the network connection to the spectral database has been interrupted, and the task status changes to FAILED.

[0063] The scheduler detects the failure event of Node4; it checks the DAG and finds that Node7 (the final report) depends on Node4; the scheduler immediately triggers a pre-defined "exception handling" logic: instead of aborting the entire process, it generates a special output for Node4: {"status":"DATA_UNAVAILABLE","reason":"NetworkconnectiontoOES-DBtimedout"}; the scheduler passes this special result to Node7 and allows Node7 to continue execution; at the same time, it records the exception in the execution log and notifies the operations team to check the network connectivity. Furthermore, after the node positions of multiple semiconductor processing nodes are adjusted, the first semiconductor processing information is determined based on the semiconductor processing sequence and the semiconductor processing tasks corresponding to each semiconductor processing node. This takes into account both the overall consideration of the semiconductor processing sequence and the semiconductor processing tasks corresponding to each semiconductor processing node, ensuring the accuracy of the first semiconductor processing information.

[0064] At this point, the final execution order after dynamic adjustment by S31 is clearly listed, including which tasks can be performed in parallel and which tasks must be performed sequentially; at the same time, the direct prerequisites of each task are clearly marked; the purpose is to provide unambiguous scheduling instructions for the execution engine and to provide a clear baseline path for subsequent real-time monitoring.

[0065] Describe in detail the data flow path between nodes; for each node, define the source of its input data (from which preceding node's output), the expected data format (such as JSON, Protobuf, CSV), the data schema, and the approximate data volume; the purpose is to ensure that data transfer between nodes is compatible and efficient.

[0066] Describe in detail the data flow path between nodes; for each node, define the source of its input data (from which preceding node's output), the expected data format (such as JSON, Protobuf, CSV), the data schema, and the approximate data volume; the purpose is to ensure that data transfer between nodes is compatible and efficient.

[0067] Define the output results that should be generated after each node task is successfully executed; for calculation nodes, it is the specific calculated value; for analysis nodes, it is the analysis conclusion or confidence score; for output nodes, it is the format and content outline of the final report.

[0068] Specifically, assuming in S31, because Node4 (analyzing OES signals) is predicted to have network risks, the scheduler decides to stagger its execution order with Node3 (analyzing process parameter stability) and sets a longer timeout for it; based on this adjusted processing order, the system generates the following first semiconductor processing information: First semiconductor processing information (for etching event Wafer#W789): Execution sequence summary: Layer1: [Task:Query_Pre_Etch_Thickness,Task:Query_Post_Etch_Thickness] (parallel); Layer2: [Task:Analyze_Process_Stability] (serial, high priority); Layer3:[Task:Analyze_OES_Signal](Serial, long timeout); Layer4:[Task:Calculate_Actual_Depth] (depends on Layer1); Layer5:[Task:Judge_Depth_Compliance] (depends on Layer4); Layer6:[Task:Generate_Final_Report](depends on Layer2,3,5).

[0069] Data Flow Contract: Task: Calculate_Actual_Depth; Input 1: From Task: Query_Post_Etch_Thickness; The format is {"wafer_id":"W789","thickness":450.2,"unit":"nm"}; Input 2: from Task:Query_Pre_Etch_Thickness, with the same format as above; Output: in the format {"actual_depth":498.5,"unit":"nm"}.

[0070] Resource Requirements Estimation: Task: Analyze_Process_Stability: Expected to require 2 CPU cores, 4GB of memory, and an execution time of approximately 30 seconds; Task: Generate_Final_Report: Expected to require 1 CPU core, 2GB of memory, and an execution time of approximately 10 seconds; Total: Peak resource requirements are 3 CPU cores and 4GB of memory.

[0071] Expected Output and Success Criteria: Task: Judge_Depth_Compliance: The success criterion is to output a boolean value is_compliant; if actual_depth is within the range of 500nm±5nm, then it is true, otherwise it is false; Task: Generate_Final_Report: The success criterion is to generate a PDF report containing the following sections: 1. Execution Summary, 2. Film Thickness Analysis Results, 3. Process Stability Assessment, 4. Endpoint Detection Analysis, 5. Conclusions and Recommendations.

[0072] Therefore, the current processing history of each semiconductor processing node is collected. Based on the current processing history of each semiconductor processing node and the real-time processing image of the semiconductor, the node state of each corresponding semiconductor processing node is determined. Based on the semiconductor processing sequence and the node state of each semiconductor processing node, the second semiconductor processing information is determined. Based on the first and second semiconductor processing information, the corresponding processing context information is predicted. This approach takes into account both the semiconductor processing sequence and the node state of each semiconductor processing node, ensuring the accuracy of the second semiconductor processing information. At the same time, a semiconductor processing planner and semiconductor processing statements are introduced, and the directed acyclic graph is further controlled. This approach takes into account both the semiconductor processing sequence, the semiconductor processing tasks corresponding to each semiconductor processing node, and the node state, improving the accuracy of the processing context information.

[0073] At this point, a comprehensive "health check" and "environment scan" are performed on each node (task) in the DAG to generate a dynamic "node status" that reflects the current actual situation. This process integrates historical data and real-time perception. The system will query the historical operation records of the physical entities (such as specific devices, databases, and algorithm models) associated with each node. This includes: mean time between failures (MTBF) in the past 24 hours, task execution success rate, average response latency, recent calibration records, maintenance logs, and historically occurring abnormal patterns.

[0074] "Processed image" is a broad concept that refers to all real-time data streams that can reflect the current physical or virtual state. This includes: device sensor data (temperature, pressure, flow, etc.), visual inspection data (wafer surface images), system performance indicators (server CPU, memory usage), and data quality signals (data integrity, outliers).

[0075] The system uses a fusion model (such as a weighted scoring model or a rule-based expert system) to integrate information from the "processing history" and "real-time images" to generate a standardized status label for each node. Common status labels include: NOMINAL, DRIFTING, DEGRADED, ANOMALY_DETECTED, and OFFLINE.

[0076] Based on the dynamic status of all nodes, a "risk assessment" and "impact analysis" are performed on the execution plan, generating a dynamic information summary reflecting the current execution risks. The second semiconductor processing information mainly includes: a list of risky nodes: all nodes in non-NOMINAL states and their specific status descriptions; an impact chain analysis: analyzing the impact of each risky node on subsequent dependent nodes; for example, a DEGRADED data source node will cause a decrease in the reliability of the results of all analysis nodes that depend on it; execution probability prediction: predicting the probability of successful execution of each task based on the node status; for example, a node ANOMALY_DETECTED has a predicted success probability of 70%; and an expected delay warning: for nodes in the DEGRADED state, predicting how much their execution time will exceed the original plan based on their current performance indicators.

[0077] The first processed information (static plan) and the second processed information (dynamic risk) are deeply integrated, and a predictive model (such as a Bayesian network, causal inference model or rule-based inference engine) is used to generate the final, guiding "processing context information". This context information is no longer a simple description, but contains predictive insights and action suggestions.

[0078] Prediction Content: Result Confidence Adjustment: "Since Node3 is in the DRIFTING state, the confidence level of its conclusion regarding 'process stability' should be reduced by 20%"; Parameter Adaptation Recommendation: "Based on Node3's real-time drift mode, it is recommended to appropriately relax the control limits in subsequent Statistical Process Control (SPC) analyses to avoid false alarms"; Execution Path Dynamic Replanning Recommendation: "Node3 has a high risk, and it is recommended to clearly mark this risk in the final report and prioritize engineers checking ETCHER-01's MFC; if real-time requirements are extremely high, consider skipping Node3 and directly generating a simplified report without process stability analysis; Predictive Alert: "Node3's current state indicates a performance failure within the next 50 processing cycles, and it is recommended to arrange preventative maintenance in advance."

[0079] Specifically, regarding Node3 (analysis of process parameter stability): A check of the ETCHER-01 maintenance log revealed that its CF4 gas mass flow controller (MFC) had been calibrated 7 days prior and historically exhibited stable performance. Real-time acquisition of the MFC's flow readings revealed slight fluctuations of ±0.5% around the setpoint, but the frequency was high, inconsistent with normal noise models. After comprehensive system evaluation, Node3's status was marked as DRIFTING, with the note: "The MFC flow signal exhibits high-frequency, slight fluctuations, affecting the accuracy of stability analysis."

[0080] The system generates the second semiconductor processing information: "Risk Node: Node3 (Status: DRIFTING); Impact Chain: The credibility of the output of Node3 (process stability report) has decreased, which will affect the diagnostic conclusions about process parameters in the final report (Node7); Execution Probability: The success probability of Node3 is estimated to be 85%; No unexpected delay warning."

[0081] For Node1 & 2 (querying membrane thickness data): The historical query success rate of the Metrology-DB is 99.9%, with an average response time of 50ms; the current database connection pool is healthy, and the CPU load is 15%; the system marks the status of Node1 and Node2 as NOMINAL.

[0082] The system integrates the first and second processing information to predict the final processing context information: "Etching analysis of Wafer#W789 is about to be performed; the planned execution sequence is: [Query film thickness] > [Analyze process parameters] > ... (first information); (second information) A slight data drift is detected in the node (Node3) for analyzing process parameters; (predictive context) Therefore, the system predicts: 1) The confidence level of the conclusion in this analysis report regarding 'highly stable process parameters' is low; 2) It is recommended to add a note to the final report: 'The process parameter data source has a slight drift, and the conclusion is for reference only'; 3) Automatically create a low-priority work order for the equipment maintenance system, and it is recommended to check ETCHER-01's CF4MFC during the next shutdown."

[0083] refer to Figure 5 In step S4, the specific steps are as follows: S41: Collect processing context information, determine multiple sub-processing information based on the processing context information and corresponding information tags, and determine the first sub-processing information combination based on the multiple sub-processing information and corresponding semiconductor processing nodes; S42: Collect semiconductor processing events, determine the corresponding semiconductor processing area based on the semiconductor processing events and multiple sub-processing information, determine the second sub-processing information combination based on the semiconductor processing area and the corresponding semiconductor processing node, and determine the corresponding sub-processing event based on the first sub-processing information combination and the second sub-processing information combination.

[0084] In the embodiments of this application, the “processing context information” output by S13 is semantically parsed and decomposed into instructions; the processing context information is usually a natural language or structured text fragment containing predictions, suggestions, risk warnings and confidence adjustments, and each fragment is marked with an “information tag”.

[0085] The system first scans the context information and identifies the information markers within it. Common markers include: CONFIDENCE_ADJUSTMENT (Confidence Adjustment): Indicates that the reliability of a certain analysis conclusion needs to be corrected; PARAMETER_SUGGESTION (Parameter Suggestion): Suggests adjusting the internal parameters of a certain algorithm or analysis; RISK_WARNING (Risk Warning): Indicates that a certain data source or device has a risk that affects the results; ACTION_RECOMMENDATION (Action Recommendation): Recommends performing an additional operation that is not part of the DAG plan (such as creating a work order or sending an alarm); EXECUTION_PATH_CHANGE (Execution Path Change): Suggests modifying the execution path of the DAG, such as skipping a certain node.

[0086] After identifying the information marker, the system will generate one or more structured "sub-processing information" based on the marker type and context content. Each sub-processing information is an independent instruction unit that can be understood by a specific node or system module. It usually contains two fields: instruction (instruction content) and target_node (target node ID).

[0087] Specifically, the system collected the processing context information generated by S13: "Since the status of Node3 (analyzing process parameters) is DRIFTING, the confidence level of its conclusion should be reduced by 20%; it is recommended to clearly mark this risk in the final report and automatically create a low-priority work order for the equipment maintenance system, and it is recommended to check CF4MFC of ETCHER-01."

[0088] The system identified the first sentence, "...confidence level should be reduced by 20%", and marked it as CONFIDENCE_ADJUSTMENT; its target is the final report generation node Node7; it generates sub-processing information 1: target_node: "Node_7"; instruction: "Add confidence level comments to the process stability analysis conclusions in the report, such as 'This conclusion is based on data with slight drift, and the overall confidence level is assessed as 80%'"; the system identified the second sentence, "It is recommended to clearly mark this risk in the final report", and marked it as ACTION_RECOMMENDATION; its target is also Node7.

[0089] Subprocessing information 2 is generated: target_node: "Node_7"; instruction: "In the 'Conclusions and Recommendations' section of the report, add a risk warning: 'The process parameter data source has slight drift, which has affected the accuracy of the analysis. It is recommended to check the relevant hardware'"; The system recognizes the third sentence "Automatically create a work order for the equipment maintenance system" and marks it as ACTION_RECOMMENDATION; its target is not the analysis node within the DAG, but an external "system integration interface".

[0090] Generating subprocessing information 3: target_node: "System_Integration_Module"; instruction: "Call CMMS (Computerized Maintenance Management System) API to create a preventive maintenance work order; Equipment: ETCHER-01; Component: CF4MFC; Priority: Low; Description: The data analysis system detected high-frequency micro-amplitude drift in this MFC and recommends calibration or inspection in the next planned downtime window."

[0091] All the "subprocessing information" generated in the previous step are organized into a structured data set, namely the "first subprocessing information combination". This combination is the final output of S41, which provides a clear and distributed list of instructions for subsequent steps. This combination is usually a map or dictionary structure, where the key is target_node and the value is a list containing all instructions sent to that node.

[0092] Specifically, the system aggregates the three sub-processing information generated in the previous step to form the first sub-processing information combination: the two instructions in the instruction list for Node_7 (i.e., the node responsible for generating the final report) perfectly embody this; the first instruction requires adding a confidence level note to the conclusion of the process stability analysis in the report, directly integrating the quantitative insight of "confidence level assessed at 80%" into the output, improving the rigor and credibility of the report; the second instruction goes a step further, requiring the addition of a clear risk warning in the "Conclusions and Recommendations" section of the report, which not only points out the problem but also provides specific action directions - "It is recommended to check the relevant hardware".

[0093] It goes beyond analysis itself, achieving intelligent linkage with external systems; the instructions for System_Integration_Module in the list are a concentrated reflection of the system's intelligence level; it does not stop at the level of "discovering problems", but actively promotes the solution of problems; by calling the API of CMMS (Computerized Maintenance Management System), the system can automatically create a preventive maintenance work order containing detailed equipment information (CF4MFC of ETCHER-01), problem description and priority suggestions, which is equivalent to the data analysis system playing the role of a "virtual process engineer".

[0094] In summary, this "first sub-processing information combination" is like a precise command and dispatch center. It breaks down high-level strategic intentions (contextual information) into tactical-level operational instructions and ensures that they are accurately transmitted to the report generation system and external maintenance system.

[0095] Furthermore, the system reviews and collects the "semiconductor processing event" initially defined in S1. This original event contains the most fundamental physical information. The system extracts the most core and specific physical operation object, namely the "processing area," which is usually defined by product identification (such as wafer ID), structural hierarchy (such as specific thin film layers), and spatial location (such as a specific die or region on the wafer). It answers the fundamental question of "what exactly is the object of analysis and where is it?"

[0096] After determining the processing area, the system associates this physical coordinate with each "semiconductor processing node" (i.e. analysis task) defined in S2. This process creates a "task-location" mapping relationship. For each node, the system clearly indicates which specific physical area its analysis target is. This combination represents the precise correspondence of "which analysis task is performed in which physical location" and is the specific direction of the analysis task in the physical world.

[0097] The system integrates information from three different levels to generate a complete, self-contained "sub-processing event" that can be directly manipulated by the "actuator" in S15. The system integrates the following three key information sources: semiconductor processing node: provides the core task definition of "what to do"; second sub-processing information combination: provides the physical coordinates and target of "where to do it"; first sub-processing information combination: provides context instructions and dynamic adjustments of "how to do it intelligently".

[0098] The merged information is encapsulated into a standardized "subprocess event" object, which is the final execution unit. It contains all the information needed for the executor to complete the task: event_id: a unique identifier for the event; target_area: the specific physical area of ​​effect; core_task: a description of the core task to be executed; contextual_instructions: a list containing all smart instructions from S141 for this task; priority: the execution priority; dependencies: the IDs of other dependent events.

[0099] Specifically, the system collected the original semiconductor processing event: "Plasma etching of POLY_SI_LAYER on Wafer#W789"; the core processing area was extracted as: {"wafer_id":"W789","layer":"POLY_SI_LAYER"}.

[0100] The system iterates through all semiconductor processing nodes and binds them to the processing region; Node1 (query pre-etch film thickness) > bound region Wafer#W789,POLY_SI_LAYER; Node3 (analyze process parameter stability) > bound region Wafer#W789,POLY_SI_LAYER; Node7 (generate final report) > bound region Wafer#W789,POLY_SI_LAYER; ... and so on, establishing this association for all nodes; the final second sub-processing information combination (taking Node7 as an example) can be represented as: Second combination = {"Node_7":{"target_area":{"wafer_id":"W789","layer":"POLY_SI_LAYER"},"task_description":"Generate final analysis report"}}.

[0101] The system takes Node7 (generating the final report) as an example to perform information fusion and generate sub-processing events; Semiconductor processing node: Node7 (generating the final report); Second combined information: target_area:{"wafer_id":"W789","layer":"POLY_SI_LAYER"}; First combined information: contextual_instructions:["Add confidence annotation","Add risk warning"]; The finally generated sub-processing events are as follows: This instruction clarifies the target and identity of the action; Sub-processing event ID: SubEvent_FinalReport_W789_POLY is like a unique code for this task, ensuring that it can be accurately tracked and managed throughout the entire complex analysis process; The target area: Wafer#W789,POLY_SI_LAYER clearly indicates the physical coordinates of the task's action—specifically, which wafer and which layer, to avoid object confusion; It defines the core content of the task; The core task section uses the most concise language to explain "what to do".

[0102] The most intelligent and valuable part of this instruction lies in its contextual instruction set. It's no longer a simple execution command, but a "smart toolkit" integrating predictive insights from the S33 phase. It tells the actuator that when generating reports, data cannot be presented mechanically, but must be intelligently adjusted. For example, it requires adding a "confidence level note" to the conclusions of the process stability analysis, directly including the quantitative assessment of "80%" in the report, greatly enhancing the professionalism and credibility of the results. Furthermore, it proactively adds a "risk warning" to the report, not only pointing out problems with the data source but also providing a "suggestion to check relevant hardware" action direction. This elevates the final analysis report from a passive result presentation to a forward-looking and guiding decision support document. The instruction also contains key information at the execution level: execution priority: "high" tells the scheduling system the importance of the task, ensuring it is processed first; and the dependency event list clarifies the preconditions for the task, namely, the final report can only be generated after the film thickness calculation, process stability analysis, and OES signal analysis are all completed.

[0103] refer to Figure 6 In step S5, the specific steps are as follows: S51: Based on the analysis of semiconductor processing events, multiple processing factors are determined. The corresponding semiconductor processing actuator is matched according to the multiple processing factors, the overall shape of the semiconductor, and the semiconductor database. The first execution parameter of the sub-processing event is determined according to the semiconductor processing actuator and each sub-processing event. S52: Determine the second execution parameters of the sub-processing event based on the node status corresponding to the semiconductor processing actuator and each semiconductor processing node; determine the execution status of the sub-processing event based on the mapping relationship between the first execution parameters, the second execution parameters and the execution status corresponding to the sub-processing event; S53: Determine the corresponding execution priority based on the detection of multiple sub-processing events, determine the execution content status of the semiconductor processing event based on the execution status of multiple sub-processing events and their corresponding execution priorities, determine the processing progress status of the semiconductor processing event based on the execution status of multiple sub-processing events and the processing progress of the semiconductor processing event, and determine the analysis result of the semiconductor processing event based on the semiconductor processing event, the execution content status, and the processing progress status.

[0104] In the embodiments of this application, the system first performs in-depth analysis of the "semiconductor processing event" and its various derived sub-processing events, extracting key features that determine the executor type, namely "processing factors." These factors include: task type: whether it is data query, numerical calculation, algorithm model inference, or report generation; data source type: whether the data is stored in a relational database (such as PostgreSQL), a time-series database (such as InfluxDB), a data lake, or needs to be obtained through an API; algorithm / model requirements: whether it requires executing a Python script, an R language statistical model, or a deep learning model deployed on TensorFlowServing or TorchServe; and interaction mode: whether it is a synchronous request-response mode or an asynchronous batch processing mode.

[0105] The system matches the extracted processing factors with an "executor registry" maintained within the system. This registry is a metadata store that records a list of all available execution services within the factory; for example: SQL-Executor-Service-v2: specifically handles query requests to PostgreSQL and MySQL; TimeSeries-Analytics-Engine: has built-in various time series analysis algorithms and connects to the factory's time series database; ML-Model-Serving-Cluster: used to host and provide inference services for machine learning models; Report-Generator-Microservice: specifically used to generate PDF or HTML reports based on templates and data. The overall form of the semiconductor (such as the factory's IT architecture, cloud-native or on-premises deployment strategy) and the specific configuration of the semiconductor database (such as address, authentication information) determine which specific executor instance is ultimately selected.

[0106] The first set of execution parameters are static, predefined, and essential core inputs for task execution. These parameters are extracted directly from the core_task and target_area of ​​the subprocessing events generated in S14, and the executor type matched in S151. They constitute a complete set of execution instructions, including: connection information: the JDBC / ODBC connection string for the database, the endpoint URL for the API, and the path to the file system; credentials information: the username, password, and API key required to access the database or API (usually dynamically obtained from a secure key management system); task payload: the specific SQL query statement, the name and version of the algorithm model, the parameters to be passed to the script, and the ID of the report template; target identifier: specific values ​​used to populate the query statement or API parameters, such as WaferID, LayerName, ToolID, etc.

[0107] Furthermore, the second execution parameters of the sub-processing event are determined based on the node status corresponding to the semiconductor processing actuator and each semiconductor processing node; the execution status of the sub-processing event is determined based on the mapping relationship between the first execution parameters, the second execution parameters and the execution status corresponding to the sub-processing event, which takes into account the overall consideration of the mapping relationship between the first execution parameters, the second execution parameters and the execution status corresponding to the sub-processing event, and ensures the accuracy of the execution status of the sub-processing event.

[0108] At this point, the system directly obtains the "node state" corresponding to each semiconductor processing node from the output of S33. These states are: (Such as NOMINAL, DRIFTING, DEGRADED, ANOMALY_DETECTED) are real-time assessments of the risks in the current execution environment.

[0109] The system maintains a set of "state-parameter" mapping rules. When a node state is received, the system queries this set of rules and generates corresponding second execution parameters. These parameters are mainly used to control the non-functional requirements of the execution process, such as robustness, efficiency, and resource allocation.

[0110] For DEGRADED or DRIFTING states: the system infers that the node's execution is slower or less stable than usual; therefore, the second execution parameter will include: increased timeout, more retries, and longer health check intervals.

[0111] For the ANOMALY_DETECTED state: the system considers the node to be at high risk of failure; the second execution parameters include: enabling fail-fast mode (not retrying to save resources), reducing CPU / memory resource allocation (to avoid abnormal nodes consuming too many resources), and triggering a parallel diagnostic task.

[0112] For the HIGH_PRIORITY flag: even if the node state is NOMINAL, the second execution parameter includes: increasing the priority of the execution thread, allocating more computing resources, and using a better performing executor instance.

[0113] The system merges the "first execution parameter" (static task instruction) and the "second execution parameter" (dynamic environment configuration) into a complete execution request, and then sends it to the matched semiconductor processing actuator. The actuator starts working. After execution, the actuator returns a raw execution result, which includes data, error codes, exception stacks, execution time, etc. The system does not use this raw result directly, but instead inputs it into an "execution status mapping engine". This engine is a rule-based decision system that standardizes the raw output into several distinct "execution status" states.

[0114] Mapping rule example: IF return code in [200, 201] AND result data not empty THEN execution status = "SUCCESS"; IF return code = 404 THEN execution status = "DATA_NOT_FOUND"; IF execution time > execution_timeout_seconds THEN execution status = "TIMEOUT"; IF exception type = "ConnectionException" THEN execution status = "CONNECTION_ERROR"; IF exception type = "InvalidArgumentException" THEN execution status = "INVALID_PARAMETERS".

[0115] Therefore, this method determines the corresponding execution priority based on the detection of multiple sub-processing events, determines the execution content status of semiconductor processing events based on the execution status and corresponding execution priorities of multiple sub-processing events, determines the processing progress status of semiconductor processing events based on the execution status and processing progress of multiple sub-processing events, and determines the analysis results of semiconductor processing events based on semiconductor processing events, execution content status, and processing progress status. This method considers the overall situation of semiconductor processing events, execution content status, and processing progress status, ensuring the accuracy of the analysis results of semiconductor processing events. At the same time, a semiconductor processing actuator is introduced, which outputs the execution status of sub-processing events, realizing the overall consideration of the execution status, corresponding execution priorities, and processing progress of multiple sub-processing events, thus improving the accuracy of the analysis results of semiconductor processing events.

[0116] At this point, the system first checks the execution status of all sub-processing events and combines them with their execution priorities determined in S131; the failure or success of high-priority tasks has a much greater impact on the overall evaluation than low-priority tasks.

[0117] The system determines the "execution content status" through a weighted decision tree or rule engine; COMPLETE: All sub-processing events, especially high-priority events on all critical paths, are SUCCESS; COMPLETE_WITH_WARNINGS: All high-priority events are SUCCESS, but one or more low-priority tasks on non-critical paths fail (e.g., TIMEOUT, DATA_NOT_FOUND); the core analysis conclusions are reliable, but some auxiliary information is missing; PARTIAL: At least one high-priority event fails, but some of its dependent downstream tasks can still be executed; the core analysis chain is damaged, and the conclusions are incomplete or inaccurate; FAILED: One or more critical upstream nodes (e.g., data query nodes) fail, causing the entire DAG execution chain to be interrupted.

[0118] The system calculates a quantified "processing progress" based on the structure of the DAG and the number of completed nodes; for example, the number of completed nodes / the total number of nodes. The system compares this quantified progress with a dynamic "expected progress," which can be estimated based on historical average execution time. ON_TRACK (normal): The actual progress is basically in line with the expected progress, or slightly ahead of schedule; DELAYED (delayed): Due to some nodes taking too long to execute or failing and retrying, the actual progress is significantly behind the expected progress; STALLED (stagnant): A critical node is in the RUNNING state for a long time or repeatedly fails, causing the entire analysis process to be stuck and the progress not to be updated for a long time; COMPLETED (completed): All nodes (or all executable nodes) have been processed.

[0119] The system integrates the following three parts of information in a structured manner: Semiconductor processing events: providing the basic background and objectives of the analysis; Execution content status: providing a meta-evaluation of the credibility and completeness of the analysis results; Processing progress status: providing a meta-evaluation of the efficiency of the analysis process; The final analysis result is not just a simple "qualified / unqualified" conclusion, but a structured data object or report that clearly presents "what the conclusion is," "how reliable the conclusion is," and "whether the process of reaching the conclusion was smooth"; The system delivers no longer a cold number, but a comprehensive intelligent analysis report with background, conclusion, confidence level, process record, and action recommendations, truly realizing a closed loop from data to decision.

[0120] Please see Figure 7 , Figure 7 This is a schematic diagram of the structural composition of the semiconductor processing event analysis system in an embodiment of the present invention; the semiconductor processing event analysis system includes: Semiconductor processing statement module 10 is used to collect semiconductor processing events and determine the corresponding semiconductor processing statements based on the analysis of the semiconductor processing events; The semiconductor processing task module 20 is used to determine the corresponding directed acyclic graph based on the semiconductor processing statement and the corresponding semiconductor processing planner; and to determine multiple semiconductor processing nodes based on the identification of the directed acyclic graph, with each semiconductor processing node matching the corresponding semiconductor processing task. The processing context information module 30 is used to determine the semiconductor processing sequence based on the node positions of multiple semiconductor processing nodes and preset semiconductor processing requirements; and to predict the corresponding processing context information based on the semiconductor processing sequence, the semiconductor processing tasks corresponding to each semiconductor processing node, and the node status. The subprocessing event module 40 is used to determine multiple subprocessing information based on the recognition of processing context information, and to determine the corresponding subprocessing event based on the multiple subprocessing information, the corresponding semiconductor processing node and semiconductor processing event; The analysis results module 50 is used to match the corresponding semiconductor processing actuator based on the semiconductor processing event, determine the execution status of the sub-processing event based on the semiconductor processing actuator, each sub-processing event and the node status corresponding to each semiconductor processing node, and determine the analysis results of the semiconductor processing event based on the execution status of multiple sub-processing events, the corresponding execution priority and the processing progress of the semiconductor processing event.

[0121] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method for analyzing semiconductor processing events, characterized in that, include: Step S1: Collect semiconductor processing events and determine the corresponding semiconductor processing statements based on the analysis of the semiconductor processing events; Step S2: Determine the corresponding directed acyclic graph based on the semiconductor processing statement and the corresponding semiconductor processing planner; determine multiple semiconductor processing nodes based on the identification of the directed acyclic graph, and match each semiconductor processing node with the corresponding semiconductor processing task; Step S3: Determine the semiconductor processing sequence based on the node positions of multiple semiconductor processing nodes and the preset semiconductor processing requirements; predict the corresponding processing context information based on the semiconductor processing sequence, the semiconductor processing tasks corresponding to each semiconductor processing node, and the node status. Step S4: Based on the identification of processing context information, determine multiple sub-processing information, and determine the corresponding sub-processing event according to the multiple sub-processing information, the corresponding semiconductor processing node, and the semiconductor processing event; Step S5: Match the corresponding semiconductor processing actuator based on the semiconductor processing event, determine the execution status of the sub-processing event according to the semiconductor processing actuator, each sub-processing event and the node status corresponding to each semiconductor processing node, and determine the analysis result of the semiconductor processing event based on the execution status of multiple sub-processing events, the corresponding execution priority and the processing progress of the semiconductor processing event.

2. The method for analyzing semiconductor processing events according to claim 1, characterized in that, Step S1 includes: Step S11: Monitor the semiconductor processing in real time and collect multiple processing data of the semiconductor. Determine the processing content of the semiconductor based on the multiple processing data and the corresponding processing technology. At the same time, collect the processing route of the semiconductor and determine the semiconductor processing event based on the semiconductor processing route, the semiconductor processing content and the corresponding position. Step S12: Based on the detection of semiconductor processing events, determine multiple sub-semiconductor processing events, and determine the corresponding semiconductor processing statement according to the processing content of the multiple sub-semiconductor processing events, the semiconductor processing area, and the corresponding semiconductor processing equipment.

3. The method for analyzing semiconductor processing events according to claim 1, characterized in that, Step S2 includes: Step S21: Collect the semiconductor processing statement, and determine multiple sub-processing segments of different dimensions based on the detection of the semiconductor processing statement. Each sub-processing segment presents the processing content of the corresponding dimension; determine the corresponding key processing content based on the identification of multiple sub-processing segments. Step S22: Collect the semiconductor processing planner corresponding to the semiconductor processing event, and determine the corresponding directed acyclic graph based on each key processing content, the corresponding sub-processing segment and the corresponding semiconductor processing planner; Step S23: Determine multiple semiconductor processing nodes based on the identification of the directed acyclic graph, and mark the node position of each semiconductor processing node; match the corresponding semiconductor processing task based on the detection of each semiconductor processing node.

4. The method for analyzing semiconductor processing events according to claim 1, characterized in that, Step S3 includes: Step S31: Collect multiple semiconductor processing nodes and present the corresponding semiconductor processing tasks. Determine the semiconductor processing sequence based on the semiconductor processing tasks, node positions, and preset semiconductor processing requirements of the multiple semiconductor processing nodes, and dynamically adjust the node positions of the multiple semiconductor processing nodes.

5. The method for analyzing semiconductor processing events according to claim 4, characterized in that, Step S3 further includes: Step S32: After the node positions of multiple semiconductor processing nodes are adjusted, the first semiconductor processing information is determined based on the semiconductor processing sequence and the semiconductor processing task corresponding to each semiconductor processing node. Step S33: Collect the current processing history of each semiconductor processing node, determine the node status of each semiconductor processing node based on the current processing history of each semiconductor processing node and the real-time processing image of the semiconductor, determine the second semiconductor processing information based on the semiconductor processing sequence and the node status of each semiconductor processing node, and predict the corresponding processing context information based on the first semiconductor processing information and the second semiconductor processing information.

6. The method for analyzing semiconductor processing events according to claim 1, characterized in that, Step S4 includes: Step S41: Collect processing context information, determine multiple sub-processing information based on the processing context information and corresponding information tags, and determine the first sub-processing information combination based on the multiple sub-processing information and corresponding semiconductor processing nodes.

7. The method for analyzing semiconductor processing events according to claim 6, characterized in that, Step S4 further includes: Step S42: Collect semiconductor processing events, determine the corresponding semiconductor processing area based on the semiconductor processing events and multiple sub-processing information, determine the second sub-processing information combination based on the semiconductor processing area and the corresponding semiconductor processing node, and determine the corresponding sub-processing event based on the first sub-processing information combination and the second sub-processing information combination.

8. The method for analyzing semiconductor processing events according to claim 1, characterized in that, Step S5 includes: Step S51: Based on the analysis of semiconductor processing events, determine multiple processing factors, match the corresponding semiconductor processing actuators according to the multiple processing factors, the overall shape of the semiconductor and the semiconductor database, and determine the first execution parameters of the sub-processing events according to the semiconductor processing actuators and each sub-processing event; Step S52: Determine the second execution parameters of the sub-processing event based on the node status corresponding to the semiconductor processing actuator and each semiconductor processing node; determine the execution status of the sub-processing event based on the mapping relationship between the first execution parameters, the second execution parameters and the execution status corresponding to the sub-processing event.

9. The method for analyzing semiconductor processing events according to claim 8, characterized in that, Step S5 further includes: Step S53: Determine the corresponding execution priority based on the detection of multiple sub-processing events; determine the execution content status of the semiconductor processing event based on the execution status of multiple sub-processing events and their corresponding execution priorities; determine the processing progress status of the semiconductor processing event based on the execution status of multiple sub-processing events and the processing progress of the semiconductor processing event; and determine the analysis result of the semiconductor processing event based on the semiconductor processing event, its execution content status, and its processing progress status.

10. A semiconductor processing event analysis system, characterized in that, The semiconductor processing event analysis system is applied to the semiconductor processing event analysis method as described in any one of claims 1-9, and the semiconductor processing event analysis system comprises: The semiconductor processing statement module is used to collect semiconductor processing events and determine the corresponding semiconductor processing statements based on the analysis of these events. The semiconductor processing task module is used to determine the corresponding directed acyclic graph based on the semiconductor processing statement and the corresponding semiconductor processing planner; based on the identification of the directed acyclic graph, multiple semiconductor processing nodes are determined, and each semiconductor processing node is matched with a corresponding semiconductor processing task; The processing context information module is used to determine the semiconductor processing sequence based on the node positions of multiple semiconductor processing nodes and preset semiconductor processing requirements; and to predict the corresponding processing context information based on the semiconductor processing sequence, the semiconductor processing tasks corresponding to each semiconductor processing node, and the node status. The subprocessing event module is used to determine multiple subprocessing information based on the identification of processing context information, and to determine the corresponding subprocessing event based on the multiple subprocessing information, the corresponding semiconductor processing node, and the semiconductor processing event. The analysis results module is used to match the corresponding semiconductor processing actuators based on semiconductor processing events, determine the execution status of sub-processing events based on the semiconductor processing actuators, each sub-processing event, and the node status corresponding to each semiconductor processing node, and determine the analysis results of semiconductor processing events based on the execution status of multiple sub-processing events, their corresponding execution priorities, and the processing progress of semiconductor processing events.

Images