Timing management in serial data interface

Abstract

The invention relates to managing signal timing on a serial data interface of an electronic device. The electronic device includes an interface controller configured to drive an output interface. The interface controller receives a first clock signal and determines a low cycle length of the first clock signal. The interface controller dynamically determines a duty cycle of a second clock signal based on the low cycle length of the first clock signal. The second clock signal having the duty cycle is generated by the interface controller and provided to the output interface. In some embodiments, the interface controller determines an outgoing delay, an incoming delay, and a sample allowance time. A difference between the low cycle length of the first clock signal and a sum of the incoming delay and the outgoing delay may be further determined and applied to control the duty cycle of the second clock signal.

Description

Technical Field

[0001] This application generally relates to electronic circuits, including but not limited to methods, apparatus, structures, devices, and systems for managing signal timing on serial output interfaces of electronic devices or systems (e.g., those housed in server racks). Background Technology

[0002] Electronic devices often couple to peripherals via serial data buses, and one potential problem is clock-data misalignment due to signal latency. In serial communication, data bits are transmitted sequentially, and any delay in the signal can cause the receiving device to misinterpret the data. If the clock signal controlling the timing of data sampling is out of sync with the incoming data stream, bits may be read too early or too late, leading to misunderstandings of the transmitted information. This misalignment can be exacerbated by factors such as cable length, interference, interruptions in intermediate modules, and variations in processing speed between devices. Therefore, errors can occur in data transmission, resulting in corrupted information, system instability, or even complete failure to communicate. Properly managing signal integrity and ensuring precise synchronization between clock and data signals is crucial for maintaining effective communication in these setups. Summary of the Invention

[0003] Various embodiments of this application relate to methods, apparatuses, structures, devices, and systems for timing alignment of a processor clock signal and an incoming data stream for controlling an electronic device. According to some embodiments of this application disclosed herein, achieving precise synchronization between a first clock signal for the processor of an electronic device and an incoming data stream provided by a peripheral device coupled to the electronic device may result in loss of precise synchronization between the clock signal and the data signal. In some cases, the incoming data stream is generated by the peripheral device based on a second clock signal derived from the first clock signal and provided to the peripheral device with clock latency. The incoming data stream has a time shift relative to the first clock signal. The time shift includes both clock latency and its own data latency caused by the signal path coupling the output of the peripheral device to the input of the processor of the electronic device. In particular, in some cases, the signal path includes an interface controller (e.g., a complex programmable logic device (CPLD), a field-programmable gate array (FPGA) device), which may contribute to both clock latency and data latency. In some embodiments, the interface controller is configured to control the synchronization of the first clock signal with the incoming data stream by controlling the second clock signal provided to the peripheral device. The interface controller can partially or completely compensate for clock latency or data latency, thereby allowing the processor of the electronic device to properly process the incoming data stream based on a first clock signal, without the clock latency or data latency having an effect or an acceptable effect.

[0004] In one aspect, some embodiments include a method for managing signal timing of an electronic device (e.g., a server computer). The method is implemented at an interface controller coupled to and configured to drive a serial output interface of the electronic device. The method includes: receiving a first clock signal; determining a low-cycle length of the first clock signal; dynamically determining a duty cycle of a second clock signal based on the low-cycle length of the first clock signal; and generating a second clock signal having a duty cycle (e.g., by varying the edge shift time of the second clock signal without any change in the duty cycle).

[0005] In some implementations, determining the low cycle length of the first clock signal further includes determining the period and duty cycle of the first clock signal. The low cycle length of the first clock signal is determined based on the period and duty cycle of the first clock signal.

[0006] In some embodiments, the method further includes determining the outgoing delay and incoming delay of the interface controller, and the duty cycle of the second clock signal is determined based on the sum of the outgoing delay and incoming delay of the interface controller.

[0007] In some embodiments, the method further includes determining a sampling allowance time for the host processor. An interface controller is configured to couple between the host processor and a serial output interface. The sampling allowance time defines a time length limitation between the edge of a host-incoming serial signal and a first clock signal of the host processor. The duty cycle of a second clock signal is determined based on the sampling allowance time.

[0008] In another embodiment, some implementations include an electronic device (e.g., a server computer). The electronic device includes: a host processor configured to provide a first clock signal and process host-incoming serial signals; an interface controller coupled to the host processor; and a serial output interface coupled to the interface controller. The interface controller is configured to receive the first clock signal, determine a low-cycle length of the first clock signal, dynamically determine a duty cycle of a second clock signal based on the low-cycle length of the first clock signal, and generate a second clock signal having the duty cycle. The serial output interface is configured to be coupled to a peripheral device and provide the second clock signal to the peripheral device.

[0009] In another aspect, some embodiments include a non-transitory computer-readable storage medium storing one or more programs for execution by an interface controller. The interface controller is configured to drive a serial output interface of an electronic device. The one or more programs further include receiving a first clock signal, determining a low-cycle length of the first clock signal, dynamically determining a duty cycle of a second clock signal based on the low-cycle length of the first clock signal, and generating a second clock signal having the duty cycle.

[0010] These illustrative embodiments and implementations are mentioned not to limit or restrict this disclosure, but to provide examples to aid in understanding it. Additional embodiments are discussed in the detailed description and are further described herein. Attached Figure Description

[0011] To better understand the various described implementation schemes, refer to the detailed implementation methods below in conjunction with the following figures, where the same reference numerals refer to corresponding parts throughout the figures.

[0012] Figure 1 This is a front view of an instance server rack supporting one or more servers according to some embodiments.

[0013] Figure 2 According to some embodiments, it can be used as Figure 1 A block diagram of an example system module in a typical electronic device used in server applications.

[0014] Figure 3A This is a block diagram of an example electronic device according to some embodiments, including an interface controller coupled to a serial output interface.

[0015] Figure 3B This is a timing diagram of a set of sample signals including a first clock signal, a host-output serial signal, and an externally input serial signal, according to some embodiments.

[0016] Figure 4 This is a time map of multiple instance signals measured at the output of the host processor or first controller of an electronic device and the input of a peripheral device, according to some embodiments.

[0017] Figure 5 A timing diagram illustrating multiple instance compensation schemes associated with the duty cycle of a second clock signal according to some embodiments.

[0018] Figure 6 A timing diagram illustrating another example of a compensation scheme applied to modify the duty cycle of a second clock signal according to some embodiments.

[0019] Figure 7 For managing electronic devices according to some embodiments (e.g., Figure 1 The flowchart illustrates an example method for signal timing on the serial output interface of a server.

[0020] In a diagram, the same reference numerals refer to the corresponding parts in several views. Detailed Implementation

[0021] Specific embodiments will now be described in detail with reference to the accompanying drawings. In the following detailed description, numerous non-limiting specific details are set forth to aid in understanding the subject matter presented herein. However, it will be apparent to those skilled in the art that various alternatives may be used without departing from the scope of the claims, and that the subject matter may be practiced without these specific details.

[0022] Various embodiments of this application relate to methods, apparatuses, structures, devices, and systems for timing alignment of a clock signal and an incoming data stream for controlling a host processor of an electronic device (e.g., server 120). According to some embodiments of this application disclosed herein, achieving precise synchronization between a first clock signal for the host processor of the electronic device and an incoming data stream provided by a peripheral device coupled to the electronic device may result in loss of precision. The electronic device includes a serial output interface and an interface controller coupled to and configured to drive the serial output interface. The interface controller, for example, receives a first clock signal from the host processor of the electronic device, determines a low cycle length of the first clock signal, dynamically determines a duty cycle of a second clock signal based on the low cycle length of the first clock signal, and generates a second clock signal having the duty cycle. The duty cycle of the second clock signal is controlled to partially or completely compensate for clock latency or data latency, such that the first clock signal of the host processor of the electronic device is synchronized with the incoming data stream provided by the peripheral device based on the second clock signal.

[0023] Figure 1 This is a front view of an example server rack 100 (also referred to as a rack mount, rack cabinet, or simply rack) supporting one or more servers 120 according to some embodiments. The server rack 100 includes a frame 102 and a plurality of slots 104, and is used in a data center, server room, or network cabinet to support, organize, and manage multiple computing device modules 106 (e.g., servers 120, storage devices 116S and 116N, networking devices, and other types of hardware). Each of the plurality of slots 104 of the server rack 100 is configured to receive and support a corresponding computing device module 106. In some embodiments, the plurality of slots 104 includes at least one blank slot 104B that is not used to provide mechanical support to any device module 106 and can receive a device module 106 if needed. In some embodiments, the server rack 100 has a predefined width of 19 or 23 inches, a height of up to 84 inches or more, and a depth selected from 24, 32, 40, or 48 inches.

[0024] Examples of computing device modules 106 supported by multiple slots 104 of server rack 100 include, but are not limited to, firewall module 108, switch box 110, server 120, display device 112, keyboard 114, solid-state drive (SSD) 116S, network attached storage 116N, and uninterruptible power supply (UPS) 118. Each computing device module 106 plays a corresponding role in maintaining the network and computing environment. In some embodiments, firewall module 108 is a network security device that monitors and controls incoming and outgoing network traffic based on predetermined security rules, thereby establishing a barrier between a trusted internal network and an untrusted external network. Firewall module 108 may be placed near the network entry point to protect server rack 100 from unauthorized access, malware, and network attacks. In some embodiments, firewall module 108 includes packet filtering, stateful inspection, VPN support, and intrusion prevention system (IPS). In some embodiments, the switch box 110 is placed in conjunction with the firewall module 108 near the network entry point and configured to receive incoming signals and forward them (e.g., which may be converted to electrical signals) to different servers 120 mounted on the server rack 100. The switch box 110 is used in the server rack 100 to minimize cable length and ensure effective network traffic management. The switch box 110 may support different speeds (e.g., 800 gigabits per second, 1.6 Tbs, 3.2 Tbs), has multiple ports (24, 48, etc.), and provides features such as Virtual LAN (VLAN) support, PoE (Power over Ethernet), and managed or unmanaged capabilities.

[0025] The multiple computing device modules 106 of server rack 100 may include multiple servers 120, each configured to provide data, resources, services, or programs to other client devices via one or more wired or wireless communication networks. Each server 120 is mounted in a slot 104 of server rack 100 and configured to provide one or more services (e.g., website hosting, database management, and application support). Compared to individual client devices, the servers 120 mounted on server rack 100 can provide higher processing power, larger memory capacity, redundant power supplies, and hot-swappable components to achieve high availability and reliability. In some embodiments, one or more rack servers 120 include multiple graphics processing units (GPUs) configured to perform machine learning operations, for example, in a data center associated with machine learning tasks. In some embodiments, server 120 includes one or more processors, memory for storing one or more programs to be executed by the one or more processors, memory, and power supply components (e.g., ...). Figure 3A , Figure 3B and Figure 5The system enclosure of PSU 216 in the system.

[0026] The SSD 116S and NAS 116N are configured to provide storage space for server 120, which is mounted in server rack 100. The SSD uses flash memory to store data and, compared to hard disk drives (HDDs), exhibits high speed, low latency, durability, and lower power consumption, as well as different capacities and form factors. Conversely, the NAS 116N is a dedicated file storage device that provides data access to a network and allows a large number of different types of client devices to retrieve data from a centralized disk capacity. In some embodiments, the NAS 116N may have high capacity, redundant array of independent disks (RAID), support for multiple file sharing protocols (NFS, SMB / CIFS, FTP), user management, and backup features. In some embodiments, the SSD 116S is a storage drive for speed and is used, for example, within server 120 housed in the same server rack 100, while the NAS 116N is configured for file sharing, data backup, and remote access.

[0027] In some implementations, a UPS 118 is used to provide emergency power to other computing device modules 106 in the event of a power outage, allowing them to remain operational long enough to safely shut down or switch to an alternative power source. In examples, the UPS 118 is mounted in a server rack 100 or placed in a bottom slot to support its weight, thereby providing backup power to other computing device modules 106. The UPS 118 provides one or more of the following: battery backup, surge protection, voltage regulation, real-time monitoring, management software, and / or runtime based on capacity and load variations.

[0028] The server rack 100 further includes a plurality of mechanical structures configured to provide mechanical support for or facilitate access to a plurality of computing device modules 106. The plurality of mechanical structures includes one or more of the following: an open-frame rack (e.g., without doors or side panels), mounting rails, cable management features (e.g., arms, hooks, and trays), power strips, shelves, drawers, and concealed panels. In some embodiments, the plurality of mechanical structures also include a rack housing (e.g., a cabinet), lockable doors, and side panels to protect the computing device modules 106 from unauthorized access. In an example, the server rack 100 includes or is coupled to a plurality of panels configured to convert the server rack 100 into a server cabinet. In some embodiments, the server rack 100 further includes a cooling system or ventilation system to facilitate heat dissipation. Using the server rack 100 helps optimize space, improve cooling efficiency, simplify maintenance, and enhance the overall organization and management of information technology (IT) infrastructure.

[0029] Figure 2 According to some embodiments, it can be used as Figure 1 The diagram illustrates an example system module 200 in a typical electronic device used in server 120. This system module 200 in the electronic device includes at least a processor module 202, a memory module 204 for storing programs, instructions, and data, an input / output (I / O) controller 206, one or more communication interfaces such as a network interface 208, and one or more communication buses 240 for interconnecting these components. In some embodiments, the I / O controller 206 allows the processor module 202 to communicate with I / O devices (e.g., a keyboard, mouse, or touchpad) via a universal serial bus interface. In some embodiments, the network interface 208 includes one or more interfaces for Wi-Fi, Ethernet, and Bluetooth networks, each allowing the electronic device to exchange data with an external source (e.g., a server or another electronic device). In some embodiments, the communication bus 240 includes a circuitry (sometimes referred to as a chipset) that interconnects the various system components included in the system module 200 and controls communication between the system components.

[0030] In some embodiments, memory module 204 includes high-speed random access memory, such as DRAM, static random access memory (SRAM), double data rate (DDR) dynamic random access memory (RAM), or other random access solid-state memory devices. In some embodiments, memory module 204 includes non-volatile memory, such as one or more disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state memory devices. In some embodiments, memory module 204, or alternatively, one or more non-volatile memory devices within memory module 204, include non-transitory computer-readable storage media. In some embodiments, a memory slot is reserved on system module 200 for housing memory module 204. Once inserted into the memory slot, memory module 204 is integrated into system module 200.

[0031] In some embodiments, system module 200 further includes one or more components selected from memory controller 210, solid-state drive (SSD) 212, hard disk drive (HDD) 214, power supply unit (PSU) 216, power management integrated circuit (PMIC) 218, graphics module 220, and audio module 222. Memory controller 210 is configured to control communication between processor module 202 in the electronic device and memory components including memory module 204. SSD 212 is configured to apply integrated circuit assemblies to store data in the electronic device and, in many embodiments, is configured based on NAND or NOR memory. HDD 214 is a conventional data storage device for storing and retrieving digital information based on electromechanical disk. PSU 216 is configured to receive multiple power supply signals 260 and provide multiple DC power supplies 250 (e.g., 12V, 54V). PMIC 218 is configured to modulate multiple DC power supplies 250 to other desired DC voltage levels, such as 5V, 3.3V, or 1.8V, required by various components or circuits within the electronic device (e.g., processor module 202). Graphics module 220 is configured to generate output images to one or more display devices according to their desired image / video formats. Audio module 222 is configured to facilitate the input and output of audio signals to and from the electronic device under the control of a computer program.

[0032] It should be noted that the communication bus 240 also interconnects various system components including components 210 to 222 and controls communication between the system components.

[0033] Figure 3A This is a block diagram of an example electronic device 300 according to some embodiments, including an interface controller 320 coupled to a serial output interface 302. An example of the electronic device 300 is a server 120 mounted on a server rack 100. The electronic device 300 includes (e.g., Figure 2The processor module 202 comprises one or more processors 304, a serial output interface 302, and an interface controller 320. One or more processors 304 are coupled to the interface controller 320. Examples of the one or more processors 304 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a mobile processor, a multi-core processor, a quantum processor, and a digital signal processor (DSP). In some embodiments, the electronic device 300 further includes a first controller 314, which is also coupled to the serial output interface 302. In some embodiments, the electronic device 300 is coupled to a peripheral device 306 via the serial output interface 302 and configured to provide a clock signal and an outgoing serial signal 308 to the peripheral device 306 and to receive a peripheral incoming serial signal 310 from the peripheral device 306. In an example, the peripheral device 306 includes a flash memory device (e.g., NAND-based or NOR-based flash memory), and the serial output interface 302 of the electronic device 300 is mechanically and electrically coupled to the flash memory device. The clock signal and the output serial signal 308 are provided to the flash memory device via the serial output interface 302.

[0034] In some embodiments, the host device 330 includes one or more processors 304, a first controller 314, or both. An interface controller 320 is coupled between the host device 330 and a serial output interface 302 and configured to drive the serial output interface 302 to facilitate data communication between the host device 330 and a peripheral device 306. In some embodiments, the interface controller 320 is configured to receive a host-outgoing serial signal 312 from one or more processors 304 and determine whether the host-outgoing serial signal 312 satisfies data verification conditions. In some embodiments, the interface controller 320 includes one of a field-programmable gate array (FPGA) and a complex programmable logic device (CPLD). More specifically, an FPGA is an integrated circuit that can be configured after manufacturing and includes an array of programmable logic blocks that can be reconfigured to perform specific tasks. FPGAs can be customized or adapted in server systems in data centers (e.g., configured to implement high-performance computing and artificial intelligence or machine learning workloads). In some embodiments, a CPLD is a type of programmable logic device that provides a balance between the flexibility of an FPGA and the simplicity of a smaller programmable device. The CPLD is coupled to signal output interface 302 and configured to perform one or more control-oriented tasks, such as interfacing with and managing basic digital functions. The CPLD includes programmable logic blocks and interconnects, and employs non-volatile memory to retain its configuration even after power-off. In this example, the CPLD includes either glue logic or a state machine.

[0035] An example of the first controller 314 is a baseboard management controller (BMC), a dedicated microcontroller embedded in a server motherboard that enables remote management and monitoring of the server 120 independently of its operating system. The BMC is configured for out-of-band management, including but not limited to monitoring system health, viewing hardware status (temperature, fan speed, power supply), and even performing remote diagnostics, firmware updates, and server restarts. The BMC is used in some situations when the server 120 is unresponsive or the operating system has crashed. In some embodiments, the server 120 is used in data center and enterprise environments, and the BMC is used in the server 120 to control downtime and enable remote management. In some embodiments, the interface controller 320 receives a host-transmitted serial signal 312 from the first controller 314 (e.g., the BMC) and determines whether the host-transmitted serial signal 312 meets data verification conditions.

[0036] In some embodiments of this application, the interface controller 320 receives a first clock signal 316, determines a low cycle length of the first clock signal 316, dynamically determines the duty cycle of a second clock signal 318 based on the low cycle length of the first clock signal 316, and generates a second clock signal 318 having the duty cycle. The second clock signal 318 is provided to a peripheral device 306 and used to recover host data from a serial signal 308 emitted from the peripheral and serialized back to the host processor 330. Furthermore, in some embodiments, the interface controller 320 includes or is coupled to a non-volatile memory 322 that stores one or more of the following: an outgoing delay 324, an incoming delay 326, and a sampling allowance 328. The interface controller 320 extracts at least one of the outgoing delay 324, the incoming delay 326, and the sampling allowance 328 to determine the duty cycle of the second clock signal 318. In other words, at least one of the outgoing delay 324, the incoming delay 326, and the sampling allowance time 328 can be precalibrated and stored as a specification of the electronic device 300, and does not need to be measured every time during the process of controlling the duty cycle of the second clock signal 318.

[0037] Figure 3BThis is a timing diagram of a sample signal set 350 according to some embodiments, including a first clock signal 316, a host output serial signal 312, and a peripheral input serial signal 310. Electronic device 300 is electrically coupled to peripheral device 306 and sends the first clock signal 316 and the host output serial signal 312 carrying host data (also referred to as first serial data) to peripheral device 306 by means of interface controller 320. Interface controller 320 may output a second clock signal 318 and an output serial signal 308 based on the first clock signal 316 and the host output serial signal 312. After receiving signals 308 and 318 from serial output interface 302, peripheral device 306 extracts host data from output serial signal 308 based on the second clock signal 318 and generates peripheral data (e.g., based on the extracted host data). Peripheral device 306 further generates a peripheral input serial signal 310 carrying the peripheral data and returns it to electronic device 300. The interface controller 320 receives the external input serial signal 310 via the serial output interface 302 and generates a host input serial signal 332 carrying external data. The host input serial signal 332 has an input delay of 326 relative to the external input serial signal 310.

[0038] In some embodiments, one or more processors 304 and the first controller 314 act as a host processor 330 to generate a first clock signal 316 and a host outgoing serial signal 312 and receive a host incoming serial signal 332. From the host's perspective, host data is extracted from the rising edge of the host outgoing serial signal 312, and peripheral data is written into the host incoming serial signal 332 near the falling edge of the first clock signal 316, thereby allowing peripheral data to be extracted from the host incoming serial signal 332 at the rising edge of the first clock signal 316. Alternatively, in some embodiments not shown, host data is extracted from the falling edge of the host outgoing serial signal 312, and peripheral data is written into the host incoming serial signal 332 near the rising edge of the first clock signal 316, thereby allowing peripheral data to be extracted from the host incoming serial signal 332 at the falling edge of the first clock signal 316.

[0039] Figure 4 This is a timing map of multiple instance signals 400 measured at the output of the host processor 330 or the first controller 314 of the electronic device 300 and the input of the peripheral device 306, according to some embodiments. The electronic device 300 includes an interface controller 320 and a serial output interface 302, and is coupled to the peripheral device 306 via the serial output interface 302. The electronic device 300 is configured to provide a second clock signal 318 and a peripheral outgoing serial signal 308 to the peripheral device 306 and to receive a peripheral incoming serial signal 310 from the peripheral device 306.

[0040] In some embodiments, one of the processor 304 and the first controller 314 acts as the host processor 330. Figure 3A The host processor 330 generates a first clock signal 316, and the interface controller 320 receives the first clock signal 316 and generates a second clock signal 318. The rising edge of the second clock signal 318 has a rising edge delay 402 relative to the rising edge of the first clock signal 316. In some embodiments, the falling edge of the second clock signal 318 has an outgoing delay 324 (e.g., a falling edge delay) relative to the falling edge of the first clock signal 316. In one example, the falling edge of the second clock signal 318 follows the falling edge of the first clock signal 316 and is not adjusted by the interface controller 320. In another example, the falling edge of the second clock signal 318 follows the falling edge of the first clock signal 316 and is adjusted by the interface controller 320 to be closer to the falling edge of the first clock signal 316. In yet another example, the falling edge of the second clock signal 318 is generated after the rising edge of the second clock signal 318, regardless of whether the interface controller 320 receives the falling edge of the first clock signal 316. The falling edge of the second clock signal 318 may occur before or simultaneously with the falling edge of the first clock signal 316.

[0041] In some embodiments, the host processor 330 generates a host outgoing serial signal 312 carrying host data and sends it to the peripheral device 306. The interface controller 320 generates a peripheral outgoing serial signal 308 based on the host outgoing serial signal 312. After receiving signals 308 and 318, the peripheral device 306 extracts host data from the outgoing serial signal 308 based on a second clock signal 318.

[0042] In some embodiments, peripheral device 306 generates a peripheral incoming serial signal 310 carrying peripheral data and returns it to host processor 330. In some embodiments, peripheral device 306 generates the peripheral incoming serial signal 310 carrying peripheral data based on the falling edge of a second clock signal 318. Interface controller 320 receives the peripheral incoming serial signal 310 and generates a host incoming serial signal 332 carrying peripheral data. The host incoming serial signal 332 has an incoming delay 326 relative to the peripheral incoming serial signal 310. In some embodiments, host processor 330 extracts peripheral data from the host incoming serial signal 332 based on the rising edge of a first clock signal 316.

[0043] refer to Figure 4In some embodiments, signal readout operations occur at the rising edge of either the first clock signal 316 or the second clock signal 318, and signal write operations occur at the falling edge of either the first clock signal 316 or the second clock signal 318. The first clock signal 316 has a low cycle length 408. The low cycle length 408 is the sum of the outgoing delay 324, the incoming delay 326, and the time margin 410. The time margin 410 measures the time distance between the edge of the host incoming serial signal 332 and the rising edge of the first clock signal 316. In some embodiments, the time margin 410 needs to be equal to or greater than the sampling allowance time 328, which defines the time length limit between the edges of the host incoming serial signal 332 and the first clock signal 316. In some cases, the time margin 410 is less than the sampling allowance time 328. The edges of the host incoming serial signal 332 and the first clock signal 316 are close together, making it impossible for the host processor 330 to extract peripheral data from the host incoming serial signal 332. Conversely, in some cases, when the time tolerance 410 is greater than or equal to the sampling allowable time 328, the host processor 330 can appropriately extract peripheral data from the serial signal 332 transmitted from the host.

[0044] exist Figure 4 In some embodiments not shown, signal readout operations occur at the falling edge of the first clock signal 316 or the second clock signal 318, and signal write operations occur at the rising edge of the first clock signal 316 or the second clock signal 318. The first clock signal 316 has a high cycle length. The high cycle length is the sum of the rising edge delay 402, the incoming delay 326, and the time margin. The time margin measures the time distance between the edge of the host incoming serial signal 332 and the falling edge of the first clock signal 316. In some embodiments, the time margin 410 needs to be equal to or greater than the associated sampling allowance time 328 to properly extract peripheral data from the host incoming serial signal 332.

[0045] In various embodiments of this application, the duty cycle of the second clock signal 318 is dynamically determined based on the low cycle length 408 of the first clock signal 316. In some examples, the first clock signal 316 has a known duty cycle, and the low cycle length 408 of the first clock signal 316 may be determined based on the period of the first clock signal 316. Furthermore, in some embodiments, a time tolerance 410 is determined based on the low cycle length 408, the outgoing delay 324, and the incoming delay 326, and said time tolerance is compared with a sampling allowance 328 to determine whether and by how much the edge of the second clock signal 318 associated with the generation of the peripheral incoming serial signal 310 needs to be moved. The time variation of the edge of the second clock signal 318 represents a variation in the duty cycle of the second clock signal 318.

[0046] Figure 5 To illustrate a timing diagram of multiple instance compensation schemes 500 associated with the duty cycle of a second clock signal 318 according to some embodiments. Interface controller 320 receives a first clock signal 316 and determines a low-cycle length 408 of the first clock signal 316. Interface controller 320 dynamically determines the duty cycle of the second clock signal 318 based on the low-cycle length 408 of the first clock signal 316 and generates a second clock signal 318 having the duty cycle. In some embodiments, interface controller 320 determines the low-cycle length 408 of the first clock signal 316 by determining the period T and the duty cycle D1 of the first clock signal 316. The low-cycle length 408 of the first clock signal 316 is determined based on the period T and the duty cycle D1 of the first clock signal 316. For example, the low-cycle length 408 of the first clock signal 316 is equal to T × (1 - D1).

[0047] In general, in some embodiments, the interface controller 320 determines an outgoing delay 324 and an incoming delay 326, and the duty cycle of the second clock signal 318 is determined based on the sum of the outgoing delay 324 and the incoming delay 326. In some embodiments, the interface controller 320 is coupled between a host processor 330 (e.g., one or more processors 304, a first controller 314) of the electronic device 300 and a serial output interface 302. The interface controller 320 determines a sampling allowance time 328 for the host processor 330 (e.g., one or more processors 304, a first controller 314), and the sampling allowance time 328 defines a time length limit between the edges of the host incoming serial signal 332 and the first clock signal 316 of the host processor 330. If the edges of the host incoming serial signal 332 and the first clock signal 316 of the host processor 330 are too close to each other, for example, within the sampling allowance time 328, then the host processor 330 cannot extract peripheral data provided by the peripheral device 306 from the first clock signal 316. The duty cycle of the second clock signal 318 is determined based on the sampling allowance time 328.

[0048] More specifically, in some embodiments, the interface controller 320 determines one or more of the following: the outgoing delay 324 of the second clock signal 318 relative to the first clock signal 316, the incoming delay 326 of the host incoming serial signal 332 relative to the peripheral incoming serial signal 310, and the sampling allowance 328 of the host processor 330 (e.g., one or more processors 304, the first controller 314). The interface controller 320 is coupled between the host processor 330 and the serial output interface 302, and the sampling allowance 328 defines a time length limitation between the edges of the host incoming serial signal 332 and the first clock signal 316 of the host processor 330. Furthermore, in some embodiments, one or more of the outgoing delay 324, the incoming delay 326, and the sampling allowance 328 are retrieved from the memory 322. Alternatively, in some embodiments, one or more of the outgoing delay 324, the incoming delay 326, and the sampling allowance 328 are determined by the interface controller 320 in real time.

[0049] In some embodiments, the interface controller 320 determines a first difference 502 between the low cycle length 408 of the first clock signal 316 and the sum of the incoming delay 326 and the outgoing delay 324 (e.g., corresponding to...). Figure 4 The interface controller 320 determines whether to change the duty cycle of the second clock signal 318 based on a time tolerance 410 and a first difference 502. Furthermore, in some embodiments associated with the host incoming serial signal 332-1, the interface controller 320 maintains the duty cycle of the second clock signal 318 unchanged based on a determination that the first difference 502 is equal to or greater than the sampling allowance 328 of the host processor 330 (e.g., one or more processors 304, the first controller 314). In other words, in some cases, the sum of the outgoing delay 324, the sampling allowance 328, and the incoming delay 326-1 is less than the low cycle length 408 of the first clock signal 316. Adjustment of the duty cycle of the second clock signal 318 is not required.

[0050] Conversely, in some embodiments associated with the host incoming serial signal 332-2, based on the determination that the first difference 502' is less than the sampling allowance 328 of the host processor 330 (e.g., one or more processors 304, the first controller 314), the interface controller 320 increases the low cycle length of the second clock signal 318 by a time variation 404, thereby changing the duty cycle of the second clock signal 318. In some instances, the first difference 502' is negative. In other words, in some cases, the sum of the outgoing delay 324, the sampling allowance 328, and the incoming delay 326-2 is greater than the low cycle length 408 of the first clock signal 316. The time variation 404 is equal to or greater than the second difference between the sum of the outgoing delay 324, the sampling allowance 328, and the incoming delay 326 and the low cycle length of the first clock signal 316.

[0051] In this example, time variation 404 is applied to the falling edge 504 of the second clock signal 318. In some embodiments, the falling edge of the second clock signal 318 is generated after the rising edge of the second clock signal 318, regardless of whether the falling edge of the first clock signal 318 occurs at the host processor 330. The falling edge 504 of the second clock signal 318 may precede or follow the corresponding falling edge 506 of the first clock signal 316.

[0052] In some embodiments, the interface controller 320 determines a high time width 406 based on the duty cycle of a second clock signal 318, which is dynamically determined based on a low cycle length 408 of a first clock signal 316. The interface controller 320 terminates the high voltage level of the second clock signal 318 in response to the termination of the high time width 406 measured from the corresponding rising edge of the second clock signal 318. Alternatively, in some embodiments, the interface controller 320 determines a time distance 414 of the falling edge of the second clock signal 318 measured from the rising edge of the first clock signal 316, for example, as the sum of the rising edge delay 402 and the high time width 406. The interface controller 320 terminates the high voltage level of the second clock signal 318 in response to the termination of the time distance 414 measured from the corresponding rising edge of the first clock signal 316.

[0053] In some embodiments, the first clock signal 316 has multiple rising edges 508. The interface controller 320 receives a host outgoing serial signal 312, which includes first serial data (also referred to as host data), in conjunction with the first clock signal 316 from a host processor 330 (e.g., one or more processors 304), and the host outgoing serial signal 312 is synchronized with the multiple rising edges 508 of the first clock signal 316. Furthermore, in some embodiments, the first clock signal 316 has multiple falling edges 506. The interface controller 320 receives a peripheral incoming serial signal 310 from a peripheral device 306 (FIG. 3) coupled to the electronics 300, and the host processor 330 (e.g., one or more processors 304) processes second serial data (also referred to as peripheral data) in the peripheral incoming serial signal 310 based on the multiple falling edges 506 of the first clock signal 316.

[0054] In some embodiments, the serial output interface 302 conforms to high-speed data communication protocols, such as Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), and Peripheral Component Interconnect High Speed ​​(PCIe). A first clock signal 316 has a baseband frequency and is applied to exchange data at the baseband frequency (e.g., during equalization) for the purpose of establishing data communication between the electronic device 300 and the peripheral device 306 at high data rates. High data rates are achieved through a data clock frequency greater than the baseband frequency. Examples of baseband frequencies include 100 MHz, and examples of high data rates include, but are not limited to, 5 to 40 gigabits per second (Gbps), 20 Gbps, 40 Gbps, 1.5 to 6 Gbps (SATA) for USB 3.0 and above, and 4 to 128 gigabits per second (GB / s) for PCIe.

[0055] Figure 6 To illustrate another example of a compensation scheme 600 applied to modify the duty cycle of a second clock signal 318 according to some embodiments, a timing diagram is provided. The interface controller 320 of the electronic device 300 (FIG. 3) determines the low cycle length 408 of the first clock signal 316 with an input delay 326 (e.g., ...). Figure 5 The first difference 502' between the sum of the delay 326-2 in the middle and the output delay 324 (in the middle) and the output delay 324 Figure 5 Based on the determination that the first difference 502' is less than the sampling allowance time 328 of the host processor 330 (e.g., one or more processors 304, the first controller 314), the interface controller 320 increases the low cycle length of the second clock signal 318 by a time variation 602, thereby changing the duty cycle of the second clock signal 318. For example, the duty cycle of the second clock signal 318 corresponds to the high cycle length of the second clock signal 318 and decreases based on the time variation 602.

[0056] In some embodiments, the sum of the outgoing delay 324, the sampling allowance time 328, and the incoming delay 326-2 is greater than the low cycle length 408 of the first clock signal 316. The time variation 602 is equal to or greater than a second difference between the sum of the outgoing delay 324, the sampling allowance time 328, and the incoming delay 326, and the low cycle length 408 of the first clock signal 316. In these ways, the time length 604 between the edge of the host incoming serial signal 332 and the first clock signal 316 of the host processor 330 is greater than the sampling allowance time 328, and peripheral data can be appropriately extracted from the host incoming serial signal 332.

[0057] In some embodiments, the rising edge of the second clock signal 318 has a rising edge delay 402 relative to the rising edge 508 of the first clock signal 316. At the rising edge 508 of the first clock signal, the interface controller 320 starts a timeout counter to terminate the high voltage level of the second clock signal 318 after a timeout length 606, and the second clock signal 318 falls to a low voltage level with a timeout delay 608. The combination of the timeout length 606 and the timeout delay 608 produces a time distance 414 (measured from the rising edge 508 of the first clock signal 316) of the falling edge 504 of the second clock signal 318. Figure 4 As explained above, the time interval 414 is also equal to the sum of the rising edge delay 402 and the high time width 406. In other words, the duty cycle of the second clock signal 318 is dynamically determined based on the low cycle length 408 of the first clock signal 316 and is further applied to derive the timeout length 606. The timeout counter can further control each falling edge 504 of the second clock signal 316 based on the timeout length 606 relative to the corresponding rising edge 508 of the first clock signal 316.

[0058] Figure 7 For managing electronic device 300 according to some embodiments (e.g., Figure 1 The flowchart illustrates an example method 700 for signal timing on a serial output interface 302 of a server 120. In some embodiments, method 700 is implemented at an electronic device 300 having a serial output interface and an interface controller 320. The interface controller 320 is configured to drive the serial output interface of the electronic device 300. More specifically, in some embodiments, method 700 is implemented at the interface controller 320 of the electronic device 300 (operation 701). Method 700 is optionally controlled by instructions stored in a non-transitory computer-readable storage medium and executed by the electronic device 300 (e.g., by the interface controller 320). Figure 7 Each of the operations shown may correspond to instructions stored in computer memory or a non-transitory computer-readable storage medium. The computer-readable storage medium may include a disk or optical disk storage device, a solid-state storage device such as flash memory, or one or more other non-volatile memory devices. Instructions stored on the computer-readable storage medium may include one or more of the following: source code, assembly language code, object code, or other instruction formats interpreted by the interface controller 320. Some operations in method 700 may be combined, and / or the order of some operations may be changed.

[0059] Interface controller 320 is configured to drive serial output interface 302 of electronic device 300. Interface controller 320 receives (operation 702) a first clock signal 316, determines (operation 704) the low cycle length 408 of the first clock signal 316, dynamically determines (operation 706) the duty cycle of a second clock signal 318 based on the low cycle length 408 of the first clock signal 316, and generates (operation 708) a second clock signal 318 having a duty cycle.

[0060] In some embodiments, the interface controller 320 determines the outgoing delay 324 and the incoming delay 326 of the interface controller 320, and the duty cycle of the second clock signal 318 is determined based on the sum of the outgoing delay 324 and the incoming delay 326 of the interface controller 320.

[0061] In some embodiments, interface controller 320 determines a sampling allowance time 328 for host processor 330. Interface controller 320 is configured to couple between host processor 330 and serial output interface 302. The sampling allowance time 328 defines a time length limitation between the edge of host-incoming serial signal 332 and the edge of first clock signal 316 of host processor 330. The duty cycle of second clock signal 318 is determined based on sampling allowance time 328.

[0062] In some embodiments, when the interface controller 320 determines the low cycle length 408 of the first clock signal 316, the interface controller 320 determines (operation 710) the period T and duty cycle D1 of the first clock signal 316. The low cycle length 408 of the first clock signal 316 is determined based on the period and duty cycle of the first clock signal 316.

[0063] In some embodiments, interface controller 320 determines (operation 712) one or more of the following: an outgoing delay 324 of the second clock signal 318 relative to the first clock signal 316, an incoming delay 326 of the host incoming serial signal 332 relative to the peripheral incoming serial signal 310, and a sampling allowance 328 of the host processor 330. Interface controller 320 is coupled between host processor 330 and serial output interface 302, and the sampling allowance 328 defines a time length limitation between the edges of the host incoming serial signal 332 and the first clock signal 316 of host processor 330. Furthermore, in some embodiments, one or more of the outgoing delay 324, incoming delay 326, and sampling allowance 328 are retrieved (operation 714) from memory 322 (FIG. 3).

[0064] In some embodiments, interface controller 320 determines (operation 716) a first difference 502 between the low cycle length 408 of the first clock signal 316 and the sum of the incoming delay 326 and the outgoing delay 324, and determines (operation 718) whether to change the duty cycle of the second clock signal 318 based on the first difference 502. Additionally, in some embodiments, based on the determination that the first difference 502 is equal to or greater than the sampling allowance 328 of the host processor 330, interface controller 320 maintains (operation 720) the duty cycle of the second clock signal 318 unchanged. Conversely, in some embodiments, based on the determination that the first difference 502 is less than the sampling allowance 328 of the host processor 330, interface controller 320 increases (operation 722) the low cycle length 408 of the second clock signal 318 by a time variation 602. Figure 6 In some embodiments, the time variation 602 is equal to or greater than the second difference between the sum of the outgoing delay 324, the sampling allowance time 328, and the incoming delay 326 and the low cycle length 408 of the first clock signal 316.

[0065] In some embodiments, the duty cycle of the second clock signal 318 corresponds to the time variation 602 of the falling edge of the second clock signal 318, and the time variation 602 is equal to or greater than the second difference between the sum of the outgoing delay 324, the sampling allowance time 328 and the incoming delay 326 and the low cycle length 408 of the first clock signal 316.

[0066] In some embodiments, the interface controller 320 determines the time distance from the rising edge of either the first clock signal 316 or the second clock signal 318 based on the duty cycle of the second clock signal 318. For example, the high time width is 406 ( Figure 4 The time distance 414 is determined to be the time distance from the rising edge of the second clock signal 318. In another example, the time distance 414 is determined from the rising edge of the first clock signal 316. Figure 4 The interface controller 320 generates a second clock signal 318 having a duty cycle by terminating the high voltage level of the second clock signal 318 in response to the termination of a time distance measured from the rising edge of one of the first clock signal 316 and the second clock signal 318.

[0067] In some embodiments, the first clock signal 316 has multiple rising edges 508. An interface controller 320 receives a host outgoing serial signal 312, which includes first serial data (e.g., host data), in conjunction with the first clock signal 316, from a host processor 330 of the electronic device 300. The host outgoing serial signal 312 is synchronized with the multiple rising edges of the first clock signal 316. Furthermore, in some embodiments, the first clock signal 316 has multiple falling edges 506. The interface controller 320 receives a peripheral incoming serial signal 310 from a peripheral device coupled to the electronic device 300. The host processor 330 is configured to process second serial data in the peripheral incoming serial signal 310 based on the multiple falling edges of the first clock signal 316.

[0068] In some embodiments, the electronic device 300 includes an interface controller 320 and at least one of a central processing unit (CPU) and a baseboard management controller (BMC) 314, and the interface controller 320 receives a first clock signal 316 from at least one of the CPU and the BMC 314.

[0069] In some embodiments, the serial output interface 302 is coupled to the flash memory device, and the second clock signal 318 is provided to the flash memory device.

[0070] In some embodiments, the interface controller 320 receives the serial signal 312 transmitted from the host and determines whether the serial signal 312 transmitted from the host meets the data verification conditions.

[0071] In some embodiments, the interface controller 320 receives a host output serial signal 312 associated with a first clock signal 316 from the host processor 330 of the electronic device 300, and receives a peripheral input serial signal 310 via the serial output interface 302.

[0072] In some embodiments, the interface controller 320 includes one of a field-programmable gate array (FPGA) and a complex programmable logic device (CPLD).

[0073] It should be understood that in some embodiments, the incoming delay 326 and the outgoing delay 324 are at least partially caused by the interface controller 320, and different controllers of the electronic device are applied to implement method 700 to determine the duty cycle of the second clock signal 318 and control the interface controller 320 to move the edges of the second clock signal 318 accordingly, thereby compensating for delays 324 and 326.

[0074] It should be understood that the description has been made. Figure 7The specific order of operations described herein is merely illustrative and is not intended to indicate that the described order is the only possible order of executable operations. Those skilled in the art will recognize various ways to manage signal timing on serial data interfaces as described herein. Additionally, it should be noted that the timing of operations described herein is relative to other figures (e.g., Figures 1 to 6 The details of other processes described can also be similar to those described above. Figure 7 The method described is applied in the manner of 700. For the sake of brevity, these details will not be repeated here.

[0075] The terminology used in the description of the various described embodiments herein is for the purpose of describing a particular embodiment only and is not intended to be restrictive. As used in the description of the various described embodiments and the appended claims, the singular forms “a(a)”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and / or” as used herein refers to and covers any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “includes,” “including,” “comprises,” and / or “comprising,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, it will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another.

[0076] As used herein, depending on the context, the term "if" may optionally be interpreted as "when," "at," "in response to determining," "in response to detecting," or "according to the determination of." Similarly, depending on the context, the phrase "if determining," or "if [the stated condition or event] is optionally interpreted as "in response to determining," "when [the stated condition or event] is detected," or "in response to detecting [the stated condition or event]," or "according to the determination of detecting [the stated condition or event]."

[0077] For purposes of explanation, the foregoing description has been described with reference to specific embodiments. However, the above illustrative discussions are not intended to be exhaustive or to limit the claims to the precise form disclosed. Many modifications and variations are possible in light of the foregoing teachings. The embodiments were chosen and described in order to best explain the operating principles and practical applications, thereby enabling others skilled in the art to implement them.

[0078] Although various diagrams illustrate multiple logical phases in a specific order, phases that are not sequentially related can be reordered, and other phases can be combined or decomposed. While some reorderings or other groupings are specifically mentioned, other reorderings or groupings will be apparent to those skilled in the art, and therefore the orderings and groupings presented herein are not an exhaustive list of alternatives. Furthermore, it should be recognized that phases can be implemented in hardware, firmware, software, or any combination thereof.

Claims

1. A method for managing signal timing in an electronic device, comprising: At the interface controller, wherein the interface controller is configured to drive the serial output interface of the electronic device: Receive the first clock signal; Determine the low cycle length of the first clock signal; The duty cycle of the second clock signal is dynamically determined based on the low cycle length of the first clock signal; and A second clock signal with the stated duty cycle is generated.

2. The method of claim 1, further comprising determining the outgoing delay and incoming delay of the interface controller, wherein the duty cycle of the second clock signal is determined based on the sum of the outgoing delay and the incoming delay of the interface controller.

3. The method of claim 1, further comprising determining a sampling allowance time for the host processor, wherein: The interface controller is configured to be coupled between the host processor and the serial output interface; The sampling allowable time defines the time length limit between the edge of the host-input serial signal and the first clock signal of the host processor; and The duty cycle of the second clock signal is determined based on the sampling allowance time.

4. The method of claim 1, wherein determining the low cycle length of the first clock signal further comprises: The period and duty cycle of the first clock signal are determined, wherein the low cycle length of the first clock signal is determined based on the period and the duty cycle of the first clock signal.

5. The method of claim 1, further comprising determining one or more of the following: The second clock signal is delayed relative to the first clock signal. The input delay of the host-input serial signal relative to the input serial signal from the external source; and The sampling allowance time of the host processor, wherein the interface controller is coupled between the host processor and the serial output interface, the sampling allowance time defines the time length limit between the edge of the host-input serial signal and the first clock signal of the host processor.

6. The method of claim 5, wherein determining one or more of the outgoing delay, the incoming delay, and the sampling allowance time further comprises: Retrieve one or more of the outgoing delay, the incoming delay, and the sampling allowance from memory.

7. The method of claim 5, further comprising: Determine a first difference between the low cycle length of the first clock signal and the sum of the input delay and the output delay; and The duty cycle of the second clock signal is determined based on the first difference.

8. The method of claim 7, wherein determining the duty cycle of the second clock signal further comprises: Based on the determination that the first difference is equal to or greater than the sampling allowable time of the host processor, the duty cycle of the second clock signal is maintained unchanged.

9. The method of claim 7, wherein determining the duty cycle of the second clock signal further comprises: Based on the determination that the first difference is less than the sampling allowable time of the host processor, the low cycle length of the second clock signal is increased by time variation; The time variation is equal to or greater than the second difference between the sum of the outgoing delay, the sampling allowance time, and the incoming delay, and the low cycle length of the first clock signal.

10. The method of claim 5, wherein the duty cycle of the second clock signal corresponds to the time variation of the falling edge of the second clock signal, and the time variation is equal to or greater than the second difference between the sum of the outgoing delay, the sampling allowance time, and the incoming delay and the low cycle length of the first clock signal.

11. The method of claim 1, further comprising: The time distance from the rising edge of either the first clock signal or the second clock signal is determined based on the duty cycle of the second clock signal; The generation of the second clock signal having the duty cycle further includes terminating the high voltage level of the second clock signal in response to the termination of the time distance measured from the rising edge of one of the first clock signal and the second clock signal.

12. The method of claim 1, wherein the first clock signal has a plurality of rising edges, the method further comprising: The host processor of the electronic device receives a host output serial signal comprising first serial data in conjunction with the first clock signal, wherein the host output serial signal is synchronized with the plurality of rising edges of the first clock signal.

13. The method of claim 12, wherein the first clock signal has a plurality of falling edges, the method further comprising: A peripheral incoming serial signal is received from a peripheral device coupled to the electronic device, wherein the host processor is configured to process second serial data in the peripheral incoming serial signal based on the plurality of falling edges of the first clock signal.

14. The method of claim 1, wherein the electronic device includes the interface controller and at least one of a central processing unit (CPU) and a baseboard management controller (BMC), and the interface controller receives the first clock signal from the at least one of the CPU and the BMC.

15. The method of claim 1, wherein the serial output interface is coupled to the flash memory device, and the second clock signal is provided to the flash memory device.

16. The method of claim 1, further comprising receiving a serial signal transmitted from a host and determining whether the serial signal transmitted from the host satisfies the data verification conditions.

17. The method of claim 1, further comprising: Receives a serial signal from the host processor of the electronic device, which is combined with the first clock signal; and The serial output interface receives serial signals from external sources.

18. The method of claim 1, wherein the interface controller comprises one of a field-programmable gate array (FPGA) and a complex programmable logic device (CPLD).

19. An electronic device comprising: A host processor configured to provide a first clock signal and process serial signals received from the host. An interface controller, coupled to the host processor, is configured to: Receive the first clock signal; Determine the low cycle length of the first clock signal; The duty cycle of the second clock signal is dynamically determined based on the low cycle length of the first clock signal; and Generate a second clock signal having the stated duty cycle; and A serial output interface coupled to the interface controller, the serial output interface being configured to be coupled to a peripheral device and to provide the second clock signal to the peripheral device.

20. A non-transitory computer-readable storage medium storing one or more programs for execution by an interface controller, said one or more programs further comprising instructions for: At the interface controller, wherein the interface controller is configured to drive the serial output interface of the electronic device: Receive the first clock signal; Determine the low cycle length of the first clock signal; The duty cycle of the second clock signal is dynamically determined based on the low cycle length of the first clock signal; and A second clock signal with the stated duty cycle is generated.

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