Output impedance calibration and related apparatus, systems, and methods

Abstract

Output impedance calibration and related apparatuses, systems, and methods are disclosed. An apparatus can include a plurality of drivers, where each driver of the plurality of drivers includes a plurality of transistors coupled to an output node. The apparatus can further include circuitry coupled to the plurality of drivers. The circuitry can configure at least one driver of the plurality of drivers in each of a plurality of configurations, where each of the plurality of configurations is associated with one calibration code of a plurality of calibration codes. Each configuration generates an associated channel performance response of a plurality of channel performance responses in response to a signal transmission via the output node. The circuitry can also store a calibration code of the at least one cell driver, where the calibration code generates a desired channel performance response of the plurality of channel performance responses.

Description

[0001] Priority Statement

[0002] This application claims the benefit of U.S. Patent Application Serial No. 17 / 141,031, filed January 4, 2021, entitled “Output Impedance Calibration, and Relatted Devices, Systems, and Methods”. Technical Field

[0003] Embodiments of this disclosure relate to impedance calibration. More specifically, some embodiments of this disclosure relate to output impedance calibration of microelectronic devices and related methods, apparatus, and systems. Background Technology

[0004] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. Many different types of memory exist, including, for example, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive random access memory (RRAM), double data rate memory (DDR), low-power double data rate memory (LPDDR), phase-change memory (PCM), and flash memory.

[0005] Electronic systems, such as memory systems, typically contain one or more types of memory, and the memory is usually coupled to one or more communication channels within the memory system. Time-varying signals in such systems are used to transfer information (e.g., data) via one or more conductors, commonly referred to as signal lines. These signal lines are often bundled together to form a communication bus, such as an address or data bus.

[0006] To meet the demand for higher performance operating characteristics, designers continue to strive to increase operating speeds to transfer data across communication buses within electronic systems. One challenge in increasing data transfer rates is maintaining signal integrity during data bursts on the communication bus of an electronic (e.g., memory) system. As transfer rates increase, the impedance characteristics of the communication bus may become more pronounced, and signal waveforms may begin to spread and / or reflections may occur at locations of impedance mismatch on the communication bus. Signal integrity (e.g., data integrity) can be compromised when the impedance (e.g., output impedance) of one or more nodes of a memory device coupled to the communication bus is not properly matched to the impedance of the communication bus. Summary of the Invention

[0007] One or more embodiments of this disclosure include an apparatus. The apparatus may include an output driver comprising a plurality of unit drivers. Each of the plurality of unit drivers may include a plurality of transistors coupled to an output node. The output driver may also include a circuit system coupled to the plurality of unit drivers. The circuit system may be adapted to configure at least one of the plurality of unit drivers in each of a plurality of configurations. Each of the plurality of configurations may be associated with a calibration code of a plurality of calibration codes, and each configuration generates an associated channel performance response of a plurality of channel performance responses in response to signal transmission via the output node. The circuit system may also be adapted to store a selected calibration code of the at least one unit driver in response to signal reception, wherein the selected calibration code generates a desired channel performance response of the plurality of channel performance responses.

[0008] Some embodiments of this disclosure include a system. The system may include a semiconductor device comprising at least one driver, the driver comprising a plurality of transistors. The semiconductor device may also include a circuit system coupled to the at least one driver and adapted to configure the at least one driver in multiple configurations, wherein each configuration includes a unique number of active transistors among the plurality of transistors. The system may also include a host coupled to the semiconductor device. The host may be configured to transmit multiple signals to the driver to configure the driver in each of the plurality of configurations. The host may also be configured to evaluate the signal integrity response of each of the plurality of configurations to select one of the plurality of configurations. Furthermore, the host may be configured to transmit signals to the semiconductor device to store a calibration code associated with the selected configuration.

[0009] Further embodiments of this disclosure include an electronic system. The electronic system may include at least one input device, at least one output device, at least one processor device operatively coupled to the input device and the output device, and at least one memory system operatively coupled to the at least one processor device. The memory system may include a memory device that includes a driver, the driver including a plurality of transistors coupled to an output node. The memory device may also include a circuit system coupled to the driver and adapted to configure the driver in each of a plurality of configurations, wherein each configuration includes a unique number of active transistors among the plurality of transistors. The circuit system may be further adapted to store calibration codes of the driver in response to the reception of a signal, wherein the calibration codes generate a desired channel performance response of the driver.

[0010] Other embodiments of this disclosure include a method. The method may include at least one unit driver configuring an output driver of a semiconductor device based on a calibration code. Furthermore, the method may include transmitting a signal from the semiconductor device. The method may also include comparing a channel performance response associated with the transmitted signal with a previous channel performance response. Additionally, the method may include storing the calibration code in response to an improvement in the channel performance response relative to the previous channel performance response. Attached Figure Description

[0011] Figure 1 This is a block diagram of an exemplary memory system comprising multiple memory devices according to various embodiments of the present disclosure.

[0012] Figure 2 This is a functional block diagram of an exemplary memory device according to various embodiments of the present disclosure.

[0013] Figure 3 Exemplary memory systems comprising dual in-line memory modules coupled to a host are described according to various embodiments of the present disclosure.

[0014] Figure 4A and 4B Each describes an exemplary channel performance response of the memory system.

[0015] Figure 5 An exemplary memory system comprising an output driver for a memory device coupled to a host computer is described.

[0016] Figure 6 An exemplary memory system comprising an output driver of a memory device coupled to a host, according to various embodiments of the present disclosure, is described.

[0017] Figure 7A This is a flowchart illustrating exemplary methods of operating a memory system according to various embodiments of the present disclosure.

[0018] Figure 7B This is a flowchart illustrating an exemplary method for reading training a memory device according to various embodiments of the present disclosure.

[0019] Figure 8 This is a flowchart illustrating an exemplary method for calibrating a memory device according to various embodiments of the present disclosure.

[0020] Figure 9 This is a simplified block diagram of an exemplary memory system implemented according to one or more embodiments described herein.

[0021] Figure 10 This is a simplified block diagram of an exemplary electronic system implemented according to one or more embodiments described herein. Detailed Implementation

[0022] Memory devices (e.g., memory systems) may include output devices containing one or more output drivers for driving signals (e.g., off-chip) during data transfer. As will be understood, various memory systems, including, for example, two dual in-line memory modules (DIMMs) per channel (2DPC) memory systems and four DIMMs per channel (4DPC) memory systems, may contain variable internal characteristics and may exhibit variable channel performance responses (e.g., during data transfer). Channel performance can affect signal integrity, and although a memory system may meet design specifications, its signal integrity may be less than ideal (e.g., due to less than ideal channel performance). In some conventional devices, systems, and methods, signal integrity issues are addressed via manual adjustment of the output driver circuitry (e.g., manual adjustment of the on-resistance (Ron) of the output drivers). However, manual adjustment of the output driver circuitry requires additional resources and time and may lead to other problems (e.g., design fragmentation due to variable characteristics).

[0023] As disclosed herein, various embodiments may involve automatic impedance calibration (e.g., performed via automatic training operations) (e.g., for semiconductor device readout operations). Various embodiments of this disclosure may enhance and potentially optimize the signal integrity associated with semiconductor devices (e.g., memory devices and / or memory systems). For example, in some embodiments, the signal integrity of a semiconductor device may be enhanced and potentially optimized without manual adjustment (e.g., without adjustment by a designer and / or user) of the output impedance. Furthermore, according to some embodiments, undesirable design fragments may be avoided (e.g., via automatic impedance calibration, as described herein). It will be understood that the various embodiments disclosed herein can be used in place of (i.e., may replace) conventional calibration operations.

[0024] Although various embodiments have been described herein with reference to memory systems and / or memory devices, this disclosure is not limited thereto, and the embodiments are generally applicable to microelectronic systems and / or devices that may or may not include semiconductor devices and / or memory devices. Embodiments of this disclosure will now be explained with reference to the accompanying drawings.

[0025] Figure 1An exemplary memory system 100 according to various embodiments of the present disclosure is shown. The memory system 100 includes a plurality of memory devices 102-105 coupled to a communication bus 110 (e.g., a system bus). Each memory device 102-105 may include one or more memory dies, and the memory devices 102-105 may be collectively referred to as dual in-line memory modules (DIMMs), multi-chip packages (MCPs), or stacked packages (POPs). Each memory device 102-105 of the memory system 100 may include an output driver comprising a plurality of cell drivers and associated calibration circuitry, as described more fully below.

[0026] The memory system 100 further includes a controller 112 coupled to each memory device 102-105 via a communication bus 110. The controller (also referred to herein as a “host”) 112 may include a processor or any other type of controller, which can be configured to control and / or regulate various operations of the memory system 100, and provide interactivity with another device or system coupled to the memory system 100 via an interface 114.

[0027] The communication bus 110 may include one or more of an address bus 120, a data bus 122, and a control signal bus 124. In some embodiments, memory devices 102-105, the communication bus 110, and the controller 112 may be configured (e.g., physically arranged and mounted) on a printed circuit board (PCB).

[0028] Figure 2 This is a functional block diagram illustrating an exemplary memory device 200 according to at least one embodiment of the present disclosure. The memory device 200 may include, for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), DDR SDRAM (Double Data Rate SDRAM, such as DDR4 SDRAM, etc.), or SGRAM (Synchronous Graphics Random Access Memory). For example, Figure 1 One or more of the memory devices 102-105 may include memory device 200. Memory device 200, which may be integrated on a semiconductor chip, may include memory array 202.

[0029] exist Figure 2In this embodiment, memory array 202 is shown as comprising eight memory banks BANK0-7. More or fewer memory banks may be included in memory array 202 in other embodiments. Each memory bank includes multiple access lines (word lines WL), multiple data lines (bit lines BL and / or BL), and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL and / or BL. The selection of word lines WL can be performed by row decoder 204, while the selection of bit lines BL and / or BL can be performed by column decoder 206. Figure 2 In one embodiment, row decoder 204 may include a corresponding row decoder for each memory bank BANK0-7, while column decoder 206 may include a corresponding column decoder for each memory bank BANK0-7.

[0030] Bit lines BL and / BL are coupled to their respective sense amplifiers (SAMPs). Read data from bit lines BL or / BL can be amplified by the sense amplifiers (SAMPs) and transferred to the read / write amplifier 260 via the complementary local data line (LIOT / B), the transfer gate (TG), and the complementary main data line (MIOT / B). Conversely, write data output from the read / write amplifier 260 can be transferred to the sense amplifiers (SAMPs) via the complementary main data line (MIOT / B), the transfer gate (TG), and the complementary local data line (LIOT / B), and written to the memory cell MC coupled to bit lines BL or / BL.

[0031] The memory device 200 can typically be configured to receive various inputs (e.g., from an external controller) via various terminals, such as address terminal 210, command terminal 212, clock terminal 214, data terminal 216, and data mask terminal 218. The memory device 200 may include additional terminals, such as power supply terminals 220 and 222.

[0032] During expected operation, one or more command signals COM received via command terminal 212 can be transmitted to command decoder 250 via command input circuitry 252. Command decoder 250 may include circuitry configured to generate various internal commands by decoding one or more internal command signals COM. Examples of internal commands include activation command ACT and read / write signal R / W.

[0033] Furthermore, one or more address signals ADD received via address terminal 210 can be transmitted to address decoder 230 via address input circuit 232. Address decoder 230 can be configured to provide row address XADD to row decoder 204 and column address YADD to column decoder 206. Although command input circuit 252 and address input circuit 232 are shown as separate circuits, in some embodiments, address signals and command signals can be received via a common circuit.

[0034] The activation command ACT may include a pulse signal that is activated in response to a command signal COM indicating row access (e.g., an activation command). In response to the activation signal ACT, the row decoder 204 at the specified memory address can be activated. Therefore, the word line WL specified by the row address XADD can be selected and activated.

[0035] The read / write signal R / W may include a pulse signal activated in response to a command signal COM indicating column access (e.g., a read command or a write command). In response to the read / write signal R / W, the column decoder 206 may be activated, and the bit line BL specified by the column address YADD may be selected.

[0036] In response to the activation command ACT, the read signal, the row address XADD, and the column address YADD, data can be read from the memory cell MC specified by the row address XADD and the column address YADD. The read data can be output via the sense amplifier SAMP, the transfer gate TG, the read / write amplifier 260, the input / output circuit 262, and the data terminal 216. Furthermore, in response to the activation command ACT, the write signal, the row address XADD, and the column address YADD, write data can be provided to the memory array 202 via the data terminal 216, the input / output circuit 262, the read / write amplifier 260, the transfer gate TG, and the sense amplifier SAMP. The write data can be written to the memory cell MC specified by the row address XADD and the column address YADD.

[0037] Clock signals CK and / or CK can be received via clock terminal 214. Clock input circuit 270 can generate an internal clock signal ICLK based on clock signals CK and / or CK. The internal clock signal ICLK can be transmitted to various components of memory device 200, such as command decoder 250 and internal clock generator 272. Internal clock generator 272 can generate an internal clock signal LCLK, which can be transmitted to input / output circuit 262 (e.g., for controlling the operating timing of input / output circuit 262). Furthermore, data mask terminal 218 can receive one or more data mask signals DM. When a data mask signal DM is activated, overwriting the corresponding data can be prevented.

[0038] According to various embodiments, the input / output circuitry 262 may include one or more output drivers, wherein, as described in more detail below, each output driver may include one or more unit drivers and an associated circuitry system for calibrating (also referred to herein as “training”) the one or more unit drivers. More specifically, as described in more detail below, the desired output impedance of one or more unit drivers of the input / output circuitry 262 (e.g., for read operations) can be determined (i.e., via calibration / training operations) such that the associated memory device can exhibit acceptable (e.g., desired and / or optimal) signal integrity during device operation.

[0039] Figure 3 A memory system 300 comprising a dual in-line memory module (DIMM) 302 coupled to a host 304 is depicted according to various embodiments of the present disclosure. The DIMM 302 includes a plurality of memory components (e.g., memory devices) 306 for transferring data from the memory devices to the host (also referred to herein as a “controller”) 304 via one or more channels 305.

[0040] As will be understood, each memory component 306 may contain multiple (e.g., 4, 8, or 16) DQ components (e.g., DQ pads and / or DQ pins). Figure 3 (Not shown in the diagram). DIMM 302 further includes data strobing components 308 and 310 for transmitting strobe clock signals from DIMM 302 to host 304. As will be understood, in some instances, signal integrity (e.g., for data transfers via one or more channels 305) may vary between memory components 306 of memory system 300. Furthermore, in some instances, signal integrity (e.g., for data transfers via one or more channels 305) may vary between DQ components of a single memory component 306.

[0041] Figure 4A and 4B Each describes an exemplary channel performance response of the memory system. More specifically, Figure 4A and 4B Each describes a memory system (e.g., Figure 3 The channels of the memory system 300 (e.g., Figure 3 The signal integrity results of channel 305 (also referred to in this document as "signal integrity", "signal integrity response", "channel performance", "channel performance response"). As will be understood, Figure 4A Data Eye 402 compared to Figure 4B The data point 404 is larger, and therefore, Figure 4A The signal integrity results described in the text are relative to Figure 4BThe signal integrity results described in the paper are improved.

[0042] Figure 5 A memory system 500 is depicted including an output driver 502 (e.g., a memory device (e.g., DRAM)) coupled to a host 504 via channel 506. The output driver 502 includes a plurality of parallel-coupled drivers 508. Each driver (also referred to herein as a “cell driver”) 508 may have the same or similar circuit structure. More specifically, each driver 508 includes a plurality of transistors M. Furthermore, each driver 508 includes a resistor R coupled between a terminal (e.g., source or drain) of an associated transistor M and a node N (also referred to herein as an “output node,” “DQ node,” “DQ pin,” or “DQ pad”). As will be understood, multiple operating signals can be provided to the gate of the transistor M to select the multiple transistors. In other words, each transistor M can be individually controlled (i.e., turned on / off) based on the associated operating signal. In this example, each driver 508 has an output impedance of 240 ohms.

[0043] As will be understood, signal integrity (i.e., for memory device read operations) may be affected by the output resistance Ron (also referred to as the "on-resistance") of the output driver and may be affected by system characteristics (e.g., channel characteristics) associated with the output driver. It will also be understood that in some systems, the value of the output resistance Ron may be 240 ohms, which can be adjusted via output impedance (ZQ) calibration. Although the value of the output resistance Ron can be adjusted (e.g., according to design specifications), signal integrity may be less than ideal (e.g., due to less than ideal channel performance). Therefore, according to at least some embodiments, the value of the output resistance Ron can be adjusted (e.g., from a specified value) (e.g., to improve signal integrity). More specifically, according to at least some embodiments, the value of the output resistance Ron can be adjusted via an automatic calibration process (e.g., without manual adjustment).

[0044] In some cases, Ron values ​​outside the specification range can be used to enhance (e.g., optimize) signal integrity. For example, even if the design specification includes a Ron value of 240 ohms and a 5% permissible variation (i.e., 228–252 ohms), a Ron value of 220 ohms may still provide optimal results. As mentioned above, conventional systems, devices, and methods can tune the output resistance Ron via a manual process, which requires additional resources and / or time.

[0045] Figure 6 An exemplary memory system 600 according to various embodiments of the present disclosure is depicted. The memory system 600 includes, for example, memory devices (e.g., memory devices) coupled to a host 604 via a channel 606. Figure 2The output driver 602 of the memory device 200. For example, refer to Figure 3 and 6 The output driver 602 may be part of the memory component 306, the channel 606 may include the channel 305, and the host 604 may include the host 304.

[0046] refer to Figure 6 The output driver 602 includes multiple drivers 608, where each driver (also referred to herein as a "cell driver") 608 contains multiple transistors M. Similar to... Figure 5 The memory system 500, memory system 600, each transistor M can be individually controlled (i.e., turned on / off) based on an associated operating signal. Each driver 608 may include a resistor R coupled between a terminal (e.g., source or drain) of the associated transistor M and a node N, which may include an output node (e.g., a DQ node). As will be understood, in some embodiments (e.g., where the output resistance Ron is relatively small), the resistor R may not be necessary.

[0047] Output driver 602 further includes logic 610 (also referred to herein as "ZQ calibration logic" or "calibration logic"), register 612, multiplexer 614, and register 616. Multiplexer 614 may be configured to receive control signal 617 (e.g., for transmitting the output of register 612 during the calibration process or for transmitting the output of register 616 during device operation). According to some embodiments, each unit driver 608 may include a dedicated calibration circuitry (e.g., logic 610, registers 612 and 614, and multiplexer 614). In other embodiments, the same calibration circuitry (e.g., logic 610, registers 612 and 614, and multiplexer 614) may support more than one unit driver 608.

[0048] like Figure 6 As shown, host 604 is coupled to output driver 602 via channel 606 (e.g., for receiving various signals). Furthermore, according to some embodiments, host 604 may be coupled to logic 610 and / or register 616 of output driver 602.

[0049] According to various embodiments, the memory system 600 can be configured to determine, via testing, a value of the output resistance Ron that enhances and potentially optimizes the signal integrity associated with channel 606. Furthermore, the determined Ron value can be used during operation of the memory system 600. More specifically, for example, the memory system 600 can be configured to test multiple values ​​of the output resistance Ron (e.g., based on multiple calibration codes) to determine the optimal Ron value among the multiple Ron values. Additionally, the calibration code associated with the determined Ron value can be stored in register 616 and used during operation of the memory system 600.

[0050] A more detailed exemplary calibration operation of the memory system 600 (also referred to herein as the “training operation”) will now be described. In this example, host 604 may transmit signals to driver 608 for its configuration. More specifically, in some embodiments, host 604 may transmit calibration codes to logic 610, which may provide the calibration codes to register 612. Furthermore, in these embodiments, calibration codes may be provided to output driver 608 via multiplexer 614 for selecting a plurality of transistors M (e.g., selecting 1-N transistors to be turned on (i.e., turned on)). In other embodiments, logic 610, register 612, and / or multiplexer 614 may not be necessary (i.e., for providing calibration codes to driver 608), and in these embodiments, host 604 may transmit calibration codes to output driver 608 for selecting the plurality of transistors M.

[0051] Note that each calibration code may be associated with and / or indicate a driver configuration. For example, calibration code "one" may be associated with and / or indicate a driver configuration of "one" transistor (i.e., on) of selected driver 608. As another example, calibration code "five" may be associated with and / or indicate a driver configuration of "five" transistors (i.e., on) of selected driver 608.

[0052] Continuing this exemplary operation, with a selected number of transistors turned on, signals can be transmitted from output driver 602 to host 604 (i.e., data can be read from output driver 602), and channel performance response can be measured and / or evaluated. For example, the size of the data eye in the channel performance response can be measured and / or evaluated. Furthermore, the channel performance response can be compared to a previous channel performance response. If the channel performance response is improved compared to a previous channel performance response (i.e., a previous channel performance response associated with the calibration code stored in register 616), or if the channel performance response is the first channel performance response in the calibration operation (i.e., register 616 does not contain the stored calibration code), then the associated calibration code can be stored in register 616. For example, in response to determining that the channel performance response is improved relative to a previous channel performance response, host 604 can signal to output driver 602 that output driver 602 has stored the associated calibration code in register 616.

[0053] On the other hand, if the channel performance response does not improve compared to the previous channel performance response (i.e., the previous channel performance response associated with the calibration code stored in register 616), the associated calibration code may not be stored in register 616. This calibration (“training”) process can be repeated for each of the multiple calibration codes, such that the channel performance response of each of the multiple transistor configurations of driver 608 (e.g., one transistor on, two transistors on, three transistors on, etc.) is generated and measured and / or evaluated, and the calibration code associated with the desired (e.g., optimal) channel performance response is stored in register 616.

[0054] As will be understood, in some anticipated operations, the calibration code associated with the first test configuration (e.g., one transistor on) can be stored in register 616 (i.e., regardless of the channel performance response). In other words, because the channel performance response of the first test configuration is not compared with the channel performance response of the other configuration, the calibration code associated with the first test configuration is stored in register 616 by default. As described above, host 604 can signal to output driver 602 to instruct output driver 602 to store the calibration code associated with the first test configuration in register 616. Subsequently, in this example, host 604 can signal (e.g., calibration code) to driver 608 to configure driver 608 with the second test configuration. Furthermore, signals can be transmitted from output driver 602 (i.e., data can be read from output driver 602), and the channel performance response of the second test configuration (e.g., both transistors on) can be compared with the channel performance response of the first test configuration.

[0055] If the channel performance response of the second test configuration is improved relative to the channel performance response of the first test configuration, the calibration code associated with the second test configuration can be stored in register 616 (i.e., the calibration code associated with the second test configuration overwrites the calibration code associated with the first test configuration). For example, in response to determining that the channel performance response of the second test configuration is improved relative to the channel performance response of the first test configuration, the host 604 can send a signal to the output driver 602 to instruct the output driver 602 to store the calibration code associated with the second test configuration in register 616. Furthermore, in this example, the host 604 can send a signal (e.g., calibration code) to the driver 608 to configure the driver 608 with a third test configuration. Additionally, signals can be transmitted from the output driver 602 to the host 604, and the channel performance response of the third test configuration (e.g., three transistors on) can be compared with the channel performance response of the second test configuration.

[0056] On the other hand, if the channel performance response of the second test configuration does not improve relative to the channel performance response of the first test configuration, the calibration code associated with the second test configuration may not be stored in register 616 (i.e., the calibration code associated with the first test configuration is still stored in register 616). Note that, according to some embodiments, if the channel performance response of the second test configuration does not improve relative to the channel performance response of the first test configuration, the host may not need to send feedback to the output driver 602. Furthermore, continuing with this example, the host 604 may send a signal (e.g., calibration code) to the driver 608 for configuring the driver 608 with a third test configuration. Thereafter, in this example, the channel performance response of the third test configuration (e.g., three transistors turned on) can be compared with the channel performance response of the first test configuration.

[0057] As will be understood, after testing each of multiple (e.g., N) test configurations, calibration code associated with the test configuration that generates the best channel performance response among the multiple (e.g., N) channel performance responses can be stored in register 616. Furthermore, during operation (i.e., during the operation of output driver 602), register 616 can transmit calibration code (i.e., via multiplexer 614) to unit driver 608 for configuring unit driver 608 with the configuration that generates the best channel performance response (i.e., during the calibration / training process).

[0058] Figure 7A This is a flowchart of an exemplary method 700 for operating a memory system. More specifically, method 700 can be used to initialize and / or calibrate a memory system. Method 700 can be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 700 can be performed by means of a device or system, such as... Figure 1 The memory system 100, one or more memory devices of the memory system 100, Figure 2 Memory device 200, Figure 6 Memory system 600, Figure 9 Memory system 900, Figure 10 The electronic system 1000, or another device or system. Although shown as discrete blocks, the individual blocks may be divided into other blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0059] Method 700 may begin at block 702, where the memory system (e.g., Figure 6 The memory system 600 can be powered on or reset, and method 700 can proceed to block 704. In blocks 704, 706, and 708, various calibration and / or training operations of the memory system can be performed. More specifically, for example, as those skilled in the art will understand, ZQ calibration can be performed in block 704, command and address (CA) training can be performed in block 706, and write training can be performed in block 708.

[0060] Furthermore, in box 710, reading training according to various embodiments of this disclosure can be performed. (See reference...) Figure 7B The flowcharts depicted herein will now be described, illustrating an exemplary method 720 for performing read training on a memory device. Method 720 can be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 720 can be performed by a device or system, such as… Figure 1 The memory system 100, one or more memory devices of the memory system 100, Figure 2 Memory device 200, Figure 6 Memory system 600, Figure 9 Memory system 900, Figure 10 The electronic system 1000, or another device or system. Although shown as discrete blocks, the individual blocks may be divided into other blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0061] As will be understood, in box 722, one or more data and / or clock timing alignment operations can be performed, and method 720 can proceed to box 724. In box 724, calibration codes for configuring the unit driver can be set, and method 720 can proceed to box 726. More specifically, for example, in response to the receipt of calibration codes (e.g., from host 604), the unit driver (e.g., ...) can be turned on. Figure 6 The unit driver 608 has multiple transistors (e.g., 1, 2, 3, etc.) (i.e., to adjust the output resistance Ron).

[0062] In block 726, in response to a signal transmitted from output driver 602 to host 604 (e.g., data read out via output driver 602), channel performance response (i.e., for calibration codes and associated configurations) can be measured (e.g., via...). Figure 6 (Host 604). For example, the eye size (e.g., height and / or width) of the channel performance response can be measured. Furthermore, in box 728, the channel performance response can be compared to a previous "best" channel performance response (i.e., if a previous "best" response exists). For example, the eye height of the channel performance response can be compared to the eye height of the previous "best" channel performance response. Furthermore, if the channel performance response is better than the previous "best" channel performance response (or if the previous channel performance response has not yet occurred), a calibration code can be stored in box 730 (i.e., at an associated memory device (e.g., in...). Figure 6 In register 616)).

[0063] As will be understood, boxes 724-730 can be repeated for each of the multiple calibration codes. More specifically, multiple driver configurations (e.g., containing 1-N on-state transistors) can be tested for multiple (e.g., N) calibration codes. Each possible calibration code is tested, and the calibration code associated with the desired (e.g., optimal) channel performance response is stored (e.g., in...). Figure 6 After (in register 616), method 720 can proceed to block 732, where one or more reference voltage training operations can be performed.

[0064] Refer again Figure 7A After completing the read training operation in box 710, method 700 can proceed to box 712, where the memory system can be operated (e.g., performing various operations such as reading, writing, refreshing, etc.).

[0065] As described above, signal integrity can vary between memory components (e.g., memory devices) of a memory system. Therefore, according to some embodiments, one or more memory devices (e.g., memory devices of a DIMM) of a memory system can be calibrated according to the various embodiments disclosed herein. More specifically, for example, one or more memory devices 102-105 (see [document name missing]) can be calibrated (i.e., individually) (e.g., via different calibration processes) according to the various embodiments disclosed herein. Figure 1 As another example, one or more memory components 306 of the memory system 300 may be calibrated (i.e., individually) according to the various embodiments disclosed herein (see...). Figure 3In these instances, each memory component may or may not use the same calibration code (i.e., during operation). In other instances, (e.g., a memory system) multiple memory components may be calibrated together (i.e., via a single calibration process). In this instance, each memory component may use the same calibration code (i.e., during operation).

[0066] As also described above, signal integrity can vary between components of a single memory device (e.g., DQ components and / or cell drivers). Therefore, according to various embodiments, one or more output drivers and one or more cell drivers of the memory device can be calibrated (i.e., individually) (e.g., via different calibration processes) according to the various embodiments disclosed herein. Furthermore, for example, one or more DQ components of the memory device can be calibrated (i.e., individually) according to the various embodiments disclosed herein. For example, one or more cell drivers 608 (see […]) can be calibrated (i.e., individually) according to the various embodiments disclosed herein. Figure 6 In these instances, each component (e.g., each cell driver and / or DQ component) may or may not use the same calibration code (i.e., during operation). In other instances, multiple cell drivers and / or DQ components (e.g., memory devices) may be calibrated together (i.e., via a single calibration process). In this instance, each component may use the same calibration code (i.e., during operation).

[0067] As will be understood, the top-of-die termination (ODT) value can be determined by the output resistor Ron. Therefore, the various embodiments disclosed herein can be used to determine (e.g., via training / testing) the ODT value to enhance and potentially optimize signal integrity. In at least some embodiments, additional registers can be used for ODT training / testing. Furthermore, in at least some embodiments, training can be performed after reading the training data (e.g., after...). Figure 7A After the operation of box 710, another ODT is performed. Figure 8 This is a flowchart of an exemplary method 800 for calibrating a memory device. Method 800 can be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 800 can be performed by a device or system, such as... Figure 1 The memory system 100, one or more memory devices of the memory system 100, Figure 2 Memory device 200, Figure 6 Memory system 600, Figure 9 Memory system 900, Figure 10 The electronic system 1000, or another device or system. Although shown as discrete blocks, the individual blocks may be divided into other blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0068] Method 800 may begin at block 802, where at least one unit driver of the output driver of the system's semiconductor device can be configured based on a calibration code, and method 800 may proceed to block 804. For example, the at least one unit driver can be configured (i.e., based on the calibration code) (e.g., Figure 6 The unit driver 608 of the output driver 602 enables one or more transistors (e.g., Figure 6 The transistor M) is turned on (i.e., switched on). Furthermore, for example, calibration codes can be obtained from the host (e.g., Figure 6 The host 604) sends to the output driver (e.g., Figure 6 (output driver 602).

[0069] In block 804, a signal can be transmitted from the semiconductor device to the host computer of the system, and method 800 can proceed to block 806. For example, refer to... Figure 6 Data can be read and transmitted from node N to host 604 via channel 606.

[0070] In block 806, a channel performance response associated with the transmitted signal can be compared with a previous channel performance response, and method 800 can proceed to block 808. For example, a channel performance response associated with a unit driver configuration (e.g., two (2) transistors on) can be compared with a previous channel performance response associated with another unit driver configuration (e.g., one (1) transistor on). For example, the host (e.g., Figure 6 The host (604) can measure the channel performance response and compare it with a previous channel performance response.

[0071] In block 808, in response to an improvement in the channel performance response relative to a previous channel performance response, calibration codes can be stored. For example, the calibration codes can be stored in a register of a memory device (e.g., ...). Figure 6 In register 616). For example, in response to an improvement in the channel performance response relative to the previous channel performance response, the host (e.g., Figure 6 The host 604 can send signals to the output driver (e.g., Figure 6 The output driver 602 transmits a signal, thereby instructing the output driver to store a calibration code (e.g., in...). Figure 6 (in register 616).

[0072] As will be understood, various operations of method 800 can be repeated so that the unit driver can be configured in multiple configurations (i.e., based on multiple calibration codes), and the channel performance response of each of the multiple configurations can be analyzed and / or compared with the other channel responses to identify the optimal channel response of the unit driver and associated calibration code.

[0073] Modifications, additions, or omissions may be made to method 800 without departing from the scope of this disclosure. For example, the operations of method 800 may be performed in a different order. Furthermore, the operations and actions outlined are provided by way of example only, and some operations and actions may be optional, combined into fewer operations and actions, or extended to other operations and actions without departing from the essence of the disclosed embodiments. For example, in various embodiments, method 800 may include, prior to configuring the at least one cell driver of the semiconductor device, the method from an external host (e.g., ...) at the memory device. Figure 6 The host (604) receives the calibration code.

[0074] A memory system is also disclosed. The memory system may include multiple memory devices. As described herein, each memory device may include one or more arrays (e.g., memory arrays) and one or more output drivers.

[0075] Figure 9 This is a simplified block diagram of a memory system 900 implemented according to one or more embodiments described herein. The memory system 900 includes a plurality of memory devices 902 and a controller 904. For example, one or more memory devices 902 may include... Figure 6 The output driver 602, and the controller 904 may be and / or include Figure 1 Controller 112 and / or Figure 6 Host 604. As described herein, each memory device 902, which may include one or more memory cells, may include one or more output driver circuits, the output driver circuits including one or more cell drivers.

[0076] An electronic system is also disclosed. The electronic system may include a memory system containing multiple memory devices. Figure 10 This is a simplified block diagram of an electronic system 1000 implemented according to one or more embodiments described herein. The electronic system 1000 includes at least one input device 1002. The input device 1002 may be a keyboard, mouse, or touchscreen. The electronic system 1000 further includes at least one output device 1004. The output device 1004 may be a monitor, touchscreen, or speaker. The input device 1002 and the output device 1004 need not be separate from each other. The electronic system 1000 further includes a storage device 1006. The input device 1002, output device 1004, and storage device 1006 are coupled to a processor 1008.

[0077] The electronic system 1000 further includes a memory system 1010 coupled to the processor 1008. It may include... Figure 9 The memory system 900 and the memory system 1010 include multiple memory devices (e.g., Figure 1 (Memory devices 102-105). Electronic system 1000 may include computing, processing, industrial, or consumer products. For example, but not limited to, electronic system 1000 may include personal computers or computer hardware components, servers or other networking hardware components, handheld devices, tablet computers, electronic notebooks, cameras, telephones, music players, wireless devices, displays, chipsets, games, vehicles, or other known systems.

[0078] According to the various embodiments disclosed herein, and compared to some conventional methods, systems, and apparatuses, memory systems can tune the output impedance of one or more cell drivers without manually adjusting the output impedance. As will be understood, the apparatuses, systems, and methods disclosed herein can reduce the time and / or resource requirements that might be needed to calibrate the output impedance of one or more semiconductor devices in a calibration system. Furthermore, as described above, the various embodiments can allow the output resistance Ron to be adjusted to any suitable value, even values ​​outside the design specification range. Additionally, according to some embodiments, it is desirable that calibration codes (e.g., indicating the desired value of the output resistance Ron) can be stored at the memory device, and therefore, the load on the associated host (e.g., host 604) can be reduced.

[0079] One or more embodiments of this disclosure include an apparatus. The apparatus may include an output driver comprising a plurality of unit drivers. Each of the plurality of unit drivers may include a plurality of transistors coupled to an output node. The output driver may also include a circuit system coupled to the plurality of unit drivers. The circuit system may be adapted to configure at least one of the plurality of unit drivers in each of a plurality of configurations. Each of the plurality of configurations may be associated with a calibration code of a plurality of calibration codes, and each configuration generates an associated channel performance response of a plurality of channel performance responses in response to signal transmission via the output node. The circuit system may also be adapted to store a selected calibration code of the at least one unit driver in response to signal reception, wherein the selected calibration code generates a desired channel performance response of the plurality of channel performance responses.

[0080] Some embodiments of this disclosure include a system. The system may include a semiconductor device comprising at least one driver, the driver comprising a plurality of transistors. The semiconductor device may also include a circuit system coupled to the at least one driver and adapted to configure the at least one driver in multiple configurations, wherein each configuration includes a unique number of active transistors among the plurality of transistors. The system may also include a host coupled to the semiconductor device. The host may be configured to transmit multiple signals to the driver to configure the driver in each of the plurality of configurations. The host may also be configured to evaluate the signal integrity response of each of the plurality of configurations to select one of the plurality of configurations. Furthermore, the host may be configured to transmit signals to the semiconductor device to store a calibration code associated with the selected configuration.

[0081] Further embodiments of this disclosure include an electronic system. The electronic system may include at least one input device, at least one output device, at least one processor device operatively coupled to the input device and the output device, and at least one memory system operatively coupled to the at least one processor device. The memory system may include a memory device that includes a driver, the driver including a plurality of transistors coupled to an output node. The memory device may also include a circuit system coupled to the driver and adapted to configure the driver in each of a plurality of configurations, wherein each configuration includes a unique number of active transistors among the plurality of transistors. The circuit system may be further adapted to store calibration codes of the driver in response to the reception of a signal, wherein the calibration codes generate a desired channel performance response of the driver.

[0082] Other embodiments of this disclosure include a method. The method may include at least one unit driver configuring an output driver of a semiconductor device based on a calibration code. Furthermore, the method may include transmitting a signal from the semiconductor device. The method may also include comparing a channel performance response associated with the transmitted signal with a previous channel performance response. Additionally, the method may include storing the calibration code in response to an improvement in the channel performance response relative to the previous channel performance response.

[0083] As is customary, the various features shown in the accompanying drawings may not be drawn to scale. The illustrations presented in this disclosure are not intended to be actual views of any particular device (e.g., apparatus, system, etc.) or method, but are merely idealized representations for describing various embodiments of this disclosure. Therefore, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Furthermore, some figures may be simplified for clarity. Consequently, the drawings may not depict all components of a given device (e.g., apparatus) or all operations of a particular method.

[0084] The terminology used herein, particularly in the appended claims (e.g., the body of the appended claims), is generally intended to be “open” terms (e.g., the term “including / includes” should be interpreted as “including, but not limited to / includes, but is not limited to”, and the term “having” should be interpreted as “at least having”, etc.).

[0085] Furthermore, if the intention is to specify a particular number of claimed statements introduced, this intention will be explicitly stated in the claims, and if such a statement is not made, this intention does not exist. For example, to aid understanding, the appended claims below may contain the introductory phrases “at least one” and “one or more” to introduce claimed statements. However, the use of such phrases should not be construed as implying that introducing claimed statements with the indefinite article “a” or “an” limits any particular claim containing such introduced claimed statements to embodiments containing only one such claimed statement, even if the same claim contains the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles used to introduce claimed statements. As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0086] Furthermore, even if a specific number of the introduced claim statements is explicitly stated, it should be understood that such a statement should be interpreted as referring to at least the stated number (e.g., a statement of "two statements" without other modifiers refers to at least two statements, or two or more statements). Additionally, in cases where conventional usages such as "at least one of A, B, and C" or "one or more of A, B, and C" are used, this structure is generally intended to include only A, only B, only C, A and B together, A and C together, B and C together, or A, B, and C together, etc. For example, the use of the term "and / or" is intended to be interpreted in this manner.

[0087] Furthermore, any antonymous conjunction or phrase indicating two or more alternative terms, whether in the specification, claims, or drawings, should be understood to imply the possibility of including one of the terms, including either one of the terms, or including both terms. For example, the phrase "A or B" should be understood to imply the possibility of including "A" or "B" or "A and B".

[0088] Furthermore, the use of terms such as "first," "second," and "third" in this document does not necessarily indicate a specific order or quantity of elements. Generally, the terms "first," "second," and "third" are used as genus identifiers to distinguish different elements. Unless otherwise stated, these terms should not be interpreted as indicating a specific order. Similarly, unless otherwise stated, these terms should not be interpreted as indicating a specific quantity of elements.

[0089] The embodiments of this disclosure illustrated in the above description and accompanying drawings do not limit the scope of this disclosure, which is encompassed by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this disclosure. In fact, various modifications to this disclosure, such as alternative useful combinations of the described elements, will become apparent to those skilled in the art based on the description, in addition to those shown and described herein. Such modifications and embodiments also fall within the scope of the appended claims and their equivalents.

Claims

1. An apparatus comprising: The output driver includes: Multiple unit drivers, each of the multiple unit drivers comprising multiple transistors coupled to an output node; and A circuit system, coupled to the plurality of unit drivers and adapted to: At least one of the plurality of unit drivers is configured with each of the plurality of configurations, wherein each of the plurality of configurations is associated with one of the plurality of calibration codes, and each configuration generates an associated channel performance response of the plurality of channel performance responses in response to signal transmission via the output node; and The selected calibration code of the at least one unit driver is received in response to a signal from an external host, wherein the selected calibration code generates the desired channel performance response among the plurality of channel performance responses.

2. The apparatus of claim 1, wherein the circuitry includes a register configured to store the selected calibration code in response to the signal.

3. The apparatus of claim 2, wherein the register is configured to be coupled to and receive the signal therefrom from the external host.

4. The apparatus of claim 2, wherein the circuitry further comprises a multiplexer, a first input of which is coupled to the output of the register, and the multiplexer is configured to transmit the calibration code to one or more of the plurality of unit drivers.

5. The apparatus of claim 4, wherein the circuit system further comprises: Logic, which is configured to be coupled to the external host; and The second register has its input coupled to the output of the logic, and its output coupled to the second input of the multiplexer.

6. The apparatus of claim 1, wherein each of the plurality of configurations comprises a unique number of on-state transistors coupled to the output node.

7. A system comprising Semiconductor device, comprising: At least one driver, which contains multiple transistors; and A circuit system coupled to the at least one driver and adapted to configure the at least one driver in a plurality of configurations, each configuration containing a unique number of active transistors among the plurality of transistors; and A host computer, coupled to the semiconductor device, is external to the semiconductor device and configured to: Multiple signals are transmitted to the driver to configure the driver in each of the multiple configurations; Evaluate the signal integrity response of each of the plurality of configurations to select one of the plurality of configurations; and Signals are transmitted to the semiconductor device to store calibration codes associated with the selected configuration.

8. The system of claim 7, wherein the circuitry includes a first register configured to store the calibration code associated with the selected configuration of the plurality of configurations.

9. The system of claim 8, wherein the circuit system further comprises: Logic, which is coupled to the host; A second register, the input of which is coupled to the output of the logic; and A multiplexer having a first input coupled to the output of the first register and a second input coupled to the output of the second register, the multiplexer being configured to transmit signals to the at least one driver to configure the at least one driver in one of the plurality of configurations.

10. The system of claim 7, wherein the host is configured to compare the signal integrity responses of two or more of the plurality of configurations to select the configuration among the plurality of configurations.

11. The system of claim 7, wherein the at least one driver comprises a plurality of transistors, and each of the plurality of configurations comprises a unique number of transistors in an on state.

12. The system of claim 7, wherein the host is configured to compare a current signal integrity response with a previous signal integrity response to determine whether the current signal integrity is improved relative to the previous signal integrity response.

13. A system comprising: At least one input device; At least one output device; At least one processor device operatively coupled to the input device and the output device; and At least one memory system operatively coupled to the at least one processor device, the memory system comprising: A memory device comprising: A driver comprising a plurality of transistors coupled to an output node; and a circuit system coupled to the driver and adapted to: The driver is configured in each of a plurality of configurations, each configuration containing a unique number of active transistors among the plurality of transistors; and The driver's calibration code is stored in response to the reception of a signal from an external host, wherein the calibration code is associated with the driver's desired channel performance response.

14. The system of claim 13, wherein the memory device is configured to transmit a plurality of signals via the output node, wherein each of the plurality of signals is associated with one of the plurality of configurations.

15. The system of claim 14, wherein the memory system further includes the external host, the external host being coupled to the memory device and configured to: Receive the plurality of signals from the memory device; The optimal configuration among the multiple configurations is determined based on the received signals, and the optimal configuration is associated with the desired channel performance response; and The signal is transmitted to the memory device in response to determining the optimal configuration.

16. A method comprising: At least one unit driver for configuring the output driver of a semiconductor device based on a calibration code; Transmit signals from the semiconductor device; The host computer outside the semiconductor device compares the channel performance response associated with the transmitted signal with the previous channel performance response. and The calibration code is stored in response to an improvement in the channel performance response compared to the previous channel performance response.

17. The method of claim 16, further comprising receiving at the output driver a signal indicating that the channel performance response has improved relative to the previous channel performance response.

18. The method of claim 16, further comprising receiving the calibration code from the host at the semiconductor device prior to configuring the at least one unit driver.

19. The method of claim 16, wherein configuring the at least one unit driver comprises turning on a plurality of transistors of the at least one unit driver.

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