An input buffer circuit linearizing input parasitic capacitance

Abstract

This invention discloses an input buffer circuit that linearizes input parasitic capacitance, relating to the field of integrated circuit design technology. It addresses the problems of low linearity in existing input buffers and the failure to handle the nonlinearity introduced by input node parasitic capacitance, which leads to performance degradation of the input buffer front-end at high frequencies. The circuit includes a main input buffer circuit, a two-stage level shifting circuit, an auxiliary operational amplifier circuit, a common-mode generation circuit, and a bias circuit. The main input buffer circuit performs input signal tracking, the two-stage level shifting circuit performs level shifting, the auxiliary operational amplifier circuit increases the output impedance, the common-mode generation circuit generates the input common-mode level, and the bias circuit provides the bias voltage. All circuits work together to generate the output signal. This solution provides an input buffer with high linearity, wide bandwidth, and PVT stability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an input buffer circuit for linearizing input parasitic capacitance. Background Technology

[0002] Analog-to-digital converters (ADCs) are used to convert analog signals into digital signals and are widely used in wireless communication, testing equipment, image and speech processing, and other fields.

[0003] With the development of advanced processes and design technologies, as well as the expansion of application scenarios, the demand for high-speed, high-precision ADCs is becoming increasingly significant.

[0004] The performance of high-speed, high-precision ADCs is often limited by their front-end buffer circuits and sample-and-hold circuits. As the front-end circuit module of the system, the input buffer is crucial to the overall performance of the ADC.

[0005] Traditional input buffers improve linearity by introducing feedforward capacitors to compensate for high-frequency performance, but this is insufficient to meet current requirements.

[0006] Existing compensation techniques only optimize tube performance parameters and do not address the parasitic capacitance of the input node of the input buffer. At high frequencies, the nonlinearity introduced by these parasitic capacitances can severely degrade the front-end performance of the input buffer.

[0007] Therefore, there is an urgent need to provide a more reliable input buffer circuit that linearizes the input parasitic capacitance. Summary of the Invention

[0008] The purpose of this invention is to provide an input buffer circuit that linearizes input parasitic capacitance, in order to solve the problems of low linearity of existing input buffers and the deterioration of the front-end performance of input buffers at high frequencies caused by the nonlinearity introduced by input node parasitic capacitance.

[0009] To achieve the above objectives, the present invention provides the following technical solution: In a first aspect, the present invention provides an input buffer circuit for linearizing input parasitic capacitance, the circuit comprising: The main circuit of the input buffer, the two-stage level shifting circuit, the auxiliary operational amplifier circuit, the common-mode generation circuit, and the bias circuit; The two-stage level shifting circuit is connected to the input terminal and the drain terminal of the input transistor of the main circuit of the input buffer; the auxiliary operational amplifier circuit is connected to the common-source common-gate load transistor of the main circuit of the input buffer; the common-mode generation circuit is connected to the output terminal of the main circuit of the input buffer to detect the output common-mode voltage; the bias circuit is connected to the main circuit of the input buffer and the auxiliary operational amplifier circuit respectively to provide bias voltage.

[0010] Optionally, the main circuit of the input buffer includes at least: Five NMOS transistors and a feedforward compensation capacitor; wherein, the third NMOS transistor is the input transistor, the first NMOS transistor and the second NMOS transistor are common-source and common-gate load transistors, and the fourth and fifth NMOS transistors are stacked on the drain of the input transistor; one end of the feedforward compensation capacitor is connected to the input terminal, and the other end of the feedforward compensation capacitor is connected to the source of the next stage transistor in the common-source and common-gate load transistor; The common-source, common-gate load transistor increases the output impedance to generate a high output impedance signal; the feedforward compensation capacitor compensates for the nonlinear transconductance of the third NMOS transistor at high frequencies to generate a compensation signal; the fourth NMOS transistor reduces the nonlinear impedance change introduced by the VDS change of the third NMOS transistor to generate a low impedance change signal; and the fifth NMOS transistor reduces the nonlinear impedance change of the fourth NMOS transistor to generate a stable impedance signal.

[0011] Optionally, the two-stage level shifting circuit adopts a switched capacitor circuit, and the two-stage level shifting circuit includes at least a first-stage level shifting circuit and a second-stage level shifting circuit; The first-stage level shifting circuit is connected to the input terminal of the input buffer, and the second-stage level shifting circuit is connected to the drain terminal of the input transistor. The two-stage level shifting circuit performs DC operating point setting processing on the input transistors in the two-stage level shifting circuit to generate the corresponding DC operating point signal.

[0012] Optionally, the switched capacitor circuit includes at least four switches and two capacitors. By selecting an appropriate potential, the fourth NMOS transistor and the fifth NMOS transistor are made to operate at an appropriate operating point. The input signal is coupled to the gate of the fourth NMOS transistor through a capacitor, and the AC signal at the source of the fourth NMOS transistor is coupled to the gate of the fifth NMOS transistor through a capacitor.

[0013] Optionally, the auxiliary operational amplifier circuit adopts a common-source amplifier. The auxiliary operational amplifier circuit receives the output signal of the main circuit of the input buffer, increases the equivalent transconductance of the common-source cascode load, and outputs a high-impedance signal.

[0014] Optionally, the gate of the input transistor of the auxiliary operational amplifier circuit is connected to the drain of the input transistor in the main circuit of the input buffer, and the drain of the input transistor of the auxiliary operational amplifier circuit is connected to the gate of the upper stage transistor in the common source common gate load transistor. The current mirror load transistor provides bias current for the input transistor of the auxiliary operational amplifier circuit.

[0015] Optionally, the common-mode generation circuit includes a resistor, an operational amplifier, a current source, and a MOS transistor with its gate and drain shorted; the common-mode generation circuit detects and processes the output common-mode voltage PVT change through a negative feedback network and compares it with the ideal output common-mode level to generate an appropriate input common-mode voltage signal.

[0016] Optionally, the bias circuit adopts a common-source common-gate structure, and the bias circuit provides a bias voltage signal for the main circuit of the input buffer and the auxiliary operational amplifier circuit.

[0017] Optionally, the input terminal of the third NMOS transistor is provided with a variable capacitor and a control switch; The variable capacitor includes an accumulation-type MOS transistor. The gate voltage of the variable capacitor is connected to a fixed level, and the drain-source terminal of the variable capacitor is connected to the input signal. When the main circuit of the input buffer is working, the control switch is closed; when the main circuit of the input buffer is not working, the control switch is open.

[0018] Optionally, the main circuit of the input buffer processes the input analog signal to generate a high-speed, high-linearity output signal with linearized input parasitic capacitance.

[0019] Compared with the prior art, the present invention provides an input buffer circuit for linearizing input parasitic capacitance.

[0020] It includes an input buffer main circuit, a two-stage level shifting circuit, an auxiliary operational amplifier circuit, a common-mode generation circuit, and a bias circuit. The input buffer main circuit performs follow-up processing on the input signal, the two-stage level shifting circuit performs level shifting processing, the auxiliary operational amplifier circuit increases the output impedance, the common-mode generation circuit generates the input common-mode level, and the bias circuit provides the bias voltage. All circuits work together to generate the output signal.

[0021] The above scheme provides an input buffer with high linearity, wide bandwidth, and PVT stability. Attached Figure Description

[0022] The accompanying drawings, which are provided to further illustrate the invention and constitute a part of this invention, are illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention.

[0023] In the attached diagram: Figure 1 This is a schematic diagram of the overall circuit structure of a traditional input buffer in the prior art; Figure 2 The overall circuit diagram of the input buffer provided by the present invention; Figure 3 The auxiliary operational amplifier circuit structure diagram provided by the present invention; Figure 4 The circuit structure diagram of the switched capacitor provided by the present invention; Figure 5 The bias circuit structure diagram provided by the present invention; Figure 6 The common-mode generation circuit structure diagram provided by the present invention; Figure 7 The present invention provides simulation diagrams of the input buffer performance at various frequency points; Figure 8 The input buffer output spectrum diagram provided by this invention.

[0024] Figure label: 1-Two-stage level shifting circuit, 2-Auxiliary operational amplifier circuit, 3-Bias circuit, 4-Variable capacitor. Detailed Implementation

[0025] To facilitate a clear description of the technical solutions of the embodiments of the present invention, the terms "first" and "second" are used in the embodiments of the present invention to distinguish identical or similar items with essentially the same function and effect.

[0026] For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not restricted.

[0027] Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or the order of execution, and that the words "first" and "second" do not necessarily imply that they are different.

[0028] It should be noted that in this invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions.

[0029] Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs.

[0030] To be precise, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a specific way.

[0031] In this invention, "at least one" means one or more, and "more than one" means two or more.

[0032] "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone. A and B can be singular or plural.

[0033] The character " / " generally indicates that the objects before and after it are in an "or" relationship.

[0034] "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items.

[0035] For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0036] Traditional input buffer circuit structure diagram as follows Figure 1 As shown, Figure 1 The circuit structure in the circuit suffers from limited linearity of the input buffer (especially at high frequencies) and existing compensation techniques do not effectively address the parasitic capacitance problem at the input node. Specifically, a feedforward capacitor is introduced into the circuit to compensate for the high-frequency performance of the input buffer and improve linearity at high frequencies.

[0037] However, existing methods such as introducing feedforward capacitors are mainly aimed at optimizing the performance parameters of the input transistor.

[0038] For example, the nonlinearity introduced by the input transistor transconductance variation can be reduced, as can the nonlinearity introduced by the channel length modulation effect by reducing the input transistor gate-source voltage variation.

[0039] However, these methods only focus on adjusting the characteristic parameters of the tube itself, and do not fundamentally solve the problem caused by the parasitic capacitance of the input node.

[0040] For example, at high frequencies, input nodes have parasitic capacitances that interact with other components in the circuit, introducing additional nonlinearity.

[0041] Parasitic capacitance can cause changes in the phase and amplitude of the input signal during transmission, resulting in a deviation between the signal received by the input buffer and the original signal, thus affecting linearity.

[0042] The parasitic capacitance is coupled with components such as the feedforward capacitor, which changes the frequency response characteristics of the circuit and further aggravates nonlinear distortion.

[0043] For example, at high frequencies, parasitic capacitance may form a resonant circuit with the feedforward capacitor, causing abnormal gain or phase changes in the signal at certain frequency points, which seriously affects the performance of the input buffer front end.

[0044] Therefore, although the circuit structure of the prior art adopts compensation techniques such as feedforward capacitors, the problem of limited linearity of the input buffer due to the nonlinearity introduced by the parasitic capacitance at high frequencies still exists because these techniques do not effectively deal with the parasitic capacitance of the input node.

[0045] To address the problems in the prior art, the present invention provides a high-speed, high-linearity input buffer circuit structure with linearized input parasitic capacitance, thereby improving the linearity of the input buffer at high frequencies.

[0046] It can be applied to high-speed data acquisition and mixed signal processing systems, broadband communication systems, high-end test and measurement instruments, and other fields.

[0047] This invention can provide excellent buffering performance for high-performance analog-to-digital converters, thereby improving the overall performance of the chip.

[0048] Next, the solutions provided in the embodiments of this specification will be described in conjunction with the accompanying drawings: like Figure 2 As shown, the input buffer circuit for linearizing input parasitic capacitance provided by the present invention may include the following main structures: The main circuit of the input buffer consists of a two-stage level shifting circuit 1, an auxiliary operational amplifier circuit 2, a common-mode generation circuit, and a bias circuit 3. The two-stage level shifting circuit 1 is connected to the input terminal and the drain terminal of the input transistor of the main circuit of the input buffer; the auxiliary operational amplifier circuit 2 is connected to the common source cascode load transistor of the main circuit of the input buffer; the common mode generation circuit is connected to the output terminal of the main circuit of the input buffer and detects the output common mode voltage; the bias circuit 3 is connected to the main circuit of the input buffer and the auxiliary operational amplifier circuit 2 respectively and provides bias voltage.

[0049] Specifically, the main circuit of the input buffer uses an NMOS input transistor, the load transistor uses a common-source common-gate transistor, and a two-stage level shifting structure is used to reduce the channel length modulation effect of the input transistor; the two-stage level shifting circuit 1 uses a switched capacitor circuit to provide a suitable DC operating point; the auxiliary operational amplifier circuit 2 uses a common-source amplifier to increase the transconductance of the common-gate transistor; the common-mode generation circuit provides a suitable input common-mode level through a negative feedback network; the bias circuit 3 uses a common-source common-gate structure to provide bias voltage to the input buffer and the auxiliary operational amplifier.

[0050] Furthermore, for the input transistor and load transistor in the main circuit of the input buffer, the input transistor can be an NMOS input transistor.

[0051] NMOS transistors have some unique characteristics, such as relatively large transconductance under the same size and bias conditions, which can more effectively convert input voltage signals into current signals, thereby improving the gain and response speed of the circuit to a certain extent. At the same time, the manufacturing process of NMOS transistors is relatively mature, and they have high reliability and consistency in integrated circuit manufacturing.

[0052] The load transistor uses a common source cascode structure. The common source cascode structure can provide higher output impedance, which can reduce signal loss at the output end, so that the output signal can more accurately reflect the changes in the input signal.

[0053] In addition, the cascode structure can effectively suppress the channel length modulation effect, which causes nonlinear changes in the output characteristics of the transistor. The cascode structure can improve the linearity of the circuit.

[0054] For the two-stage level shifter circuit 1, the channel length modulation effect of the input transistor can be further reduced.

[0055] By appropriately adjusting the level of the input signal, the input transistor can maintain a relatively stable current-voltage characteristic under different operating conditions, thereby reducing the impact of channel length modulation effect on circuit performance.

[0056] The two-stage level shifting circuit 1 is connected to the input terminal and the drain terminal of the input tube of the main circuit of the input buffer, which can provide a suitable DC operating point for the input buffer.

[0057] Using a switched capacitor circuit to achieve two-stage level shifting, the charge on the capacitor can be precisely adjusted by controlling the on / off state of the switch, thereby achieving precise level shifting.

[0058] Compared to traditional resistor-capacitor circuits, switched capacitor circuits are easier to implement in integrated circuits and offer higher precision and stability.

[0059] In addition, switched capacitor circuits can adapt to different operating frequency requirements by adjusting the switching frequency, thus offering good flexibility.

[0060] For the auxiliary operational amplifier circuit 2, connecting it to the common-source cascode load transistor of the main circuit of the input buffer can increase the transconductance of the cascode transistor.

[0061] A common-source amplifier is used as the auxiliary operational amplifier circuit 2. The common-source amplifier has high voltage gain and good frequency response characteristics, which can amplify the input signal and feed the amplified signal back to the common-gate transistor through a suitable feedback network, thereby effectively increasing the transconductance of the common-gate transistor.

[0062] By connecting the common-mode generation circuit to the output terminal of the main circuit of the input buffer, the output common-mode voltage can be detected.

[0063] By detecting the output common-mode voltage and feeding it back to the circuit, appropriate measures can be taken to suppress the influence of the common-mode signal.

[0064] Specifically, a suitable input common-mode voltage can be provided through a negative feedback network, which can feed back a portion of the output signal to the input terminal in opposite phase, thereby adjusting the common-mode level of the input signal.

[0065] When the output common-mode voltage changes, the negative feedback network automatically adjusts the input common-mode level to keep the output common-mode voltage stable, thereby improving the circuit's common-mode rejection ratio and enhancing its anti-interference capability.

[0066] The bias circuit 3 is connected to the main circuit of the input buffer and the auxiliary operational amplifier circuit 2 respectively, and can provide a stable bias voltage for the main circuit of the input buffer and the auxiliary operational amplifier circuit 2.

[0067] This ensures that transistors maintain stable performance under different operating conditions, thereby improving the reliability and stability of the circuit.

[0068] Specifically, a cascode structure can be used to provide the bias voltage. The cascode structure has a high output impedance and can provide a stable bias current and voltage.

[0069] It can maintain a stable bias voltage under different temperature environments, thereby ensuring the consistent performance of the circuit under different operating conditions.

[0070] Figure 2 The circuit structure includes an input buffer main circuit, a two-stage level shift circuit 1, an auxiliary operational amplifier circuit 2, a common-mode generation circuit, and a bias circuit 3. The input buffer main circuit performs follow-up processing on the input signal, the two-stage level shift circuit 1 performs level shifting processing, the auxiliary operational amplifier circuit 2 increases the output impedance, the common-mode generation circuit generates the input common-mode level, and the bias circuit 3 provides the bias voltage. All circuits work together to generate the output signal.

[0071] Through the above scheme, the present invention can realize a wide-bandwidth, high-linearity and PVT-stable input buffer, which can be widely used in the field of high-speed and high-precision analog circuits.

[0072] based on Figure 2 The circuit structure described in this specification is further illustrated in the embodiments. The embodiments of this circuit structure also provide some specific implementation structures, the connection relationships between the various structures, and the operation process of the overall structure, which will be explained below.

[0073] The main circuit of the input buffer may include at least: The input transistor, common-source cascode load transistor, feedforward compensation capacitor, and two NMOS transistors stacked on the drain of the input transistor; among them, the common-source cascode load transistor is used to increase the output impedance, which can improve the linearity of the input buffer; the feedforward compensation capacitor can compensate for the nonlinear transconductance caused by the current flowing through the input transistor at high frequencies; and the first NMOS transistor is used to reduce the nonlinear impedance change introduced by the VDS change of the input transistor.

[0074] The second NMOS transistor is used to reduce the nonlinear impedance change of the first NMOS transistor, and the stacking of the two transistors can effectively prevent overvoltage.

[0075] The auxiliary operational amplifier circuit 2 is mainly used for gain enhancement technology, that is, to further increase the impedance of the common source cascode load, thereby improving linearity. The common mode generation circuit is mainly used to provide a stable input DC bias. This circuit can detect the change of the output common mode voltage PVT, compare it with the ideal output common mode level, and determine the appropriate input common mode voltage through a feedback mechanism.

[0076] Furthermore, such as Figure 2 As shown, the main circuit of the input buffer may include M1-M5 and a compensation capacitor C1; wherein, M1-M5 are all MOS transistors, specifically the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, the fourth NMOS transistor M4 and the fifth NMOS transistor M5 respectively.

[0077] The drain of M5 is connected to a 2.5V power supply, the source of M1 is connected to ground, and the other MOSFETs are connected in sequence with their source and drain connected in the same way.

[0078] Among them, M3 is the input transistor of the input buffer, and M1-M2 serve as a common-source, common-gate load, increasing the output impedance of the output buffer and thus improving the overall linearity. M4 and its switched capacitor circuit are used to bootstrap the input voltage, reduce the drain-source variation of the input transistor, and thus reduce the nonlinearity caused by the drain-source resistance of the input transistor. M5 and its switched capacitor circuit are used to reduce the nonlinearity caused by the drain-source resistance of M4. In addition, by stacking M4 and M5, the drain voltage of M1 can be effectively reduced, thereby preventing the transistor from overvoltage.

[0079] The compensation capacitor C1 is connected to the input at one end and to the source of M2 at the other end. It provides a current that varies with the input voltage in high-frequency situations, thereby reducing the transconductance nonlinearity caused by the changing current of the input transistor M1.

[0080] For the auxiliary operational amplifier circuit 2, the auxiliary operational amplifier circuit 2 adopts a common-source amplifier, which may include at least an input transistor, a current mirror load transistor, and a transistor for reducing the drain voltage of the current mirror load transistor; the gate of the input transistor is connected to the drain of the input transistor in the main circuit of the input buffer, and the drain of the input transistor is connected to the gate of the upper stage transistor in the common-source load transistor; the current mirror load transistor provides bias current for the input transistor; the auxiliary operational amplifier circuit 2 receives the output signal of the main circuit of the input buffer, increases the equivalent transconductance of the common-source load, improves the output impedance, and outputs a high-impedance signal.

[0081] Specifically, the auxiliary operational amplifier circuit 2 is as follows: Figure 3 As shown, it can include M6, M7, and M9. The input transistor is M6, and the bias current is provided by the current mirror load M7. M9 is used to reduce the drain voltage of M7, thereby preventing the transistor from overvoltage.

[0082] By using this gain bootstrap technique, connecting the gate of M6 to the drain of M1 and the drain of M6 to the gate of M2, the equivalent transconductance of the cascode load can be effectively increased, thereby improving the output impedance.

[0083] For the two-stage level shift circuit 1, the linearization parasitic capacitance technology is mainly achieved through the two-stage level shift circuit and the switch-controlled nonlinear variable capacitor 4. The first-stage level shift circuit is connected to the input terminal of the input buffer, and the second-stage level shift circuit is connected to the drain terminal of the input transistor.

[0084] For the first-stage level shifter circuit, the nonlinear parasitic capacitance at the input terminal is mainly affected by the gate-source capacitance and gate-drain capacitance of the input transistor and the first NMOS transistor. The nonlinearity of the gate-source capacitance and gate-drain capacitance mainly comes from the changes in the gate-source voltage and the gate-drain voltage. Therefore, the nonlinearity of the parasitic capacitance introduced at the input terminal of the first NMOS transistor can be ignored.

[0085] As for the second-stage level shift circuit, by separating it from the input terminal and connecting the AC signal to the drain terminal of the input transistor, the contribution of the second-stage level shift circuit to the nonlinearity of the parasitic capacitance at the input terminal is avoided.

[0086] Therefore, the change in input nonlinear parasitic capacitance of the entire input buffer is greatly reduced, thereby improving the performance of the input buffer. At high frequencies, the performance of the input end of the input buffer is often greatly limited. Therefore, this technology further improves the output performance of the output buffer.

[0087] Furthermore, the input terminal of the input transistor is equipped with a variable capacitor 4 and a control switch. The variable capacitor 4 includes an accumulation-type MOSFET with its gate voltage connected to a fixed level and its drain-source terminal connected to the input signal. When the input buffer is working, the control switch is closed, and the variable capacitor 4 cancels out part of the nonlinear capacitance introduced by the input transistor. When the input buffer is not working, the control switch is open to avoid nonlinearity introduced in the case of multiple input buffers.

[0088] The switched capacitor circuit can include at least four switches and two capacitors. By selecting the corresponding potential, the fourth NMOS transistor and the fifth NMOS transistor operate at their respective operating points. The input signal is coupled to the gate of the fourth NMOS transistor through the capacitor, causing the drain voltage of the input transistor to change with the input signal. The AC signal at the source of the fourth NMOS transistor is coupled to the gate of the fifth NMOS transistor through the capacitor, causing the drain voltage of the fourth NMOS transistor to change with the source voltage. This reduces the input nonlinear parasitic capacitance change of the input buffer and outputs a level-shifted signal.

[0089] like Figure 4 As shown, by selecting appropriate VB1, VB2, VB3, and VB4, M4 and M5 are made to operate at suitable operating points. The input signal is coupled to the gate of M4 through capacitor C3. At this time, M4 is the input transistor of the source follower, so that the drain voltage of M3 changes with the input signal. The source AC signal of M4 is coupled to the gate of M5 through capacitor C4. At this time, M5 can be regarded as the input transistor of the source follower, so that the drain voltage of M4 also follows the change of the source voltage.

[0090] For the switched capacitor circuit, switches S0, S2, S6, and S7 are turned on at the sampling time, and switches S1, S3, S4, and S5 are turned off at the sampling time; switches S0, S2, S6, and S7 are turned off at the holding time, and switches S1, S3, S4, and S5 are turned on at the holding time.

[0091] For bias circuit 3, bias circuit 3 can adopt a common source common gate structure, including a transistor for reducing the power supply voltage, a current mirror transistor for providing bias to other transistors, and a low-voltage current mirror transistor; the bias circuit 3 provides bias voltage signals for the main circuit of the input buffer and the auxiliary operational amplifier circuit 2.

[0092] like Figure 5 As shown, in bias circuit 3, M9 is used to reduce the power supply voltage, M8 acts as a current mirror to provide bias for M7, M10 and M11 are connected to current IB2 as low-voltage current mirrors to generate a suitable bias voltage for M1; M12 and M13 are connected to current IB3 to generate a suitable bias voltage for M11.

[0093] The common-mode generation circuit includes resistors, operational amplifiers (op-amps), current sources, and a MOSFET with its gate and drain shorted. The resistor detects the output common-mode voltage of the input buffer and uses it, along with the desired common-mode voltage, as inputs to the op-amp. The op-amp's output is connected to a MOSFET, whose drain is connected to a current source. The difference between the current source and the MOSFET's current source flows through the resistor and the MOSFET with its gate and drain shorted, generating the input common-mode voltage. This input common-mode voltage is then superimposed onto the input signal using a resistor to apply a DC level. The common-mode generation circuit receives the output signal from the input buffer, detects changes in the output common-mode voltage (PVT), compares it with the ideal output common-mode level, and determines an appropriate input common-mode voltage through a feedback mechanism, outputting a stable input common-mode level signal.

[0094] like Figure 6 As shown, the common-mode generation circuit detects the output common-mode voltage of the input buffer through resistors R1 and R2, and uses it and the ideal common-mode voltage VCM to be set as the inputs of the operational amplifier. The output of the operational amplifier is connected to transistor M13. A current source is connected to the drain of transistor M13. The difference between the current source and the current source of M13 flows through R3 and the gate-drain shorted MOS transistor to generate the input common-mode voltage. The input common-mode voltage is superimposed on the input signals VIP and VIN through resistors R4 and R5.

[0095] Regarding the nonlinearity caused by the input parasitic capacitance of the input transistor, for M3, due to the follower characteristic of the buffer, its gate-source voltage remains relatively constant. Due to the follower effect of M4, the drain-source voltage of M3 also remains relatively constant.

[0096] Therefore, the gate-source parasitic capacitance and gate-drain parasitic capacitance of M3 remain relatively constant, thus greatly reducing the nonlinearity they cause.

[0097] For M4, its nonlinear parasitic capacitance is connected to the input terminal through capacitor C3. Therefore, the nonlinear parasitic capacitance of M4 will also have a significant impact on the input terminal of the input buffer.

[0098] The buffer bootstraps the drain voltage of M3 to the gate of M5, causing the source of M5 to follow the AC component of the input signal, thereby keeping the drain-source voltage of M4 constant. As a result, the gate-source capacitance and drain-source capacitance of M4 remain relatively constant, reducing the nonlinearity they introduce.

[0099] In this way, by bootstrapping the source voltage of M4, we can effectively avoid the nonlinearity caused by the gate-drain capacitance of M5, because this parasitic capacitance is not connected to the input terminal of the input buffer, which can effectively reduce the nonlinear parasitic capacitance at the input terminal of the input buffer.

[0100] The input transistor M3 is directly connected to the input terminal, and its nonlinear parasitic capacitance has a significant impact on the input. Adding a variable capacitor 4 to the input terminal of the input buffer can also effectively reduce the nonlinear parasitic capacitance introduced by the input transistor.

[0101] The variable capacitor 4 is composed of an accumulation-type MOS transistor. The gate voltage of the transistor is connected to a fixed level, and the drain-source terminals are connected to the input signal. The parasitic capacitance from the P substrate to the deep N well of the input transistor M3 can be offset by the change in the source-drain-to-substrate capacitance of the accumulation-type MOS transistor. Since the capacitance changes of the two are in opposite directions, the nonlinearity caused by the capacitance can be effectively eliminated.

[0102] As one possible implementation, the present invention provides an input buffer circuit for linearizing input parasitic capacitance, which can be applied to fields such as high-speed data acquisition and mixed signal processing systems, broadband communication systems, and high-end test and measurement instruments, according to actual needs. Taking a high-speed data acquisition and mixed signal processing system as an example, the system includes the input buffer circuit of the present invention. When the system is working, the input analog signal first enters the main circuit of the input buffer, and after being processed by the input transistor, the common source common gate load transistor, etc., the linearity of the signal is initially improved.

[0103] Then, a two-stage level shifting circuit performs level shifting on the signal to further reduce the input channel length modulation effect and the input nonlinear parasitic capacitance change.

[0104] The auxiliary operational amplifier circuit increases the impedance of the common-source cascode load, thereby improving the output impedance; the common-mode generation circuit provides a stable input common-mode level for the signal, and the bias circuit provides a suitable bias voltage for the entire circuit; after these processes, the output signal has the characteristics of high linearity, wide bandwidth, and PVT stability, which can meet the signal processing requirements of high-speed data acquisition and mixed signal processing systems, and provide high-quality input signals for subsequent analog-to-digital conversion and other operations, thereby improving the performance of the entire system.

[0105] The high-speed, high-linearity input buffer provided by this invention can effectively isolate the influence of the sampling switch on the input source and achieve high linearity at the Nyquist frequency.

[0106] The technique of linearizing input parasitic capacitance reduces the nonlinear parasitic capacitance connected to the input terminal through a two-stage bootstrapping technique, thereby achieving higher linearity.

[0107] A variable capacitor is introduced to offset some of the nonlinear capacitance introduced by the input transistors, thereby achieving higher linearity. When the input buffer is not working, the switch is turned off, avoiding nonlinearity introduced at the input of the multi-input buffer.

[0108] By incorporating a bias circuit and an input common-mode generation circuit structure to support the overall circuit, the overall circuit can operate normally and stably near the target voltage range.

[0109] Next, in order to further demonstrate the technical effects that the technical solution of the present invention can achieve, simulation experiments were conducted, combined with... Figure 7 and Figure 8 The experimental results illustrate the technical effects of the present invention in detail: The simulation experiment first employed dynamic circuit simulation technology in Cadence simulation software, with an input frequency range of 0–1.25 GHz. Ten frequency points were selected, and the performance at each frequency point was as follows: Figure 7 As shown, when the input frequency is approximately 1.25 GHz, its output spectrum is as follows. Figure 8 As shown.

[0110] Specifically, Figure 7 The graph shows the changes of three different metrics (effective number of bits, signal-to-noise ratio, and spurious-free dynamic range) under different input frequency variations (horizontal axis, unit: GHz, labeled Fin (G)), represented by three curves: enob1, sinad1, and sfdr1.

[0111] Among them, enob1 (red curve): represents the effective number of bits, which is an important indicator for measuring the performance of analog-to-digital converters (ADCs) or similar circuits. The higher the effective number of bits, the less noise the circuit introduces during the conversion process, and the better the performance.

[0112] sinad1 (yellow curve): represents the signal-to-noise and distortion ratio, which comprehensively considers the ratio of signal power to noise plus distortion power, and measures the noise performance of the circuit. The higher the value, the smaller the impact of noise and distortion on the signal.

[0113] sfdr1 (green curve): Represents the spurious-free dynamic range, which measures the linearity of a circuit. It is the power difference between the maximum signal that the circuit can handle and the maximum spurious signal. The larger the value, the better the linearity of the circuit and the smaller the distortion.

[0114] Figure 7 The enob1 curve shows that the effective number of bits increases and reaches a peak when the input frequency increases from 0.1 GHz to about 0.2 GHz. Subsequently, as the frequency increases further, the effective number of bits shows a slow downward trend, with a more obvious drop near 1.0 GHz, and then rebounds.

[0115] This indicates that the number of significant bits remains at a relatively high level overall in this circuit.

[0116] The sinad1 curve shows that the signal-to-noise ratio is relatively low in the low-frequency band (around 0.1 GHz), rises first and then falls as the frequency increases, has a relatively stable region in the mid-frequency band, and then rises again in the high-frequency band (close to 1.2 GHz).

[0117] The sfdr1 curve shows that the spurious-free dynamic range rises rapidly in the low-frequency range and reaches a relatively high value. Subsequently, it fluctuates slightly with increasing frequency, but remains relatively stable overall. This indicates that the circuit provided by this invention has good noise and linearity performance across the entire frequency range, can effectively suppress spurious signals, and can work effectively over a wide frequency range.

[0118] Figure 8 The output spectrum of the input buffer is shown when the input frequency is slightly higher than 1.25 GHz. The horizontal axis represents frequency in MHz, ranging from 0 MHz to 600 MHz, showing the distribution of the input buffer output signal at different frequencies. The vertical axis represents noise power in dB, reflecting the signal strength at each frequency.

[0119] from Figure 8 As can be seen, the noise power is generally low across the entire frequency range, with most areas having noise power below -100dB. This indicates that the input buffer of this invention introduces less additional noise during signal transmission and can better maintain signal quality.

[0120] A low third harmonic indicates that the input buffer has low nonlinear distortion and good linearity, enabling it to transmit signals accurately without generating excessive harmonic distortion.

[0121] When the input frequency is slightly higher than 1.25 GHz, the output spectrum of the input buffer exhibits high frequency domain performance, low noise, and low third harmonic distortion. This fully demonstrates that the input buffer has good linearity and signal transmission quality, and can meet the application scenarios with high requirements for signal fidelity.

[0122] Although the invention has been described herein in conjunction with various embodiments, other variations of the disclosed embodiments will be understood and implemented by those skilled in the art in carrying out the claimed invention by reviewing the accompanying drawings, the disclosure, and the appended claims.

[0123] In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components.

[0124] A single processor or other unit can perform several of the functions listed in the claims.

[0125] Although different dependent claims describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0126] Although the invention has been described in conjunction with specific features and embodiments thereof, it is obvious that various modifications and combinations may be made therein without departing from the spirit and scope of the invention.

[0127] Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined in the appended claims, and are to be regarded as covering any and all modifications, variations, combinations or equivalents within the scope of the invention.

[0128] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from the spirit and scope of this invention.

[0129] Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. An input buffer circuit for linearizing input parasitic capacitance, characterized in that, The circuit includes: The main circuit of the input buffer, the two-stage level shifting circuit, the auxiliary operational amplifier circuit, the common-mode generation circuit, and the bias circuit; The two-stage level shifting circuit is connected to the input terminal and the drain terminal of the input transistor of the main circuit of the input buffer; the auxiliary operational amplifier circuit is connected to the common-source common-gate load transistor of the main circuit of the input buffer; the common-mode generation circuit is connected to the output terminal of the main circuit of the input buffer to detect the output common-mode voltage; the bias circuit is connected to the main circuit of the input buffer and the auxiliary operational amplifier circuit respectively to provide bias voltage.

2. The circuit according to claim 1, characterized in that, The main circuit of the input buffer includes at least: Five NMOS transistors and a feedforward compensation capacitor; wherein, the third NMOS transistor is the input transistor, the first NMOS transistor and the second NMOS transistor are common-source and common-gate load transistors, and the fourth and fifth NMOS transistors are stacked on the drain of the input transistor; one end of the feedforward compensation capacitor is connected to the input terminal, and the other end of the feedforward compensation capacitor is connected to the source of the next stage transistor in the common-source and common-gate load transistor; The common-source, common-gate load transistor increases the output impedance to generate a high output impedance signal; the feedforward compensation capacitor compensates for the nonlinear transconductance of the third NMOS transistor at high frequencies to generate a compensation signal; the fourth NMOS transistor reduces the nonlinear impedance change introduced by the VDS change of the third NMOS transistor to generate a low impedance change signal; and the fifth NMOS transistor reduces the nonlinear impedance change of the fourth NMOS transistor to generate a stable impedance signal.

3. The circuit according to claim 2, characterized in that, The two-stage level shifting circuit adopts a switched capacitor circuit, and the two-stage level shifting circuit includes at least a first-stage level shifting circuit and a second-stage level shifting circuit; The first-stage level shifting circuit is connected to the input terminal of the input buffer, and the second-stage level shifting circuit is connected to the drain terminal of the input transistor. The two-stage level shifting circuit performs DC operating point setting processing on the input transistors in the two-stage level shifting circuit to generate the corresponding DC operating point signal.

4. The circuit according to claim 3, characterized in that, The switched capacitor circuit includes at least four switches and two capacitors. By selecting an appropriate potential, the fourth NMOS transistor and the fifth NMOS transistor are made to operate at an appropriate operating point. The input signal is coupled to the gate of the fourth NMOS transistor through a capacitor, and the AC signal at the source of the fourth NMOS transistor is coupled to the gate of the fifth NMOS transistor through a capacitor.

5. The circuit according to claim 1, characterized in that, The auxiliary operational amplifier circuit adopts a common-source amplifier. The auxiliary operational amplifier circuit receives the output signal of the main circuit of the input buffer, increases the equivalent transconductance of the common-source cascode load, and outputs a high-impedance signal.

6. The circuit according to claim 5, characterized in that, The gate of the input transistor of the auxiliary operational amplifier circuit is connected to the drain of the input transistor in the main circuit of the input buffer, and the drain of the input transistor of the auxiliary operational amplifier circuit is connected to the gate of the upper stage transistor in the common source common gate load transistor. The current mirror load transistor provides bias current to the input transistor of the auxiliary operational amplifier circuit.

7. The circuit according to claim 1, characterized in that, The common-mode generation circuit includes resistors, operational amplifiers, current sources, and a MOS transistor with its gate and drain shorted. The common-mode generation circuit detects and processes the output common-mode voltage PVT change through a negative feedback network and compares it with the ideal output common-mode level to generate an appropriate input common-mode voltage signal.

8. The circuit according to claim 1, characterized in that, The bias circuit adopts a common source and common gate structure, and provides bias voltage signals for the main circuit of the input buffer and the auxiliary operational amplifier circuit.

9. The circuit according to claim 2, characterized in that, The input terminal of the third NMOS transistor is equipped with a variable capacitor and a control switch; The variable capacitor includes an accumulation-type MOS transistor. The gate voltage of the variable capacitor is connected to a fixed level, and the drain-source terminal of the variable capacitor is connected to the input signal. When the main circuit of the input buffer is working, the control switch is closed; when the main circuit of the input buffer is not working, the control switch is open.

10. The circuit according to claim 1, characterized in that, The main circuit of the input buffer processes the input analog signal to generate a high-speed, high-linearity output signal with linearized input parasitic capacitance.

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