DIMM for high bandwidth memory channels

Abstract

A DIMM is described. The DIMM includes circuitry that multiplexes write data to different groups of memory chips on the DIMM during the same burst write sequence.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 201910438515.2, filed on May 24, 2019, entitled "DIMM for High Bandwidth Memory Channel". Technical Field

[0002] The field of this invention generally relates to DIMMs for high-bandwidth memory channels. Background Technology

[0003] The performance of a computing system is highly dependent on the performance of its system memory. However, increasing memory channel capacity and memory speed often leads to challenges regarding power consumption in memory channel implementation. Therefore, system designers are seeking ways to increase memory channel capacity and bandwidth while keeping power consumption under control. Attached Figure Description

[0004] The invention can be better understood through the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 The first prior art DIMM is shown; Figure 2 A second prior art DIMM is shown; Figure 3a The third prior art DIMM is shown; Figure 3b It shows the relationship with Figure 3a The first layout of the memory channel connected to the DIMM interface; Figure 4a An emerging layout for memory channels is shown; Figure 4b An improved layout of the memory channels is shown; Figure 4c It shows the relationship with Figure 4b Improved layout interface connection of DIMM; Figure 4d Comparison based on Figure 3b The first layout and Figure 4c The timing of each memory channel in the improved DIMM implementation; Figure 4e It shows the relationship with Figure 4b Another improved DIMM for improved layout interface connections; Figure 4f Comparison based on Figure 3b The first layout and Figure 4e The timing of each memory channel in the improved DIMM implementation; Figure 4g It shows Figure 4f Additional information regarding the timing; Figure 5a It shows the relationship with Figure 4c Improved DIMM interface connection for memory controllers; Figure 5b It shows the relationship with Figure 4e Improved DIMM interface connection for memory controllers; Figure 6 The computing system is shown. Detailed Implementation

[0005] As is well known in the art, the main memory (also known as "system memory") in high-performance computing systems (such as high-performance servers) is typically implemented using dual in-line memory modules (DIMMs) inserted into memory channels. Here, multiple memory channels originate from the main memory controller, and one or more DIMMs are inserted into each memory channel. Each DIMM includes multiple memory chips that define the memory storage capacity of the DIMM. The combined memory capacity of the DIMMs inserted into the memory channels of the memory controller corresponds to the system memory capacity of the system.

[0006] Over time, the design and structure of DIMMs have changed to meet the ever-increasing demands for memory capacity and memory channel bandwidth. Figure 1 This demonstrates a traditional DIMM scheme. For example... Figure 1 As shown, the memory chip of a single "unbuffered" DIMM (UDIMM) 100 is directly coupled to the wires of memory channel buses 101, 102. UDIMM 100 includes multiple memory chips with a data width sufficient to form at least one rank 103. The rank corresponds to the width of the data bus, which typically corresponds to the number of data signals and ECC signals on the memory channel.

[0007] Thus, the total number of memory chips used on a DIMM is a function of the block size and bit width of the memory chips. For example, for a block with 64 bits of data and 8 bits of ECC, a DIMM can include eighteen “x4” (four-bit wide) memory chips (e.g., 16 chips × 4 bits / chip = 64 bits of data plus 2 chips × 4 bits / chip to implement 8 bits of ECC), or nine “x8” (e.g., 8 chips × 8 bits / chip = 64 bits of data plus 1 chip × 8 bits / chip to implement 8 bits of ECC).

[0008] For simplicity, please refer to Figure 1 In the subsequent diagrams, the ECC bits can be ignored, and the observed block width M simply corresponds to the number of data bits on the memory bus. That is, for example, for a data bus with 64 data bits, block = M = 64.

[0009] Traditionally, UDIMMs have storage capacity for two separate blocks of memory chips, with one side of the DIMM containing memory chips for the first block and the other side containing memory chips for the second block. Here, the memory chips have a certain amount of storage space, which is associated with the total number of different addresses that can be provided to the memory chips. A memory structure consisting of an appropriate number of memory chips connected to a data bus width interface (eighteen x4 or nine x8 memory chips in the aforementioned example) corresponds to a block of memory chips. Therefore, a block of memory chips can store multiple transfers from a data bus that corresponds to its address space. For example, if a block of memory chips is implemented using memory chips supporting 256M different addresses, then the block of memory chips can store information from 256M different bus transfers.

[0010] It is worth noting that the memory chips used to implement the two blocks of the memory chip are coupled to the memory channels 101 and 102 in a multi-branch manner. In this way, UDIMM 100 can provide up to two memory chip loads to each line of the memory channel data bus 101 (one memory chip load for each block of the memory chip).

[0011] Similarly, the command and address signals for the two blocks of the memory chip are coupled to the command address (CA) bus 102 of the memory channel in a multi-branch configuration. Control signals carried on the CA bus 102 include, to name a few, row address strobe (RAS), column address strobe (CAS), write enable (WE), and multiple address (ADDR) signals. Some signals on the CA bus 102 typically have tight timing margins. Thus, if more than one DIMM is inserted into the memory channel, the load presented on the CA bus 102 can be sufficient to interfere with the quality of the CA signals and limit the performance of the memory channel.

[0012] Figure 2A later-generation DIMM, referred to as Register DIMM 200 (RDIMM), is shown, which includes registers and re-drive circuitry 205 to address the aforementioned limitations in memory channel performance presented by the loaded CA bus 202. Here, the registers and re-drive circuitry 205 serve as a single load for each DIMM on each CA bus 202 line, rather than a load for each block of memory chips (as with UDIMMs). Thus, a nominal dual-block UDIMM will present a load on each line of the CA bus 202 for the memory channels of the memory chips on the UDIMM (because each memory chip wire on the UDIMM is wired to the CA bus 202), whereas a dual-block RDIMM with the same set of memory chips, etc., will present only one chip load on each CA bus 202 line of the memory channels.

[0013] In operation, the register and redrive circuit 205 latches and / or redrives the CA signals from the CA bus 202 of the memory channel to a specific block of memory chips on the DIMM to which the CA signals are specifically sent. Here, for each memory access issued on the memory channel (a read or write access with a corresponding address), the corresponding set of CA signals includes a chip select signal (CS) and / or other signals that specifically identify not only a specific DIMM on the channel but also a specific block on the identified DIMM to which the access is targeted. Therefore, the register and redrive circuit 205 includes logic circuitry that monitors these signals and identifies when its corresponding DIMM is accessed. When the logic circuitry identifies its DIMM as the target, the logic further parses the CA signals to identify the specific block of memory chips on the targeted DIMM. The register and redrive circuitry then effectively routes the CA signals on the memory channel to the specific target block of memory chips on the DIMM 200.

[0014] However, a problem with RDIMM 200 is that the signal lines of the memory channel data bus 201 (DQ) are also coupled to the memory chip blocks 203_1 to 203_X of the DIMM in a multi-branch configuration. That is, for each block of memory chips disposed on the RDIMM, the RDIMM will present a memory chip load on each DQ signal line. Therefore, similar to UDIMM, the number of memory chip blocks that can be disposed on the RDIMM is traditionally limited (e.g., limited to two blocks of memory chips) in order to keep the load on the memory channel data bus 201 of each RDIMM under control.

[0015] Figure 3aA later generation DIMM, called a Load-Reduced DIMM (LRDIMM) 300, is shown, where the CA bus 302 and DQ bus 301 present only a single load of the LRDIMM 300. Here, similar to the register and redrive circuitry of the RDIMM, the LRDIMM includes a buffer circuitry 306 that stores and forwards data that will be transferred between the memory channel data bus 301 and a specific block 303 of the memory chip targeted by the access. The register and redrive circuitry 305 enables any block of the memory chip targeted by a specific access, and the data associated with that access appears "behind" the buffer circuitry 306.

[0016] With only a single point of load on the DQ and CA lines 301, 302 on the memory channels, the memory capacity of the LRDIMM 300 can be unrestricted, expanding its memory storage capacity beyond just two blocks of memory chips (e.g., four blocks on a single DDR4 DIMM). New memory chip packaging technologies that strive to pack more chips into a given space volume have gained significant attention in recent years, thanks to the increased number of memory chip blocks per DIMM and / or the general insensitivity to the number of memory chips per DIMM (at least from a signal loading perspective). For example, stacked chip packaging solutions can be integrated on LRDIMMs to form, for example, 3D stacked (3DS) LRDIMMs.

[0017] Even though the memory capacity of each DIMM has greatly expanded with the advent of LRDIMMs, the memory channel bandwidth is still limited by LRDIMMs because multiple LRDIMMs can be inserted into the same memory channel. That is, multi-branch schemes still exist on memory channels because more than one DIMM can be coupled to the CA and DQ lines of the same memory channel.

[0018] Here, Figure 3b A high-performance memory channel layout 310 is shown, in which two DIMM slots 311_1 and 311_2 are coupled to the same memory channel. Figure 3b Its specific layout is consistent with the Joint Electronic Equipment Committee (JEDEC) Double Data Rate 4 (DDR4) memory standard. Figure 3b As can be seen from layout 310, if the corresponding LRDIMM is inserted into each of the two slots 311_1 and 311_2, then each CA bus and DQ bus will have two loads (one for each LRDIMM). If the load can be further reduced, the timing margin of the CA and DQ signals can also be increased, which in turn will provide a higher memory channel frequency and a corresponding memory channel bandwidth (read / write operations can be performed in a shorter time).

[0019] The next-generation JEDEC memory interface standard (called DDR5) adopts a method of physically separating the CA bus and DQ bus into two separate multi-branch buses, such as... Figure 4a As shown. Here, comparison. Figure 3b and Figure 4a , noticed Figure 3b The layout shows a single N-bit wide CA bus, which is multiplexed to two DIMM slots 311_1 and 311_2; and a single M-bit wide DQ data bus, which is also multiplexed to two DIMM slots 311_1 and 311_2; in contrast, Figure 4a The DDR5 layout includes two separate N / 2-bit wide CA buses, which are multiplexed to two DIMM slots 411_1 and 411_2; and two separate M / 2-bit wide DQ data buses, which are multiplexed to DIMM slots 411_1 and 411_2.

[0020] Furthermore, for simplicity, in two implementations respectively used for DDR4 and DDR5... Figure 3b and 4a In DDR5, the ECC bit is ignored, and M = 64. Therefore, DDR4 has a single 64-bit wide data bus, while DDR5 has two 32-bit wide data buses (DQ_1 and DQ_2). Thus, a "block" in a DDR5 system corresponds to 32 bits instead of 64 bits (the width of the DQ_1 and DQ_2 data buses is M / 2 = 64 / 2 = 32 bits). Similarly, in a DDR5 system, a block of memory chip receives 32 bits of data from the sub-channel in a single transfer, unlike in DDR4 which receives 64 bits.

[0021] However, it is worth noting that Figure 4a The JEDEC DDR5 layout still uses a multi-branch bus scheme. That is, as... Figure 4a As shown, these two pairs of CA and DQ buses are branched to two DIMM slots 411_1 and 411_2. Because the CA and DQ buses employ a multi-branch scheme, ... Figure 3b Compared to earlier channels, the operating frequency of DDR5 channels did not increase fundamentally, and the data rate of DDR5 memory channels did not increase accordingly. That is, in terms of data rate, Figure 4a The physical layout usually has the same as Figure 3b It has the same physical limitations as the previous generation of memory channels.

[0022] therefore, Figure 4b An improved memory channel scheme is shown, which conforms to the DDR5 host-side interface 430 (at least in terms of CA and DQ bus line count, pinouts, and / or signaling), but in which the different DIMMs are not coupled to the interface 430 in a multi-branch manner. Instead, a comparison is made. Figure 4aand Figure 4b , Figure 4b The data bus of the memory channel is divided into a pair of point-to-point (P2P) data buses, DQ_1 and DQ_2, each connecting a different DIMM to the host. This utilizes point-to-point links instead of multi-branch buses. Figure 4b In the improved layout, Figure 4b The layout should be able to show more than Figure 4a The nominal DDR5 method has a faster operating frequency and / or data rate.

[0023] Figure 4c An improved DIMM 400, called an enhanced LRDIMM (eLRDIMM), is shown, which can be inserted... Figure 4b In either of slots 421_1 or 421_2, the improved memory channel design is used. Here, Figure 4c The eLRDIMM 400 is designed to multiplex 32-bit transfers to two different blocks of a memory chip within the same burst time window. More specifically, the DIMM 400 is designed to multiplex data transfers between a block (rank_0 or rank_1) of a memory chip from group 409_1 and a block (rank_2 or rank_3) of a memory chip from group 409_2.

[0024] Figure 4d A high-level view of the write timing is shown. Illustration 410 shows the... Figure 4c The improved eLRDIMM 400 performs write transfers, while illustration 420 shows a comparison point. Figure 3a The write transfer of the prior art DDR4 LRDIMM 300. As observed in Illustration 420, the prior art DDR4 LRDIMM 300 receives eight 64-bit transfers on eight cycles 0 to 7 to achieve a total burst of 512 bits.

[0025] In contrast, the improved eLRDIMM write process described in reference illustration 410 involves a transfer process on a single data bus (DQ_1) comprising two multiplexed data streams 408, 412, targeting different blocks of the memory chip of the eLRDIMM coupled to the data bus (eLRDIMM 1). Specifically, reference... Figure 4c Data stream 408 is targeted to one of block 0 and block 1, and data stream 412 is targeted to one of block 2 and block 3. Multiplexer 407 on eLRDIMM provides multiplexing of data transfer on DQ_1 bus between the two target blocks of the memory chip.

[0026] More specifically, during the first cycle (0) of the eLRDIMM data strobe (DQS) signal 413, the first 32-bit transfer on the DQ_1 bus targets the first block of the memory chip in group 409_1 at base address A. During the immediately following second DQS cycle (1), the second 32-bit transfer on the DQ_1 bus targets the second block of the memory chip in group 409_2 at base address B. During the immediately following third DQS cycle (3), the third 32-bit transfer on the DQ_1 bus targets the first block of the memory chip in group 409_1 at the incremented address A+1. During the immediately following fourth DQS cycle, the fourth 32-bit transfer on the DQ_1 bus targets the fourth block of the memory chip in group 409_2 at the incremented address B+1.

[0027] This process continues until 512 bits are transferred for the two target blocks of the memory chip. This corresponds to 16 cycles for each target block of the memory chip (32 bits transferred each time × 16 transfers = 512 bits), which, due to multiplexing activity, corresponds to a total of 32 cycles for the DQS signal 413. Therefore, Figure 4d Only half of the full 512 transfers for each target block of the memory chip are shown (only eight cycles are shown for each target block).

[0028] Note that the total amount of data transferred on the DQ_1 bus in the eight cycles shown by eLRDIMM process 420 (256 bits per stream 408 and 412 = 512 bits in total) is the same as the total amount of data transferred by prior art DDR4 process 410 (64 bits per transfer × 8 transfers = 512 bits). However, because there are two separate DQ data buses (DQ_1 and DQ_2) with eLRDIMM interface 430, two different eLRDIMMs (eLRDIMM 1 on DQ_1 and eLRDIMM 2 on DQ_2) can be accessed simultaneously, thus doubling the bandwidth of the entire eLRDIMM memory interface 430 from the host's perspective compared to the DDR4 interface.

[0029] That is, when considering DQ_1 and DQ_2, the data transmitted by the eLRDIMM write process 420 is twice that of the prior art DDR4 process 410. Therefore, from the host's perspective, the doubled speed of the eLRDIMM DQS signal 413 compared to the prior art DDR4 DQS signal translates to a doubled total data rate through the interface 430. Utilizing the higher frequency DQS signal 413 and associated data signals on the DQ_1 and DQ_2 buses of the eLRDIMM method 410 is feasible because, as mentioned above... Figure 4bThe discussion did not employ a multi-branch bus approach on either the DQ_1 or DQ_2 buses, which allows for higher frequency signals to exist on these buses.

[0030] Importantly, the speed / frequency of the memory chips on the eLRDIMM does not need to be doubled. Here, the multiplexing activity of the eLRDIMM enables one transmission to each target block of the memory chip per DQS cycle. Thus, with only one transmission per DQS cycle, both blocks of the target memory chip are transmitted at a speed comparable to... Figure 3a The existing LRDIMM300 memory chip operates at roughly the same frequency / speed.

[0031] eLRDIMM method 410 also transmits combined data for two blocks of the memory chip according to double data rate technology on the DQ_1 and DQ_2 buses (the rising and falling edges of the DQS signal 413 correspond to the DQS cycle). However, the multiplexing activity on the eLRDIMM results in access to the memory chip itself according to double data rate technology, where the clock frequency is half the frequency of the DQS signal 413 (each memory chip experiences data transmission on the rising and falling edges of a clock similar to the slower clock 414). These clocks are... Figure 4d The DQS / 2_Φ1 and DQS / 2_Φ2 signals are represented in the figure.

[0032] The DQS / 2_Φ1 and DQS / 2_Φ2 signals indicate that different target blocks of memory chips multiplexed on the same burst window can be accessed at different times. For example, blocks from memory chips in the first group 409_1 are accessed during the first clock phase, and blocks from memory chips in the second group 409_2 are accessed during the second (e.g., lagging) clock phase. In such an embodiment, data blocks arrive from buffer logic 406 in the order they are received from the data bus (in the case of a write). The multiplexer 407 then directs the data to the target in the correct memory chip. Here, the register and re-drive circuit 405 can generate the correct channel selection input to the multiplexer 407 and the memory chip access signal to the correct block of memory chip to achieve correct multiplexing activity.

[0033] Other methods may select to access different target blocks of a memory chip that are multiplexed in phase (simultaneously) on the same burst window. For example, according to the method, buffer logic circuitry 406 may, for example, apply a store-and-forward method to one of the target block data streams to eliminate phase differences between the individual data streams of the pair of target blocks on the data bus. For example, refer to Figure 4dThe data for the memory chip blocks in the first group 409_1 (represented by stream 408) can be delayed by one cycle of the DQS signal 413 by the buffer circuit 406, which temporarily aligns the data with the data for the memory chip blocks in the second group 409_2 (represented by stream 412). Data from both streams can then be written simultaneously to the two target blocks of the memory chip.

[0034] Note that this method eliminates the presence of any actual multiplexing circuitry 406. That is, the multiplexing activity of the eLRDIMM is logically (but not actually) implemented as store-and-forward by buffer circuitry. Thus, multiplexing circuitry should be understood to include not only the actual multiplexing circuitry (e.g., multiplexer 407) but also circuitry for eliminating phase differences in the data through store-and-forward (which can be performed by buffer circuitry 406). Other embodiments may include actual multiplexing circuitry alongside store-and-forward circuitry. In embodiments that do use actual multiplexing circuitry, this actual multiplexing circuitry may be physically integrated into the buffer semiconductor chip used to implement buffer circuitry 406.

[0035] To reiterate, in actual DDR5 implementations, the block size is 32 bits, corresponding to the amount of data transferred on the data bus per DQS cycle. However, the data bus size is larger than the size that can accommodate ECC bits (e.g., 32 bits of data plus 8 bits of ECC = 40 total data bus bits). The memory chip blocks are also designed with a data width to accommodate both data and ECC (e.g., 40 bits wide).

[0036] Although the above description pertains to the write process, a read process can occur by reading data from selected blocks on two DIMMs consistent with the techniques described above. Similar to writing, a pair of target blocks on a memory chip can be accessed out of phase with each other (e.g., using actual multiplexing circuitry and without store-and-forward in the read direction of the buffer circuitry) or simultaneously with each other (e.g., with store-and-forward in the read direction of the buffer circuitry).

[0037] Figure 4eAnother eLRDIMM embodiment is shown, in which the data bus simultaneously transmits two “half rank” segments of two target blocks of the memory chip. For example, again using the DDR5 example, the data bus physically includes wiring for 32 data transmission bits. However, during any single transmission on the bus, a first set of 16 bits is used for the first target block of the memory chip, and a second set of 16 bits is used for the second target block of the memory chip. Therefore, the multiplexing performed on the eLRDIMM is “in-block” because two consecutive 16-bit transmissions on the data bus are either up-multiplexed (in the case of a write) or down-multiplexed (in the case of a read) between the data bus and the 32-bit wide target blocks of the memory chip.

[0038] Therefore, the eLRDIMM consists of two separate 16-bit wide data interfaces 421 and 422, each with its own dedicated logic that multiplexes two different 16-bit halves of the target block of the memory chip. Figure 4e In a specific eLRDIMM embodiment, for any given burst write sequence, the first 16-bit wide interface 421 multiplexes between half of the rank_0 block or the rank_1 block of the memory chip, and the second 16-bit wide interface 422 multiplexes between half of the rank_2 block or the rank_3 block of the memory chip.

[0039] Figure 4f The corresponding timing diagram is shown. Here, it is observed that the DQ_1 and DQ_2 data buses are multiplexed between: 1) a first data stream 438, which simultaneously carries the first half of block 0 or block 1 and the first half of block 2 or block 3; and 2) a second data stream 442, which simultaneously carries the second half of block 0 or block 1 and the second half of block 2 or block 3. Again, in the case of DDR5, half a block corresponds to 16 bits. By carrying two half blocks simultaneously during any given DQS cycle, 32 data bits are transmitted per cycle.

[0040] Figure 4g It shows the use of Figure 4e Additional details regarding the specific data bus transfers in the eLRDIMM embodiment. Here, it is noteworthy that the addresses of different target blocks (A and B) of the memory chip are multiplexed on the CA bus over consecutive DQS cycles. Figure 4g The relative timing between data bus transfers and memory accesses during write and read processes is also shown. Similar to... Figure 4cFor eLRDIMM, the multiplexing of half a block can be accomplished using actual multiplexing circuitry (e.g., multiplexers 427, 429) or logic multiplexing circuitry (e.g., using buffer circuitry 426, 428 for storage and forwarding) or some combination of both. The actual multiplexer circuitry can be integrated into the buffer semiconductor chip.

[0041] Figure 5a An exemplary memory controller 501 is shown, which is capable of driving a memory controller having data buses DQ_1 and DQ_2 inserted therein, as described above. Figure 4c The memory controller includes first and second memory interfaces 504_1 and 504_2, each including a pair of DQ point-to-point link interfaces for corresponding to the respective DIMM in a point-to-point manner, as described above. Therefore, each interface includes first and second sets of input / output (I / O) coupled to the first and second DQ point-to-point links, respectively.

[0042] like Figure 5a As observed, the memory controller receives memory read and write requests at input node 502. The scheduler and address mapping circuitry 503 command the requests and direct them to the appropriate memory channel interface (e.g., interface 504_1 or 504_2). It is worth noting that each memory channel interface includes its own address mapping logic (not shown in the diagram for illustration purposes). Figure 5a As shown in the diagram, each request is mapped to its correct DIMM slot (in other words, the correct one of DQ_1 and DQ_2). Thus, utilizing two separate DQ channels terminating in two separate DIMM slots, the memory interface circuit 504_1 itself must map the address of the request it receives to a specific one of the DQ channels / DIMM slots.

[0043] Here, inbound queues 505_1 and 505_2 precede each interface 504_1 and 504_2, and the interface's address mapping circuitry can extract requests out of order from the queues to keep the two DIMMs coupled to the interface busy (e.g., if the front of the queue contains a request mapped to only one of the DQ buses, the address mapping logic can extract a request mapped to the other DQ channel from a deeper back of the queue). This request extraction can further account for multiplexing activities on any given DQ bus. For example, as per [reference to...] Figure 4c As described in the eLRDIMM implementation, the eLRDIMM is configured to simultaneously multiplex memory chip blocks between two different groups, "left" group 409_1 and "right" group 409_2.

[0044] Here, certain higher bits of the requested address can be mapped to one or the other of these groups 409_1, 409_2. In order to maintain the maximum capacity of a particular DQ bus where possible, the interface's address mapping logic can serve requests out of order from the interface's queue, so that requests whose addresses are mapped to different groups of the same eLRDIMM (same DQ bus) can be served simultaneously and multiplexed on the specific DQ bus of the eLRDIMM.

[0045] Similarly, the memory interface circuit 504_1 includes a pair of multiplexer circuits 506_1 and 506_2, one for each DQ bus (DQ_1 and DQ_2), to multiplex data from two different block groups to / from the same DQ bus during the same burst transmission process as described above. As described above, the two multiplexers 506_1 and 506_2 can operate simultaneously to transmit four data blocks of data simultaneously between the interface 504_1 and a pair of DIMM slots coupled thereto during the same burst transmission sequence. Multiplexing can be performed either physically or logically (e.g., using store-and-forward circuitry).

[0046] Each memory interface 504_1, 504_2 also includes signal generation logic to generate appropriate CA and DQ signals for each DIMM, consistent with the teachings above. The memory controller 501 may include a configuration register space (not shown in Figure 5 for illustration purposes), with corresponding information used to configure each memory interface. In one embodiment, the register space is used to define whether the memory interface will operate in eLRDIMM mode as described above, or according to DDR5 mode. If the latter is specified, multiplexing activities of the memory controller are disabled, and only a single block of data from the memory chip is propagated on either DQ_1 or DQ_2 bus during burst transfers.

[0047] Figure 5b An embodiment of a memory controller is shown, which is designed to work with... Figure 4e The eLRDIMM implementation communicates. For simplicity, each interface shows circuitry that only feeds one of the DQ buses of the interface. Here, the memory controller is as described above. Figure 5a The operation described herein, except that the transfer of memory chips in the left and right groups of the same eLRDIMM is carried out simultaneously on different halves of the DQ bus to which the eLRDIMM is connected (in Figure 4eIn this context, rank_0 and rank_1 correspond to the left block group, while rank_2 and rank_3 correspond to the right block group. Thus, there are left block group channels and right block group channels, which are physically attached to each other at the DQ interface. The two channels have corresponding multiplexers 516_1 and 516_2 for multiplexing between halves of the same target block, as referenced above. Figure 4e and 4f As stated above.

[0048] Here, the address mapping circuitry within interface 514 enables the interface to serve requests out of order, not only keeping different DQ buses busy but also facilitating multiplexing on any particular DQ bus. Similarly, the address mapping circuitry will again be expected to pull together requests for different block groups of the same eLRDIMM so that they can be multiplexed together on the eLRDIMM's DQ bus.

[0049] While the above discussion pertains to a specific DDR5 implementation, specifying, for example, the number of cycles per burst transaction, the number of DIMM slots per interface, a 2:1 multiplexing ratio, and the memory chip clock being half the channel clock, it should be recognized that other embodiments with different numbers of these and other features beyond those described above are appropriate. For example, DIMMs architecturally grouped into blocks of four can use a 4:1 multiplexing ratio and memory chips receiving a DQS / 4 clock. Embodiments also exist with values ​​of M other than 64 or block sizes other than 32.

[0050] Figure 6 An exemplary illustration of a computing system 600 (e.g., a smartphone, tablet computer, laptop computer, desktop computer, server computer, etc.) is provided. Figure 6 As observed, the basic computing system 600 may include a central processing unit 601 (which may include, for example, multiple general-purpose processing cores 615_1 to 615_X) and a main memory controller 617 disposed on a multi-core processor or application processor, system memory 602, a display 603 (e.g., a touch screen, a tablet), a local wired point-to-point link (e.g., USB) interface 604, various network I / O functions 605 (e.g., Ethernet interface and / or cellular modem subsystem), a wireless local area network (e.g., WiFi) interface 606, a wireless point-to-point link (e.g., Bluetooth) interface 607 and a global positioning system interface 608, various sensors 609_1 to 609_Y, one or more cameras 610, a battery 611, a power management control unit 612, speakers and microphones 613, and an audio encoder / decoder 614.

[0051] The application processor or multi-core processor 650 may include one or more general-purpose processing cores 615, one or more graphics processing units 616, memory management functions 617 (e.g., a memory controller), and I / O control functions 618 within its CPU 601. The general-purpose processing cores 615 typically execute the operating system and application software of the computing system. The graphics processing units 616 typically perform graphics-intensive functions, such as generating graphical information to be displayed on the display 603. The memory control functions 617 interface with the system memory 602 to write / read data to / from the system memory 602. The power management control unit 612 typically controls the power consumption of the system 600.

[0052] Each of the touchscreen display 603, communication interfaces 604-507, GPS interface 608, sensor 609, camera 610, and speaker / microphone codecs 613, 614 can be considered as various forms of I / O (input and / or output) relative to the overall computing system, and where appropriate, integrated peripherals (e.g., one or more cameras 610) may also be included. Depending on the implementation, various components of these I / O components may be integrated on the application processor / multi-core processor 650, or may be located off-die or outside the package of the application processor / multi-core processor 650. The computing system also includes non-volatile memory 620, which may be a high-capacity storage component of the system.

[0053] The main memory control function 617 (e.g., main memory controller, system memory controller) can be designed to conform to the teachings of the host-side memory interface described above, which is capable of multiplexing data pointing to / from different blocks of the memory chip to / from, for example, an eLRDIMM as described above, through the same host-side memory interface during the same burst transfer.

[0054] Embodiments of the present invention may include the various processes described above. These processes may be embodied in machine-executable instructions. These instructions may be used to cause a general-purpose or special-purpose processor to perform certain processes. Alternatively, these processes may be executed by specific / custom hardware components that include hard-wired logic circuitry or programmable logic circuitry (e.g., field-programmable gate arrays (FPGAs), programmable logic devices (PLDs)) for performing the processes, or by any combination of programmed computer components and custom hardware components.

[0055] The elements of the present invention can also be provided as a machine-readable medium for storing machine-executable instructions. Machine-readable media may include, but are not limited to, floppy disks, optical disks, CD-ROMs and magneto-optical disks, flash memory, ROM, RAM, EPROM, EEPROM, magnetic cards or optical cards, propagation media, or other types of media / machine-readable media suitable for storing electronic instructions. For example, the present invention can be downloaded as a computer program that can be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a modem or network connection) via a carrier wave or other propagation medium embodied in the data signal.

[0056] In the foregoing description, the invention has been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and changes can be made to the invention without departing from the broader spirit and scope set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A DIMM (Dual In-line Memory Module) device, comprising: A multiplexer DIMM, the multiplexer DIMM including circuitry for multiplexing write data onto different groups of memory chips during the same burst write sequence; Specifically, time-based multiplexing is used to write the write data to different groups of memory chips on the DIMM; and The multiplexer circuit includes a buffer for storing and forwarding the written data; and Specifically, a separate channel is used for multiple groups of memory chips on the DIMM.

2. The apparatus according to claim 1, wherein, The different groups of memory chips are memory chips in different blocks.

3. The apparatus according to claim 1, wherein, The different groups of memory chips are memory chips in different half blocks.

4. The apparatus according to claim 1, wherein, The multiplexer is used to multiplex different target address values ​​with different base address values ​​during the same first burst write sequence to the first DIMM.

5. The apparatus according to claim 4, wherein, The multiplexer is used to multiplex the reception of read data from different groups of memory chips on the same DIMM in the first DIMM and the second DIMM during the same burst read sequence time period.

6. The apparatus according to claim 4, wherein, The multiplexer is used to multiplex the reception of read data from memory chips from different groups on another DIMM of the first DIMM and the second DIMM during the same burst read sequence.

7. The apparatus of claim 1 further includes a DDR5 memory channel interface.

8. The apparatus of claim 1, further comprising a memory controller configured to disable DDR5 operation to facilitate multiplexing between different groups of memory chips on the same DIMM during burst write and burst read sequences.

9. A hardware computer-readable storage device, comprising instructions that, when executed, cause a machine to at least: During the same burst write sequence, write data is multiplexed to different groups of memory chips on a dual in-line memory module (DIMM); The write data is written to different groups of memory chips on the DIMM by using time-based multiplexing; as well as The written data is stored and forwarded in a buffer by a multiplexer circuit; as well as In this case, a separate channel is used for multiple groups of memory chips on the DIMM.

10. The device according to claim 9, wherein, The different groups of memory chips are memory chips in different blocks.

11. The device according to claim 9, wherein, The different groups of memory chips are memory chips in different half blocks.

12. The device according to claim 9, wherein, During the same first burst write sequence to the first DIMM, the write data is multiplexed between different target address values ​​with different base address values.

13. The device according to claim 12, wherein, The written data is multiplexed during the same burst read sequence time period, and the read data received from different groups of memory chips on the same DIMM in the first DIMM and the second DIMM is multiplexed.

14. The apparatus of claim 12 is further configured to multiplex the reception of read data from memory chips of different groups on another DIMM of the first DIMM and the second DIMM during the same burst read sequence.

15. The device of claim 9 is further configured to write the write data using a DDR5 memory channel interface.

16. The device of claim 9 is further configured to disable DDR5 operation to facilitate multiplexing between different groups of memory chips on the same DIMM during burst write and burst read sequences.

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