Extensible distributed board card structure based on PXIe bus

Abstract

The invention relates to the technical field of computer buses, and particularly discloses a PXIe bus-based extensible distributed board card structure, which comprises a carrier board and a daughter board, and is characterized in that the carrier board comprises an FPGA module, a memory module, a flash memory module, a power management module, two high-speed interfaces and two PXIe interfaces; the carrier plate is connected with the daughter board through two high-speed interfaces; the first PXIe interface transmits a synchronous clock to the FPGA module; the second PXIe interface is in two-way communication with the FPGA module; the power supply management module converts an external power supply input by the second PXIe interface and then supplies power to the FPGA module, the memory module, the flash memory module and the two high-speed interfaces; the FPGA module is used for outputting the high-speed differential signals and the synchronous clock to the two high-speed interfaces and receiving the high-speed differential signals input by the two high-speed interfaces. According to the invention, systematic breakthrough is realized in key dimensions such as expansibility, supply chain safety, power management, electromagnetic compatibility, structural flexibility and environmental adaptability.

Description

Technical Field

[0001] This invention relates to the field of computer bus technology, and more specifically, to a scalable distributed board structure based on the PXIe bus. Background Technology

[0002] PXIe bus technology, as a key supporting technology in the test and measurement field, has been widely used in high-end testing scenarios such as aerospace, semiconductor testing, and automotive electronics due to its high-speed data transmission capabilities (supporting up to PCIe 4.0 protocol, with a unidirectional bandwidth of up to 32Gbps) and modular architecture advantages. Traditional PXIe board structures generally adopt a single-interface design and centralized power management scheme. Its typical architecture is characterized by the board communicating with the bus backplane through a single connector, with the power module centrally deployed on the board and supplying power to all functional modules. The core processing unit mostly relies on imported FPGA chips (such as the Xilinx Kintex series) to realize signal processing and bus control. This architecture can meet the basic functional requirements of small and medium-sized test systems, but as the complexity of the test objects increases (such as 5G multi-channel RF testing and chip multi-pin parallel testing), its inherent defects have gradually become a key bottleneck restricting the performance improvement of test systems.

[0003] Analysis of existing technological defects: 1. Limitations in scalability Traditional circuit boards employ a fixed interface design, with each module virtualized to match standard benchtop instruments. Signal output and input remain consistent with standard instruments, making expansion impossible to fully adapt to the needs of various applications. External signal conditioning circuitry is required for interface matching, leading to extended hardware development cycles (an average increase of 3-6 months) and increased costs (40%-60% increase in R&D expenses). This model severely limits the flexible configuration capabilities of testing systems, making it difficult to adapt to the dynamic demands of modern testing scenarios involving diverse products and small batches.

[0004] 2. Complex power management In a centralized power supply architecture, simultaneous power-on of multiple modules generates instantaneous high currents (peak values ​​exceeding 20A), causing voltage fluctuations exceeding ±5% (beyond the ±3% range recommended in the chip datasheet). Furthermore, the lack of an independent timing control unit leads to frequent instances of disordered power-on sequences. Industry statistics show that approximately 32% of board hardware failures originate from power timing issues, directly causing chip damage and test interruptions.

[0005] 3. Poor electromagnetic compatibility High-speed signals (such as differential signals above 10Gbps) are prone to generating electromagnetic radiation in long-distance wiring of traditional circuit boards. The radiation intensity can reach 40dBμV / m (at a frequency of 30MHz), exceeding the limit of 34dBμV / m specified by the CISPR22 standard. This electromagnetic interference not only affects the signal integrity between modules within the board, but also causes crosstalk to nearby test equipment, leading to a decrease in test accuracy (such as an increase in RF signal measurement error of more than 0.5dB).

[0006] 4. Dependence on imported core chips The core processing units of current mainstream PXIe boards (such as FPGAs and high-speed serial transceivers) are highly dependent on foreign manufacturers such as Xilinx and Altera, making them significantly affected by fluctuations in the international supply chain. Between 2021 and 2023, the delivery cycle for Xilinx FPGA chips increased from 12 weeks to over 52 weeks, leading to a 28% increase in board production downtime and severely impacting the delivery cycle of test systems. Furthermore, export restrictions on high-end chips have further exacerbated supply chain security risks.

[0007] 5. Low collaboration efficiency Traditional architectures employ a shared clock and data channel design, which can easily lead to data conflicts when multiple modules work in parallel. For example, in an 8-channel synchronous acquisition scenario, due to the lack of an independent channel arbitration mechanism, data transmission latency fluctuations can reach 200ns, and synchronization accuracy drops to the 1μs level, failing to meet the requirements of high-precision testing (such as coherent radar signal testing which requires 10ns-level synchronization).

[0008] Summary of technical pain points: The traditional PXIe board structure has significant defects in five dimensions: scalability, power management, electromagnetic compatibility, supply chain security and collaborative efficiency. These problems are superimposed, making it difficult for the test system to break through the bottleneck in terms of channel density, test accuracy, reliability and cost control. It is urgent to achieve technical upgrades through architectural innovation. Summary of the Invention

[0009] To address the shortcomings of existing technologies, this invention provides a scalable distributed board structure based on the PXIe bus, aiming to solve the technical problems of limited scalability, complex power management, poor electromagnetic compatibility, dependence on imported core chips, and low collaborative efficiency in existing technologies.

[0010] As a first aspect of the present invention, a scalable distributed board structure based on the PXIe bus is provided. The scalable distributed board structure based on the PXIe bus includes a carrier board and a daughter board. The carrier board includes an FPGA module, a memory module, a flash memory module, a power management module, a first high-speed interface, a second high-speed interface, a first PXIe interface, and a second PXIe interface. The carrier board is connected to the daughter board through the first high-speed interface and the second high-speed interface. The first PXIe interface is used to transmit the clock PXIe_CLK100 and the synchronization clock PXIe_SYNC100 of the external PXIe bus to the FPGA module; the second PXIe interface communicates bidirectionally with the FPGA module through a trigger bus. The second PXIe interface is used to transmit external power to the power management module; the power management module is used to convert the external power into multiple isolated power supplies to power the FPGA module, memory module, flash memory module, first high-speed interface and second high-speed interface; The FPGA module and the memory module can complete the writing and reading of cached data; the FPGA module and the flash memory module can complete the writing and reading of configuration data; the FPGA module is used to output the high-speed differential signal and the synchronous clock PXIe_SYNC100 to the first high-speed interface and the second high-speed interface respectively, and to receive the high-speed differential signal input from the first high-speed interface and the second high-speed interface.

[0011] Furthermore, when the carrier board is connected to a sub-board, the sub-board includes a third high-speed interface and a fourth high-speed interface; The carrier plate is provided with a plurality of M3 studs, and the sub-plate is provided with a plurality of through holes that mate with the M3 studs. The sub-plate is placed on the carrier plate through the mating M3 studs and through holes, and the carrier plate and the sub-plate are fixed with M3 screws. At this time, the third high-speed interface is plugged into the first high-speed interface, and the fourth high-speed interface is plugged into the second high-speed interface for signal and data interaction.

[0012] Furthermore, when the carrier board connects two sub-boards, each sub-board includes a high-speed interface. The high-speed interface on the first sub-board is plugged into the first high-speed interface, and the high-speed interface on the second sub-board is plugged into the second high-speed interface to perform signal and data interaction.

[0013] Furthermore, the second PXIe interface is used to transmit external power supplies of +3.3V, +5V, +12V and -12V to the power management module; The power management module is used to convert the external power supply into isolated +3.3V and +12V power supplies to power the first high-speed interface and the second high-speed interface respectively. The power management module is used to convert the external power supply into isolated power supplies of +0.675V and +1.35V to power the memory module. The power management module is used to convert the external power supply into isolated power supplies of +1.8V and +3.3V to power the flash memory module; The power management module is used to convert the external power supply into isolated power supplies of +0.85V, +1.2V, +1.8V and +3.3V to power the FPGA module.

[0014] Furthermore, the power management module includes a three-way buck converter, a dual-channel converter, and an LDO regulator; wherein, the voltage output by the three-way buck converter supplies power to the FPGA module; the voltage output by the three-way buck converter and the dual-channel converter supplies power to the memory module; and the voltage output by the LDO regulator supplies power to the first high-speed interface and the second high-speed interface, respectively.

[0015] Furthermore, both the first high-speed interface and the second high-speed interface are model QSH-060-01-LDAK, each containing 120 signal pins, and the transmission rate of the high-speed differential signal reaches 5GHz.

[0016] Furthermore, the FPGA module has 285 I / O interfaces, including 16 GTP high-speed serial transceivers, with a single-channel data rate of 6.5Gbps.

[0017] Furthermore, the memory module is model MT41K256M16, with a capacity of 256Mb×16bit, an operating voltage of 1.35V, a data rate of 1600MT / s, an 8-bit prefetch architecture, and supports 8 / 4 burst length mode switching; the flash memory module is model YX2M256I, with a capacity of 256MB, supports a four-channel SPI interface, a maximum transmission rate of 416Mbit / s, and is used to store the FPGA module's configuration file and firmware.

[0018] Furthermore, the carrier board also includes an ESD protection module, which comprises three release strips that achieve electrostatic discharge through a 10MΩ resistor and direct grounding. The first release strip is connected to the front panel of the chassis via a 10MΩ resistor to release static electricity generated by contact with the carrier board or external sources, with the 10MΩ resistor limiting the discharge current. When the carrier board is further inserted into the chassis rail slot, the second release strip is used to release static electricity from the carrier board's ground plane. The third release strip is directly connected to the front panel of the chassis to provide an electrostatic discharge path for the carrier board to be further inserted into the backplane connector, and also to provide an electrostatic discharge path from the front panel of the chassis to the chassis ground.

[0019] Furthermore, the daughterboard obtains a 12V DC input voltage through the second PXIe interface of the carrier board, generates the required operating voltage through the local DC-DC converter of the daughterboard, and supports a maximum current output of 5A. The carrier board provides a 100MHz differential reference clock, and the daughter board multiplies the clock to the operating frequency via a PLL, supporting an adjustable range of 1MHz to 200MHz. The sub-board uses multiple pairs of high-speed differential signals to achieve high-speed data transmission, and is supplemented by multiple GPIO interfaces to realize control signal interaction; The daughterboard supports hot-plugging functionality, and a dedicated detection circuit enables real-time detection of daughterboard insertion / removal and system state switching.

[0020] The scalable distributed board structure based on the PXIe bus provided by this invention has the following advantages: Through hardware architecture design and localization technology path, it has achieved systematic breakthroughs in key dimensions such as scalability, supply chain security, power management, electromagnetic compatibility, structural flexibility and environmental adaptability, effectively solving the technical pain points of traditional PXIe boards such as limited scalability, reliance on imported core chips and insufficient power stability. Attached Figure Description

[0021] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof.

[0022] Figure 1 The schematic diagram of the scalable distributed board structure based on the PXIe bus provided by this invention.

[0023] Figure 2 This is a schematic diagram showing the connection between the carrier plate and the sub-plate provided by the present invention.

[0024] Figure 3 This is a schematic diagram of the carrier plate provided by the present invention.

[0025] Figure 4This is a schematic diagram of the sub-plate provided by the present invention.

[0026] Figure 5 The pin definition diagram of the high-speed interface provided by this invention.

[0027] Figures 6A-6D The circuit diagram of the power management module provided by the present invention.

[0028] Figure 7 The design diagram of the ESD protection module for the carrier board provided by the present invention. Detailed Implementation

[0029] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of the scalable distributed board structure based on the PXIe bus proposed by the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0030] This embodiment provides a scalable distributed board structure based on the PXIe bus, such as... Figure 1 As shown, the scalable distributed board structure based on the PXIe bus includes a carrier board 1 and a daughter board 2. The carrier board 1 includes an FPGA module 11, a memory module, a flash memory module, a power management module, a first high-speed interface 12, a second high-speed interface 13, a first PXIe interface XJ3, and a second PXIe interface XJ4. The carrier board 1 is connected to the daughter board 2 through the first high-speed interface 12 and the second high-speed interface 13. The first PXIe interface XJ3 is used to transmit the clock PXIe_CLK100 and the synchronization clock PXIe_SYNC100 of the external PXIe bus to the FPGA module 11; the second PXIe interface XJ4 communicates bidirectionally with the FPGA module 11 through the trigger bus TRIGER0..7 of the PXIe bus. The second PXIe interface XJ4 is used to transmit external power supplies of +3.3V, +5V, +12V and -12V to the power management module; the power management module is used to convert the external power supplies into multiple isolated power supplies to power the FPGA module 11, memory module, flash memory module, first high-speed interface 12 and second high-speed interface 13. The FPGA module 11 and the memory module can complete the writing and reading of cached data, providing high-speed storage space for data caching and complex algorithm processing; the FPGA module 11 and the flash memory module can complete the writing and reading of configuration data, realizing the storage and loading of FPGA firmware, ensuring system flexibility and reliability; the FPGA module 11 is used to output high-speed differential signals and synchronous clock PXIe_SYNC100 to the first high-speed interface 12 and the second high-speed interface 13 respectively, and receive high-speed differential signals input from the first high-speed interface 12 and the second high-speed interface 13.

[0031] Preferably, such as Figures 2-4 As shown, when the carrier board 1 is connected to a sub-board 2, the sub-board 2 includes a third high-speed interface 21 and a fourth high-speed interface 22; The carrier plate 1 is provided with a plurality of M3 studs 14, and the sub-plate 2 is provided with a plurality of through holes 23 that mate with the M3 studs 14. The sub-plate 2 is placed on the carrier plate 1 through the mating M3 studs 14 and through holes 23, and the carrier plate 1 and the sub-plate 2 are fixed with M3 screws 3. At this time, the third high-speed interface 21 is plugged into the first high-speed interface 12, and the fourth high-speed interface 22 is plugged into the second high-speed interface 13 for signal and data interaction.

[0032] Preferably, when the carrier board 1 is connected to two sub-boards 2, each sub-board includes a high-speed interface. The high-speed interface on the first sub-board 2 is connected to the first high-speed interface 12, and the high-speed interface on the second sub-board 2 is connected to the second high-speed interface 13 for signal and data interaction.

[0033] Specifically, such as Figure 3 As shown, the upper surface of the carrier board 1 is provided with a hollow heat dissipation groove 15 (accounting for 15% of the area), and a total of 8 M3 studs 14 at the four corners and the center. The hollow heat dissipation groove 15 can improve air convection efficiency (heat dissipation capacity is improved by 20%), and the layout of 8 M3 studs 14 provides rigid support for the stacking of twin boards, meeting the requirements of the PXIe specification for the physical interface of the board.

[0034] In embodiments of the present invention, such as Figure 3As shown, the carrier board 1 has specific structural dimensions of 161mm × 100mm. The carrier board adopts a standard PXIe modular design, resulting in a compact and rational overall structure. A large area of ​​open space is designed in the central region of the board, primarily to provide space for the installed sub-boards, optimize heat dissipation, and reduce the weight of the board. Evenly distributed fixing studs around the open space are used to securely connect the sub-boards, allowing for the simultaneous fixing of two sub-boards and ensuring good mechanical stability during vibration or long-term operation. A PXIe backplane connector is located on the right side, supporting modular plugging and unplugging and high-speed data exchange. The right side also features a power interface and heat dissipation structure, further enhancing the overall system reliability and thermal management performance.

[0035] Specifically, such as Figure 4 As shown, one side of daughterboard 2 has an external interface 24, and the other side has a high-speed interface, which is tightly connected to the carrier board. The carrier board is partially perforated to facilitate heat dissipation for the daughterboard, and there are 8 fixing studs on the carrier board for fixing the daughterboard. According to the PXI / CPCI specifications, the thickness of each board should be within 20.32mm (800mil), the thickness of the carrier board PCB is 1.6mm, the high-speed interface combination between boards is 10mm, the height of components placed on the back of the carrier board should not exceed 2mm, the thickness of the daughterboard PCB is 1.6mm, and the height of components on the back of the daughterboard should preferably not exceed 2mm. The daughterboard can place components according to the height of the components on the carrier board to avoid position conflicts that would cause the height between boards to exceed 10mm.

[0036] Preferably, the second PXIe interface XJ4 is used to transmit external power supplies of +3.3V, +5V, +12V and -12V to the power management module; The power management module is used to convert the external power supply into isolated power supplies of +3.3V and +12V, which are used to supply power to the first high-speed interface 12 and the second high-speed interface 13 respectively. The power management module is used to convert the external power supply into isolated power supplies of +0.675V and +1.35V to power the memory module. The power management module is used to convert the external power supply into isolated power supplies of +1.8V and +3.3V to power the flash memory module; The power management module is used to convert the external power supply into isolated power supplies of +0.85V, +1.2V, +1.8V and +3.3V to power the FPGA module 11.

[0037] To meet the requirement of supporting two daughterboards operating independently, the carrier board has been optimized in both structure and electrical design. Both high-speed interfaces require independent power supplies, clock signals, and high-speed data transmission channels for the daughterboards to ensure complete functional support when operating independently. Specifically, the carrier board uses a precise pin assignment scheme to connect independent power pins to each high-speed interface, providing stable power to the daughterboards. It also includes a clock signal channel to ensure accurate synchronization between the daughterboards during operation. Furthermore, the high-speed data transmission pins are designed to be independently allocated to the two daughterboards, avoiding signal cross-interference and improving the overall system reliability and performance.

[0038] The power supply must comply with the power supply requirements of the PXI Express Hardware Specification. The power signal is input to the carrier board through the second PXIe interface XJ4, with a power supply of 25.6W, and its distribution is shown in Table 1.

[0039] Table 1 Power parameters for the second PXIe interface XJ4

[0040] The required power-on sequence for the FPGA is VCCINT→VCCAUX→VCCO, and the power-on time range is as shown in Table 2.

[0041] Table 2 FPGA Power-on Sequence

[0042] Preferably, both the first high-speed interface 12 and the second high-speed interface 13 are model QSH-060-01-LDAK, each containing 120 signal pins with a 0.8mm pitch design. The high-speed differential signal transmission rate reaches 5GHz, meeting the requirements for high-speed serial signal transmission. Each signal pin has a rated current of 2A and supports hot-swap protection. Its metal casing design provides 360° EMI shielding, effectively reducing signal crosstalk. The interface signal definition adopts a differential pair priority principle, partitioning the GTP high-speed channel, synchronous clock, control signals, and power supply pins to optimize signal integrity.

[0043] Preferably, such as Figure 5As shown in the table, the pin assignments for the first high-speed interface 12 and the second high-speed interface 13 are listed separately. The power supply pin area includes 12V (3A rated current) and 3.3V (2A) power supply lines. The differential signal area is labeled IO_A / B_01 to 32, totaling 64 high-speed differential pairs. The clock area defines the CLK0 / 1_P / N differential clock pair (100MHz reference frequency). The GND pins are distributed among the signal pins in a 2:1 ratio. The interface electrical characteristics are standardized, achieving 25Gbps signal transmission through differential pair impedance control (100Ω±10%). An independent power domain design reduces crosstalk and provides clear pin function definitions for daughterboard development.

[0044] Preferably, such as Figures 6A-6D As shown, the power management module includes a three-way buck converter, a dual-channel converter, and an LDO regulator. The voltage output from the three-way buck converter powers the FPGA module 11; the voltage output from the three-way buck converter and the dual-channel converter powers the memory module; and the voltage output from the LDO regulator powers the first high-speed interface 12 and the second high-speed interface 13, respectively. The power management module supports precise power monitoring and power-on sequence management to ensure the module's startup sequence and operational stability.

[0045] Specifically, the power management module adopts a two-layer power architecture. The upper-layer power architecture is implemented by a three-channel buck converter of the TPS65265RHB, and the lower-layer power architecture is implemented by a dual-channel converter and an LDO regulator; for example Figure 6A As shown, this three-channel buck converter integrates three synchronous buck converters with an output voltage range of 0.8V to 5V and a total output current of 15A. The three buck converters achieve programmable power-on timing control via an I2C interface, strictly following the power-on sequence of VCCINT (1.0V) → VCCAUX (1.8V) → VCCO (3.3V). A 5ms delay interval is set between each power rail to prevent power-on surges from damaging the FPGA module's 11 core. After all three voltages have been output, the PG signal outputs a high level. The timing control avoids power surges (reducing peak current by 40%), the high-precision voltage output meets the stringent power supply requirements of the FPGA module and memory module, and the EMI filtering design keeps power ripple below 50mV. Figure 6B As shown, when the PG signal is high, the N-channel MOSFET BSS138 is turned on, point A is pulled to ground, and thus the P-channel MOSFET AO3401 is turned on, and the 3.3V power-on is completed, which satisfies the power-on sequence requirements.

[0046] Specifically, such as Figure 6CAs shown, the dedicated power supply for the memory module is provided by the TPS51200DRC dual-channel converter, which outputs a 1.35V core voltage and a 0.675V VTTREF reference voltage and supports Dynamic Voltage Regulation (DVS) function, which can automatically adjust the supply current according to the system load.

[0047] Specifically, such as Figure 6D As shown, the TPS7A8701 is selected as the power management chip for the first high-speed interface 12 and the second high-speed interface 13. The TPS7A8701 is a dual 500mA low-noise (3.8µVRMS) LDO regulator. It has two independent LDO channels, low output noise, and low voltage drop. Each output can be adjusted from 0.8V to 5.2V via an external resistor. The wide input voltage range of the TPS7A8701 allows it to operate from 1.4V to 6.5V. Its output voltage accuracy (across the entire line, load, and temperature range) reaches 1%, and its soft-start function reduces inrush current.

[0048] Preferably, the FPGA module 11 has 285 I / O interfaces, including 16 GTP high-speed serial transceivers, with a single-channel data rate of 6.5Gbps.

[0049] Specifically, FPGA module 11 is selected as the core processor, responsible for high-speed data acquisition, processing, and transmission. It employs a high-bandwidth, multi-channel design to ensure fast, efficient, and stable data interaction with the daughterboard and PXIe system. Based on a 28nm process, this device, compared to the traditional XC7A200T device, increases the number of I / O interfaces to 285 while maintaining the same logic resources, including 16 GTP high-speed serial transceivers, with a single-channel data rate of up to 6.5Gbps. The device integrates four clock management units (CMTs) and two PCIe Gen2 hard-core controllers, enabling direct high-speed data interaction with the PXIe backplane. FPGA module 11 is configured with SPI flash boot mode, supporting automatic power-on loading and remote online upgrade functions.

[0050] Specifically, the FPGA module 11 supports parallel operation of two daughterboards. The carrier board connects to the daughterboards via a first high-speed interface 12 and a second high-speed interface 13. The FPGA module distributes high-speed differential signals to the two high-speed interfaces to achieve synchronous data processing and communication between the two daughterboards. It supports independent operation or collaborative operation of each daughterboard. The FPGA module 11 is connected to an external PXIe bus (PCIe Gen2x8 interface) and supports complete interaction of PXIe clock signals (PXIe_CLK100, PXIe_SYNC100) and trigger signals (PXIe_PXITRIG0-7), providing high-precision synchronization and trigger control for the entire system.

[0051] Preferably, the memory module is model MT41K256M16, with a capacity of 256Mb×16bit, an operating voltage of 1.35V, a data rate of 1600MT / s, an 8-bit prefetch architecture, and supports 8 / 4 burst length mode switching; the flash memory module is model YX2M256I, with a capacity of 256MB, supports a four-channel SPI interface (QSPI), a maximum transmission rate of 416Mbit / s, and is used to store the configuration file and firmware of the FPGA module 11. Storage control is implemented by the internal logic of the FPGA module 11, supporting ECC error checking and automatic refresh functions to ensure data storage reliability.

[0052] Preferably, such as Figure 7 As shown, the PXI / CPCI bus specifies the location and size of the ESD discharge strips and ESD terminals on the chassis and carrier board, which must be strictly followed during the PCB structural design process. The carrier board 1 also includes an ESD protection module, which comprises three discharge strips that achieve electrostatic discharge through a 10MΩ resistor and direct grounding. The first discharge strip is connected to the front panel of the chassis via a 10MΩ resistor to discharge static electricity generated by the carrier board 1 or external contact; the 10MΩ resistor limits the discharge current. When the carrier board 1 is further inserted into the chassis rail slot, the second discharge strip is used to discharge static electricity from the ground plane of the carrier board 1, also through a 10MΩ resistor. The third discharge strip is directly connected to the front panel of the chassis to provide an electrostatic discharge path for the carrier board 1 to be further inserted into the backplane connector, and also to provide an electrostatic discharge path from the front panel of the chassis to the chassis ground.

[0053] Specifically, such as Figure 7 As shown, the ESD protection circuit on the substrate's edge employs a three-stage release structure: the first stage protection is a 10MΩ current-limiting resistor grounded (response time <1ns); the second stage protection is a TVS diode array (breakdown voltage 8kV); and the third stage protection is directly connected to the chassis ground via a 3mm wide copper foil. By constructing a multi-stage ESD protection system, the contact discharge protection level reaches ±8kV (IEC 61000-4-2 standard). The chassis ground connection design avoids ground loop interference, ensuring the transmission stability of high-speed signals in harsh electromagnetic environments.

[0054] Preferably, the daughterboard expansion adopts a fully isolated design, with each expansion daughterboard having its own independent: (1) Power supply system: The sub-board 2 obtains a 12V DC input voltage through the second PXIe interface XJ4 of the carrier board 1, and generates the required working voltage through the local DC-DC converter of the sub-board 2, and supports a maximum current output of 5A; (2) Clock link: The carrier board 1 provides a 100MHz differential reference clock, and the daughter board 2 multiplies the clock to the operating frequency through a PLL, supporting an adjustable range of 1MHz to 200MHz; (3) Communication channel: The sub-board 2 uses 4 pairs of high-speed differential signals to realize high-speed data transmission, supplemented by 8 GPIO interfaces to realize control signal interaction; (4) Hot-swap control: The daughterboard 2 supports hot-swap function, and the real-time detection of daughterboard access / removal and system status switching are realized through a dedicated detection circuit.

[0055] This expansion mechanism ensures that each daughterboard can operate as an independent functional unit, enabling collaborative work between multiple daughterboards through a carrier board. The system supports up to four levels of cascading expansion, with a total of up to 1140 I / O interfaces, meeting the needs of large-scale data acquisition and processing.

[0056] Key technical indicators are shown in Table 3 below: Table 3

[0057] Advantages of expansion: The daughterboard adopts a fully isolated design, supports independent power supply, clock and communication channels, and enables plug-and-play and online maintenance of functional modules. There is no performance loss when the system is cascaded and expanded.

[0058] This architecture enables modular reconfiguration of system functions through distributed hardware resource configuration, making it particularly suitable for test and measurement, industrial control, and communication processing fields that require flexible expansion. Compared to traditional centralized boards, it offers significant improvements in system throughput, functional scalability, and reliability, providing a highly efficient hardware platform solution for complex electronic systems.

[0059] This invention employs a hierarchical distributed architecture, with the carrier board serving as the core functional module. It connects to daughter boards via two independent high-speed interfaces, supporting a maximum of two daughter boards operating in parallel. This architecture overcomes the physical limitations of traditional centralized boards, allowing each daughter board to be configured with differentiated functional modules based on application requirements, such as signal acquisition, protocol conversion, or dedicated algorithm acceleration units. Data exchange between the carrier board and daughter boards is achieved through a fully isolated power supply system, a synchronous clock link, and a high-speed differential signal channel, ensuring signal integrity and system stability when multiple daughter boards operate in parallel.

[0060] This invention, based on the PXIe bus architecture, constructs a scalable distributed board structure. Its core design concept lies in achieving flexible configuration of hardware resources through a modular architecture. This structure uses a carrier board as the core control hub, employs a dual-daughterboard parallel expansion mode, and achieves distributed data processing through independent high-speed interfaces, forming a two-level architecture of "carrier board + daughterboard." The dual-daughterboard parallel expansion is achieved through independent high-speed interfaces, supporting flexible configuration and plug-and-play functionality of modules.

[0061] In this embodiment of the invention, by adopting distributed interface design, modular power management, electromagnetic isolation optimization, domestic chip adaptation, and independent channel arbitration mechanism, the aim is to fundamentally solve the inherent defects of traditional architecture and provide a hardware foundation for building a high-density, high-reliability, and low-cost next-generation test system.

[0062] This invention uses the PXIe high-speed serial bus as its core and integrates a modular hardware design concept to solve the problems of multi-module collaboration and performance expansion in high-precision testing systems.

[0063] This invention transforms centralized resource allocation into a distributed collaborative architecture, enabling the testing system to have flexible scalability and environmental adaptability, while reducing dependence on imported chips and improving supply chain security.

[0064] The scalable distributed board structure based on the PXIe bus provided by this invention realizes the parallel expansion of distributed nodes through the independent interface design of "carrier board + daughter board", and supports conflict-free communication between multiple functional boards on a single board.

[0065] This invention achieves systemic breakthroughs in key dimensions such as scalability, supply chain security, power management, electromagnetic compatibility, structural flexibility, and environmental adaptability through innovative hardware architecture design and a domestic technology path. It effectively solves the technical pain points of traditional PXIe boards, such as limited scalability, reliance on imported core chips, and insufficient power stability. The following details its technical effects and implementation mechanism from six aspects: 1. Enhanced scalability: Dual-board parallel architecture doubles efficiency. Employing a modular design that separates the daughterboard and the carrier board, this system supports parallel operation of 1-2 daughterboards. Each daughterboard is equipped with an independent power supply module, clock source, and communication interface. This architecture overcomes the physical limitations of traditional single-module designs. Expansion requires only adding more daughterboards without modifying the carrier board hardware or re-verifying signal integrity, improving system expansion efficiency by 100% compared to traditional solutions. The independent daughterboard working domain design ensures no resource contention when multiple modules operate in parallel. A daisy-chain topology via the PXIe bus enables linear expansion of data throughput, meeting the multi-channel synchronous acquisition requirements of complex testing scenarios.

[0066] 2. Breakthrough in domestic production: 100% self-sufficient and controllable core chips Complete replacement of core processors and memory units: The Xilinx XC7A200T is replaced by the domestically produced JYX200T-484 FPGA. This chip achieves the same level of performance in key parameters such as the number of logic cells (200K LUTs), DSP slicing (360 18x18 multipliers), and high-speed interface (supporting PCIe Gen2 x4). The memory module uses the YX2M256I SPI FLASH instead of the Micron MT25QX256, achieving a domestic match between 256Mb capacity and 108MHz clock frequency. The 100% domestic production rate of core chips completely eliminates the risk of restrictions from foreign supply chains and has passed AEC-Q100 Grade 2 reliability certification, ensuring stable application in key fields such as military and aerospace.

[0067] 3. Enhanced power supply stability: Timing control and ripple suppression technology The power management module employs the TI TPS65265RHB multi-channel power controller, achieving precise timing control of VCCINT (core voltage) → VCCAUX (auxiliary voltage) → VCCO (I / O voltage). The power-on interval for each voltage rail is strictly controlled within 5ms to avoid instantaneous current surges. Through a combination of a π-type filter network and low-ESR ceramic capacitors, the output voltage ripple is controlled to ≤50mV (peak-to-peak), reducing ripple interference by 60% compared to traditional LDO solutions. Long-term reliability testing shows that this power solution reduces chip failure rate by 90% and increases MTBF (Mean Time Between Failures) to over 100,000 hours.

[0068] 4. Electromagnetic compatibility optimization: Multi-dimensional EMI suppression design To address the electromagnetic interference (EMI) issue in PXIe high-speed signal transmission, a layered grounding strategy was adopted, connecting digital ground, analog ground, and power ground at a single point through a 0Ω resistor to form an independent grounding plane. A π-type RC filter network was added to the crystal oscillator circuit to control clock jitter to ≤5ps. A 0402 packaged ferrite bead (120Ω impedance @ 100MHz) was connected in series along critical signal paths to suppress high-frequency noise. Actual test results show that radiated interference in the 30MHz–1GHz frequency band is ≤30dBμV / m, far below the 40dBμV / m limit specified in GJB151B-2013, meeting the electromagnetic compatibility requirements for military equipment.

[0069] 5. Increased structural flexibility: Quick-change stacking design The daughterboard uses a 2mm pitch board-to-board connector to mechanically fix and transmit signals to the carrier board, supporting stacking configurations of 1-2 daughterboards. Through standardized guide pins and snap-locking mechanisms, daughterboard replacement time is ≤10 minutes, improving maintenance efficiency by 80% compared to traditional screw fixing methods. The carrier board has reserved expansion interfaces, allowing for flexible configuration of different functional daughterboards (such as AD / DA conversion, digital I / O, protocol analysis, etc.) according to testing needs, enabling dynamic reconfiguration of test resources.

[0070] 6. Strong environmental adaptability: Military-grade reliability assurance Through material optimization and process improvement, the equipment maintains stable performance even in extreme environments. The PCB uses FR-4 material (Tg≥170℃) and immersion gold process, and key components are selected from automotive-grade or military-grade models. The whole machine has passed high and low temperature cycle tests of -40℃ to +85℃, 500 hours of salt spray test and random vibration test of 10~2000Hz. All functional indicators have a deviation of ≤3% before and after the test, which fully meets the requirements of MIL-STD-810H standard for adaptability to harsh environments. It can be deployed in complex scenarios such as ships, aircraft, and field operations.

[0071] In summary, this invention, through hardware architecture innovation and breakthroughs in key technologies, has constructed a PXIe board solution that integrates high scalability, localization, and high reliability. Its technical indicators have reached industry-leading levels in multiple dimensions, providing important technical support for the independent and controllable development of high-end test and measurement equipment.

[0072] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A scalable distributed board structure based on the PXIe bus, characterized in that, The scalable distributed board structure based on the PXIe bus includes a carrier board (1) and a daughter board (2). The carrier board (1) includes an FPGA module (11), a memory module, a flash memory module, a power management module, a first high-speed interface (12), a second high-speed interface (13), a first PXIe interface (XJ3), and a second PXIe interface (XJ4). The carrier board (1) is connected to the daughter board (2) through the first high-speed interface (12) and the second high-speed interface (13). The first PXIe interface (XJ3) is used to transmit the clock PXIe_CLK100 and the synchronization clock PXIe_SYNC100 of the external PXIe bus to the FPGA module (11); the second PXIe interface (XJ4) communicates bidirectionally with the FPGA module (11) through a trigger bus. The second PXIe interface (XJ4) is used to transmit external power to the power management module; the power management module is used to convert the external power into multiple isolated power supplies for powering the FPGA module (11), memory module, flash memory module, first high-speed interface (12) and second high-speed interface (13); The FPGA module (11) can write and read cached data with the memory module; the FPGA module (11) can write and read configuration data with the flash memory module; the FPGA module (11) is used to output high-speed differential signal and synchronous clock PXIe_SYNC100 to the first high-speed interface (12) and the second high-speed interface (13) respectively, and receive high-speed differential signal input from the first high-speed interface (12) and the second high-speed interface (13).

2. The scalable distributed board structure based on the PXIe bus according to claim 1, characterized in that, When the carrier board (1) is connected to a sub-board (2), the sub-board (2) includes a third high-speed interface (21) and a fourth high-speed interface (22). The carrier plate (1) is provided with a plurality of M3 studs (14), and the sub-plate (2) is provided with a plurality of through holes (23) that cooperate with the M3 studs (14). The sub-plate (2) is placed on the carrier plate (1) through the cooperating M3 studs (14) and through holes (23), and the carrier plate (1) and the sub-plate (2) are fixed with M3 screws (3). At this time, the third high-speed interface (21) is inserted into the first high-speed interface (12), and the fourth high-speed interface (22) is inserted into the second high-speed interface (13) for signal and data interaction.

3. The scalable distributed board structure based on the PXIe bus according to claim 1, characterized in that, When the carrier board (1) connects two sub-boards (2), each sub-board includes a high-speed interface. The high-speed interface on the first sub-board (2) is connected to the first high-speed interface (12), and the high-speed interface on the second sub-board (2) is connected to the second high-speed interface (13) for signal and data interaction.

4. The scalable distributed board structure based on the PXIe bus according to claim 1, characterized in that, The second PXIe interface (XJ4) is used to transmit external power supplies of +3.3V, +5V, +12V and -12V to the power management module; The power management module is used to convert the external power supply into isolated power supplies of +3.3V and +12V, which are used to supply power to the first high-speed interface (12) and the second high-speed interface (13) respectively. The power management module is used to convert the external power supply into isolated power supplies of +0.675V and +1.35V to power the memory module. The power management module is used to convert the external power supply into isolated power supplies of +1.8V and +3.3V to power the flash memory module; The power management module is used to convert the external power supply into isolated power supplies of +0.85V, +1.2V, +1.8V and +3.3V to power the FPGA module (11).

5. The scalable distributed board structure based on the PXIe bus according to claim 1, characterized in that, The power management module includes a three-way buck converter, a dual-channel converter, and an LDO regulator; wherein, the voltage output by the three-way buck converter powers the FPGA module (11); the voltage output by the three-way buck converter and the dual-channel converter powers the memory module; and the voltage output by the LDO regulator powers the first high-speed interface (12) and the second high-speed interface (13), respectively.

6. The scalable distributed board structure based on the PXIe bus according to claim 1, characterized in that, The first high-speed interface (12) and the second high-speed interface (13) are both QSH-060-01-LDAK, each containing 120 signal pins, and the transmission rate of the high-speed differential signal reaches 5GHz.

7. The scalable distributed board structure based on the PXIe bus according to claim 1, characterized in that, The FPGA module (11) has 285 I / O interfaces, including 16 GTP high-speed serial transceivers, with a single-channel data rate of 6.5Gbps.

8. The scalable distributed board structure based on the PXIe bus according to claim 1, characterized in that, The memory module is model MT41K256M16, with a capacity of 256Mb×16bit, an operating voltage of 1.35V, a data rate of 1600MT / s, an 8-bit prefetch architecture, and supports 8 / 4 burst length mode switching; the flash memory module is model YX2M256I, with a capacity of 256MB, supports a four-channel SPI interface, and has a maximum transmission rate of 416Mbit / s, and is used to store the configuration file and firmware of the FPGA module (11).

9. The scalable distributed board structure based on the PXIe bus according to claim 1, characterized in that, The carrier board (1) also includes an ESD protection module, which includes three release strips that achieve electrostatic discharge through a 10MΩ resistor and direct grounding. The first release strip is connected to the front panel of the chassis through a 10MΩ resistor to release the static electricity generated by the carrier board (1) or external contact, and the 10MΩ resistor limits the release current. When the carrier board (1) is further inserted into the chassis guide rail slot, the second release strip is used to release the static electricity on the ground plane of the carrier board (1). The third release strip is directly connected to the front panel of the chassis to provide an electrostatic discharge path for the carrier board (1) to be further inserted into the backplane connector, and to provide an electrostatic discharge path from the front panel of the chassis to the chassis ground.

10. The scalable distributed board structure based on the PXIe bus according to claim 1, characterized in that, The sub-board (2) obtains a 12V DC input voltage through the second PXIe interface (XJ4) of the carrier board (1), generates the required operating voltage through the local DC-DC converter of the sub-board (2), and supports a maximum current output of 5A. The carrier board (1) provides a 100MHz differential reference clock, and the daughter board (2) multiplies the clock to the operating frequency through a PLL, supporting an adjustable range of 1MHz to 200MHz; The sub-board (2) uses multiple pairs of high-speed differential signals to achieve high-speed data transmission, and is supplemented by multiple GPIO interfaces to achieve control signal interaction; The subboard (2) supports hot-plugging and can realize real-time detection of subboard access / removal and system status switching through a dedicated detection circuit.

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