Power consumption optimization method and device, equipment and storage medium

Abstract

The invention discloses a power consumption optimization method and device, equipment and a storage medium, and relates to the technical field of chips. The method comprises the following steps: acquiring a first time delay of a first module, a second time delay of a second module, an inter-module time delay between the first module and the second module, and a total time sequence margin; determining a first time sequence margin and a second time sequence margin from the total time sequence margin; the first time sequence margin is a time sequence margin distributed to the first module and used for executing power consumption optimization, the second time sequence margin is a time sequence margin distributed to the second module and used for executing power consumption optimization, and the sum of the first time sequence margin and the second time sequence margin is smaller than or equal to the total time sequence margin; and performing power consumption optimization on the first module and the second module based on the first timing margin and the second timing margin. According to the method, the sum of the first time sequence margin and the second time sequence margin is smaller than or equal to the total time sequence margin, so that the power consumption of the module is saved while the signal can be transmitted in the clock period.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a power consumption optimization method, apparatus, device, and storage medium. Background Technology

[0002] Power consumption optimization for a module can include power consumption optimization within the module and power consumption optimization of the module interface.

[0003] In related technologies, power consumption optimization methods for the internal modules can include timing-based VTswap (Threshold Voltage Swap) methods and SDF (Standard Delay Format)-based power consumption optimization methods.

[0004] However, the power optimization methods described above for the internal modules are not applicable to power optimization scenarios at the module interfaces. Therefore, further research is needed on power optimization methods for module interfaces. Summary of the Invention

[0005] This application provides a power consumption optimization method, apparatus, device, and storage medium. The technical solutions provided by this application include the following aspects.

[0006] According to one aspect of the embodiments of this application, a power consumption optimization method is provided, the method comprising: The first delay of the first module, the second delay of the second module, the inter-module delay between the first module and the second module, and the total timing margin are obtained; wherein, the first delay is used to indicate the delay of signal transmission within the first module, the second delay is used to indicate the delay of signal transmission within the second module, the inter-module delay is used to indicate the delay of signal transmission between the first module and the second module, and the total timing margin is used to indicate the timing margin to be allocated during power optimization of the first module and the second module; Based on the first delay, the second delay, and the inter-module delay, a first timing margin and a second timing margin are determined from the total timing margin; wherein, the first timing margin is the timing margin allocated to the first module for performing power optimization, the second timing margin is the timing margin allocated to the second module for performing power optimization, and the sum of the first timing margin and the second timing margin is less than or equal to the total timing margin; Based on the first timing margin and the second timing margin, power consumption optimization is performed on the first module and the second module.

[0007] According to one aspect of the embodiments of this application, a power consumption optimization apparatus is provided, the apparatus comprising: An acquisition module is used to acquire a first delay of a first module, a second delay of a second module, an inter-module delay between the first module and the second module, and a total timing margin; wherein, the first delay is used to indicate the delay of signal transmission within the first module, the second delay is used to indicate the delay of signal transmission within the second module, the inter-module delay is used to indicate the delay of signal transmission between the first module and the second module, and the total timing margin is used to indicate the timing margin to be allocated during power optimization of the first module and the second module; A determining module is configured to determine a first timing margin and a second timing margin from the total timing margin based on the first delay, the second delay, and the inter-module delay; wherein the first timing margin is the timing margin allocated to the first module for performing power optimization, the second timing margin is the timing margin allocated to the second module for performing power optimization, and the sum of the first timing margin and the second timing margin is less than or equal to the total timing margin; An execution module is configured to perform power consumption optimization on the first module and the second module based on the first timing margin and the second timing margin.

[0008] According to one aspect of the embodiments of this application, a computer device is provided, the computer device including a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the above-described power optimization method.

[0009] According to one aspect of the present application, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, the computer program being loaded and executed by a processor to implement the above-described power optimization method.

[0010] According to one aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program stored in a computer-readable storage medium, and a processor reading from the computer-readable storage medium and executing the computer program to implement the above-described power optimization method.

[0011] The technical solution provided in this application can bring the following beneficial effects: For power consumption optimization scenarios of module interfaces, power consumption optimization is performed on the first module and the second module based on the first timing margin and the second timing margin. Since the sum of the first timing margin and the second timing margin is less than or equal to the total timing margin, it ensures that the signal can be transmitted within the clock cycle while saving module power consumption. Attached Figure Description

[0012] Figure 1This is a schematic diagram of module A and module B in one possible implementation of this application; Figure 2 This is a flowchart of a power consumption optimization method in one possible implementation of this application; Figure 3 This is a schematic diagram of a chip in one possible implementation of this application; Figure 4 This is a flowchart of a power optimization method in another possible implementation of this application; Figure 5 This is a block diagram of a power optimization device in one possible implementation of this application; Figure 6 This is a structural block diagram of a computer device in one possible implementation of this application. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0014] Before introducing and explaining the technical solution of this application, some concepts involved in this application will be defined and explained.

[0015] Module interface power consumption optimization: In the field of integrated circuit design, power optimization can be divided into module interface power optimization and module internal power optimization. Module interface power optimization refers to optimizing power consumption during signal transmission between different modules in integrated circuit design. Module internal power optimization refers to optimizing power consumption during signal transmission within an integrated circuit module.

[0016] Current backend design primarily focuses on power optimization within modules, employing techniques such as timing-based VTswap and SDF-based power optimization. These can be based on PrimeTime or PNR tools, such as Synopsys' fc_compiler or Cadence's Innovus. However, these existing power optimization methods are not suitable for power optimization of module interfaces. Specifically, power optimization often involves timing changes, and the timing of a module interface depends not only on its own logic structure but also, to a greater extent, on external constraints. In related technologies, these constraints are typically derived from timing budgets or uniformly set parameters. However, the way these constraints are defined cannot truly reflect the actual external environment of the module. The actual external environment of the module can include interface latency (including input and output delays) and on-chip variation (OCV). If power optimization of the module interface is performed based on the original constraints (i.e., constraints from timing budgets or uniformly set constraints) in related technologies, it can lead to timing degradation or poor power optimization results.

[0017] like Figure 1 As shown, a signal is transmitted from register A inside module A to register B inside module B, and the path it takes can include a, c, and b. Then the timing margin... The calculation formula is shown in Formula 1 below: (Formula 1) in, This refers to the signal transmission delay within module A. This refers to the signal transmission delay within module B. This refers to the transmission delay of the signal between module A and module B. It refers to the clock cycle.

[0018] In related technologies, power optimization can be performed on modules A and B separately, which may include the following steps: determining the timing margins corresponding to module A and module B; and performing power optimization on modules A and B separately based on the timing margins corresponding to modules A and B to obtain power-optimized modules A and B. In related technologies, since power optimization is performed on modules A and B individually, the timing margin corresponding to module A is as described above. The timing margin corresponding to module B is also as described above. In this scenario, the timing margin during signal transmission from register A within the power-optimized module A to register B within the power-optimized module B is... The calculation formula is shown in Formula 2 below: (Formula 2) The calculation yielded: In this approach, because modules A and B overlap and overwrite the timing margin, the timing margin becomes negative. In other words, the delay in signal transmission from register A within the power-optimized module A to register B within the power-optimized module B exceeds the preset clock cycle. This can lead to timing violations during signal transmission.

[0019] Based on the above, this application provides a novel power consumption optimization method for module interfaces. In the embodiments of this application, power consumption optimization is performed on the first module and the second module based on the first timing margin and the second timing margin. Since the sum of the first timing margin and the second timing margin is less than or equal to the total timing margin, it ensures that the signal can be transmitted within the clock cycle while saving module power consumption.

[0020] Please refer to Figure 2 The diagram illustrates a flowchart of a power optimization method in one possible implementation of this application. The execution entity for each step of the method can be a computer device. The method may include at least one of the following steps (210-230).

[0021] Step 210: Obtain the first delay of the first module, the second delay of the second module, the inter-module delay between the first module and the second module, and the total timing margin; wherein, the first delay is used to indicate the delay of signal transmission within the first module, the second delay is used to indicate the delay of signal transmission within the second module, the inter-module delay is used to indicate the delay of signal transmission between the first module and the second module, and the total timing margin is used to indicate the timing margin to be allocated during power optimization of the first module and the second module.

[0022] like Figure 3 The diagram shows a schematic of chip 30 in one possible implementation of this application. Chip 30 includes a first module 31 and a second module 32.

[0023] A module of a chip refers to a circuit unit or subsystem within the chip that has a specific circuit function, divided according to its function and / or physical partitioning. The first module and the second module may include at least one of the following: a central processing unit, a graphics processing unit, a digital signal processor, a memory controller, an interface controller, an image signal processor, and a display controller. The above are merely examples, and the first module and the second module refer to any two different modules of the chip. This application does not limit them.

[0024] The signal is transmitted from the first register inside the first module 31 to the second register inside the second module, and the path may include a, c, and b. The first delay refers to the signal transmission delay within the first module, which can be the delay from the first register to the output interface of the first module (i.e., the corresponding path a), and can be denoted as Delay A in this application. The second delay refers to the signal transmission delay within the second module, which can be the delay from the input interface of the second module to the second register (i.e., the corresponding path b), and can be denoted as Delay B in this application. The inter-module delay, also known as the interface delay, refers to the signal transmission delay between the first and second modules, which can be the delay from the output interface of the first module to the input interface of the second module (i.e., the corresponding path c), and can be denoted as Delay C in this application.

[0025] Total latency refers to the total time delay experienced by a signal from the first module to the second module. Specifically, it refers to the total time delay between the transmission of a signal from the first register within the first module to the transmission of a signal from the second register within the second module. In some embodiments, total latency = first latency + second latency + inter-module latency, i.e., total latency. .

[0026] Total timing margin indicates the timing margin to be allocated during power optimization of the first and second modules. In other words, total timing margin refers to the remaining time after a signal is transmitted from the first register inside the first module to the second register inside the second module within one (single) clock cycle or a set clock cycle. The set clock cycle can be an integer multiple of a single clock cycle, or a preset time interval that can be flexibly set according to complex timing logic and circuit function requirements. It can be set based on the experience of those skilled in the art, and this application does not impose any limitations on it. Total timing margin is an important indicator for measuring chip timing performance, reflecting the degree of timing leeway of the chip in the current clock cycle.

[0027] The aforementioned clock cycle refers to the time required for the clock signal in the chip to complete one full cycle change. It provides a synchronization reference for the operation of various modules within the chip, ensuring that each module can process and transmit data in a predetermined order and time. For example, if the frequency of the clock signal is 1 GHz (gigahertz), its clock cycle is 1 ns (nanosecond), indicating that the chip will perform a basic synchronization operation every 1 ns.

[0028] In some embodiments, the total timing margin and chip power consumption can be positively correlated. That is, a larger total timing margin indicates a faster signal transmission speed, which in turn means higher chip power consumption; conversely, a smaller total timing margin indicates a slower signal transmission speed, which in turn means lower chip power consumption. To save chip power consumption, when the total timing margin is sufficient, appropriate power optimization processing can be performed on the chip to save power. In this application, the focus is mainly on optimizing the power consumption of module interfaces to save power consumption caused by signal transmission between modules. For example, when the total timing margin is large, power consumption can be reduced by appropriately lowering the operating voltage of certain modules (e.g., the first module and / or the second module) or adjusting the circuit structure. Furthermore, module power optimization should be performed within a reasonable range to ensure that timing violations are not introduced.

[0029] In some embodiments, the first module and the second module are applied in either chip. Obtaining the first delay of the first module, the second delay of the second module, the inter-module delay between the first module and the second module, and the total timing margin includes performing timing analysis processing on the chip to obtain the first delay, the second delay, the inter-module delay, and the total timing margin.

[0030] Optionally, timing analysis may include STA (Static Timing Analysis). Static timing analysis is a method used in integrated circuit design to verify whether the timing of a circuit meets design requirements. It calculates and analyzes the signal propagation delays of each path in the circuit, evaluating the timing performance of the circuit under different operating conditions without actual dynamic simulation, and checking for timing violations (such as setup time violations, hold time violations, etc.), thereby ensuring that the chip can operate stably and correctly at the specified clock frequency. In this application, performing STA processing on the chip utilizes static timing analysis to obtain key timing parameters such as the first delay, the second delay, inter-module delay, and total timing margin.

[0031] The above method, through timing analysis (e.g., STA), can accurately obtain key parameters such as the first delay, the second delay, the inter-module delay, and the total timing margin, which facilitates the accurate determination of the first timing margin and the second timing margin in the future.

[0032] Step 220: Based on the first delay, the second delay, and the inter-module delay, determine the first timing margin and the second timing margin from the total timing margin; wherein, the first timing margin is the timing margin allocated to the first module for performing power optimization, the second timing margin is the timing margin allocated to the second module for performing power optimization, and the sum of the first timing margin and the second timing margin is less than or equal to the total timing margin.

[0033] In some embodiments, the total timing margin is accurately obtained based on timing analysis, and its numerical value approximates the difference between the clock cycle and the total delay (i.e., the first delay + the second delay + the inter-module delay). The total timing margin represents the degree of time leeway in the entire signal transmission process. The first timing margin is a portion of the total timing margin allocated to the first module for time buffering during signal transmission within the first module; the second timing margin is a portion of the total timing margin allocated to the second module for time buffering during signal transmission within the second module. When allocating the total timing margin to the first and second modules, to ensure that the entire transmission process can be completed within the clock cycle, the sum of the timing margins allocated to the two modules cannot exceed the total timing margin. If it exceeds this, it means that the allocated time buffer exceeds the actual available leeway, which will cause the signal transmission to fail to complete within the preset clock cycle.

[0034] In some embodiments, the sum of the first timing margin and the second timing margin is less than or equal to the total timing margin. It is understood that when the sum of the first timing margin and the timing margin of the second module equals the total timing margin, power consumption can be maximized while ensuring signal transmission within a preset clock cycle. When the sum of the first timing margin and the timing margin of the second module is less than the total timing margin, the chip system gains higher reliability and stronger anti-interference capabilities. Specifically, from a reliability perspective, the additional remaining timing margin can act as a time buffer to cope with various uncertainties that may occur during chip operation. For example, during actual operation, changes in ambient temperature can affect transistor performance; high temperatures may slow down transistor switching speeds, thereby increasing signal transmission delay. With an additional timing margin, even with this increased delay due to temperature changes, the signal can still be transmitted from the first module to the second module within a preset clock cycle, avoiding timing violations and ensuring the stable operation of the chip system. Regarding interference immunity, the chip may be affected by external electromagnetic interference or internal power supply noise during operation, which may cause signal transmission delays or errors. Additional timing margins provide a certain degree of fault tolerance to cope with these interferences. When interference increases signal transmission delay, the remaining timing margin can absorb this increased delay, allowing the signal to still arrive at the second module from the first module on time, ensuring correct data transmission. Furthermore, this also provides flexibility for subsequent chip function expansion or performance improvements. As technology advances and application requirements change, it may be necessary to upgrade certain modules of the chip or add new functional modules. If the sum of the timing margins of the first and second modules is less than the total timing margin, certain time resources can be allocated to the newly added functions or upgraded modules without requiring large-scale adjustments to the entire chip's clock system, reducing the difficulty and cost of chip upgrades.

[0035] In summary, in step 220 above, since the sum of the first timing margin and the second timing margin is less than or equal to the total timing margin, it ensures that the delay of the signal transmission from the first module to the second module will not exceed the clock cycle. This avoids the timing violation problem caused by the two modules (module A and module B) repeatedly covering the timing margin in related technologies, thereby ensuring that the signal can be transmitted within the preset clock cycle while significantly saving module power consumption.

[0036] Step 230: Based on the first timing margin and the second timing margin, perform power consumption optimization on the first module and the second module.

[0037] In some embodiments, power optimization is performed on the first module based on a first timing margin to obtain a power-optimized first module. The latency corresponding to the power-optimized first module can be the sum of the first latency and the first timing margin. That is, the latency corresponding to the power-optimized first module = first latency + first timing margin.

[0038] In some embodiments, performing power optimization on the first module based on a first timing margin to obtain a power-optimized first module may include the following steps: adjusting the configuration information of the first module based on the first timing margin to obtain the power-optimized first module. Optionally, the configuration information may include at least one of the following: threshold voltage, driving capability, which is not limited in this application.

[0039] Threshold voltage refers to the minimum gate-source voltage required for a transistor to turn on. In chip design, threshold voltage is closely related to power consumption. A higher threshold voltage can reduce transistor leakage current, thereby reducing static power consumption; a lower threshold voltage can increase transistor switching speed, but will increase leakage current. Based on the first timing margin, if the timing margin is sufficient, the threshold voltage of the transistors in the first module can be appropriately increased to reduce static power consumption. For example, increasing the threshold voltage of a transistor that originally had a threshold voltage of 0.4V to 0.5V can reduce the transistor's leakage current and thus reduce static power consumption.

[0040] Drive capability refers to the ability of a circuit's output to provide or absorb current. A stronger drive capability results in faster signal transmission speeds, but also increases power consumption. Conversely, a weaker drive capability leads to slower signal transmission speeds, but reduces power consumption. Based on the first timing margin, if the timing margin allows, the drive capability of the first module can be appropriately reduced to decrease dynamic power consumption. For example, the width of the transistor in the drive circuit can be reduced from 10 μm to 8 μm to decrease dynamic power consumption.

[0041] Similar to the principle of power optimization for the first module, power optimization is performed on the second module based on the second timing margin, resulting in a power-optimized second module. The latency of the power-optimized second module can be the sum of the second latency and the second timing margin. That is, the latency of the power-optimized second module = second latency + second timing margin.

[0042] In some embodiments, performing power optimization on the second module based on the second timing margin to obtain a power-optimized second module may include the following steps: adjusting the configuration information of the second module based on the second timing margin to obtain the power-optimized second module. Optionally, the configuration information may include at least one of the following: threshold voltage, driving capability, which is not limited in this application. Please refer to the corresponding description above for details, which will not be repeated here.

[0043] In some embodiments, power optimization is performed on the first module and the second module based on the first timing margin and the second timing margin, including: performing timing analysis processing on the chip to generate a context model, the context model being used to indicate the actual external timing environment of the first module and the second module within the chip; and performing power optimization on the first module and the second module based on the first timing margin, the second timing margin, and the context model.

[0044] Optionally, the timing analysis includes STA.

[0045] In some embodiments, power optimization is performed on the first module based on a first timing margin and a context model. Here, the context model indicates the actual external environment of the first module. In other words, the context model is used to provide the actual external environment for the first module.

[0046] The real external environment of the first module refers to the actual working environment constituted by other modules, signals, power supplies, and other factors that interact with it in the actual chip system operation scenario. The real external environment of the first module indicates the various constraints and conditions faced by the first module in the entire chip system, which directly affect the performance and power consumption of the first module.

[0047] For example, the real external environment can include the influence of signals from other modules. This includes the timing characteristics of input signals from a second module or other adjacent modules, such as arrival time and frequency of change. If the arrival time of the input signal is unstable, the first module may require additional timing margin to process it, thus affecting power consumption. For example, the real external environment can also include the power supply environment, such as voltage fluctuations and noise. An unstable power supply may cause changes in the performance of transistors in the first module, affecting signal transmission speed. To ensure normal operation, the first module may need to consume more energy. For example, the real external environment can also include clock signal characteristics, such as clock signal frequency and jitter. The clock signal is fundamental for the synchronous operation of modules within the chip. If the clock signal jitters, it will affect the timing within the first module, thereby affecting its power consumption.

[0048] It should be noted that the above is merely illustrative and is not intended to be limiting.

[0049] Similarly, for the second module, power optimization is performed based on the second timing margin and the context model. Here, the context model indicates the actual external environment of the second module. In other words, the context model is used to provide the actual external environment for the second module.

[0050] The real external environment of the second module refers to the actual operating environment constituted by other modules, signals, power supplies, and other factors interacting with it in the actual chip system operation scenario. The real external environment of the second module indicates the various constraints and conditions faced by the second module within the entire chip system, which directly affect its performance and power consumption. For example, the real external environment may include at least one of the following: signal influences from other modules, power supply environment, and clock signal characteristics. For details, please refer to the above text; further elaboration is not provided here.

[0051] In some embodiments, performing timing analysis (such as STAR) on the chip to generate a context model may include: performing STAR on the chip using the Hyperscale method based on PrimeTime to generate a context model. PrimeTime is a static timing analysis tool widely used in integrated circuit design, capable of comprehensive and accurate timing verification and analysis of chip designs. PrimeTime can handle complex circuit structures and various timing constraints. By calculating and checking the signal propagation time of each path in the chip, it helps designers discover and resolve potential timing problems, ensuring that the chip meets timing requirements under different operating conditions, thus guaranteeing chip reliability and performance. Hyperscale is an advanced analysis method within the PrimeTime tool, primarily used for handling large-scale, complex chip design scenarios. The Hyperscale method employs efficient algorithms and optimization techniques, significantly improving the speed and efficiency of static timing analysis. When dealing with chip designs with numerous modules and complex interfaces, the Hyperscale method can quickly and accurately generate context models corresponding to each module. These context models realistically reflect the external timing environment of the module within the entire chip system, including interactions with other modules and signal input / output characteristics. By using the context model generated by the Hyperscale method, the timing of the module interface is kept consistent with the top-level design, providing a more accurate basis for subsequent design optimization and power management, which helps to improve the quality and performance of chip design.

[0052] The above method, by combining a context model to perform power consumption optimization on the first and second modules, leverages the context model's ability to provide a realistic external environment for their interfaces. This ensures that the first and second modules maintain consistency with the top-level timing, enabling more precise power consumption optimization. For example, by adjusting the operating voltage and frequency of the first and second modules based on the arrival time and frequency of external signals, performance requirements are met while minimizing power consumption. Furthermore, it ensures the accuracy and stability of signal transmission. Specifically, the top-level timing represents the global clock requirements and signal transmission time standards for the entire chip system. When the first and second modules are consistent with the top-level timing, signal transmission between modules strictly adheres to the preset clock cycle. For instance, during data transmission from the first module to the second module, the context model provides accurate information about the real external environment, allowing the first module to send signals at the appropriate time and the second module to receive signals at the correct time. This avoids timing violations such as signal loss and data errors caused by timing inconsistencies, ensuring the accuracy of signal transmission.

[0053] Taking timing analysis as an example (STA), this paper introduces a power consumption optimization method in another possible implementation of this application. Please refer to [link / reference]. Figure 4 The diagram illustrates a flowchart of a power optimization method in another possible implementation of this application. It may include the following steps S11-S17.

[0054] Step S11: Perform STA processing on the chip.

[0055] On one hand, performing STA processing on the chip may include steps S13 to S15. On the other hand, performing STA processing on the chip may result in step S12. In some embodiments, steps S12 and S13 to S15 may be executed simultaneously, and this application does not limit this.

[0056] Step S12: Generate the context model.

[0057] In some embodiments, STA processing is performed on the chip to generate a context model, which is used to indicate the real external environment of the first module and the second module.

[0058] Step S13: Obtain the signal transmission path between the first module and the second module.

[0059] The signal transmission path refers to the path a signal takes from the first module to the second module. For example... Figure 3 As shown, the signal is transmitted from the first register inside the first module 31 to the second register inside the second module 32. The path (i.e. the signal transmission path) can include a, c, and b.

[0060] Step S14: Obtain delay information.

[0061] In some embodiments, the delay information may include at least one of the following: a first delay, a second delay, and an inter-module delay. The first delay refers to the delay of signal transmission within the first module, which can be the delay of signal transmission from the first register to the output interface of the first module (i.e., corresponding path a), and can be denoted as Delay A in this application. The second delay refers to the delay of signal transmission within the second module, which can be the delay of signal transmission from the input interface of the second module to the second register (i.e., corresponding path b), and can be denoted as Delay B in this application. The inter-module delay refers to the delay of signal transmission between the first module and the second module, which can be the delay of signal transmission from the output interface of the first module to the input interface of the second module (i.e., corresponding path c), and can be denoted as Delay C in this application.

[0062] In some embodiments, the method further includes obtaining the total timing margin.

[0063] Step S15: Generate constraint instructions, which are used to indicate the timing margin for the first module to perform power optimization and the timing margin for the second module to perform power optimization.

[0064] A constraint instruction refers to one or more virtual timing constraint instructions. These virtual timing constraint instructions are used to carry the power optimization quotas (i.e., the first timing margin and the second timing margin) that should be allocated to the first module and the second module, calculated by the power optimization method. The constraint instructions are used as virtual timing indicators in the subsequent module-level timing analysis in step S16 and the power optimization process in step S17 to drive the power optimization process in step S17 to perform power optimization on the first module and the second module, thereby saving power consumption of the modules.

[0065] In some embodiments, the constraint instruction includes a timing margin instruction for a first module, the timing margin instruction including a first timing margin. Exemplarily, the timing margin instruction for the first module may be... In some embodiments, a timing margin instruction for a second module is generated, the timing margin instruction including a second timing margin. Exemplarily, the timing margin instruction for the second module may be... .

[0066] In some embodiments, before step S15, the method further includes: determining a first timing margin from the total timing margin based on a first delay, a second delay, inter-module delay, and total delay, and determining a second timing margin from the total timing margin.

[0067] Step S16: Perform module-level static timing analysis.

[0068] In some embodiments, module-level static timing analysis is performed on the first module and the second module. This can be referred to as Tile level PT (PrimeTime), where PT indicates the static timing analysis.

[0069] Module-level static timing analysis refers to analyzing the timing performance of the first and second modules statically without running a full chip-level simulation. Specifically, this module-level static timing analysis process uses predefined timing libraries (e.g., .lib files that define the delay, transition time, and other characteristics of standard cells) and timing constraints (e.g., clock cycles, input / output delays) to check whether all signal paths in the first and second modules meet the setup and hold time requirements.

[0070] Step S17: Perform power consumption optimization.

[0071] In some embodiments, based on constraint instructions and a context model, module-level static timing analysis is performed on the first module and the second module to generate a module-level timing analysis report. This module-level timing analysis report is used to perform power consumption optimization on the first module and the second module.

[0072] In some embodiments, power optimization (opt) is performed on the first module and the second module based on the timing analysis report. For example, the configuration information of the first module and the second module is adjusted to obtain a power-optimized first module and a power-optimized second module. Optionally, the configuration information may include at least one of the following: threshold voltage, drive capability, which is not limited in this application.

[0073] For details not covered above, please refer to the corresponding descriptions above; they will not be elaborated upon here.

[0074] In summary, the technical solution provided by the embodiments of this application can optimize the power consumption of the first module and the second module based on the first timing margin and the second timing margin. Since the sum of the first timing margin and the second timing margin is less than or equal to the total timing margin, it ensures that the signal can be transmitted within the clock cycle while saving module power consumption.

[0075] The following describes the specific implementation method for determining the first and second timing margins from the total timing margin.

[0076] In some embodiments, the first timing margin is negatively correlated with the first delay, and the second timing margin is negatively correlated with the second delay.

[0077] In some embodiments, a smaller first delay indicates that the signal propagates faster on the corresponding path, and its actual arrival time has more lead time than the required arrival time, thus the first timing margin is larger (i.e., the larger the positive margin, the better the timing performance); a larger first delay indicates that the signal propagates slower on the corresponding path, and its actual arrival time is closer to or even later than the required arrival time, thus the first timing margin is smaller (i.e., the margin decreases, or even becomes a negative margin, representing a timing violation).

[0078] Similarly, the smaller the second delay, the faster the signal propagation speed in the second module, and the larger the second timing margin; the larger the second delay, the slower the signal propagation speed in the second module, and the smaller the second timing margin.

[0079] For example, suppose the first module is responsible for the initial data acquisition, and the second module is responsible for the initial processing of the acquired data. When the first module has a small first delay, for example, due to its simple internal circuit structure and excellent transistor performance, the signal propagates quickly along the path corresponding to this module, and the actual arrival time is 2 clock cycles ahead of the required arrival time. In this case, the first timing margin is large. A larger timing margin can be allocated to the first module, thereby utilizing this large timing margin to appropriately increase the threshold voltage of the first module, reduce its power consumption, and still ensure stable signal transmission within the specified clock cycle. However, when the second module has a large second delay, for example, due to its complex internal processing logic and long wiring, the signal propagation speed is slow, and the actual arrival time is only 0.5 clock cycles ahead of the required arrival time or even later. In this case, the second timing margin is small. To avoid timing violations, a smaller timing margin can be allocated to the first module to limit the signal transmission delay.

[0080] The above method fully considers the relationship between the timing margins of the first and second modules and the first and second delays, namely the negative correlation between the first and second delays and the timing margins. This allows for the allocation of a larger timing margin to the first or second module with shorter delays during power optimization, thereby saving module power consumption. Conversely, a smaller timing margin is allocated to the first or second module with longer delays, thus limiting signal transmission delays and preventing timing violations.

[0081] In some embodiments, step 220 above can be implemented as steps 221 to 223. Figure 2 (not shown in the image) Step 221: Determine the first adjustment delay and the second adjustment delay based on the first delay, the second delay, the inter-module delay, and the total timing margin.

[0082] The first adjustment delay refers to a comprehensive delay amount determined to adapt the first module to the timing requirements of the entire system, after considering the first module's own delay, the external delay of signal transmission outside the first module, and corrections to that external delay. It integrates the delay characteristics of the first module itself and the delay during interaction with external systems, and includes corrections to the external delay, enabling the first module to perform timing coordination more accurately throughout the system.

[0083] The second adjustment delay refers to a comprehensive delay amount determined to adapt the second module to the timing requirements of the entire system, after considering the second delay of the second module itself, the external delay of signal transmission outside the second module, and the correction of the external delay. It integrates the delay characteristics of the second module itself and the delay situation in the interaction process with the outside, and includes the correction amount for the external delay, so that the second module can perform timing coordination more accurately in the entire system.

[0084] Step 222: Determine the first timing margin from the total timing margin based on the clock cycles corresponding to the first module and the second module and the first adjustment delay.

[0085] In some embodiments, a first timing margin is determined based on the difference between the clock period and the first adjustment delay. Optionally, the first timing margin is obtained by subtracting the first adjustment delay from the clock period. That is, first timing margin = clock period – first adjustment delay.

[0086] Step 223: Determine the second timing margin from the total timing margin based on the clock cycle and the second adjustment delay.

[0087] In some embodiments, a second timing margin is determined based on the difference between the clock period and the second adjustment delay. Optionally, the second timing margin is obtained by subtracting the second adjustment delay from the clock period. That is, second timing margin = clock period – second adjustment delay.

[0088] The above method, based on the clock cycle, the first adjustment delay, and the second adjustment delay, yields the first timing margin and the second timing margin. This method decouples the timing design between modules, decomposing and converting complex timing path constraints that span the first and second modules into two independent module-level timing constraints specific to their respective modules.

[0089] The specific methods for determining the first and second adjustment delays are described below. That is, step 221 above can be implemented as the following steps 2211~2213 (not shown in the figure).

[0090] Step 2211: Determine the first external delay based on the second delay and the inter-module delay; and determine the second external delay based on the first delay and the inter-module delay, wherein the first external delay represents the external delay of the signal transmission outside the first module, and the second external delay represents the external delay of the signal transmission outside the second module.

[0091] The first external delay refers to the delay of the signal from the first module to the second module along other paths, excluding the first delay experienced by the signal transmission within the first module. It is used to indicate the delay consumption during the interaction between the first module and the outside world, and mainly includes factors such as the second delay of the second module and the inter-module delay between the first module and the second module.

[0092] The second external delay refers to the delay of the signal from the first module to the second module along other paths, excluding the second delay experienced by the signal transmission within the second module. It is used to indicate the delay consumption during the interaction between the second module and the outside world, and mainly includes factors such as the first delay of the first module and the inter-module delay between the first module and the second module.

[0093] In some embodiments, the first external delay includes a second delay and an inter-module delay. Optionally, the first external delay Delayout_A = the second delay + the inter-module delay.

[0094] In some embodiments, the second external delay includes the first delay and the inter-module delay. Optionally, the second external delay Delayout_B = the first delay + the inter-module delay.

[0095] Step 2222: Based on the first external delay, the second external delay, and the total timing margin, determine the first correction delay and the second correction delay; wherein, the first correction delay is used to indicate the amount of correction to the external delay of the first module, and the second correction delay is used to indicate the amount of correction to the external delay of the second module.

[0096] The first corrected delay is a correction value determined to better adapt the external delay of the first module to the timing requirements of the entire system. This correction value takes into account various uncertainties that may occur during actual system operation, such as the impact of process fluctuations and environmental changes on the external delay of the first module. By correcting the first external delay, the timing performance of the first module in the entire system becomes more stable and accurate.

[0097] The second corrected delay is a correction value determined to better adapt the external delay of the second module to the timing requirements of the entire system. This correction value takes into account the impact of factors such as process deviations, temperature changes, and power fluctuations that may occur during actual system operation on the external delay of the second module. By correcting the second external delay, it is ensured that the second module can maintain good timing coordination with other modules in the entire system.

[0098] Step 2213: Based on the first delay, the second delay, the inter-module delay, the first corrected delay, and the second corrected delay, determine the first adjusted delay and the second adjusted delay.

[0099] In some embodiments, the first adjustment delay is determined based on a first external delay, a first correction delay, and a first delay. In some embodiments, the first adjustment delay is determined based on the sum of the first external delay, the first correction delay, and the first delay. Optionally, the first adjustment delay = the first external delay + the first correction delay + the first delay. Then the first timing margin Tnew_margin_A = clock cycle – (second delay + inter-module delay + second correction delay) – first delay. As shown in Formula 3 below: Tnew_margin_A = Tperiod - (Delayout_A + TmarginA) – DelayA (Formula 3) Where Tperiod refers to the clock cycle, Delayout_A refers to the sum of the second delay and the inter-module delay, that is, Delayout_A = Delay B (second delay) + Delay C (inter-module delay). TmarginA refers to the first correction delay.

[0100] In some embodiments, the second adjustment delay is determined based on the sum of the second external delay, the second correction delay, and the second delay. Optionally, the second adjustment delay = the second external delay + the second correction delay + the second delay. Similarly, the second timing margin Tnew_margin_B = clock cycle – (first delay + inter-module delay + second correction delay) – second delay, as shown in Formula 4 below: Tnew_margin_B = Tperiod - (Delayout_B + TmarginB) – DelayB (Formula 4) Where Tperiod refers to the clock cycle, Delayout_B refers to the sum of the first delay and the inter-module delay, and Delayout_B = Delay A (first delay) + Delay C (inter-module delay). TmarginB refers to the second correction delay.

[0101] The above method can accurately determine the first adjustment delay based on the first external delay and the first correction delay, and can accurately determine the second adjustment delay based on the second external delay and the second correction delay.

[0102] The following describes the specific methods for determining the first and second correction delays.

[0103] In some embodiments, a first corrected delay and a second corrected delay are determined based on a first external delay, a second external delay, and a total timing margin.

[0104] In some embodiments, a first corrected delay is determined based on a first external delay, total delay, and total timing margin. Optionally, the ratio between the first external delay (i.e., the sum of the second delay and the inter-module delay) and the total delay is determined; the product of this ratio and the total timing margin is determined, and the first corrected delay is determined based on this product. Optionally, this product is determined as the first corrected delay. Exemplarily, the formula for calculating the first corrected delay TmarginA is shown in Formula 5 below: (Formula 5) in, This refers to the second time delay. This refers to the inter-module latency. This refers to the total delay. This refers to the total timing margin. The total delay is determined based on the first delay, the second delay, and the inter-module delay. Optionally, the total delay is equal to the sum of the first delay, the second delay, and the inter-module delay.

[0105] Similarly, in some embodiments, a second corrected delay is determined based on a second external delay, total delay, and total timing margin. The ratio between the second external delay (i.e., the sum of the first delay and the inter-module delay) and the total delay is determined; the product of this ratio and the total timing margin is determined, and the second corrected delay is determined based on this product. Optionally, this product is determined as a second adjusted delay. For example, the formula for calculating the second corrected delay TmarginB is shown in Formula 6 below: (Formula 6) in, This refers to the first time delay. This refers to the inter-module latency. This refers to the total delay. This refers to the total timing margin.

[0106] The above method achieves a reasonable allocation of the total timing margin by calculating the first and second correction delays.

[0107] In some embodiments, the first corrected delay and the second corrected delay are determined based on the first external delay, the second external delay, and the total timing margin, including the following steps S21~S25 (not shown in the figure): In some embodiments, the first module includes a plurality of first units, the plurality of first units corresponding to N unit types, and the second module includes a plurality of second units, the plurality of second units corresponding to M unit types, where N and M are both positive integers.

[0108] In some embodiments, the first module includes a plurality of first units, which correspond to N unit types, and the second module includes a plurality of second units, which correspond to M unit types, where N and M are both positive integers.

[0109] The multiple units (first unit, second unit) included in a module refer to the basic components that constitute the module and realize its specific functions. These units can be circuit elements, sub-modules, or functional blocks with independent logical functions. They cooperate and interact with each other to complete the tasks undertaken by the module.

[0110] In some embodiments, the configuration information of different types of first units is different, and the configuration information may include at least one of the following: threshold voltage, driving capability, and logic function. This application does not limit the scope of the configuration information. The logic function may include at least one of the following: inverter, NAND gate, NOR gate, XOR gate, flip-flop, latch, adder, etc. These are merely examples and are not limited in scope.

[0111] Similarly, the configuration information of different types of second units is different. The configuration information may include at least one of the following: threshold voltage, driving capability, and logic function. This application does not limit the specific configuration information. The logic function may include at least one of the following: inverter, NAND gate, NOR gate, XOR gate, flip-flop, latch, adder, etc. These are merely examples and are not limited in this application.

[0112] For example, the first module can be a data path module with extremely high timing performance requirements, so its N types can contain a large number of LVT (Low Threshold Voltage) and high drive capability (such as X8, X16, etc.) units. The second module can be a power-sensitive control logic module, so its M types can contain more HVT (High Threshold Voltage) units, which is not limited in this application.

[0113] Step S21: Obtain the delay, first quantity, and first delay difference value of the first unit corresponding to each of the N unit types, to obtain the delay of the N first units, the N first quantities, and the N first delay difference values; wherein, the first delay difference value is used to indicate the difference between the optimized delay of the first unit of the corresponding unit type and the delay of the first unit; the optimized delay of the first unit of the corresponding unit type refers to the predicted delay of the signal transmission inside the first unit after power consumption optimization.

[0114] The latency of the first unit, also known as the pre-optimization latency of the first unit, refers to the latency of signal transmission within the first unit before power consumption optimization is performed.

[0115] The optimized latency of the first cell refers to the signal transmission delay within the first cell after power optimization. It should be noted that the optimized latency of the first cell here refers to the predicted signal transmission delay within the first cell after power optimization; that is, the optimized latency of the first cell is an estimate. For example, a standard cell library contains cell type A (NAND2_X1_LVT, low threshold) and cell type B (NAND2_X1_HVT, high threshold), which have the same logic function and driving capability. The latency of the first cell can be defined as the latency of type A (LVT), for example, Delay_pre = 20ns. The optimized latency of the first cell can be defined as the latency of type B (HVT), for example, Delay_post = 35ns. In power optimization, NAND2_X1_LVT is replaced with NAND2_X1_HVT to save leakage power. In this case, the optimized latency of the first cell changes from 20ns to 35ns.

[0116] The first delay difference value is used to indicate the difference between the optimized delay of the first unit and the delay of the first unit. The larger the difference, the greater the timing performance sacrifice (i.e., the increase in delay) of the first unit when performing power optimization (e.g., replacing from a low threshold voltage LVT to a high threshold voltage HVT). The smaller the difference, the less the timing characteristics of the unit type change before and after optimization (e.g., the unit itself is already an HVT, or the delay between the LVT and HVT versions is similar).

[0117] In some embodiments, the first delay difference value is determined based on the ratio between the optimized delay of the first unit and the delay of the first unit. Optionally, the first delay difference value refers to the ratio between the optimized delay of the first unit and the delay of the first unit.

[0118] The ratio between the optimized latency of the first unit and the latency of the first unit reflects the impact of power optimization on latency. A larger ratio indicates a greater impact of power optimization on latency, while a smaller ratio indicates a smaller impact. For example, based on the above example, a latency ratio of 35 / 20 = 1.75 for the unit type means that the latency increased by 1.75 times after optimization.

[0119] The above method uses the ratio of the optimized latency of the first unit to the actual latency of the first unit to reflect the impact of power consumption optimization on latency. By comparing the latency ratios under different optimization strategies, it is possible to determine which strategy reduces power consumption while minimizing the impact on timing performance.

[0120] In some embodiments, the first delay difference value is determined based on the difference between the optimized delay of the first unit and the delay of the first unit. Optionally, the first delay difference value refers to the difference between the optimized delay of the first unit and the delay of the first unit, and this application does not limit the method of determining the first delay difference value.

[0121] Step S22: Obtain the delay, second quantity, and second delay difference value of the second unit corresponding to each of the M unit types, to obtain the delay of the M second units, the M second quantities, and the M second delay difference values; wherein, the second delay difference value is used to indicate the difference between the optimized delay of the second unit of the corresponding unit type and the delay of the second unit; the optimized delay of the second unit of the corresponding unit type refers to the predicted delay of the signal transmission inside the second unit after power consumption optimization.

[0122] The principle of step S23 is similar to that of step S22 above, that is, the content of step S22 above applies to step S23, and will not be repeated here.

[0123] Step S23: Determine a first value based on the delay of N first units, N first quantities, and N first delay difference values; and determine a second value based on the delay of M second units, M second quantities, and M second delay difference values; wherein the first value is determined based on the predicted delay after power consumption optimization of the first module; and the second value is determined based on the predicted delay after power consumption optimization of the second module.

[0124] In some embodiments, for each of the N unit types, the product of the delay, the first quantity, and the first delay difference value of the first unit of that unit type is determined to obtain the product corresponding to that unit type; a first value is determined based on the products corresponding to the N unit types respectively. Optionally, the first value is determined based on the sum of the products corresponding to the N unit types respectively. Optionally, the sum of the products corresponding to the N unit types is determined as the first value. Exemplarily, the first value... The calculation formula can be shown in Figure 7 below: (Formula 7) in, This refers to the latency of the first unit of the nth unit type. Kn refers to the first delay difference value of the nth unit type, and Kn refers to the first quantity of the nth unit type, where n ranges from 1 to N.

[0125] Similarly, for each of the M unit types, the product of the delay, quantity, and delay difference of the second unit of that unit type is determined to obtain the product corresponding to that unit type; based on the products corresponding to the M unit types respectively, the second value is determined. Optionally, the second value is determined based on the sum of the products corresponding to the M unit types respectively. Optionally, the sum of the products corresponding to the M unit types respectively is used to determine the second value. For example, the second value... The calculation formula can be shown in Figure 8 below: (Formula 8) in, This refers to the delay of the second unit of the m-th unit type. This refers to the second delay difference value of the m-th unit type. m refers to the second quantity of the m-th unit type, and the value of m can be from 1 to M.

[0126] Step S24: Determine the total delay based on the first delay, the second delay, and the inter-module delay.

[0127] In some embodiments, the total latency is determined based on the sum of the first latency, the second latency, and the inter-module latency. Optionally, the sum of the first latency, the second latency, and the inter-module latency is used to determine the total latency.

[0128] Step S25: Based on the first external delay, the second external delay, the first value, the second value, the total delay, and the total timing margin, determine the first corrected delay and the second corrected delay.

[0129] The above method, by considering the individual delays and post-delay delays of the multiple first units included in the first module and the multiple second units included in the second module, can more accurately assess the impact of different unit types within each module on the overall timing. Different unit types exhibit different delay changes before and after power optimization. This detailed analysis helps to accurately determine the first and second corrected delays, thereby achieving a reasonable allocation of the total timing margin. For example, assuming the current delays of the first and second modules are similar, but the second delay difference value of the second module is much higher than the first delay difference value of the first module, the calculated second value is larger. That is, when determining the first and second corrected delays, the calculated second corrected delay is greater than the first corrected delay, thus strategically allocating more timing margin to the first module, thereby avoiding timing violations while reducing module power consumption. Alternatively, assuming that the current delays of the first module and the second module are similar, but the first delay difference value of the first module is much higher than that of the second module, the calculated first value is larger. That is, when determining the first corrected delay and the second corrected delay, the calculated first corrected delay is greater than the second corrected delay. This allows for a more strategic allocation of timing margin to the second module, thereby avoiding timing violations while reducing module power consumption.

[0130] In some embodiments, the first corrected delay and the second corrected delay are determined based on the first external delay, the second external delay, the first value, the second value, the total delay, and the total timing margin, including the following sub-steps S31 to S33 (not shown in the figure).

[0131] Step S31: Obtain the first sum between the first external delay and the first value, and obtain the second sum between the second external delay and the second value.

[0132] Step S32: Obtain the first difference between the first sum and the second value, and obtain the second difference between the second sum and the first value.

[0133] Step S33: Determine the first corrected delay based on the first difference, the total delay, and the total timing margin; and determine the second corrected delay based on the second difference, the total delay, and the total timing margin.

[0134] In some embodiments, a first ratio of a first difference to a total delay is determined; a first corrected delay is determined based on the first ratio and the total timing margin. Optionally, a first product between the first ratio and the total timing margin is determined; the first corrected delay is determined based on the first product. Optionally, the first product is determined as the first corrected delay. Exemplarily, the formula for calculating the first corrected delay is shown in Formula 9 below: (Formula 9) in, This refers to the first value. It refers to the second value. This refers to the second time delay. This refers to the latency between modules. This refers to the total delay. Total timing margin.

[0135] In some embodiments, a second ratio of the second difference to the total delay is determined; a second corrected delay is determined based on the second ratio and the total timing margin. Optionally, a second product between the second ratio and the total timing margin is determined; the second corrected delay is determined based on the second product. Optionally, the second product is determined as the second corrected delay. Exemplarily, the formula for calculating the second corrected delay is shown in Formula 10 below: (Formula 10) in, This refers to the first value. It refers to the second value. This refers to the second time delay. This refers to the latency between modules. This refers to the total delay. Total timing margin.

[0136] In some embodiments, based on formulas 9 and 10 above, if the first value is larger and the second value is smaller, the calculated first corrected delay is larger and the second corrected delay is smaller. Thus, the subsequently calculated first timing margin is smaller and the second timing margin is larger. In other words, in this case, more timing margin is allocated to the second module, thereby reducing the power consumption of the second module while avoiding large transmission delays caused by signals within the first module, thus preventing timing violations.

[0137] In some embodiments, based on formulas 9 and 10 above, if the first value is smaller and the second value is larger, the calculated first corrected delay is smaller and the second corrected delay is larger. Thus, the subsequently calculated first timing margin is larger and the second timing margin is smaller. In other words, in this case, more timing margin is allocated to the first module, thereby reducing the power consumption of the first module while avoiding significant signal transmission delays within the second module, thus preventing timing violations.

[0138] In some embodiments, optimizing the power consumption of two modules with the same latency has different effects on latency. By combining a first value and a second value, the total timing margin can be intelligently allocated preferentially to the module with the smaller latency difference, thereby avoiding timing violations while reducing module power consumption. For example, assuming the current latency of the first and second modules is similar, but the second latency difference of the second module is much higher than that of the first module, the calculated second value is larger. That is, when determining the first and second corrected latency, the calculated second corrected latency is greater than the first corrected latency, thus strategically allocating more timing margin to the first module, thereby avoiding timing violations while reducing module power consumption. Alternatively, assuming the current latency of the first and second modules is similar, but the first latency difference of the first module is much higher than that of the second module, the calculated first value is larger. That is, when determining the first and second corrected latency, the calculated first corrected latency is greater than the second corrected latency, thus strategically allocating more timing margin to the second module, thereby avoiding timing violations while reducing module power consumption.

[0139] As shown in Table 1 below, the power consumption of modules A, B and C was optimized according to the method of this application, and the data before and after the power consumption optimization are shown in Table 1 below.

[0140] Table 1

[0141] As shown in Table 1 above, Ori_power refers to the original power consumption of the module before power optimization. It reflects the power consumed by the module under normal operating conditions and serves as a benchmark for evaluating the effectiveness of power optimization. Opt_power refers to the power consumption achieved after power optimization using the method described in this application, reflecting the actual power consumed by the module after the optimization measures are implemented. Total_power refers to the percentage reduction in total power consumption after power optimization. This indicator is presented as a percentage, intuitively demonstrating the effectiveness of the optimization method in reducing the overall power consumption of the module. Leakage_power refers to the percentage reduction in leakage power consumption after power optimization. Leakage power consumption is an important component of chip power consumption, and this indicator reflects the effectiveness of the optimization method in reducing leakage losses. Test results show that the overall power consumption can be further reduced by about 1%, and the leakage power consumption of modules B and C can be reduced by more than 35%.

[0142] The above method calculates the first corrected delay by adding a first value and subtracting a second value; and calculates the second corrected delay by adding a second value and subtracting a first value. This method can flexibly allocate timing margins between the first and second modules according to different needs, thereby achieving targeted optimization of power consumption for different modules and effectively avoiding timing violations.

[0143] Specifically, when calculating the first corrected delay, a first value is added and a second value is subtracted. The larger the first value and the smaller the second value, the larger the calculated first corrected delay and the smaller the second corrected delay. This results in a smaller first timing margin and a larger second timing margin in subsequent calculations. In other words, under these conditions, more timing margin is allocated to the second module, thereby reducing the power consumption of the second module while avoiding significant signal transmission delays within the first module, thus preventing timing violations.

[0144] When calculating the second corrected delay, a second value is added and the first value is subtracted. The smaller the first value and the larger the second value, the smaller the calculated first corrected delay and the larger the second corrected delay. This results in a larger calculated first timing margin and a smaller second timing margin. In other words, in this scenario, more timing margin is allocated to the first module, thereby reducing the power consumption of the first module while avoiding significant signal transmission delays within the second module, thus preventing timing violations.

[0145] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0146] Please refer to Figure 5 This diagram illustrates a block diagram of a power optimization device in one possible implementation of this application. The device has the function of implementing the aforementioned power optimization method; this function can be implemented in hardware or by hardware executing corresponding software. The device can be a computer device or can be installed within a computer device. The device 500 may include: an acquisition module 510, a determination module 520, and an execution module 530.

[0147] The acquisition module 510 is used to acquire a first delay of the first module, a second delay of the second module, an inter-module delay between the first module and the second module, and a total timing margin; wherein, the first delay is used to indicate the delay of signal transmission within the first module, the second delay is used to indicate the delay of signal transmission within the second module, the inter-module delay is used to indicate the delay of signal transmission between the first module and the second module, and the total timing margin is used to indicate the timing margin to be allocated during power optimization of the first module and the second module.

[0148] The determining module 520 is configured to determine a first timing margin and a second timing margin from the total timing margin based on the first delay, the second delay, and the inter-module delay; wherein the first timing margin is the timing margin allocated to the first module for performing power optimization, the second timing margin is the timing margin allocated to the second module for performing power optimization, and the sum of the first timing margin and the second timing margin is less than or equal to the total timing margin.

[0149] The execution module 530 is used to perform power consumption optimization on the first module and the second module based on the first timing margin and the second timing margin.

[0150] In some embodiments, the first timing margin is negatively correlated with the first delay, and the second timing margin is negatively correlated with the second delay.

[0151] In some embodiments, the determining module 520 is configured to determine a first adjustment delay and a second adjustment delay based on the first delay, the second delay, the inter-module delay, and the total timing margin; determine the first timing margin from the total timing margin based on the clock cycles corresponding to the first module and the second module and the first adjustment delay; and determine the second timing margin from the total timing margin based on the clock cycles and the second adjustment delay.

[0152] In some embodiments, the determining module 520 is configured to: determine a first external delay based on the second delay and the inter-module delay; and determine a second external delay based on the first delay and the inter-module delay, wherein the first external delay represents the external delay of signal transmission outside the first module, and the second external delay represents the external delay of signal transmission outside the second module; determine a first corrected delay and a second corrected delay based on the first external delay, the second external delay, and the total timing margin; wherein the first corrected delay indicates the amount of correction to the external delay of the first module, and the second corrected delay indicates the amount of correction to the external delay of the second module; and determine a first adjusted delay and a second adjusted delay based on the first delay, the second delay, the inter-module delay, the first corrected delay, and the second corrected delay.

[0153] In some embodiments, the first module includes a plurality of first units, the plurality of first units corresponding to N unit types, and the second module includes a plurality of second units, the plurality of second units corresponding to M unit types, where N and M are both positive integers; the determining module 520 is used to obtain the delay, first quantity, and first delay difference value of the first unit corresponding to each of the N unit types, to obtain the delay of N first units, N first quantities, and N first delay difference values; wherein, the first delay difference value is used to indicate the difference between the optimized delay of the first unit of the corresponding unit type and the delay of the first unit; the optimized delay of the first unit of the corresponding unit type refers to the predicted delay of signal transmission within the first unit after power optimization; obtain the delay, second quantity, and second delay difference value of the second unit corresponding to each of the M unit types, to obtain the delay of M second units, M second quantities, and M second delay difference values; wherein, the second The delay difference value is used to indicate the difference between the optimized delay of the second unit of the corresponding unit type and the delay of the second unit; the optimized delay of the second unit of the corresponding unit type refers to the predicted delay of signal transmission within the second unit after power optimization; a first value is determined based on the delay of the N first units, the N first quantities, and the N first delay difference values, and a second value is determined based on the delay of the M second units, the M second quantities, and the M second delay difference values; wherein, the first value is determined based on the predicted delay after power optimization of the first module; the second value is determined based on the predicted delay after power optimization of the second module; the total delay is determined based on the first delay, the second delay, and the inter-module delay; the first corrected delay and the second corrected delay are determined based on the first external delay, the second external delay, the first value, the second value, the total delay, and the total timing margin.

[0154] In some embodiments, the determining module 520 is configured to obtain a first sum between the first external delay and the first value, and to obtain a second sum between the second external delay and the second value; to obtain a first difference between the first sum and the second value, and to obtain a second difference between the second sum and the first value; to determine a first corrected delay based on the first difference, the total delay, and the total timing margin; and to determine a second corrected delay based on the second difference, the total delay, and the total timing margin.

[0155] In some embodiments, the first module and the second module are applied within any chip; the execution module 530 is used to perform timing analysis processing on the chip to generate a context model, the context model being used to indicate the actual external timing environment of the first module and the second module within the chip; and to perform power consumption optimization on the first module and the second module based on the first timing margin, the second timing margin, and the context model.

[0156] In some embodiments, the execution module 530 is configured to generate constraint instructions based on the first timing margin and the second timing margin, the constraint instructions being used to indicate the timing margin for the first module to perform power optimization and the timing margin for the second module to perform power optimization; and to perform power optimization on the first module and the second module based on the constraint instructions and the context model.

[0157] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the content structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0158] Please refer to Figure 6 The diagram shows a structural block diagram of a computer device 600 provided in one embodiment of this application.

[0159] Typically, computer device 600 includes a processor 610 and a memory 620.

[0160] Processor 610 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 610 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 610 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 610 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 610 may also include an AI processor for handling computational operations related to machine learning.

[0161] The memory 620 may include one or more computer-readable storage media, which may be non-transitory. The memory 620 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 620 is used to store a computer program configured to be executed by one or more processors to implement the power optimization method described above.

[0162] Those skilled in the art will understand that Figure 6 The structure shown does not constitute a limitation on the computer device 600, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0163] In an exemplary embodiment, a computer-readable storage medium is also provided, wherein a computer program is stored in the storage medium, and the computer program, when executed by a processor, implements the power optimization method described above. Optionally, the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random Access Memory), SSD (Solid State Drives), or optical disc, etc. The random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0164] In an exemplary embodiment, a computer program product is also provided, the computer program product including a computer program stored in a computer-readable storage medium. A processor of a terminal device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, causing the terminal device to perform the power optimization method described above.

[0165] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0166] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A power consumption optimization method, characterized in that, The method includes: The first delay of the first module, the second delay of the second module, the inter-module delay between the first module and the second module, and the total timing margin are obtained; wherein, the first delay is used to indicate the delay of signal transmission within the first module, the second delay is used to indicate the delay of signal transmission within the second module, the inter-module delay is used to indicate the delay of signal transmission between the first module and the second module, and the total timing margin is used to indicate the timing margin to be allocated during power optimization of the first module and the second module; Based on the first delay, the second delay, and the inter-module delay, a first timing margin and a second timing margin are determined from the total timing margin; wherein, the first timing margin is the timing margin allocated to the first module for performing power optimization, the second timing margin is the timing margin allocated to the second module for performing power optimization, and the sum of the first timing margin and the second timing margin is less than or equal to the total timing margin; Based on the first timing margin and the second timing margin, power consumption optimization is performed on the first module and the second module.

2. The method according to claim 1, characterized in that, The step of determining the first timing margin and the second timing margin from the total timing margin based on the first delay, the second delay, and the inter-module delay includes: Based on the first delay, the second delay, the inter-module delay, and the total timing margin, the first adjustment delay and the second adjustment delay are determined; Based on the clock cycles corresponding to the first module and the second module and the first adjustment delay, the first timing margin is determined from the total timing margin; The second timing margin is determined from the total timing margin based on the clock cycle and the second adjustment delay.

3. The method according to claim 2, characterized in that, The step of determining the first adjustment delay and the second adjustment delay based on the first delay, the second delay, the inter-module delay, and the total timing margin includes: Based on the second delay and the inter-module delay, a first external delay is determined; and based on the first delay and the inter-module delay, a second external delay is determined, wherein the first external delay represents the external delay of signal transmission outside the first module, and the second external delay represents the external delay of signal transmission outside the second module; Based on the first external delay, the second external delay, and the total timing margin, a first corrected delay and a second corrected delay are determined; wherein, the first corrected delay is used to indicate the amount of correction to the external delay of the first module, and the second corrected delay is used to indicate the amount of correction to the external delay of the second module; Based on the first delay, the second delay, the inter-module delay, the first corrected delay, and the second corrected delay, the first adjusted delay and the second adjusted delay are determined.

4. The method according to claim 3, characterized in that, The first module includes multiple first units, each corresponding to N unit types; the second module includes multiple second units, each corresponding to M unit types, where N and M are both positive integers. The step of determining the first corrected delay and the second corrected delay based on the first external delay, the second external delay, and the total timing margin includes: Obtain the delay, first quantity, and first delay difference value of the first unit corresponding to each of the N unit types, to obtain the delay of N first units, N first quantities, and N first delay difference values; wherein, the first delay difference value is used to indicate the difference between the optimized delay of the first unit of the corresponding unit type and the delay of the first unit; the optimized delay of the first unit of the corresponding unit type refers to the predicted delay of signal transmission within the first unit after power optimization; Obtain the delay, second quantity, and second delay difference value of the second unit corresponding to each of the M unit types, to obtain the delay of the M second units, the M second quantities, and the M second delay difference values; wherein, the second delay difference value is used to indicate the difference between the optimized delay of the second unit of the corresponding unit type and the delay of the second unit; the optimized delay of the second unit of the corresponding unit type refers to the predicted delay of signal transmission within the second unit after power optimization; A first value is determined based on the delay of the N first units, the N first quantities, and the N first delay difference values; and a second value is determined based on the delay of the M second units, the M second quantities, and the M second delay difference values; wherein the first value is determined based on the predicted delay after power consumption optimization of the first module; and the second value is determined based on the predicted delay after power consumption optimization of the second module. The total delay is determined based on the first delay, the second delay, and the inter-module delay; The first corrected delay and the second corrected delay are determined based on the first external delay, the second external delay, the first value, the second value, the total delay, and the total timing margin.

5. The method according to claim 4, characterized in that, The step of determining the first corrected delay and the second corrected delay based on the first external delay, the second external delay, the first value, the second value, the total delay, and the total timing margin includes: Obtain a first sum between the first external delay and the first value, and obtain a second sum between the second external delay and the second value; Obtain a first difference between the first sum and the second value, and obtain a second difference between the second sum and the first value; The first corrected delay is determined based on the first difference, the total delay, and the total timing margin; and the second corrected delay is determined based on the second difference, the total delay, and the total timing margin.

6. The method according to any one of claims 1 to 5, characterized in that, The first module and the second module are applied within any chip; The step of performing power consumption optimization on the first module and the second module based on the first timing margin and the second timing margin includes: Timing analysis is performed on the chip to generate a context model, which is used to indicate the actual external timing environment of the first module and the second module within the chip. Based on the first timing margin, the second timing margin, and the context model, power consumption optimization is performed on the first module and the second module.

7. The method according to claim 6, characterized in that, The step of performing power consumption optimization on the first module and the second module based on the first timing margin, the second timing margin, and the context model includes: Based on the first timing margin and the second timing margin, a constraint instruction is generated, which is used to indicate the timing margin of the first module for performing power optimization and the timing margin of the second module for performing power optimization. Based on the constraint instructions and the context model, power consumption optimization is performed on the first module and the second module.

8. A power consumption optimization device, characterized in that, The device includes: An acquisition module is used to acquire a first delay of a first module, a second delay of a second module, an inter-module delay between the first module and the second module, and a total timing margin; wherein, the first delay is used to indicate the delay of signal transmission within the first module, the second delay is used to indicate the delay of signal transmission within the second module, the inter-module delay is used to indicate the delay of signal transmission between the first module and the second module, and the total timing margin is used to indicate the timing margin to be allocated during power optimization of the first module and the second module; A determining module is configured to determine a first timing margin and a second timing margin from the total timing margin based on the first delay, the second delay, and the inter-module delay; wherein the first timing margin is the timing margin allocated to the first module for performing power optimization, the second timing margin is the timing margin allocated to the second module for performing power optimization, and the sum of the first timing margin and the second timing margin is less than or equal to the total timing margin; An execution module is configured to perform power consumption optimization on the first module and the second module based on the first timing margin and the second timing margin.

9. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program that is loaded and executed by the processor to implement the method as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the method as described in any one of claims 1 to 7.

11. A computer program product, characterized in that, The computer program product includes a computer program stored in a computer-readable storage medium, which a processor reads from and executes to implement the method as described in any one of claims 1 to 7.

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