Data processing method and device of AI chip, equipment and medium

Abstract

The invention discloses a data processing method and device of an AI chip, equipment and a medium, and relates to the technical field of artificial intelligence, and the method comprises the steps: obtaining input feature map data of a convolutional neural network model; and performing convolution operation on the input feature map data by taking a plurality of basic dimensions and a plurality of extended dimensions as parallel dimensions to generate output feature map data, the extended dimensions being at least part of the basic dimensions. By adjusting the combination of the basic dimension and the extended dimension, accurate matching of the parallel architecture and the model requirement can be realized, the problem of insufficient adaptability caused by a fixed architecture is solved, and the computing power idling can be greatly reduced, so that the effective computing power of an AI chip is improved.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence technology, and in particular to a data processing method, apparatus, device, and medium for an AI chip. Background Technology

[0002] In the field of artificial intelligence, Convolutional Neural Networks (CNNs) are widely used as core algorithms in scenarios such as image recognition and object detection. To achieve efficient computation of CNNs, AI chips typically employ a multi-dimensional parallel computing architecture.

[0003] Current AI (Artificial Intelligence) chips typically employ a fixed-parallelism hardware architecture when performing CNN model computations. However, due to the highly flexible structure of CNN models and the significant differences in structural parameters between different models, a fixed-parallelism hardware architecture cannot adapt to all models. When the actual dimensionality of the model is less than the hardware parallelism, unused MACs (Multiply-Accumulate) will idle, resulting in low MAC utilization and consequently a significant discrepancy between the theoretical and actual computing power of the AI ​​chip.

[0004] In summary, improving the effective computing power of AI chips is a problem that needs to be solved. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a data processing method, apparatus, device, and medium for AI chips, which can improve the effective computing power of AI chips. The specific solution is as follows:

[0006] In a first aspect, this application discloses a method for processing convolutional neural network models, including:

[0007] Obtain the input feature map data of the convolutional neural network model;

[0008] The input feature map data is subjected to a convolution operation with multiple basic dimensions and several extended dimensions as parallel dimensions to generate output feature map data, wherein the extended dimensions are at least a part of the basic dimensions.

[0009] Optionally, performing a convolution operation on the input feature map data using multiple basic dimensions and several extended dimensions as parallel dimensions includes:

[0010] The input feature map data is used as the input data of the current convolutional layer, and convolution calculation is performed according to the parallel dimension configured for the current convolutional layer to obtain the output data of the current convolutional layer.

[0011] The output data of the current convolutional layer is used as the input data of the next convolutional layer, and the convolution calculation continues to be performed according to the parallel dimension configured for the next convolutional layer, until the calculation of all convolutional layers in the convolutional neural network model is completed.

[0012] Optional parallel dimension configurations for each convolutional layer include:

[0013] Obtain the various structural parameters corresponding to each convolutional layer and the initial parameter values ​​corresponding to each of the various structural parameters;

[0014] Based on the initial parameter values ​​corresponding to the various structural parameters, the basic dimension corresponding to each convolutional layer is determined from the various structural parameters corresponding to each convolutional layer.

[0015] The initial parameter values ​​of each convolutional layer under the base dimension are compared with the target parallelism, and the extended dimension of each convolutional layer is determined based on the comparison results.

[0016] Optionally, determining the expansion dimension corresponding to each of the convolutional layers based on the comparison results includes:

[0017] If the initial parameter value of any base dimension corresponding to any of the convolutional layers is greater than the target parallelism, then the base dimension with the initial parameter value greater than the target parallelism is set as the extended dimension.

[0018] Optionally, the method further includes:

[0019] The final parameter value of the extended dimension is configured as a / b, where a is the initial parameter value of the base dimension set as the extended dimension, and b is the target parallelism.

[0020] Optionally, the method further includes:

[0021] The final parameter value of the base dimension n1 when the initial parameter value is less than or equal to the target parallelism is configured as c, where c is the initial parameter value of the base dimension n1.

[0022] When the initial parameter value is greater than the target parallelism, the final parameter value of the base dimension n2 is configured as b, where b is the target parallelism.

[0023] Optionally, the structural parameters include the width and height of the input feature map, the number of input channels, and the number of output channels;

[0024] The basic dimension is set based on any three of the following parameters: width, height, number of input channels, and number of output channels.

[0025] Secondly, this application discloses a data processing device for an AI chip, comprising:

[0026] The data acquisition module is used to acquire the input feature map data of the convolutional neural network model;

[0027] A convolution processing module is used to perform convolution operations on the input feature map data with multiple basic dimensions and several extended dimensions as parallel dimensions to generate output feature map data, wherein the extended dimensions are at least a part of the basic dimensions.

[0028] Thirdly, this application discloses an electronic device, including:

[0029] Memory, used to store computer programs;

[0030] A processor is used to execute the computer program to implement the steps of the data processing method for the aforementioned disclosed AI chip.

[0031] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the aforementioned disclosed AI chip data processing method.

[0032] As can be seen, this application obtains the input feature map data of a convolutional neural network model; performs convolution operations on the input feature map data with multiple basic dimensions and several extended dimensions as parallel dimensions to generate output feature map data, wherein the extended dimensions are at least a part of the basic dimensions.

[0033] Beneficial Effects: This application addresses the issue that fixed-parallelism hardware architectures cannot adapt to all models. It introduces a dynamic parallel mechanism combining basic and extended dimensions, with the extended dimensions being at least a portion of the basic dimensions. This allows the parallel dimensions to be flexibly adjusted based on model parameters to suit the needs of different models. Specifically, when processing convolutional neural network models, this application uses multiple basic dimensions and several extended dimensions as parallel dimensions to perform convolution operations on the input feature map data, thereby generating output feature map data. In this way, by adjusting the combination of basic and extended dimensions, a precise match between the parallel architecture and model requirements can be achieved, solving the adaptability problem caused by fixed architectures. This significantly reduces idle computing power, thereby improving the effective computing power of AI chips. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0035] Figure 1 This is a flowchart of a data processing method for an AI chip disclosed in this application;

[0036] Figure 2 This is a simplified structural diagram of a convolutional neural network model disclosed in this application.

[0037] Figure 3 This is a schematic diagram of the data processing device structure of an AI chip disclosed in this application;

[0038] Figure 4 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0040] To efficiently perform CNN calculations, AI chips must perform parallel computations across multiple dimensions. However, current AI chips typically employ a hardware architecture with fixed parallelism when executing CNN model calculations. There are two main parallel computing schemes: the first involves parallel computation across the width (W), height (H), and number of output channels (OC) of the input feature map; the second involves parallel computation across the number of input channels (IC), the width (W), and the number of output channels (OC) of the input feature map.

[0041] Taking a computing power of 16 TOPS and a chip operating frequency of 1GHz as an example, if parallelism is adopted in three dimensions: IC, W, and OC, the following three common fixed parallel computing schemes are:

[0042] Option 1: 16W parallel × 16IC parallel × 32OC parallel = 8192 MACs, computing power = 8192 × 1GHz × 2 = 16TOPs;

[0043] Option 2: 16W parallel × 32IC parallel × 16OC parallel = 8192 MACs, computing power = 8192 × 1GHz × 2 = 16TOPs;

[0044] Option 3: 32W parallel × 16IC parallel × 16OC parallel = 8192 MACs, computing power = 8192 × 1GHz × 2 = 16TOPs.

[0045] However, due to the highly flexible structure of CNN models and the significant differences in structural parameters between different models, a fixed parallelism hardware architecture cannot adapt to all models. When the actual dimensionality of the model is less than the hardware parallelism, unused MACs will idle, resulting in low MAC utilization. This leads to a significant discrepancy between the theoretical and actual computing power of AI chips, as shown in Table 1.

[0046] Table 1

[0047]

[0048] Taking Scheme 3 as an example, there are 32 multiply-accumulators performing parallel calculations in the W direction, corresponding to MAC0~MAC31. When W=16 for a certain model, only MAC0~MAC15 will be effectively calculated. MAC16~MAC17 are idle due to a lack of valid input data, resulting in wasted computing power. Therefore, this application discloses a data processing method, apparatus, device, and medium for AI chips, which can improve the effective computing power of AI chips.

[0049] See Figure 1 As shown in the figure, this application discloses a data processing method for an AI chip, the method including:

[0050] Step S11: Obtain the input feature map data of the convolutional neural network model.

[0051] In this embodiment, the input feature map data of the convolutional neural network model is first obtained. This input feature map data contains the basic information required for subsequent convolution calculations, specifically including the height (H), width (W), and number of channels (IC) of the input feature map. The height and width directly correspond to the pixel matrix of its spatial dimension, while the number of channels refers to the feature depth of each spatial location. For example, an RGB image has 3 channels, which correspond to the pixel matrix of red (R), green (G), and blue (B) respectively.

[0052] It should also be noted that a feature map is essentially a two-dimensional grid structure, where each grid position is called a pixel, representing the feature value at that position. Therefore, the height corresponds to the number of rows in the feature map, i.e., the number of pixels in the vertical direction; and the width corresponds to the number of columns in the feature map, i.e., the number of pixels in the horizontal direction.

[0053] Figure 2 This is a simplified structural diagram of a convolutional neural network model disclosed in this application. From left to right, the layers are the input layer, the convolutional layer, and the output layer. Figure 2 In this example, the number of channels in the input feature map is IC=3, the number of channels in the output feature map is OC=4, and the number of convolutional kernels is equal to the number of output channels OC, both being 4.

[0054] Step S12: Perform a convolution operation on the input feature map data using multiple basic dimensions and several extended dimensions as parallel dimensions to generate output feature map data, wherein the extended dimensions are at least a part of the basic dimensions.

[0055] This embodiment introduces a dynamic parallel mechanism of basic dimensions plus extended dimensions, with the extended dimensions being at least a part of the basic dimensions. This allows the parallel dimensions to be flexibly adjusted according to model parameters to adapt to the needs of different models. Therefore, this embodiment uses multiple basic dimensions and several extended dimensions as parallel dimensions to perform convolution operations on the input feature map data of the convolutional neural network model, thereby generating output feature map data. In this way, by adjusting the combination of basic and extended dimensions, a precise match between the parallel architecture and model requirements can be achieved, solving the problem of insufficient adaptability caused by fixed architectures. This significantly reduces idle computing power, thereby improving the effective computing power of AI chips.

[0056] As can be seen, this application addresses the issue that a fixed-parallelism hardware architecture cannot adapt to all models. Therefore, it introduces a dynamic parallel mechanism consisting of a base dimension and extended dimensions, with the extended dimensions being at least a portion of the base dimensions. This allows the parallel dimensions to be flexibly adjusted based on model parameters to suit the needs of different models. Specifically, when processing a convolutional neural network model, this application uses multiple base dimensions and several extended dimensions as parallel dimensions to perform convolution operations on the input feature map data, thereby generating output feature map data. In this way, by adjusting the combination of base and extended dimensions, a precise match between the parallel architecture and model requirements can be achieved, solving the adaptability problem caused by a fixed architecture. This significantly reduces idle computing power, thereby improving the effective computing power of AI chips.

[0057] Based on the foregoing embodiments, the step of performing convolution operations on the input feature map data using multiple basic dimensions and several extended dimensions as parallel dimensions includes: using the input feature map data as the input data of the current convolutional layer, and performing convolution calculations according to the parallel dimensions configured for the current convolutional layer to obtain the output data of the current convolutional layer; using the output data of the current convolutional layer as the input data of the next convolutional layer, and continuing to perform convolution calculations according to the parallel dimensions configured for the next convolutional layer, until the calculations of all convolutional layers in the convolutional neural network model are completed.

[0058] It is understandable that convolutional neural network models typically consist of multiple convolutional layers, and the structure of each convolutional layer may differ, as do the corresponding computational requirements. Therefore, each convolutional layer can be independently configured with a corresponding parallel dimension, where the parallel dimension corresponds to the number of multiply-accumulators (MACs).

[0059] In a specific implementation, each convolutional layer needs to extract and transform features from the input data sequentially. That is, firstly, the input feature map data is used as the input data of the current convolutional layer, and convolution calculation is performed according to the parallel dimension configured for the current convolutional layer to obtain the output data of the current convolutional layer; then, the output data of the current convolutional layer is used as the input data of the next convolutional layer, and convolution calculation is performed according to the parallel dimension configured for the next convolutional layer, until the calculation of all convolutional layers is completed.

[0060] By configuring parallel dimensions in a hierarchical manner, a separate parallel scheme can be designed for the specific structure of each convolutional layer, avoiding the insufficient adaptability problem caused by the uniform parallel architecture used across the entire network in traditional technologies. For example, if one convolutional layer has a large number of output channels (OC) while another convolutional layer has a large number of input channels (IC), by configuring different combinations of parallel dimensions for different convolutional layers, the computational power requirements of each layer can be met respectively, ensuring that the MAC utilization rate of each layer can be maintained at a high level.

[0061] Furthermore, based on the foregoing embodiments, this application also discloses a scheme for configuring parallel dimensions separately for the specific structure of each convolutional layer. The parallel dimension configuration scheme for each convolutional layer includes: obtaining multiple structural parameters corresponding to each convolutional layer and initial parameter values ​​corresponding to each of the multiple structural parameters; determining the basic dimension corresponding to each convolutional layer from the multiple structural parameters corresponding to each convolutional layer based on the initial parameter values ​​corresponding to each of the multiple structural parameters; comparing the initial parameter values ​​under the basic dimension corresponding to each convolutional layer with the target parallelism, and determining the extended dimension corresponding to each convolutional layer based on the comparison results.

[0062] In this embodiment, to configure the parallel dimensions of each convolutional layer, it is necessary to obtain various structural parameters corresponding to each convolutional layer, as well as their initial parameter values. Among these, the structural parameters are the core factors determining the computational power requirements of the convolutional layer. Different convolutional layers have different structural parameters, and their initial parameter values ​​directly reflect the computational power requirements of that layer in each dimension.

[0063] Next, based on the initial parameter values ​​corresponding to various structural parameters, the basic dimensions for each convolutional layer are determined from the various structural parameters corresponding to each convolutional layer. It should be noted that the selection of the basic dimensions is based on the magnitude of the initial parameter values ​​of each structural parameter. Dimensions that can meet the basic computing power requirements of the layer and whose parameter values ​​are relatively stable can be prioritized as the basic dimensions to provide a stable infrastructure for subsequent parallel computing. Alternatively, all structural parameters can be directly determined as the basic dimensions corresponding to each convolutional layer.

[0064] Finally, the initial parameter values ​​for the base dimension of each convolutional layer are compared with the target parallelism, and the extended dimension for each convolutional layer is determined based on the comparison results. The target parallelism is a pre-set intrinsic parallelism corresponding to the base dimension, meaning the hardware pre-sets the parallelism in that dimension, representing the number of parallel MAC units (e.g., 16). By comparing this with the initial parameter values ​​of the base dimension, it is determined whether to supplement the parallelism by adding an extended dimension to fully utilize hardware resources.

[0065] For example, when the initial parameter value of the basic dimension is greater than the target parallelism, it means that the computing power requirement of that dimension exceeds the carrying capacity of the basic parallel architecture. It is necessary to configure part of it as an extended dimension, split the computing power requirement, and avoid resource waste caused by excessive parallelism in a single dimension.

[0066] It should be noted that the structural parameters include the width and height of the input feature map, the number of input channels, and the number of output channels; the basic dimensions are set based on any three of the following parameters: width, height, number of input channels, and number of output channels. In other words, the structural parameters can be divided into two main categories: spatial dimension parameters, namely the width and height of the input feature map; and channel dimension parameters, namely the number of input channels and the number of output channels.

[0067] It should also be noted that, for different convolutional layers, this application can determine the basic dimensions corresponding to each convolutional layer from the width, height, number of input channels, and number of output channels according to preset rules or strategies. In one specific implementation, the selection can be based on prior knowledge of the model type or layer type. For example, for standard convolutional layers, (W, IC, OC) is preferentially selected as the basic dimension; for channel-wise convolutional layers of depthwise separable convolution, since IC=1, (W, H, OC) can be preferentially selected as the basic dimension to fully utilize spatial parallelism.

[0068] In another specific implementation, the three dimensions with the larger initial parameter values ​​in the current convolutional layer can be selected as the base dimensions to maximize the data throughput of a single computation. Furthermore, it can be determined whether spatial dimension information or channel dimension information is denser, thereby selecting whether to prioritize W and H dimensions or OC and IC dimensions. Specifically, the first product between the initial parameter values ​​corresponding to the width and height (i.e., W×H) can be compared with the second product between the initial parameter values ​​corresponding to the number of input channels and the number of output channels (i.e., IC×OC). If W×H > IC×OC, then either IC or OC, along with W and H, is used as the base dimensions; otherwise, either W or H, along with IC and OC, is used as the base dimensions.

[0069] In a specific implementation, determining the extended dimension corresponding to each of the convolutional layers based on the comparison results includes: if the initial parameter value of any basic dimension corresponding to any convolutional layer is greater than the target parallelism, then the basic dimension with the initial parameter value greater than the target parallelism is set as the extended dimension. That is, this application can compare the initial parameter value of each basic dimension with the target parallelism preset by the hardware for that dimension. If the initial parameter value of any basic dimension corresponding to any convolutional layer is greater than the target parallelism, it indicates that the computational requirement of that basic dimension exceeds the inherent capabilities of the hardware; therefore, this application can mark that basic dimension as an extended dimension.

[0070] Furthermore, if the initial parameter value of any basic dimension is significantly less than the target parallelism (e.g., less than 50%), this embodiment can also trigger a resource downsizing decision. The decision may include: reducing the actual hardware parallelism enabled for that basic dimension to reduce power consumption, and after meeting the expansion needs of other dimensions, reconfiguring the idle expansion dimensions to other dimensions that are not over-limited but are larger in scale, in order to further optimize the overall computational shape and reduce the number of computation rounds.

[0071] Furthermore, the final parameter value of the extended dimension is configured as a / b, where a is the initial parameter value under the base dimension set as the extended dimension, and b is the target parallelism.

[0072] For example, assuming the chosen basic dimensions are W, IC, and OC, and each basic dimension has an inherent target parallelism of 16, then the basic parallelism pattern is 16W parallelism × 16IC parallelism × 16OC parallelism. If the initial parameter values ​​for a certain basic dimension are W=32, IC=16, and OC=16, since the initial parameter value for W is greater than the target parallelism of 16, W is set as an extended dimension. The final parameter value of this extended dimension is 32 / 16=2, meaning the final parallelism pattern is 16W parallelism × 16IC parallelism × 16OC parallelism × 2W parallelism.

[0073] Accordingly, assuming that the initial parameter values ​​of the structural parameters corresponding to a certain basic dimension are W=16, IC=32, and OC=16 respectively, since the initial parameter value corresponding to IC is greater than the target parallelism of 16, IC is set as an extended dimension. The final parameter value of this extended dimension is 32 / 16=2, that is, the final parallel mode is 16W parallelism × 16IC parallelism × 16OC parallelism × 2IC parallelism.

[0074] Correspondingly, the configuration of the final parameter values ​​for the basic dimensions described above is divided into two types. In one specific implementation, the method further includes:

[0075] The final parameter value of the base dimension n1 when the initial parameter value is less than or equal to the target parallelism is configured as c, where c is the initial parameter value of the base dimension n1.

[0076] When the initial parameter value is greater than the target parallelism, the final parameter value of the base dimension n2 is configured as b, where b is the target parallelism.

[0077] Specifically, assuming the basic parallelism pattern is 16W parallelism × 16IC parallelism × 16OC parallelism, if a certain dimension is set as the basic dimension and its initial parameter value is equal to or less than the target parallelism, then that initial parameter value is directly used as the final parameter value, i.e., the final parallelism. For example, if IC = 16 and the target parallelism (corresponding to IC) is 16, then the final parameter value of the IC dimension is 16. If IC = 32 and the target parallelism (corresponding to IC) is 16, then the final parameter value of the IC dimension as a basic dimension is 16, i.e., the target parallelism; and the final parameter value as an extended dimension is 32 / 16 = 2.

[0078] Furthermore, in supporting resource downsizing decisions, in some optional embodiments, if the initial parameter value of a certain basic dimension is significantly less than the target parallelism, the target parallelism of that basic dimension is reduced, and its initial parameter value is configured as the final parameter value, i.e., the final parallelism. For example, if IC=8 and the target parallelism corresponding to IC is 16, then the final parallelism or final parameter value of the IC dimension is 8, thereby reducing the actual hardware-enabled parallelism of that basic dimension to reduce power consumption.

[0079] In another specific embodiment, the method further includes configuring the final parameter value of the basic dimension as d, where d is the target parallelism. It is understood that the target parallelism corresponding to the basic dimension in this application can be an unchangeable fixed value, i.e., the inherent number of parallel computing units in that dimension. Therefore, when the initial parameter value of the basic dimension of a convolutional layer is lower than the target parallelism, the excess parallel MAC units still belong to that basic dimension, but will be computed idly.

[0080] Furthermore, this embodiment does not limit the value of the fixed parallelism, nor does it limit the number of extended dimensions; it can be one or more. The fixed parallelism can be 4, 8, 16, 32, etc., and the target parallelism corresponding to each basic dimension can be the same or different.

[0081] For example, in a specific example, assuming the target parallelism for the three basic dimensions (W, IC, OC) is 16, the computing power is 16 TOPS, and the chip operating frequency is 1 GHz, then the maximum scalable dimension is one. Let's assume the added dimension is X, making the hardware parallel in four dimensions, as follows: 16W parallelism × 16IC parallelism × 16OC parallelism × 2X parallelism = 8192 MACs, computing power = 8192 × 1 GHz × 2 = 16 TOPS. The fourth dimension X is determined by the compiler based on the actual network structure parameters of the model. The following is an example of X configuration:

[0082] 1. When the convolutional layer has W=32, IC=16, and OC=16, X is configured as W, i.e., 16W parallelism × 16IC parallelism × 16OC parallelism × 2W parallelism.

[0083] 2. When the convolutional layer has W=16, IC=32, and OC=16, X is configured as IC, which means 16W parallelism × 16IC parallelism × 16OC parallelism × 2IC parallelism.

[0084] 3. When the convolutional layer has W=16, IC=16, and OC=32, X is configured as OC, which means 16W parallelism × 16IC parallelism × 16OC parallelism × 2OC parallelism.

[0085] In this way, the fourth dimension can be flexibly selected and configured according to the scenario, so that MAC utilization can reach 100% in most scenarios, and the effective computing power is significantly improved.

[0086] In addition, in some special cases, assuming the basic parallel mode is 16W parallel × 16IC parallel × 16OC parallel, if W=8, IC=16, OC=32 for a certain convolutional layer, X is configured as OC, that is, 16W parallel × 16IC parallel × 16OC parallel × 2OC parallel, but there are actually 8 MAC calculations idle in the W dimension.

[0087] In another example, we can assume that the target parallelism of the three basic dimensions (W, IC, OC) is 8, the computing power is 16 TOPS, the chip operating frequency is 1 GHz, and the added extended dimensions are X, Y, and Z, so that the hardware can be parallelized in six dimensions, i.e., 8W parallel × 8IC parallel × 8OC parallel × mX parallel × nY parallel × qZ parallel, where m × n × q = 16 must be guaranteed.

[0088] When W=32, IC=16, and OC=16 for a certain convolutional layer, the initial parameter values ​​for each basic dimension are greater than the target parallelism of 8. Therefore, it is necessary to expand each basic dimension. Specifically, the expanded dimension X can be configured as W, where m=32 / 8=4; the expanded dimension Y can be configured as IC, where n=16 / 8=2; and the expanded dimension Z can be configured as OC, where q=16 / 8=2. Finally, we get 8W parallelism × 8IC parallelism × 8OC parallelism × 4W parallelism × 2IC parallelism × 2OC parallelism.

[0089] See Figure 3 As shown in the figure, this application discloses a data processing device for an AI chip, the device comprising:

[0090] Data acquisition module 11 is used to acquire input feature map data of the convolutional neural network model;

[0091] The convolution processing module 12 is used to perform convolution operations on the input feature map data with multiple basic dimensions and several extended dimensions as parallel dimensions to generate output feature map data, wherein the extended dimensions are at least a part of the basic dimensions.

[0092] As can be seen, this application addresses the issue that a fixed-parallelism hardware architecture cannot adapt to all models. Therefore, it introduces a dynamic parallel mechanism consisting of a base dimension and extended dimensions, with the extended dimensions being at least a portion of the base dimensions. This allows the parallel dimensions to be flexibly adjusted based on model parameters to suit the needs of different models. Specifically, when processing a convolutional neural network model, this application uses multiple base dimensions and several extended dimensions as parallel dimensions to perform convolution operations on the input feature map data, thereby generating output feature map data. In this way, by adjusting the combination of base and extended dimensions, a precise match between the parallel architecture and model requirements can be achieved, solving the adaptability problem caused by a fixed architecture. This significantly reduces idle computing power, thereby improving the effective computing power of AI chips.

[0093] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the data processing method of the AI ​​chip executed by the electronic device disclosed in any of the foregoing embodiments.

[0094] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0095] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0096] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored on it include operating system 221, computer program 222 and data 223, etc., and the storage method can be temporary storage or permanent storage.

[0097] The operating system 221 manages and controls the various hardware devices and computer programs 222 on the electronic device 20 to enable the processor 21 to perform calculations and processing on the massive amounts of data 223 in the memory 22. The operating system 221 can be Windows, Unix, Linux, etc. The computer program 222, in addition to including a computer program capable of performing the data processing method of the AI ​​chip executed by the electronic device 20 as disclosed in any of the foregoing embodiments, may further include computer programs capable of performing other specific tasks. The data 223 may include data received by the electronic device from external devices, as well as data collected by its own input / output interface 25.

[0098] Furthermore, this application also discloses a computer-readable storage medium storing a computer program. When the computer program is loaded and executed by a processor, it implements the data processing method steps of the AI ​​chip disclosed in any of the foregoing embodiments.

[0099] Furthermore, this application also discloses a computer program product, which, when loaded and executed by a processor, implements the data processing method steps of the AI ​​chip disclosed in any of the foregoing embodiments.

[0100] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0101] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0102] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.

[0103] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0104] The above provides a detailed description of the data processing method, apparatus, device, and medium for an AI chip provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only intended to help understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A data processing method for an AI chip, characterized in that, include: Obtain the input feature map data of the convolutional neural network model; The input feature map data is subjected to a convolution operation with multiple basic dimensions and several extended dimensions as parallel dimensions to generate output feature map data, wherein the extended dimensions are at least a part of the basic dimensions.

2. The method according to claim 1, characterized in that, The convolution operation performed on the input feature map data using multiple basic dimensions and several extended dimensions as parallel dimensions includes: The input feature map data is used as the input data of the current convolutional layer, and convolution calculation is performed according to the parallel dimension configured for the current convolutional layer to obtain the output data of the current convolutional layer. The output data of the current convolutional layer is used as the input data of the next convolutional layer, and the convolution calculation continues to be performed according to the parallel dimension configured for the next convolutional layer, until the calculation of all convolutional layers in the convolutional neural network model is completed.

3. The method according to claim 2, characterized in that, The parallel dimension configuration schemes for each convolutional layer include: Obtain the various structural parameters corresponding to each convolutional layer and the initial parameter values ​​corresponding to each of the various structural parameters; Based on the initial parameter values ​​corresponding to the various structural parameters, the basic dimension corresponding to each convolutional layer is determined from the various structural parameters corresponding to each convolutional layer. The initial parameter values ​​of each convolutional layer under the base dimension are compared with the target parallelism, and the extended dimension of each convolutional layer is determined based on the comparison results.

4. The method according to claim 3, characterized in that, The step of determining the expanded dimension corresponding to each of the convolutional layers based on the comparison results includes: If the initial parameter value of any base dimension corresponding to any of the convolutional layers is greater than the target parallelism, then the base dimension with the initial parameter value greater than the target parallelism is set as the extended dimension.

5. The method according to claim 3, characterized in that, The method further includes: The final parameter value of the extended dimension is configured as a / b, where a is the initial parameter value of the base dimension set as the extended dimension, and b is the target parallelism.

6. The method according to claim 3, characterized in that, The method further includes: The final parameter value of the base dimension n1 when the initial parameter value is less than or equal to the target parallelism is configured as c, where c is the initial parameter value of the base dimension n1. When the initial parameter value is greater than the target parallelism, the final parameter value of the base dimension n2 is configured as b, where b is the target parallelism.

7. The processing method for the convolutional neural network model according to any one of claims 3 to 6, characterized in that, The structural parameters include the width and height of the input feature map, the number of input channels, and the number of output channels; The basic dimension is set based on any three of the following parameters: width, height, number of input channels, and number of output channels.

8. A data processing device for an AI chip, characterized in that, include: The data acquisition module is used to acquire the input feature map data of the convolutional neural network model; A convolution processing module is used to perform convolution operations on the input feature map data with multiple basic dimensions and several extended dimensions as parallel dimensions to generate output feature map data, wherein the extended dimensions are at least a part of the basic dimensions.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the data processing method for an AI chip as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used to store computer programs; wherein, when the computer programs are executed by a processor, they implement the steps of the data processing method of the AI ​​chip as described in any one of claims 1 to 7.

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