Storage unit and device, and computing storage unit and device

Abstract

The embodiment of the invention relates to the technical field of memories, and discloses a memory cell and device, and a computing memory cell and device, the memory cell comprises a first transistor, a gating component, an inverter, a first process control end, a second process control end, a signal input end and a signal output end; according to a signal transmission path or a grounding path of a second process control signal, a first transistor stores a storage signal stored between the phase inverter and the first transistor for a target time length when the first transistor is turned off and the grounding path is turned on. The number of transistors in the storage unit can be reduced, so that the area of a single storage unit is reduced, the area proportion of the SRAM storage array is reduced, and the storage duration of a storage signal is prolonged.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and more specifically to a memory cell, device, equipment, and memory medium. Background Technology

[0002] Currently, the most commonly used SRAM (Static Random-Access Memory) in commercial applications is the 6T-CELL (6 transistors) structure, which consists of two inverters and two selectors, totaling six field-effect transistors in one SRAM structure. In digital in-memory computing circuits, to achieve better data stability and prevent read corruption during multi-line reads, new structures such as 8T-SRAM, 9T-SRAM, and 10T-SRAM have been developed based on the 6T-SRAM, further reducing the integration density of SRAM. In the overall digital in-memory computing architecture, the SRAM array occupies the largest area and plays a crucial role in determining the performance of the circuit system. An excessively large individual SRAM area increases the difficulty of back-end layout and routing, necessitating increased area overhead in the design and significantly reducing the area utilization rate of the in-memory chip. Furthermore, SRAM is a volatile memory cell; it cannot maintain its stored state after power loss, and the signal decays rapidly. Maintaining a normal power supply voltage increases the power consumption of the circuit. Therefore, there is an urgent need for a design scheme for a non-volatile digital memory unit with low area overhead. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention provide a storage unit to solve the technical problems of the large area ratio of SRAM storage arrays and the inability to continue storage after power failure in the prior art.

[0004] According to one aspect of the present invention, a storage cell is provided, including a first transistor, a gating component, an inverter, a first process control terminal, a second process control terminal, a signal input terminal, and a signal output terminal; a first terminal of the first transistor is connected to the signal input terminal, a second terminal of the first transistor is connected to the first terminal of the inverter, and a controlled terminal of the first transistor is connected to the first process control terminal; a first terminal of the gating component is connected to the second terminal of the inverter, a second terminal of the gating component is connected to the signal output terminal, and a controlled terminal of the first transistor is connected to the second process control terminal;

[0005] The first process control terminal is used to acquire the first process control signal;

[0006] The second process control terminal is used to acquire the second process control signal;

[0007] The signal input terminal is used to acquire the stored signal;

[0008] The first transistor is used to turn on or off according to the first process control signal, and the leakage current of the first transistor is less than or equal to a first preset current range.

[0009] The gating component is used to connect a signal transmission path or a grounding path according to the second process control signal;

[0010] The inverter is used to invert the input signal when the signal transmission path is turned on;

[0011] The first transistor is further configured to, when the first transistor is turned off and the ground path is on,

[0012] The stored signal stored between the inverter and the first transistor is stored for a target duration, the target duration being determined by the equivalent capacitance of the first transistor and the leakage current.

[0013] In one alternative approach, the first preset current range is 10. -22 -10 -18 A.

[0014] In one alternative embodiment, the gating component includes a second transistor and a third transistor. The first terminal of the second transistor is the first terminal of the gating component. The controlled terminal of the second transistor is connected to the controlled terminal of the third transistor, and their connection node is the controlled terminal of the gating component. The second terminal of the second transistor is connected to the first terminal of the third transistor, and their connection node is the second terminal of the gating component. The second terminal of the third transistor is grounded. The conduction conditions of the second transistor and the third transistor are different.

[0015] In one alternative embodiment, the inverter includes a fourth transistor and a fifth transistor. The first terminal of the fourth transistor is connected to a power supply, and the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor, with the connection node being the second terminal of the inverter. The controlled terminals of the fourth transistor and the fifth transistor are connected, with the connection node being the first terminal of the inverter. The second terminal of the fifth transistor is grounded.

[0016] The fourth transistor has a different conduction condition than the fifth transistor.

[0017] In an alternative embodiment, the storage unit further includes a logic gate disposed between the second end of the gating component and the signal output end, wherein the first end of the logic gate is connected to the storage signal output by the gating component, and the second end of the logic gate is connected to a feature signal;

[0018] The logic gate is used to perform logical operations on the stored signal and the feature signal and then output the result.

[0019] In one alternative approach, when the first process control signal is high and the second process control signal is low, the first transistor is turned on, the grounding path is turned on, and the memory cell is in a write state to write the memory signal.

[0020] When the first process control signal is low and the second process control signal is low, the first transistor is turned off, the grounding path is turned on, and the memory cell is in a holding state to store the written memory signal between the inverter and the first transistor.

[0021] When the first process control signal is low and the second process control signal is high, the first transistor is turned off, the signal transmission path is turned on, and the storage unit is in read state so that the stored signal is output after passing through the inverter.

[0022] In one alternative approach, when the first process control signal is low and the second process control signal is high, the first transistor is turned on, the grounding path is turned on, and the memory cell is in a write state to write the memory signal.

[0023] When the first process control signal is high and the second process control signal is high, the first transistor is turned off, the grounding path is turned on, and the memory cell is in a holding state to store the written memory signal between the inverter and the first transistor.

[0024] When the first process control signal is high and the second process control signal is low, the first transistor is turned off, the signal transmission path is turned on, and the storage unit is in read state so that the stored signal is output after passing through the inverter.

[0025] According to another aspect of the present invention, a computing storage unit is provided, the computing storage unit comprising N first word lines, N second word lines, M first bit lines, and a plurality of storage units as described in any one of claims 1-8; the plurality of storage units form an N*M storage matrix, where N and M are both greater than or equal to 1; the controlled terminal of the first transistor of each storage unit in the Nth row is connected to the Nth first word line, and the controlled terminal of the gating component of each storage unit in the Nth row is connected to the Nth second word line; the first terminal of the first transistor of each storage unit in the Mth column is connected to the Mth first bit line;

[0026] The first word line is used to acquire multiple first process control signals;

[0027] The second word line is used to acquire multiple second process control signals;

[0028] The first bit line is used to transmit multiple storage signals;

[0029] The storage unit is used to perform operations such as storing, maintaining, and outputting the storage signal according to the first process control signal and the second process control signal.

[0030] In an alternative embodiment, the computational storage unit further includes a shift adder, wherein the output of the logic gate of each storage unit is connected to the shift adder;

[0031] The shift adder is used to perform in-memory operations on the storage signal output by each of the storage cells.

[0032] According to another aspect of the present invention, a storage device is provided, the storage device including the storage units described above, wherein a plurality of the storage units constitute the storage device.

[0033] According to another aspect of the present invention, a computing storage device is provided, the computing storage device including the computing storage unit as described above.

[0034] In this embodiment of the invention, a first process control signal is acquired through a first process control terminal, a second process control signal is acquired through a second process control terminal, and a storage signal is acquired through a signal input terminal. The first transistor is turned on or off according to the first process control signal, and the gating component is turned on or off according to the second process control signal. When the first transistor is off and the signal transmission path is on, the inverter inverts and outputs the storage signal stored between the inverter and the first transistor. Thus, by switching the on and off states of the first transistor and switching the two paths of the gating component, different combinations of writing, reading, and saving of the storage signal can be achieved, thereby realizing the storage and reading functions of the storage unit. This application reduces the number of transistors used in a single storage unit, thereby reducing the area of ​​the SRAM array composed of multiple storage units, thus solving the technical problems of the large area ratio of SRAM arrays and the inability to continue storage after power failure in the prior art.

[0035] Furthermore, this application also extends the storage time of the stored signal by controlling the magnitude of the leakage current of the first transistor to make the leakage current value as small as possible, thereby achieving the effect of non-volatile storage.

[0036] The above description is merely an overview of the technical solutions of the embodiments of the present invention. In order to better understand the technical means of the embodiments of the present invention and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0037] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0038] Figure 1 A schematic diagram of the structure of a first embodiment of the storage unit provided by the present invention is shown;

[0039] Figure 2 A schematic diagram of the structure of a second embodiment of the storage unit provided by the present invention is shown;

[0040] Figure 3 A schematic diagram of the structure of the computing storage unit provided by the present invention is shown;

[0041] Figure 4 This diagram illustrates the voltage changes at each endpoint during the write and read operations of the memory cell provided by the present invention.

[0042] Figure 5 A schematic diagram of the equivalent circuit of the first transistor of the memory cell provided by the present invention is shown.

[0043] Figure 6 This diagram illustrates a comparison of the data retention time of the first transistor in the memory cell provided by the present invention when using the IGZO process and when using the CMOS process. Detailed Implementation

[0044] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0045] The following section analyzes existing memory structure schemes in conjunction with relevant technologies.

[0046] Traditional von Neumann architecture, with its separate storage and compute units, relies on a bus for data and instruction transmission, severely limiting system speed and resulting in significant energy consumption due to frequent data interactions. In-memory computing, by integrating storage and compute units, allows data to be processed directly in memory, drastically reducing data movement, lowering energy consumption, and improving system efficiency. In-memory computing circuits show promising application prospects in energy-efficient AI processors, smart homes, and smart cities, and warrant further exploration.

[0047] Currently, there are several solutions for implementing in-memory computing cores. First, there are analog in-memory computing circuits, where analog in-memory devices, due to their multi-level conductance states, can be used for analog calculations. Second, there are digital in-memory computing circuits composed of 1-bit in-memory devices. In this approach, one in-memory device stores one bit of data; that is, an 8-bit wide data value requires 8 in-memory devices, each representing one bit of the 8-bit number. Due to the advantages of Static Random Access Memory (SRAM)—high stability, high read / write efficiency, and highly mature process technology—SRAM is often used as the in-memory computing unit in digital in-memory computing circuits. SRAM has two storage states, "1" and "0." In-memory computing technology based on SRAM controls the SRAM storage state by adjusting the word line and bit line voltages, thereby achieving input weight operations. Logic gates such as NAND and XNOR are used to calculate the input and stored weights, and the final output is passed through a shift adder to obtain the result of the neural network calculation.

[0048] Existing SRAMs are generally new structures such as 6T-CELL (6 transistors), 8T-SRAM, 9T-SRAM and 10T-SRAM, which occupy a large area and increase the difficulty of back-end layout and routing.

[0049] When arranging the aforementioned SRAM in a storage array, it can result in a large area occupied by the SRAM storage array and the inability to continue storing data after a power outage.

[0050] This application provides a storage cell that can reduce the area of ​​an SRAM storage array by reducing the number of transistors, thereby reducing the area of ​​an SRAM storage array composed of multiple storage cells, thus solving the technical problems of the large area ratio of SRAM storage arrays and the inability to continue storing data after power failure in the prior art.

[0051] Figure 1 A structural diagram of a first embodiment of the storage unit of the present invention is shown, as follows: Figure 1As shown, the storage unit includes a first transistor NM1, a gating component 20, an inverter 10, a first process control terminal, a second process control terminal, a signal input terminal, and a signal output terminal Vin. The first terminal of the first transistor NM1 is connected to the signal input terminal, the second terminal of the first transistor NM1 is connected to the first terminal of the inverter 10, and the controlled terminal of the first transistor NM1 is connected to the first process control terminal. The first terminal of the gating component 20 is connected to the first terminal of the inverter 10, the second terminal of the gating component 20 is connected to the signal output terminal Vin, and the controlled terminal of the first transistor NM1 is connected to the second process control terminal.

[0052] In this configuration, a first process control terminal acquires a first process control signal, a second process control terminal acquires a second process control signal, and a signal input terminal acquires a stored signal. A first transistor NM1 is turned on or off according to the first process control signal, and a gating component 20 is turned on or off according to the second process control signal. When the signal transmission path or ground path is turned off and the gating component 20 is turned on, the inverter 10 outputs the stored signal inverted. The first transistor NM1 is also used to retain the stored signal between the inverter 10 and the first transistor NM1 for a target duration when the first transistor NM1 is turned off and the ground path is turned on. The target duration is determined by the equivalent capacitance of the first transistor and the leakage current.

[0053] The above-mentioned functions of writing, reading, and saving storage signals can be achieved by switching the first transistor NM1 and the gating component 20 on and off, respectively. This realizes the storage and reading functions of the storage cell, thereby reducing the number of transistors in a single storage cell. Furthermore, by reducing the number of transistors, the area of ​​the SRAM storage array is reduced, which in turn reduces the area of ​​the SRAM storage array composed of multiple storage cells. In addition, by controlling the leakage current range of the first transistor NM1, the leakage current of the first transistor is made to be less than or equal to a first preset current range, thereby greatly extending the storage time of the storage signal. This solves the technical problems of the large area ratio of the SRAM storage array and the inability to continue storing after power failure in the prior art.

[0054] In one alternative approach, the first preset current range is 10. -22 -10 -18 A.

[0055] In the above embodiments, the equivalent circuit diagram of the leakage current when the first transistor NM1, i.e., the write transistor, is turned off is as follows: Figure 5 As shown, even when the transistor is turned off, some current will still flow out through the transistor via the equivalent capacitance of the stored charge, but the first preset current range based on the first transistor NM1 is 10.-22 -10 -18 A can control the leakage current within a very small range. When the equivalent capacitance is in the range of 1af to 10uf, the storage time of the memory cell based on this write transistor can reach 10 to 10^6 seconds. 7 This achieves the effect of non-volatile storage.

[0056] Optionally, the first transistor NM1 is fabricated using the IGZO process.

[0057] Among them, IGZO process is indium gallium zinc oxide process. Figure 6 This comparison examines the hold time of a 1-bit memory cell between CMOS and IGZO processes when the equivalent capacitance is 100af. Therefore, this approach eliminates the need to continuously keep the power supply on, further reducing power consumption.

[0058] The above solution can be implemented in various ways. The following are two examples illustrating its process:

[0059] In one alternative approach, when the first process control signal is high and the second process control signal is low, the first transistor NM1 is turned on, the ground path is turned on, and the memory cell is in a write state to write the memory signal.

[0060] When the first process control signal is low and the second process control signal is low, the memory cell is in a holding state, the first transistor NM1 is turned off, and the grounding path is turned on, so as to store the written memory signal between the inverter 10 and the first transistor NM1.

[0061] When the first process control signal is low and the second process control signal is high, the storage unit is in read mode, so that the stored signal is output after passing through inverter 10.

[0062] The above scheme enables the complete writing, reading, and saving of storage signals, ensuring the functionality of the entire storage unit.

[0063] In one alternative approach, when the first process control signal is low and the second process control signal is high, the first transistor NM1 is turned on, the grounding path is turned on, and the memory cell is in a write state to write the memory signal.

[0064] When the first process control signal is high and the second process control signal is high, the first transistor NM1 is turned off, the grounding path is turned on, and the memory cell is in a holding state so that the written memory signal is stored between the inverter 10 and the first transistor NM1.

[0065] When the first process control signal is high and the second process control signal is low, the first transistor NM1 is turned off, the signal transmission path is turned on, and the storage unit is in the read state so that the stored signal is output after passing through the inverter 10.

[0066] It should be noted that when the grounding path is on, the output of the signal output terminal Vin is always 0, which reduces the static power consumption of subsequent circuits, such as logic gates. When the signal transmission path is opened as a selection path, the voltage selection loss can be reduced, so that the output high voltage is as close as possible to 1.8V, which also reduces the static power consumption of subsequent circuits, such as logic gates. The power consumption of the quasi-nonvolatile memory cell with a 4-transistor structure at a frequency of 50MHz is compared with that of the quasi-nonvolatile memory cell. Table 1 shows the comparison of the power consumption of the quasi-nonvolatile memory cell with a 4-transistor structure.

[0067]

[0068] Table 1

[0069] Specifically, refer to Figure 4 As shown, Figure 4 In the middle, the horizontal lines from top to bottom are, in order: the first line Vwg, the first character line Vwd, the second line Vsl, and Vsn. ～ Vsn, Vin, Vout. The left side shows the voltage changes at each endpoint and on the transmission line when writing 0, and the right side shows the voltage changes when reading out and when a calculation module is connected to the back for calculation.

[0070] In one alternative embodiment, the gating component 20 includes a second transistor PM1 and a third transistor NM2. The first terminal of the second transistor PM1 is the first terminal of the gating component 20. The controlled terminal of the second transistor PM1 is connected to the controlled terminal of the third transistor NM2, and their connection node is the controlled terminal of the gating component 20. The second terminal of the second transistor PM1 is connected to the first terminal of the third transistor NM2, and their connection node is the second terminal of the gating component 20. The second terminal of the third transistor NM2 is grounded. The conduction conditions of the second transistor PM1 and the third transistor NM2 are different.

[0071] At this time, the two conduction conditions are different. The two can be controlled to conduct at different times by switching the voltage, thereby realizing the switching of the signal transmission path and the grounding path. That is, when the second transistor PM1 is turned on, the signal transmission path from the second terminal of the inverter 10 to the signal output terminal Vin through the second transistor PM1 is turned on. When the third transistor NM2 is turned on, the signal output terminal Vin is directly connected to the ground through the third transistor NM2, that is, the grounding path is turned on.

[0072] In one alternative configuration, one of the second transistor PM1 and the third transistor NM2 is an NMOS transistor, and the other is a PMOS transistor.

[0073] By controlling the different types of the second transistor PM1 and the third transistor NM2, the conduction conditions of the second transistor PM1 and the third transistor NM2 can be controlled to be different.

[0074] In one alternative approach, refer to Figure 1 as well as Figure 2 As shown, inverter 10 includes a fourth transistor and a fifth transistor. The first terminal of the fourth transistor is connected to a power supply, and the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor. The connection node is the second terminal of inverter 10. The controlled terminals of the fourth transistor and the fifth transistor are connected, and the connection node is the first terminal of inverter 10. The second terminal of the fifth transistor is grounded.

[0075] Furthermore, the memory cell with five transistors proposed in this application reduces the number of field-effect transistors used in a single memory cell by nearly 37.5% compared to the 8T-SRAM structure currently widely used in digital in-memory computing circuits. This reduces the difficulty of layout and routing in the back-end layout design, not only reducing the area required for a single memory cell and greatly improving the area utilization of the in-memory computing chip, but also significantly reducing the overall area overhead of the in-memory computing cell when the array size of the in-memory computing cell reaches a certain level. This is more conducive to its application in AI in-memory computing chips that deploy large-scale neural networks.

[0076] In one alternative configuration, one of the fourth and fifth transistors is an NMOS transistor and the other is a PMOS transistor.

[0077] The above structure constitutes an inverter, which can invert the signal input to the first terminal of the inverter 10 and output it. In addition, since the input of the storage signal at this time causes the signal inside the inverter to change, the data storage is realized.

[0078] In one alternative embodiment, both the first transistor NM1 and the third transistor NM2 are NMOS transistors.

[0079] The above scheme reduces the number of PMOS transistors. Since the area of ​​a PMOS transistor is larger than that of an NMOS transistor, the overall area of ​​the memory cell can be further reduced. In addition, the carrier mobility of a PMOS transistor is lower than that of an NMOS transistor because NMOS carriers are electrons while PMOS carriers are positively charged. Using more NMOS transistors can improve the switching speed.

[0080] In one alternative configuration, the second transistor PM1 is a PMOS transistor.

[0081] Using a PMOS transistor in this scheme saves power compared to using an NMOS transistor. Specifically, when the second transistor PM1 is an NMOS transistor and the third transistor NM2 is a PMOS transistor, when the logic of the second transistor PM1 is read as off (i.e., the second bit line Vsl = 0V), the output Vin of the module is always equal to the on-state voltage of the third transistor NM2, which is 1.8V. The power consumption is higher than the original scheme. When the logic of the second transistor PM1 is a PMOS transistor and read as off, the output is always 0V.

[0082] In one alternative approach, refer to Figure 2 As shown, the storage unit also includes a logic gate, which is located between the second end of the gating component 20 and the signal output terminal Vin. The first end of the logic gate is connected to the storage signal output by the gating component 20, and the second end of the logic gate is connected to the feature signal.

[0083] The logic gates perform logical operations on the stored signals and feature signals before outputting the results.

[0084] In one alternative approach, the logic gate is a NOR gate.

[0085] Let the stored signal be A and the characteristic signal be B. Then the OR NOT operation performs the following operation:

[0086]

[0087] The following combination Figures 1-3 The specific circuit described herein illustrates the working principle of this application:

[0088] For a 1:1 weighted write operation, during the write operation, the first bit line Vwg remains high (1.8V input), and the first transistor NM1 is turned on; the second bit line Vsl remains high (1.8V input), the second transistor PM1 is turned off, and the third transistor NM2 is turned on. At this time, when the write weight is "1", the first word line Vwd remains high (1.8V input); when the write weight is "0", the first word line Vwd remains low (0V input).

[0089] 2: When performing a 1-bit weight hold operation, during the data hold / store operation, the first bit line Vwg and the first word line Vwd remain low / low level with an input of 0V. The first transistor NM1 is turned off, and the charge stored on Vsn cannot leak from the first transistor NM1, so the storage state remains stable. The second bit line Vsl remains high / high level with an input of 1.8V. The second transistor PM1 is turned off, and the third transistor NM2 is turned on, so the stored voltage of Vsn cannot be read out.

[0090] 3: Perform a 1-bit weighted read operation using a 5T-CELL memory cell. During the read operation, the first bit line Vwg and the first word line Vwd remain low with an input of 0V. The first transistor NM1 is turned off, and the charge stored on Vsn cannot leak from the first transistor NM1, keeping the storage state stable. The second bit line Vsl remains low with an input of 0V. The second transistor PM1 is turned on, and the third transistor NM2 is turned off. The stored voltage on the Vsn line is read out through inverter 10.

[0091] 4: Perform a 1-bit weight multiplication operation with the feature value / feature signal. Connect the output of the 5T-CELL to a NOR gate. During the read operation, the external feature signal is inverted at input to obtain ~Feature. Then, control the input of "0" or "1" to the ~feature (feature value) terminal of the NOR gate to perform a NOR operation with the read 5T-CELL weight value, and finally obtain the multiplication result of A*B.

[0092] The operation is shown in equation (1) below:

[0093]

[0094] The above scheme significantly improves the area utilization of the memory chip by using fewer field-effect transistors per memory cell. Furthermore, the 5T-CELL exhibits quasi-non-volatile characteristics, eliminating the need to keep the power supply voltage constantly on, further reducing power consumption. Compared to a quasi-non-volatile memory cell design with a 4-transistor structure, the selection transistors consist of parallel NMOS and PMOS transistors. When the PMOS transistor is off, the NMOS transistor is on and grounded, resulting in a constant output of 0, reducing the static power consumption of the logic gates. Conversely, when the PMOS transistor is on, it reduces voltage selection losses, allowing the output voltage to be as close to 1.8V as possible, further reducing the static power consumption of the logic gates.

[0095] This invention provides a storage device, which includes the storage unit described above.

[0096] It should be noted that since the storage device includes all embodiments of the storage unit, the storage device also has all the beneficial effects of the storage unit, which will not be elaborated here.

[0097] This invention also provides a computing storage unit, see reference. Figure 3As shown, the computational storage unit includes N first word lines Vwg, N second word lines Vsl, M first bit lines Vwd, and multiple storage units as described above; the multiple storage units form an N*M storage matrix, where N and M are both greater than or equal to 1; the controlled terminal of the first transistor NM1 of each storage unit in the Nth row is connected to the Nth first word line Vwg, and the controlled terminal of the gating component 20 of each storage unit in the Nth row is connected to the Nth second word line Vsl; the first terminal of the first transistor NM1 of each storage unit in the Mth column is connected to the Mth first bit line Vwd.

[0098] The first word line Vwg acquires multiple first process control signals, the second word line Vsl acquires multiple second process control signals, and the first bit line Vwd transmits storage signals. The storage unit performs operations such as storing, holding, and outputting storage signals based on the first and second process control signals.

[0099] A single memory cell can be located using the first word line Vwg, the second word line Vsl, and the first bit line Vwd. The first word line Vwg and the second word line Vsl can be used to perform operations such as storing, holding, and outputting on the located memory cell, thereby enabling fast and efficient storage of an N*M memory matrix composed of multiple memory cells.

[0100] It should be noted that since the computing storage unit includes all embodiments of the storage unit, the computing storage unit also has all the beneficial effects of the storage unit, which will not be repeated here.

[0101] In one alternative approach, refer to Figure 3 As shown, it also includes a shift adder 40, and the output of the logic gate of the storage cell is connected to the shift adder 40.

[0102] The result of the logic gate operation is output to the shift adder 40, ultimately realizing multi-bit in-memory operation.

[0103] This invention provides a computing storage device, which includes the computing storage unit described above.

[0104] It should be noted that since the computing storage device includes all embodiments of the computing storage unit, the computing storage device also has all the beneficial effects of the computing storage unit, which will not be repeated here.

[0105] The algorithms or displays provided herein are not inherently related to any particular computer, virtual system, or other device. Furthermore, the embodiments of this invention are not directed to any particular programming language.

[0106] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. Similarly, for the sake of brevity and to aid in understanding one or more aspects of the invention, in the description of exemplary embodiments of the invention above, various features of the embodiments are sometimes grouped together in a single embodiment, figure, or description thereof. The claims, which follow the detailed description, are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the invention.

[0107] Those skilled in the art will understand that the modules in the device of the embodiment can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiment can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components, except that at least some of such features and / or processes or units are mutually exclusive.

[0108] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

Claims

1. A storage unit, characterized in that, The storage unit includes a first transistor, a gating component, an inverter, a first process control terminal, a second process control terminal, a signal input terminal, and a signal output terminal; a first terminal of the first transistor is connected to the signal input terminal, a second terminal of the first transistor is connected to the first terminal of the inverter, and a controlled terminal of the first transistor is connected to the first process control terminal; a first terminal of the gating component is connected to the second terminal of the inverter, a second terminal of the gating component is connected to the signal output terminal, and a controlled terminal of the gating component is connected to the second process control terminal; The first process control terminal is used to acquire the first process control signal; The second process control terminal is used to acquire the second process control signal; The signal input terminal is used to acquire the stored signal; The first transistor is used to turn on or off according to the first process control signal, and the leakage current of the first transistor is less than or equal to a first preset current range. The gating component is used to connect a signal transmission path or a grounding path according to the second process control signal; The inverter is used to invert the stored signal stored between the inverter and the first transistor when the first transistor is turned off and the signal transmission path is turned on. The first transistor is further configured to, when the first transistor is turned off and the ground path is on, The stored signal stored between the inverter and the first transistor is stored for a target duration, the target duration being determined by the equivalent capacitance of the first transistor and the leakage current.

2. The storage unit according to claim 1, characterized in that, The first preset current range is 10 -22 -10 - 18 A.

3. The gating component includes a second transistor and a third transistor. The first terminal of the second transistor is the first terminal of the gating component. The controlled terminal of the second transistor is connected to the controlled terminal of the third transistor, and their connection node is the controlled terminal of the gating component. The second terminal of the second transistor is connected to the first terminal of the third transistor, and their connection node is the second terminal of the gating component. The second terminal of the third transistor is grounded. The conduction conditions of the second transistor and the third transistor are different.

4. The storage unit according to claim 1, characterized in that, The storage unit further includes a logic gate, which is disposed between the second end of the gating component and the signal output end. The first end of the logic gate is connected to the storage signal output by the gating component, and the second end of the logic gate is connected to a feature signal. The logic gate is used to perform logical operations on the stored signal and the feature signal and then output the result.

5. The storage unit according to claim 1, characterized in that, When the first process control signal is high and the second process control signal is low, the first transistor is turned on, the grounding path is turned on, and the storage cell is in a write state to write the storage signal. When the first process control signal is low and the second process control signal is low, the first transistor is turned off, the grounding path is turned on, and the memory cell is in a holding state to store the written memory signal between the inverter and the first transistor. When the first process control signal is low and the second process control signal is high, the first transistor is turned off, the signal transmission path is turned on, and the storage unit is in read state so that the stored signal is output after passing through the inverter.

6. The storage unit according to claim 1, characterized in that, When the first process control signal is low and the second process control signal is high, the first transistor is turned on, the grounding path is turned on, and the storage cell is in a write state to write the storage signal. When the first process control signal is high and the second process control signal is high, the first transistor is turned off, the grounding path is turned on, and the memory cell is in a holding state to store the written memory signal between the inverter and the first transistor. When the first process control signal is high and the second process control signal is low, the first transistor is turned off, the signal transmission path is turned on, and the storage unit is in read state so that the stored signal is output after passing through the inverter.

7. A computing storage unit, characterized in that, The computing storage unit includes N first word lines, N second word lines, M first bit lines, and a plurality of storage units as described in any one of claims 1-6; The plurality of memory cells form an N*M memory matrix, where N and M are both greater than or equal to 1; the controlled terminal of the first transistor of each memory cell in the Nth row is connected to the Nth first word line, and the controlled terminal of the gating component of each memory cell in the Nth row is connected to the Nth second word line; the first terminal of the first transistor of each memory cell in the Mth column is connected to the Mth first bit line. The first word line is used to acquire multiple first process control signals; The second word line is used to acquire multiple second process control signals; The first bit line is used to transmit multiple storage signals; The storage unit is used to perform operations such as storing, maintaining, and outputting the storage signal according to the first process control signal and the second process control signal.

8. The computing storage unit according to claim 7, characterized in that, It also includes a shift adder, wherein the output of the logic gate of each memory cell is connected to the shift adder; The shift adder is used to perform in-memory operations on the storage signal output by each of the storage cells.

9. A storage device, characterized in that, For non-volatile storage, the storage device includes a plurality of storage cells as described in any one of claims 1-6, and the plurality of storage cells constitute the storage device.

10. A computing storage device, characterized in that, The computing storage device includes the computing storage unit as described in any one of claims 7-8.

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