A CMOS ultra-wideband high-gain high-power amplifier

Abstract

This invention provides a CMOS ultra-wideband high-gain high-power amplifier, relating to the field of power amplifier technology. It includes a multi-drive improved Class D amplifier and a multi-stage compact coupled peaking distributed amplifier. The multi-stage compact coupled peaking distributed amplifiers are connected sequentially. The input RF signal is connected to the first-stage compact coupled peaking distributed amplifier via an input line. The output of the Nth-stage compact coupled peaking distributed amplifier is connected to the input of the multi-drive improved Class D amplifier via an output line. The output of the multi-drive improved Class D amplifier outputs the RF signal. The advantage of this invention is that it solves the problems of large area, low gain, and low output power in traditional distributed amplifiers.

Description

Technical Field

[0001] This invention relates to the field of power amplifier technology, and more specifically, to a CMOS ultra-wideband high-gain high-power amplifier. Background Technology

[0002] Power amplifiers, as signal amplification modules in integrated circuits or systems, play a crucial role in signal processing. Wideband amplifiers, in particular, are electronic devices capable of providing stable gain across a wide frequency range. Their application is closely related to the modern society's demand for high-speed, high-frequency, and high-capacity information transmission and processing. In 5G / 6G mobile communications, high frequency bands and large bandwidth are core characteristics, and wideband amplifiers are used in base stations and terminal equipment. They support simultaneous amplification of multiple frequency bands to meet the requirements of high-speed data throughput and low latency. In satellite communications, signals need to cover a wide frequency range from L-band to Ka-band; wideband amplifiers are used in ground stations and satellite payloads to achieve long-distance, high-bandwidth relay. In radar systems, wideband amplifiers can be used to detect, jam, or deceive enemy communication / radar signals, covering a wide frequency band to cope with complex electromagnetic environments.

[0003] Generally, amplifiers can achieve excellent performance in narrowband but poor broadband performance, making them unsuitable for wideband or complex and variable scenarios. The current mainstream ultra-wideband technology architecture is the distributed amplifier (DA), which utilizes transmission line theory to incorporate the capacitance of multiple transistors into an artificial transmission line, thereby achieving extremely wide bandwidth. While DDAs offer the advantages of ultra-wideband performance, they also have significant drawbacks. First, DDAs require a large number of transistors and very long transmission lines, resulting in a huge chip area. Furthermore, most transistors contribute to DC power consumption but do not directly contribute to output power, leading to low efficiency. In CMOS processes, the gain of a single-stage DDA is typically no more than 10dB; higher gain requires multiple cascaded stages, further degrading area, efficiency, and bandwidth. Moreover, due to architectural limitations, DDAs struggle to achieve high power output.

[0004] Therefore, it is necessary to optimize the amplifier structure to solve the problems of large area, low gain and low output power of traditional distributed amplifiers. Summary of the Invention

[0005] The purpose of this invention is to provide a CMOS ultra-wideband high-gain high-power amplifier, which can solve the problems of large area, low gain and low output power of traditional distributed amplifiers.

[0006] This invention is achieved through the following technical solution:

[0007] A CMOS ultrawideband high-gain high-power amplifier includes a multi-drive improved Class D amplifier and a multi-stage compact coupled peaking distributed amplifier;

[0008] Multi-stage compact coupled peaking distributed amplifiers are connected in sequence. The input RF signal is connected to the first stage compact coupled peaking distributed amplifier through the input line. The output terminal of the Nth stage compact coupled peaking distributed amplifier is connected to the input terminal of the multi-drive improved Class D amplifier through the output line. The output terminal of the multi-drive improved Class D amplifier outputs the RF signal.

[0009] The compact coupled peaking distributed amplifier serves as a driver stage and is used to improve bandwidth, while the multi-drive improved Class D amplifier serves as a power output stage and is used to improve the output power of the broadband.

[0010] Preferably, the higher the gain of the CMOS ultra-wideband high-gain high-power amplifier, the higher the value of the number N of the compact coupled peaking distributed amplifier.

[0011] Preferably, the compact coupled peaking distributed amplifier has 2 or 3 stages.

[0012] Preferably, the compact coupled peaking distributed amplifier improves the high-frequency bandwidth by:

[0013] An inductor is connected in series at the drain of the field-effect transistor that serves as a common gate transistor at the output terminal;

[0014] The compact coupled peaking distributed amplifier includes resistors, capacitors, multiple inductors, and multiple field-effect transistors;

[0015] The first end of the first resistor is connected to the second gate power supply, the second end of the first resistor is connected to the first end of the first capacitor and the gate of the second field-effect transistor, the second end of the first capacitor is grounded, the drain of the second field-effect transistor is connected to the first end of the first inductor, the second end of the first inductor is connected to the first end of the second inductor, the source of the second field-effect transistor is connected to the drain of the first field-effect transistor, and the source of the first field-effect transistor is grounded.

[0016] The second terminal of the fourth inductor and the first terminal of the fifth inductor are connected, and their common node is connected to the drain of the first field-effect transistor. The first terminal of the fourth inductor is the first matching input terminal, and the second terminal of the fifth inductor is the first matching output terminal.

[0017] The first end of the third inductor is connected to the second end of the first inductor, the second end of the third inductor is the second matched output terminal, and the first end of the second inductor is the second matched input terminal;

[0018] The first inductor and the second inductor are coupled.

[0019] Preferably, the connection method between the compact coupled peaking distributed amplifiers is as follows:

[0020] The first matched output of the nth stage compact coupled peaking distributed amplifier is connected to the first matched input of the (n+1)th stage compact coupled peaking distributed amplifier, and the second matched output of the nth stage compact coupled peaking distributed amplifier is connected to the second matched input of the (n+1)th stage compact coupled peaking distributed amplifier, where n = 1, 2, ..., N-1;

[0021] The second matching input of the first-stage compact coupled peaking distributed amplifier is grounded via a second resistor and a second capacitor.

[0022] The first matched input terminal of the first stage compact coupled peaking distributed amplifier is connected to the first gate power supply through a third resistor and is also the input terminal of the compact coupled peaking distributed amplifier.

[0023] The second matched output terminal of the Nth stage compact coupled peaking distributed amplifier is connected to the first DC source via the sixth inductor and is the output terminal of the compact coupled peaking distributed amplifier;

[0024] The first matched output of the Nth stage compact coupled peaking distributed amplifier is grounded via the fourth resistor and the tenth capacitor.

[0025] Preferably, the input line uses a capacitor.

[0026] Preferably, the output line uses a single capacitor.

[0027] Preferably, the multi-drive improved Class D amplifier includes a six-layer field-effect transistor unit.

[0028] Preferably, the connection method of the field-effect transistor unit is as follows:

[0029] The i-th layer field-effect transistor unit includes a capacitor and a P-type field-effect transistor, i=1,2,3;

[0030] The j-th layer field-effect transistor unit includes a capacitor and an N-type field-effect transistor, j=4,5,6;

[0031] The first terminals of the capacitors of each layer of the field-effect transistor unit are connected together to form the input terminal of the multi-drive improved Class D amplifier;

[0032] The second terminal of the fourth capacitor is connected to the gate of the first P-type field-effect transistor, and the source of the first P-type field-effect transistor is connected to the second DC source.

[0033] The second terminal of the fifth capacitor is connected to the gate of the second P-type field-effect transistor, and the source of the second P-type field-effect transistor is connected to the drain of the first P-type field-effect transistor.

[0034] The second terminal of the sixth capacitor is connected to the gate of the third P-type field-effect transistor, and the source of the third P-type field-effect transistor is connected to the drain of the second P-type field-effect transistor.

[0035] The second terminal of the seventh capacitor is connected to the gate of the third N-type field-effect transistor, and the drain of the third N-type field-effect transistor is connected to the drain of the third P-type field-effect transistor.

[0036] The second terminal of the eighth capacitor is connected to the gate of the second N-type field-effect transistor, and the drain of the second N-type field-effect transistor is connected to the source of the third N-type field-effect transistor.

[0037] The second terminal of the ninth capacitor is connected to the gate of the first N-type field-effect transistor, the drain of the first N-type field-effect transistor is connected to the source of the second N-type field-effect transistor, and the source of the first N-type field-effect transistor is grounded.

[0038] The common node of the drain of the third P-type field-effect transistor and the drain of the third N-type field-effect transistor serves as the output terminal of the multi-drive improved Class D amplifier.

[0039] The technical solution of the present invention has at least the following advantages and beneficial effects:

[0040] The power amplifier of this invention uses a coupled peaking distributed amplifier as the driver stage and a multi-drive improved Class D amplifier as the power output stage, which can achieve high gain, wide bandwidth performance and high power output in a relatively small area.

[0041] In the design of the coupled-peaking distributed amplifier of this invention, coupled-peaking technology is applied to the distributed amplifier to improve performance without increasing the area;

[0042] The multi-drive improved Class D amplifier design of this invention improves high-frequency power and bandwidth through multi-drive;

[0043] The coupled peaking distributed amplifier and multi-drive improved Class D amplifier designed in this invention improve bandwidth and high-frequency bandwidth performance. Compared with the traditional solution of simply adding the distributed amplifier and the Class D amplifier, the high-frequency performance is better.

[0044] This invention is reasonably designed, has a simple structure, and is easy to promote and implement. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the structure of a CMOS ultra-wideband high-gain high-power amplifier provided in Embodiment 1 of the present invention;

[0046] Figure 2 This is a schematic diagram of the electrical component connections for a CMOS ultra-wideband high-gain high-power amplifier provided in Embodiment 1 of the present invention;

[0047] Figure 3 This is a schematic diagram comparing the bandwidth of a compact coupled peaking distributed amplifier and a conventional distributed amplifier provided in Embodiment 1 of the present invention.

[0048] Figure 4 This is a schematic diagram comparing the gate voltage of the second N-type field-effect transistor and a conventional Class D amplifier provided in Embodiment 1 of the present invention;

[0049] Figure 5 This is a schematic diagram comparing the voltage swing of the second N-type field-effect transistor and the conventional Class D amplifier provided in Embodiment 1 of the present invention;

[0050] Figure 6 This is a schematic diagram comparing the output power of the amplifier with the conventional structure and the structure of the present invention provided in Embodiment 1 of the present invention;

[0051] Figure 7 A schematic diagram comparing the efficiency of the amplifier with the conventional structure and the structure of the present invention provided in Embodiment 1 of the present invention;

[0052] Icons: R1 - First resistor, R2 - Second resistor, R3 - Third resistor, R4 - Fourth resistor, C1 - First capacitor, C2 - Second capacitor, C3 - Third capacitor, C4 - Fourth capacitor, C5 - Fifth capacitor, C6 - Sixth capacitor, C7 - Seventh capacitor, C8 - Eighth capacitor, C9 - Ninth capacitor, C10 - Tenth capacitor, C11 - Eleventh capacitor, L1 - First inductor, L2 - Second inductor, L3 - Third inductor, L4 - Fourth inductor, L5 - Fifth inductor, M1 - First MOSFET, M2 - Second MOSFET, Mp1 - First P-type field-effect transistor, Mp2 - second P-type field-effect transistor, Mp3 - third P-type field-effect transistor, Mn1 - first N-type field-effect transistor, Mn2 - second N-type field-effect transistor, Mn3 - third N-type field-effect transistor, RFIN - input RF signal, RFOUT - output RF signal, Lg - inductance value of the fourth inductor, Lg / 2 - inductance value of the fifth inductor, CL - capacitor connected at the output of the multi-drive improved Class D amplifier, VG1 - first gate power supply, VG2 - second gate power supply, VDD1 - first DC source, VDD2 - second DC source. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0054] Example 1

[0055] This embodiment provides a CMOS ultra-wideband high-gain high-power amplifier. (See reference...) Figure 1 This includes multi-drive improved Class D amplifiers and multi-stage compact coupled peaking distributed amplifiers;

[0056] Multi-stage compact coupled peaking distributed amplifiers are connected in sequence. The input RF signal RFIN is connected to the first stage compact coupled peaking distributed amplifier through the input line. The output of the Nth stage compact coupled peaking distributed amplifier is connected to the input of the multi-drive improved Class D amplifier through the output line. The output of the multi-drive improved Class D amplifier outputs the RF signal RFOUT.

[0057] The compact coupled peaking distributed amplifier serves as a driver stage and is used to improve bandwidth, while the multi-drive improved Class D amplifier serves as a power output stage and is used to improve the output power of the broadband.

[0058] In this embodiment, the higher the gain of the CMOS ultra-wideband high-gain high-power amplifier, the higher the value of the number N of the compact coupled peaking distributed amplifier.

[0059] As a preferred embodiment, the compact coupled peaking distributed amplifier has 2 or 3 stages.

[0060] On CMOS processes with relatively low power density, high-power performance requirements inevitably necessitate the cascading of multiple stages of distributed amplifiers. This leads to further bandwidth degradation and insufficient gain and output power. Based on the design of this embodiment, the RF signal sequentially enters a multi-stage coupled peaking distributed amplifier, and can then be output from the drain of the last stage coupled peaking distributed amplifier before entering a multi-drive improved Class D amplifier for final amplification and output. To address the inherent limitations of prior art in balancing area and power, the compact coupled peaking distributed amplifier and the multi-drive improved Class D amplifier in this embodiment have undergone multiple technical improvements in miniaturization and bandwidth.

[0061] First, the compact coupled peaking distributed amplifier improves the high-frequency bandwidth by means of:

[0062] An inductor is connected in series at the drain of the field-effect transistor that functions as a common-gate transistor at the output.

[0063] For specific implementation methods, please refer to [link / reference]. Figure 2 The compact coupled peaking distributed amplifier includes resistors, capacitors, multiple inductors, and multiple field-effect transistors;

[0064] The first end of the first resistor R1 is connected to the second gate power supply VG2. The second end of the first resistor R1 is connected to the first end of the first capacitor C1 and the gate of the second field-effect transistor M2. The second end of the first capacitor C1 is grounded. The drain of the second field-effect transistor M2 is connected to the first end of the first inductor L1. The second end of the first inductor L1 is connected to the first end of the second inductor L2. The source of the second field-effect transistor M2 is connected to the drain of the first field-effect transistor M1. The source of the first field-effect transistor M1 is grounded.

[0065] The second terminal of the fourth inductor L4 and the first terminal of the fifth inductor L5 are connected, and their common node is connected to the drain of the first field-effect transistor M1. The first terminal of the fourth inductor L4 is the first matching input terminal, and the second terminal of the fifth inductor L5 is the first matching output terminal. The inductance value of the fourth inductor is Lg, and the inductance value of the fifth inductor is Lg / 2.

[0066] The first end of the third inductor L3 is connected to the second end of the first inductor L1. The second end of the third inductor L3 is the second matching output terminal, and the first end of the second inductor L2 is the second matching input terminal.

[0067] The first inductor L1 and the second inductor L2 are coupled together.

[0068] Specifically, the connection method between the compact coupled peaking distributed amplifiers is as follows:

[0069] The first matched output of the nth stage compact coupled peaking distributed amplifier is connected to the first matched input of the (n+1)th stage compact coupled peaking distributed amplifier, and the second matched output of the nth stage compact coupled peaking distributed amplifier is connected to the second matched input of the (n+1)th stage compact coupled peaking distributed amplifier, where n = 1, 2, ..., N-1;

[0070] The second matching input of the first-stage compact coupled peaking distributed amplifier is grounded via the second resistor R2 and the second capacitor C2;

[0071] The first matched input terminal of the first stage compact coupled peaking distributed amplifier is connected to the first gate power supply VG1 through the third resistor R3, and is the input terminal of the compact coupled peaking distributed amplifier;

[0072] The second matched output terminal of the Nth stage compact coupled peaking distributed amplifier is connected to the first DC source VDD1 via the sixth inductor and is the output terminal of the compact coupled peaking distributed amplifier.

[0073] The first matched output of the Nth stage compact coupled peaking distributed amplifier is grounded via the fourth resistor R4 and the tenth capacitor C10.

[0074] Based on the above scheme, the input line uses the third capacitor C3, and the output line uses the eleventh capacitor C11.

[0075] The key to the above compact coupled peaking distributed amplifier lies in the connection between the drain of the second field-effect transistor M2 and the first inductor L1. The first inductor L1 is coupled to the second inductor L2, thereby achieving a bandwidth improvement within a smaller area. The improvement effect can be found in [reference needed]. Figure 3 In the graph, the horizontal axis Freq represents frequency, and the vertical axis represents bandwidth. Figure 3 The red line With_L represents the bandwidth of the compact coupled peaking distributed amplifier in this embodiment, while the black line Without_L represents the bandwidth of a conventional distributed amplifier without an inductor connected in series with the drain of the output MOSFET. It can be seen that the bandwidth at high frequencies is significantly improved, and at the same time, only one inductor is added, which does not cause a significant increase in device area.

[0076] On the other hand, the multi-drive improved Class D amplifier includes a six-layer field-effect transistor unit, and the connection method of the field-effect transistor unit is as follows:

[0077] The i-th layer field-effect transistor unit includes a capacitor and a P-type field-effect transistor, i=1,2,3;

[0078] The j-th layer field-effect transistor unit includes a capacitor and an N-type field-effect transistor, j=4,5,6;

[0079] The first terminals of the capacitors of each layer of the field-effect transistor unit are connected together to form the input terminal of the multi-drive improved Class D amplifier;

[0080] The second terminal of the fourth capacitor C4 is connected to the gate of the first P-type field-effect transistor Mp1, and the source of the first P-type field-effect transistor Mp1 is connected to the second DC source VDD2.

[0081] The second terminal of the fifth capacitor C5 is connected to the gate of the second P-type field-effect transistor Mp2, and the source of the second P-type field-effect transistor Mp2 is connected to the drain of the first P-type field-effect transistor Mp1.

[0082] The second terminal of the sixth capacitor C6 is connected to the gate of the third P-type field-effect transistor Mp3, and the source of the third P-type field-effect transistor Mp3 is connected to the drain of the second P-type field-effect transistor Mp2.

[0083] The second terminal of the seventh capacitor C7 is connected to the gate of the third N-type field-effect transistor Mn3, and the drain of the third N-type field-effect transistor Mn3 is connected to the drain of the third P-type field-effect transistor Mp3.

[0084] The second terminal of the eighth capacitor C8 is connected to the gate of the second N-type field-effect transistor Mn2, and the drain of the second N-type field-effect transistor Mn2 is connected to the source of the third N-type field-effect transistor Mn3.

[0085] The second terminal of the ninth capacitor C9 is connected to the gate of the first N-type field-effect transistor Mn1, the drain of the first N-type field-effect transistor Mn1 is connected to the source of the second N-type field-effect transistor Mn2, and the source of the first N-type field-effect transistor Mn1 is grounded.

[0086] The common node of the drain of the third P-type field-effect transistor Mp3 and the drain of the third N-type field-effect transistor Mn3 serves as the output terminal of the multi-drive improved Class D amplifier.

[0087] It should be noted that the output terminal of the multi-drive improved Class D amplifier can also be connected to a grounded capacitor CL, which can improve the output capacitance.

[0088] After passing through a compact coupled peaking distributed amplifier, it is then amplified and output through a multi-drive improved Class D amplifier. It should be noted that the output power... and voltage swing and output impedance They are closely related. The relationship between them is shown below:

[0089] ;

[0090] Generally speaking, voltage swing The larger the voltage, the higher the output power. Typically, in CMOS processes, the typical DC source voltage is around 1.8V to 2.2V, with a voltage swing of [missing value]. The output power is also relatively low. This embodiment of the multi-drive improved Class D amplifier uses a total of six layers of field-effect transistors stacked together, for example... Figure 2 The top three P-type MOSFETs and the bottom three N-type MOSFETs in the circuit can be used as a second DC source for the power supply voltage, which can be 5V, thus enabling a larger power output.

[0091] In this embodiment of the improved Class D amplifier design using multi-drive, a multi-drive input design is employed. Besides feeding signals to the first N-type MOSFET Mn1 and the first P-type MOSFET Mp1, signals are also input to the gates of the second N-type MOSFET Mn2, the third N-type MOSFET Mn3, the second P-type MOSFET Mp2, and the third P-type MOSFET Mp3, using a multi-drive approach. In this case, the other end of the gate capacitor (the capacitor connected in series with each MOSFET) is not grounded but connected to the input terminal. Besides the fixed voltage bias, the increased input signal results in a higher gate-source voltage VGS for the N-type MOSFET in the on-state and a lower VGS for the P-type MOSFET, leading to a lower on-resistance Ron. This helps improve the high-frequency bandwidth performance of the Class D amplifier.

[0092] Appendix Figure 4 Under large-signal conditions, simulations were performed on the gate voltage of the second N-type field-effect transistor Mn2 and the gate voltage of a conventional Class D amplifier. In the graph, the horizontal axis represents time (Time), and the vertical axis represents voltage (VGS). The red line represents the improved Class D amplifier, specifically the multi-drive improved Class D amplifier in this embodiment, while the black line represents the conventional Class D amplifier. As shown in the graph, when the MOSFET is on, the gate voltage (VGS) of the multi-drive improved Class D amplifier is higher than that of the conventional Class D amplifier. This results in a lower Ron for the second N-type MOSFET Mn2 under these conditions, contributing to improved gain and bandwidth. Simultaneously, when the transistor is off (i.e., VGS is less than the transistor's turn-on threshold voltage), the multi-drive improved Class D amplifier has a longer period of time within a cycle where VGS is lower than that of the conventional Class D amplifier. This allows for a smaller turn-off current, thus improving amplifier efficiency.

[0093] Figure 5 This diagram compares the output voltage swing of a multi-drive improved Class-D amplifier and a conventional Class-D amplifier at high frequencies such as 20 GHz. The horizontal axis represents time (Time), and the vertical axis represents voltage (Vout). The red line represents the improved Class-D amplifier, specifically the multi-drive improved Class-D amplifier in this embodiment, while the black line represents the conventional Class-D amplifier. As can be seen from the diagram, under the same DC source voltage and the same large-signal input power, the voltage swing of the multi-drive improved Class-D amplifier is a few tenths of a volt, or even 1 volt, higher than that of the conventional Class-D amplifier. From the previous output power formula, we know that a larger voltage swing results in higher output power. Therefore, from both a power and gain perspective, the multi-drive improved Class-D amplifier in this embodiment can also improve high-frequency performance.

[0094] Appendix Figure 6This figure compares the output power of an amplifier combining a traditional distributed amplifier and a traditional Class D amplifier (traditional structure) with that of the CMOS ultra-wideband high-gain high-power amplifier of this embodiment (the structure of this invention). The horizontal axis of the figure represents frequency Freq, and the vertical axis represents output power Pout. As can be seen from the figure, the power of this embodiment is 2-3 dBm higher than that of the traditional amplifier in the 2-20 GHz range, which is a very significant improvement.

[0095] Appendix Figure 7 This graph compares the efficiency of the proposed structure with that of a conventional structure. The horizontal axis represents frequency (Feq), and the vertical axis represents efficiency (PAE). As can be seen from the graph, the efficiency of conventional ultra-wideband amplifiers is not particularly high, generally just over 10% within the bandwidth. However, the amplifier structure of this invention contributes to improving the efficiency of wideband amplifiers, increasing efficiency by 2-3 points within the bandwidth.

[0096] In summary, the power amplifier in this embodiment uses a coupled peaking distributed amplifier as the driver stage and a multi-drive improved Class D amplifier as the power output stage. This allows for high gain, wide bandwidth performance, and high power output within a relatively small area. Unlike traditional methods that simply add a distributed amplifier and a Class D amplifier, which may result in worse performance at high frequencies, this embodiment improves the performance of both amplifiers individually. The combined improvement in high-frequency power and gain also enhances bandwidth. Simultaneously, it enables high-power output over a wide bandwidth and achieves high efficiency.

[0097] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A CMOS ultra-wideband high-gain high-power amplifier, characterized in that, Including multi-drive improved Class D amplifiers and multi-stage compact coupled peaking distributed amplifiers; Multi-stage compact coupled peaking distributed amplifiers are connected in sequence. The input RF signal is connected to the first stage compact coupled peaking distributed amplifier through the input line. The output terminal of the Nth stage compact coupled peaking distributed amplifier is connected to the input terminal of the multi-drive improved Class D amplifier through the output line. The output terminal of the multi-drive improved Class D amplifier outputs the RF signal. The compact coupled peaking distributed amplifier serves as a driver stage and is used to improve bandwidth, while the multi-drive improved Class D amplifier serves as a power output stage and is used to improve the output power of the broadband. The multi-drive improved Class D amplifier includes a six-layer field-effect transistor unit; The connection method of the field-effect transistor unit is as follows: The i-th layer field-effect transistor unit includes a capacitor and a P-type field-effect transistor, i=1,2,3; The j-th layer field-effect transistor unit includes a capacitor and an N-type field-effect transistor, j=4,5,6; The first terminals of the capacitors of each layer of the field-effect transistor unit are connected together to form the input terminal of the multi-drive improved Class D amplifier; The second terminal of the fourth capacitor is connected to the gate of the first P-type field-effect transistor, and the source of the first P-type field-effect transistor is connected to the second DC source. The second terminal of the fifth capacitor is connected to the gate of the second P-type field-effect transistor, and the source of the second P-type field-effect transistor is connected to the drain of the first P-type field-effect transistor. The second terminal of the sixth capacitor is connected to the gate of the third P-type field-effect transistor, and the source of the third P-type field-effect transistor is connected to the drain of the second P-type field-effect transistor. The second terminal of the seventh capacitor is connected to the gate of the third N-type field-effect transistor, and the drain of the third N-type field-effect transistor is connected to the drain of the third P-type field-effect transistor. The second terminal of the eighth capacitor is connected to the gate of the second N-type field-effect transistor, and the drain of the second N-type field-effect transistor is connected to the source of the third N-type field-effect transistor. The second terminal of the ninth capacitor is connected to the gate of the first N-type field-effect transistor, the drain of the first N-type field-effect transistor is connected to the source of the second N-type field-effect transistor, and the source of the first N-type field-effect transistor is grounded. The common node of the drain of the third P-type field-effect transistor and the drain of the third N-type field-effect transistor serves as the output terminal of the multi-drive improved Class D amplifier.

2. The CMOS ultra-wideband high-gain high-power amplifier according to claim 1, characterized in that, The higher the gain of the CMOS ultra-wideband high-gain high-power amplifier, the higher the number N of the compact coupled peaking distributed amplifier.

3. A CMOS ultra-wideband high-gain high-power amplifier according to claim 2, characterized in that, The compact coupled peaking distributed amplifier has 2 or 3 stages.

4. A CMOS ultra-wideband high-gain high-power amplifier according to claim 1, characterized in that, The compact coupled peaking distributed amplifier improves the high-frequency bandwidth by: An inductor is connected in series at the drain of the field-effect transistor that serves as a common gate transistor at the output terminal; The compact coupled peaking distributed amplifier includes resistors, capacitors, multiple inductors, and multiple field-effect transistors; The first end of the first resistor is connected to the second gate power supply, the second end of the first resistor is connected to the first end of the first capacitor and the gate of the second field-effect transistor, the second end of the first capacitor is grounded, the drain of the second field-effect transistor is connected to the first end of the first inductor, the second end of the first inductor is connected to the first end of the second inductor, the source of the second field-effect transistor is connected to the drain of the first field-effect transistor, and the source of the first field-effect transistor is grounded. The second terminal of the fourth inductor and the first terminal of the fifth inductor are connected, and their common node is connected to the drain of the first field-effect transistor. The first terminal of the fourth inductor is the first matching input terminal, and the second terminal of the fifth inductor is the first matching output terminal. The first end of the third inductor is connected to the second end of the first inductor, the second end of the third inductor is the second matched output terminal, and the first end of the second inductor is the second matched input terminal; The first inductor and the second inductor are coupled.

5. A CMOS ultra-wideband high-gain high-power amplifier according to claim 4, characterized in that, The connection method between the compact coupled peaking distributed amplifiers is as follows: The first matched output of the nth stage compact coupled peaking distributed amplifier is connected to the first matched input of the (n+1)th stage compact coupled peaking distributed amplifier, and the second matched output of the nth stage compact coupled peaking distributed amplifier is connected to the second matched input of the (n+1)th stage compact coupled peaking distributed amplifier, where n = 1, 2, ..., N-1; The second matching input of the first-stage compact coupled peaking distributed amplifier is grounded via a second resistor and a second capacitor. The first matched input terminal of the first stage compact coupled peaking distributed amplifier is connected to the first gate power supply through a third resistor and is also the input terminal of the compact coupled peaking distributed amplifier. The second matched output terminal of the Nth stage compact coupled peaking distributed amplifier is connected to the first DC source via the sixth inductor and is the output terminal of the compact coupled peaking distributed amplifier; The first matched output of the Nth stage compact coupled peaking distributed amplifier is grounded via the fourth resistor and the tenth capacitor.

6. A CMOS ultra-wideband high-gain high-power amplifier according to claim 1, characterized in that, The input line uses a capacitor.

7. A CMOS ultra-wideband high-gain high-power amplifier according to claim 1, characterized in that, The output line uses a single capacitor.

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