A manufacturing method of high-order HDI circuit board blind hole butt joint zero misplacement

Abstract

This application discloses a method for fabricating high-order HDI circuit boards with zero misalignment in blind via connections, belonging to the field of fabrication and analysis technology. The method includes surface pretreatment of the high-order HDI circuit board substrate and establishment of a coordinate reference model; interlayer matching and positioning of the layer to be drilled and the connection layer based on the coordinate reference model, real-time correction of interlayer deviations, and obtaining zero-misalignment alignment coordinate data; high-precision laser drilling process based on the zero-misalignment alignment coordinate data, followed by metallization deposition process after drilling; after completing multi-layer blind via connection, global detection and local verification are performed using detection equipment. The global detection result obtains the actual position of the blind via, and the actual position of the blind via is compared with the coordinate reference model. If a deviation exists, a secondary repair plating is performed to ensure zero misalignment in the blind via connection of the high-order HDI circuit board. This application improves the efficiency of blind via connection.

Description

Technical Field

[0001] This application relates to the field of fabrication and analysis technology, and in particular to a fabrication method for zero misalignment of blind vias in high-order HDI circuit boards. Background Technology

[0002] As electronic products become increasingly dense and miniaturized, HDI (High-Density Interconnect) circuit boards are widely used in smart terminals, servers, aerospace, and high-end communication equipment. High-end HDI circuit boards often require multi-layer structures and complex inter-layer interconnection processes, and the precise alignment of blind vias (also known as micro-blind vias or buried vias) is a key step in ensuring multi-layer electrical connectivity and structural stability.

[0003] In related technologies, existing methods for fabricating blind vias with zero misalignment in high-end HDI circuit boards typically employ optical alignment or X-ray scanning for positioning. However, due to the lack of cross-layer multi-point collaborative reference and dynamic error compensation mechanisms, the problem of zero misalignment in multi-layer blind via connections cannot be solved, thereby reducing the efficiency of blind via connections in high-end HDI circuit boards, and there are areas for improvement. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this application provides a method for fabricating blind vias with zero misalignment in high-order HDI circuit boards.

[0005] In a first aspect, this application provides a method for fabricating a high-order HDI circuit board with zero misalignment of blind vias, comprising the following steps: Step S1: Perform surface pretreatment on the high-end HDI circuit board substrate, and after the surface pretreatment is completed, perform optical scanning of multiple alignment marks to establish a coordinate reference model; Step S2: Based on the coordinate reference model, perform interlayer matching and positioning between the borehole layer and the docking layer, and use bidirectional image alignment recognition and error compensation algorithm to correct the interlayer deviation in real time to obtain zero misalignment alignment coordinate data; Step S3: Perform high-precision laser drilling based on the zero-misalignment alignment coordinate data, thereby enabling the laser beam to achieve synchronous focusing and energy adjustment at different levels, and perform metallization deposition after the drilling process is completed. Step S4: After completing the multi-layer blind via connection, use the testing equipment to perform global detection and local verification. Then, obtain the actual position of the blind via from the global detection results. Compare the actual position of the blind via with the coordinate reference model. If there is a deviation, perform secondary repair plating to ensure that the blind via connection of the high-order HDI circuit board achieves zero misalignment.

[0006] Preferably, the multi-layer alignment markers include alignment markers disposed on the layer to be drilled and the docking layer. The alignment markers on the layer to be drilled are used to provide reference coordinates for the drilling position, and the alignment markers on the docking layer are used to provide spatial matching reference with the layer to be drilled.

[0007] Preferably, step S2 includes the following steps: Step S21: Analyze the crack and boundary features of the images between the layers of the high-order HDI circuit board and extract the interlayer geometric contour data; Step S22: Perform inter-layer image registration based on inter-layer geometric contour data to obtain preliminary alignment difference data; Step S23: Dynamically correct the initial alignment difference data using an error compensation algorithm, and then obtain the alignment coordinate data with zero misalignment based on the result of the dynamic correction; Step S24: Perform a stability assessment on the alignment coordinate data with zero misalignment, then confirm the stability index data based on the results of the stability assessment, and perform analysis and management based on the stability index data.

[0008] Preferably, step S23 includes the following steps: Step S231: Perform vertical distribution analysis on the metal pad reflection signals in the images of each layer of the high-order HDI circuit board to obtain the spatial distribution density data of the pad center; Step S232: Based on the spatial distribution density data to the center of the pad, perform spatial calculation of the laser focusing point between each layer of the high-order HDI circuit board to obtain the depth parameters of interlayer alignment; Step S233: Perform error decomposition based on the depth parameters of interlayer alignment, and identify potential alignment deviation data based on the results of error decomposition. Step S234: Compensate for potential alignment deviation data using a multidimensional correction algorithm, and set the compensated coordinate data as alignment coordinate data with zero misalignment.

[0009] Preferably, step S3 includes the following steps: High-precision laser drilling is performed based on zero-misalignment alignment coordinate data. The laser energy during the drilling process is adjusted in segments, and a multi-pulse laser superposition method is used to achieve stable interlayer energy transfer. After the drilling process is completed, copper electroplating is performed. After the copper electroplating is completed, the surface of the deposited copper layer is scanned to extract the thickness variation curve corresponding to the deposited copper layer. The thickness variation curve is compared with the preset standard variation curve to confirm the thickness evaluation data of the deposited copper layer. If the thickness evaluation data is found to be abnormal, a second plating repair is performed.

[0010] Preferably, step S4 includes the following steps: Step S41: Normalize the actual position of the blind hole to generate a normalized coordinate model; Step S42: Perform convolutional comparison between the normalized coordinate model and the reference coordinate model to obtain the coordinate matching result; Step S43: Classify the local errors in different regions based on the coordinate matching results to form risk level distribution data; Step S44: Perform secondary verification and repair on the risk level distribution data, and finally output the blind via connection result of the high-order HDI circuit board with zero misalignment.

[0011] Preferably, step S43 includes the following steps: Step S431: Recalibrate the spatial coordinates of different regions to generate a new docking coordinate system; Step S432: Based on the new docking coordinate system and risk level distribution data, perform a linkage analysis to obtain coordinate risk linkage data; Step S433: Calculate the local multivariate risk index based on the coordinate risk linkage data, the normalized coordinate model, and the coordinate matching degree results; Step S434: Based on the local multivariate risk index, different regions are corrected and optimized to ensure that the blind via connection of the high-order HDI circuit board achieves zero misalignment.

[0012] Secondly, this application provides a manufacturing system for zero-misalignment blind via mating of high-end HDI circuit boards, comprising: The preprocessing module is used to perform surface preprocessing on the high-end HDI circuit board substrate, and after the surface preprocessing is completed, to perform optical scanning of multi-layer alignment marks and establish a coordinate reference model. The correction module is used to perform interlayer matching and positioning between the borehole layer and the docking layer based on the coordinate reference model, and to correct the interlayer deviation in real time through bidirectional image alignment recognition and error compensation algorithm to obtain alignment coordinate data with zero misalignment. The module is used to perform high-precision laser drilling based on zero-misalignment alignment coordinate data, thereby enabling the laser beam to achieve synchronous focusing and energy adjustment at different levels, and to perform metallization deposition after the drilling process is completed. The optimization module is used to perform global detection and local verification using detection equipment after completing the multi-layer blind via connection. The global detection results are used to obtain the actual position of the blind via. The actual position of the blind via is compared with the coordinate reference model. If there is a deviation, a secondary repair plating is performed to ensure that the blind via connection of high-order HDI circuit boards achieves zero misalignment.

[0013] Thirdly, this application provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform a method for manufacturing a high-order HDI circuit board with zero misalignment of blind vias as described in any of the above claims.

[0014] In summary, this application includes the following beneficial technical effects: This application provides a method for fabricating zero-misalignment blind vias in high-order HDI circuit boards. The method involves interlayer matching and positioning of the layer to be drilled and the connecting layer based on a coordinate reference model, with real-time correction of interlayer deviations to obtain zero-misalignment alignment coordinate data. High-precision laser drilling is then performed based on this data, followed by metallization deposition. After completing the multi-layer blind via connection, global and local checks are performed using detection equipment to obtain the actual blind via positions. These positions are compared with the coordinate reference model; if deviations exist, secondary repair plating is performed to ensure zero-misalignment of the high-order HDI circuit board blind via connection. This effectively reduces the occurrence of situations where zero-misalignment in multi-layer blind via connection cannot be achieved due to a lack of cross-layer multi-point collaborative reference and dynamic error compensation mechanisms, thus significantly improving the efficiency of zero-misalignment blind via connection in high-order HDI circuit boards. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart illustrating the manufacturing method of zero-misalignment blind via connection on a high-order HDI circuit board according to an embodiment of this application.

[0017] Figure 2 This is a schematic diagram of the fabrication system for zero misalignment of blind vias in a high-order HDI circuit board according to an embodiment of this application. Detailed Implementation

[0018] The following is in conjunction with the appendix Figure 1-2 This application will be described in further detail.

[0019] Example 1 This application discloses a method for fabricating a high-order HDI circuit board with zero misalignment of blind via connections.

[0020] Reference Figure 1 A method for fabricating a high-order HDI circuit board with zero misalignment of blind vias includes the following steps: Step S1: Perform surface pretreatment on the high-end HDI circuit board substrate, and after the surface pretreatment is completed, perform optical scanning of multiple alignment marks to establish a coordinate reference model; Step S2: Based on the coordinate reference model, perform interlayer matching and positioning between the borehole layer and the docking layer, and use bidirectional image alignment recognition and error compensation algorithm to correct the interlayer deviation in real time to obtain zero misalignment alignment coordinate data; Step S3: Perform high-precision laser drilling based on the zero-misalignment alignment coordinate data, thereby enabling the laser beam to achieve synchronous focusing and energy adjustment at different levels, and perform metallization deposition after the drilling process is completed. Step S4: After completing the multi-layer blind via connection, use the testing equipment to perform global detection and local verification. Then, obtain the actual position of the blind via from the global detection results. Compare the actual position of the blind via with the coordinate reference model. If there is a deviation, perform secondary repair plating to ensure that the blind via connection of the high-order HDI circuit board achieves zero misalignment.

[0021] Specifically, in step S1, the high-end HDI circuit board substrate undergoes surface pretreatment. This pretreatment includes plasma cleaning to remove surface oil, oxide layers, and micro-dust, followed by mechanical grinding to remove surface burrs. After pretreatment, a high-precision optical scanning device is used to scan the pre-set multi-layer alignment markers on the surface of the high-end HDI circuit board substrate, acquiring the three-dimensional coordinates of each marker. A coordinate reference model containing the spatial relationship between each layer is established using a coordinate fitting algorithm. In step S2, based on the coordinate reference model, the markers of the layer to be drilled and the mating layer are matched and located. A binocular vision system is used for bidirectional image alignment recognition, capturing inter-layer displacement, rotation, and scaling deviations in real time. A PID error compensation algorithm is used to dynamically correct the deviations, ultimately outputting the corrected data. In step S3, based on the alignment coordinate data, the ultraviolet laser drilling equipment is started. A dynamic focusing system is used to achieve synchronous focusing at different levels. Energy segmentation adjustment and multi-pulse laser superposition are employed to ensure consistent drilling diameter. After drilling, chemical copper plating combined with electroplating is used for metallization deposition, achieving a copper layer thickness of 15-25 μm on the hole wall. In step S4, X-ray inspection is used for global detection to obtain the actual position coordinates of all blind holes. Simultaneously, a metallographic microscope is used for local verification of key areas. The actual positions are compared with the coordinate reference model. If the deviation is >0.5 μm, local electroplating is used for secondary repair until the alignment deviation of all blind holes is ≤0.5 μm, achieving zero misalignment.

[0022] By adopting the above technical solution, the misalignment bottleneck of blind via connection in high-order HDI circuit boards is broken through through high-precision control of the entire process. The combination of coordinate reference model and bidirectional image alignment reduces interlayer deviation. Dynamic focusing and energy adjustment of laser drilling ensure the consistency of hole positions at different levels. Metallization deposition and secondary repair ensure the conductivity of hole walls and connection reliability. The combination of global detection and local verification avoids the risk of missed detection.

[0023] It should be noted that the multi-layer alignment markers include alignment markers set on the layer to be drilled and the mating layer. The alignment markers on the layer to be drilled provide the reference coordinates for the drilling position, and the alignment markers on the mating layer provide a spatial matching reference with the layer to be drilled. Through the double-layer arrangement of alignment markers, the layer to be drilled and the mating layer can maintain consistency during optical scanning, image recognition, and deviation compensation, thereby ensuring that the laser beam can be accurately aligned with the center of the lower pad during the drilling process, achieving zero misalignment between the blind via and the mating layer. The alignment markers on the layer to be drilled undergo surface microstructure enhancement treatment to improve scanning contrast, while the alignment markers on the mating layer are reinforced by metallization deposition to improve recognition stability after multi-layer lamination and heat treatment processes, thus forming a cross-layer collaborative spatial reference system, ultimately ensuring that the blind vias of the entire high-order HDI circuit board achieve zero misalignment in the three-dimensional spatial coordinate system.

[0024] It should be noted that step S2 includes the following steps: Step S21: Analyze the crack and boundary features of the images between the layers of the high-order HDI circuit board and extract the interlayer geometric contour data; Step S22: Perform inter-layer image registration based on inter-layer geometric contour data to obtain preliminary alignment difference data; Step S23: Dynamically correct the initial alignment difference data using an error compensation algorithm, and then obtain the alignment coordinate data with zero misalignment based on the result of the dynamic correction; Step S24: Perform a stability assessment on the alignment coordinate data with zero misalignment, then confirm the stability index data based on the results of the stability assessment, and perform analysis and management based on the stability index data.

[0025] Specifically, high-resolution industrial cameras are used to capture high-definition images of each layer of the high-end HDI circuit board. Edge detection algorithms are used to extract interlayer cracks and boundary features, and contour extraction tools are used to convert the features into geometric contour data. The data sampling interval is 0.5μm to ensure the integrity of contour details. Based on the interlayer geometric contour data, an iterative nearest-point algorithm is used to perform image registration: taking the contour of the mating layer as a reference, the contour of the layer to be drilled is rotated, translated, and scaled. The overlap of the two contours after transformation is calculated, and preliminary alignment difference data is output. An error compensation algorithm (such as Kalman filtering) is used to dynamically correct the preliminary difference data: an error prediction model is established by combining historical production data to compensate for dynamic deviations caused by temperature changes and mechanical vibrations in real time. After correction, zero-misalignment alignment coordinate data is output, and the stability of the alignment coordinate data is evaluated: multiple sets of coordinate values ​​at the same position are continuously collected, and the standard deviation and range are calculated as stability index data. If the stability index data exceeds the preset threshold, the equipment calibration process is triggered to ensure the long-term stability of the coordinate data.

[0026] By adopting the above technical solution, crack and boundary feature analysis can identify interlayer hidden defects, avoiding the impact of substrate defects on alignment accuracy. The combination of ICP algorithm and Kalman filter takes into account both static registration accuracy and dynamic error compensation. Stability assessment and equipment calibration are linked, which can detect the decline in accuracy caused by equipment aging in a timely manner, thereby ensuring that the alignment deviation of each high-end HDI circuit board in mass production is controlled within the zero misalignment range, improving production consistency.

[0027] Furthermore, step S23 includes the following steps: Step S231: Perform vertical distribution analysis on the reflection signals of the corresponding metal pads in the images of each layer of the high-order HDI circuit board to obtain the spatial distribution density data of the pad center; Step S232: Based on the spatial distribution density data to the center of the pad, perform spatial calculation of the laser focusing point between each layer of the high-order HDI circuit board to obtain the depth parameters of interlayer alignment; Step S233: Perform error decomposition based on the depth parameters of interlayer alignment, and identify potential alignment deviation data based on the results of error decomposition. Step S234: Compensate for potential alignment deviation data using a multidimensional correction algorithm, and set the compensated coordinate data as alignment coordinate data with zero misalignment.

[0028] Specifically, a laser confocal microscope is used to scan the metal pads in the images of each layer of the high-order HDI circuit board. The vertical distribution of the reflected signals on the pad surface is analyzed, and the center of the pad is located by the peak signal intensity. The number and distribution density of pad centers per unit area are counted to generate spatial distribution density data. Based on the spatial distribution density data, the laser focus points between each layer are spatially calculated: in the high-density area, multi-focus synchronous calculation is used, and the depth parameters of interlayer alignment are determined by triangulation; in the low-density area, the number of focus point samples is increased to ensure calculation accuracy. Error decomposition is performed based on the depth parameters: potential alignment deviations are divided into translation error, rotation error, and scaling error. The weight of each error is determined by variance analysis, and then quantified potential alignment deviation data is output. Multidimensional correction algorithms (such as matrix transformation + neural network compensation) are used to compensate for the potential deviation data: translation and rotation errors are corrected by matrix transformation, and nonlinear scaling errors are compensated by neural network model. Finally, alignment coordinate data with zero misalignment is output.

[0029] The above technical solution utilizes the analysis of reflected signals from metal pads to directly correlate with the functional areas of the circuit board, which is more in line with actual docking requirements compared to edge-based positioning. Spatial calculation and error decomposition enable refined source tracing of deviations, avoiding insufficient local accuracy caused by general compensation. The multi-dimensional correction algorithm takes into account both linear and nonlinear errors, improving the zero misalignment rate of blind via docking.

[0030] It should be noted that step S3 includes the following steps: High-precision laser drilling is performed based on zero-misalignment alignment coordinate data. The laser energy during the drilling process is adjusted in segments, and a multi-pulse laser superposition method is used to achieve stable interlayer energy transfer. After the drilling process is completed, copper electroplating is performed. After the copper electroplating is completed, the surface of the deposited copper layer is scanned to extract the thickness variation curve corresponding to the deposited copper layer. The thickness variation curve is compared with the preset standard variation curve to confirm the thickness evaluation data of the deposited copper layer. If the thickness evaluation data is found to be abnormal, a second plating repair is performed.

[0031] Specifically, when performing high-precision laser drilling, the drilling path is first generated using computer-aided manufacturing software based on the zero-misalignment alignment coordinate data, and then imported into the ultraviolet laser drilling equipment; the laser energy is adjusted in segments: the surface energy density is set to 1-2 J / cm². 2 The middle layer is set at 2-3 J / cm. 2 The inner layer is set at 3-5 J / cm. 2Simultaneously, multi-pulse laser superposition is used to ensure smooth hole walls without carbonization. After drilling, metallization deposition is performed: first, chemical copper plating is used to cover the hole walls with a conductive layer of 0.5-1μm; then, copper is electroplated to achieve a copper layer thickness of 15-25μm. After deposition, an eddy current thickness gauge is used to scan the surface of the deposited copper layer and extract the thickness change curve. This curve is compared with a preset standard change curve. If the deviation of a certain area is >1μm (i.e., the thickness assessment data is abnormal), the area is repaired by secondary plating.

[0032] It should be noted that step S4 includes the following steps: Step S41: Normalize the actual position of the blind hole to generate a normalized coordinate model; Step S42: Perform convolutional comparison between the normalized coordinate model and the reference coordinate model to obtain the coordinate matching result; Step S43: Classify the local errors in different regions based on the coordinate matching results to form risk level distribution data; Step S44: Perform secondary verification and repair on the risk level distribution data, and finally output the blind via connection result of the high-order HDI circuit board with zero misalignment.

[0033] Specifically, the actual coordinates of the blind vias are normalized: using the origin of the coordinate reference model as a benchmark, the actual positions are converted into relative coordinates to eliminate the influence of circuit board size differences, generating a normalized coordinate model. A two-dimensional convolution algorithm is used to compare the normalized coordinate model with the reference coordinate model: a 3×3 convolution kernel is set, and the convolution similarity between the two models is calculated (range 0-1, 1 being a perfect match), obtaining the coordinate matching result (e.g., matching degree ≥ 0.99 is excellent, 0.95-0.99 is good, and matching degree < 0.95 is poor). Based on the matching result, the local errors in different areas are graded: excellent corresponds to low risk, good corresponds to medium risk, and poor corresponds to high risk, forming risk level distribution data. High-risk areas are re-verified, and after confirming the deviation position, repair is carried out through local electroplating. After repair, the inspection is repeated until the risk level of all areas is excellent or good, and finally, a blind via docking result with zero misalignment is output.

[0034] By adopting the above technical solution, the detection data of circuit boards of different sizes can be directly compared through normalization processing, which facilitates quality control in mass production; compared with traditional point-to-point comparison, convolutional comparison can capture the overall deviation trend of the region and improve detection efficiency; the combination of risk level distribution and secondary repair achieves precise positioning and targeted repair, avoids overall rework, reduces production costs, and ensures zero misalignment of blind vias in the final product, meeting the high density and high reliability requirements of high-end HDI circuit boards.

[0035] Furthermore, step S43 includes the following steps: Step S431: Recalibrate the spatial coordinates of different regions to generate a new docking coordinate system; Step S432: Based on the new docking coordinate system and risk level distribution data, perform a linkage analysis to obtain coordinate risk linkage data; Step S433: Calculate the local multivariate risk index based on the coordinate risk linkage data, the normalized coordinate model, and the coordinate matching degree results; Step S434: Based on the local multivariate risk index, different regions are corrected and optimized to ensure that the blind via connection of the high-order HDI circuit board achieves zero misalignment.

[0036] Specifically, for different regions, for example, A region: top left corner, B region: center, C region: bottom right corner, the spatial coordinates are recalibrated: three unbiased blind holes in each region are selected as reference points to establish a new docking coordinate system. The cumulative error of the original coordinate system is corrected through affine transformation. Based on the new coordinate system and risk level distribution data, coordinate risk linkage analysis is performed: the correlation of risk levels between adjacent regions (e.g., A region and B region) is calculated (correlation coefficient ≥ 0.8 indicates strong correlation), systematic deviation areas are identified, coordinate risk linkage data is generated, and based on the coordinate risk linkage data, combined with the normalized coordinate model (weight 0.3) and the coordinate matching degree result (weight... 0.7), calculate the local multivariate risk index: index = 0.3 × normalized deviation + 0.7 × (1 - matching degree) × correlation coefficient, the index range is 0-1 (0 is no risk, 1 is extremely high risk), and correct different areas according to the local multivariate risk index: for high-risk areas with local multivariate risk index > 0.6, laser micro-milling is used to correct the hole position and then metal is redeposited; for medium-risk areas with local multivariate risk index between 0.3 and 0.6, electroplating is used to thicken and compensate for the deviation; for low-risk areas with local multivariate risk index < 0.3, no treatment is required, and finally ensure that the local multivariate risk index of all areas is less than 0.3 to achieve zero misalignment of blind hole docking.

[0037] Example 2 This application also discloses a manufacturing system for zero misalignment of blind vias in high-order HDI circuit boards.

[0038] Reference Figure 2 A high-end HDI circuit board blind via interconnection zero-misalignment manufacturing system, comprising: The preprocessing module is used to perform surface preprocessing on the high-end HDI circuit board substrate, and after the surface preprocessing is completed, to perform optical scanning of multi-layer alignment marks and establish a coordinate reference model. The correction module is used to perform interlayer matching and positioning between the borehole layer and the docking layer based on the coordinate reference model, and to correct the interlayer deviation in real time through bidirectional image alignment recognition and error compensation algorithm to obtain alignment coordinate data with zero misalignment. The module is used to perform high-precision laser drilling based on zero-misalignment alignment coordinate data, thereby enabling the laser beam to achieve synchronous focusing and energy adjustment at different levels, and to perform metallization deposition after the drilling process is completed. The optimization module is used to perform global detection and local verification using detection equipment after completing the multi-layer blind via connection. The global detection results are used to obtain the actual position of the blind via. The actual position of the blind via is compared with the coordinate reference model. If there is a deviation, a secondary repair plating is performed to ensure that the blind via connection of high-order HDI circuit boards achieves zero misalignment.

[0039] The above content is merely an example and illustration of the concept of the present invention. Those skilled in the art can make various modifications or additions to the specific embodiments described or use similar methods to replace them, as long as they do not deviate from the concept of the invention, they should all fall within the protection scope of the present invention.

[0040] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0041] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to any specific implementation. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention.

Claims

1. A method for fabricating blind vias with zero misalignment in a high-order HDI circuit board, characterized in that, Includes the following steps: Step S1: Perform surface pretreatment on the high-end HDI circuit board substrate, and after the surface pretreatment is completed, perform optical scanning of multiple alignment marks to establish a coordinate reference model; The multi-layer alignment markers include alignment markers set on the layer to be drilled and the docking layer. The alignment markers on the layer to be drilled are used to provide the reference coordinates of the drilling position, and the alignment markers on the docking layer are used to provide a spatial matching reference with the layer to be drilled. Step S2: Based on the coordinate reference model, perform interlayer matching and positioning between the borehole layer and the docking layer, and use bidirectional image alignment recognition and error compensation algorithm to correct the interlayer deviation in real time to obtain zero misalignment alignment coordinate data; Step S2 includes the following steps: Step S21: Analyze the crack and boundary features of the images between the layers of the high-order HDI circuit board and extract the interlayer geometric contour data; Step S22: Perform inter-layer image registration based on inter-layer geometric contour data to obtain preliminary alignment difference data; Step S23: Dynamically correct the initial alignment difference data using an error compensation algorithm, and then obtain the alignment coordinate data with zero misalignment based on the result of the dynamic correction; Step S24: Perform a stability assessment on the alignment coordinate data with zero misalignment, then confirm the stability index data based on the results of the stability assessment, and perform analysis and management based on the stability index data. Step S3: Perform high-precision laser drilling based on the zero-misalignment alignment coordinate data, thereby enabling the laser beam to achieve synchronous focusing and energy adjustment at different levels, and perform metallization deposition after the drilling process is completed. Step S4: After completing the multi-layer blind via connection, use the testing equipment to perform global detection and local verification. Then, obtain the actual position of the blind via from the global detection results. Compare the actual position of the blind via with the coordinate reference model. If there is a deviation, perform secondary repair plating to ensure that the blind via connection of the high-order HDI circuit board achieves zero misalignment.

2. The method for fabricating a high-order HDI circuit board with zero misalignment of blind vias according to claim 1, characterized in that, Step S23 includes the following steps: Step S231: Perform vertical distribution analysis on the reflection signals of the corresponding metal pads in the images of each layer of the high-order HDI circuit board to obtain the spatial distribution density data of the pad center; Step S232: Based on the spatial distribution density data to the center of the pad, perform spatial calculation of the laser focusing point between each layer of the high-order HDI circuit board to obtain the depth parameters of interlayer alignment; Step S233: Perform error decomposition based on the depth parameters of interlayer alignment, and identify potential alignment deviation data based on the results of error decomposition. Step S234: Compensate for potential alignment deviation data using a multidimensional correction algorithm, and set the compensated coordinate data as alignment coordinate data with zero misalignment.

3. The method for fabricating a high-order HDI circuit board with zero misalignment of blind vias according to claim 1, characterized in that, Step S3 includes the following steps: High-precision laser drilling is performed based on zero-misalignment alignment coordinate data. The laser energy during the drilling process is adjusted in segments, and a multi-pulse laser superposition method is used to achieve stable interlayer energy transfer. After the drilling process is completed, copper electroplating is performed. After the copper electroplating is completed, the surface of the deposited copper layer is scanned to extract the thickness variation curve corresponding to the deposited copper layer. The thickness variation curve is compared with the preset standard variation curve to confirm the thickness evaluation data of the deposited copper layer. If the thickness evaluation data is found to be abnormal, a second plating repair is performed.

4. The method for fabricating a high-order HDI circuit board with zero misalignment of blind vias according to claim 1, characterized in that, Step S4 includes the following steps: Step S41: Normalize the actual position of the blind hole to generate a normalized coordinate model; Step S42: Perform convolutional comparison between the normalized coordinate model and the coordinate reference model to obtain the coordinate matching degree result; Step S43: Classify the local errors in different regions based on the coordinate matching results to form risk level distribution data; Step S44: Perform secondary verification and repair on the risk level distribution data, and finally output the blind via connection result of the high-order HDI circuit board with zero misalignment.

5. The method for fabricating a high-order HDI circuit board with zero misalignment of blind vias according to claim 4, characterized in that, Step S43 includes the following steps: Step S431: Recalibrate the spatial coordinates of different regions to generate a new docking coordinate system; Step S432: Based on the new docking coordinate system and risk level distribution data, perform a linkage analysis to obtain coordinate risk linkage data; Step S433: Calculate the local multivariate risk index based on the coordinate risk linkage data, the normalized coordinate model, and the coordinate matching degree results; Step S434: Based on the local multivariate risk index, different regions are corrected and optimized to ensure that the blind via connection of the high-order HDI circuit board achieves zero misalignment.

6. A fabrication system for zero-misalignment blind via mating of high-order HDI circuit boards, applied to the fabrication method for zero-misalignment blind via mating of high-order HDI circuit boards as described in any one of claims 1-5, characterized in that, include: The preprocessing module is used to perform surface preprocessing on the high-end HDI circuit board substrate, and after the surface preprocessing is completed, to perform optical scanning of multi-layer alignment marks and establish a coordinate reference model. The correction module is used to perform interlayer matching and positioning between the borehole layer and the docking layer based on the coordinate reference model, and to correct the interlayer deviation in real time through bidirectional image alignment recognition and error compensation algorithm to obtain alignment coordinate data with zero misalignment. The module is used to perform high-precision laser drilling based on zero-misalignment alignment coordinate data, thereby enabling the laser beam to achieve synchronous focusing and energy adjustment at different levels, and to perform metallization deposition after the drilling process is completed. The optimization module is used to perform global detection and local verification using detection equipment after completing the multi-layer blind via connection. The global detection results are used to obtain the actual position of the blind via. The actual position of the blind via is compared with the coordinate reference model. If there is a deviation, a secondary repair plating is performed to ensure that the blind via connection of high-order HDI circuit boards achieves zero misalignment.

7. A computer-readable storage medium, characterized in that: The device stores instructions that, when executed on a computer, cause the computer to perform a method for manufacturing a high-order HDI circuit board with zero misalignment of blind vias as described in any one of claims 1 to 6.

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