Realization method of light-induced linear reconfigurable artificial synapse

Abstract

The invention provides an implementation method based on light-induced linear reconfigurable artificial synapses, and belongs to the technical field of neuromorphic electronic devices and intelligent sensing signal preprocessing. The method comprises the following steps: providing an artificial synapse transistor capable of regulating and controlling conductance through voltage pulses, irradiating visible light in a channel or a conductance modulation area of the artificial synapse transistor, applying continuous voltage pulses under an illumination condition, reading the conductance in a preset time window after the last pulse is ended, and taking the conductance as a weight value of a corresponding pulse sequence; by adjusting illumination parameters, conductance is converted from nonlinearity to linearity along with the pulse number relation, the nonlinear factor is reduced compared with the dark state, the linear interval is widened, and linearity reconstruction in the weight updating process is achieved. According to the method, reconfigurable linear weight modulation can be obtained only by means of a light field and simple pulse driving, the method is suitable for high-fidelity compression coding of 5-bit and above time sequence pulses, feature separability and recognition accuracy can be remarkably improved in handwritten number recognition, handwriting identification and other scenes, and training time and energy consumption are reduced.

Description

Technical Field

[0001] This invention belongs to the field of neuromorphic computing and neuromorphic electronics technology, specifically relating to a reconfigurable method for linearizing artificial synaptic weights through illumination control devices. It can be applied to low-power edge intelligence scenarios such as spiking neural network training, temporal information preprocessing, and high-fidelity compression of sensory information. Background Technology

[0002] Artificial synapses, as fundamental units of neuromorphic hardware systems, possess conductance that can be progressively adjusted under continuous voltage pulses, serving to store polymorphic weights and regulate plasticity in biological synapses. However, most existing artificial synaptic devices exhibit inherent nonlinear weight update characteristics: under the same pulse excitation, the device conductance rapidly increases in the initial stage, but quickly enters the saturation region in subsequent pulses, causing the increment to decay exponentially with the number of pulses. This non-uniform response of "excessive change in the early stage and slow change in the later stage" leads to a significant inconsistency in the weight update step size with the state, making it difficult for the device to achieve stable and precise adjustment when approaching the target weight. This can easily result in overprogramming or underprogramming, thus failing to meet the requirements of deep neural networks and spiking neural networks for high linearity, constant step size, and multi-level controllable weight writing. Furthermore, in intelligent sensing tasks such as handwriting, speech, and touch, artificial synapses are often used for dynamic temporal preprocessing of raw signals to enhance key features and improve backend recognition performance. However, nonlinear weight mapping compresses the effective dynamic range of conductance, preventing the uniform expression of key information such as pulse density and start-end time variations in the temporal signal. This leads to feature distortion and reduced separability, hindering high-fidelity dynamic feature extraction. Although existing research has attempted to extend the linear update range through multi-level amplitude pulses, duty cycle modulation, or the use of layered dielectrics, multi-gate structures, and interface engineering, these approaches typically rely on complex pulse-driven strategies or device structure modifications. This increases the burden on the manufacturing process and peripheral circuits, raising manufacturing costs and integration difficulties, making it difficult to meet the needs of edge intelligent systems for low-cost, large-scale, and directly deployable artificial synapse arrays. Therefore, there is an urgent need for a weight linearization method that is not strongly coupled to the material system, requires no complex structural modifications, and is easy to integrate, in order to fundamentally improve the problems of weight error accumulation, temporal feature distortion, and increased system complexity caused by nonlinearity. Summary of the Invention

[0003] The purpose of this invention is to use photosensitive IGZO synaptic transistors as the device basis, and by setting visible light irradiation conditions of specific wavelengths and intensities, and cooperating with appropriate gate pulses and drain bias voltages, to enable the IGZO synaptic device to reconstruct under the light intensity: the conductance-pulse relationship switches from highly nonlinear to near linear, thereby achieving flexible control of linear weight updates on the same device, which is beneficial for high-fidelity compression coding of timing signals and subsequent neural network training.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A method for realizing a photo-induced linearly reconfigurable artificial synapse provides an artificial synapse transistor whose conductance can be adjusted by voltage pulses. Visible light is irradiated in its channel or conductance modulation region. Continuous voltage pulses are applied under illumination conditions, and the conductance is read within a predetermined time window after the last pulse ends, and used as the weight value of the corresponding pulse sequence. By adjusting the illumination parameters, the relationship between conductance and the number of pulses is changed from nonlinear to linear. The nonlinearity factor is reduced compared to the dark state, the linear interval is widened, and the linearity of the weight update process is reconstructed.

[0006] As a preferred approach, the nonlinearity refers to the following: the conductance modulation of the artificial synaptic transistor is mainly controlled by the occupancy change of the subbandgap defect state in the channel. After the voltage pulse injects electrons, these defect states are gradually filled, causing the free carrier concentration to increase, thereby generating an electric conduction from weak to strong. In the dark state, there are a large number of empty traps. In the early stage, electrons are quickly captured, and in the later stage, they enter the slow adjustment region due to trap saturation, resulting in the weight update exhibiting typical nonlinear characteristics.

[0007] As a preferred approach, the linearity reconstruction of the weight update process refers to the following: Under visible light illumination, photogenerated carriers inject electrons into the channel region and drive the quasi-Fermi level of the channel to move towards the conduction band, causing some sub-bandgap states originally located above it to be included in the occupiable region, thereby increasing the number of tunable effective states; when photogenerated electrons fill some shallow traps and band tail states, the number of empty defect states in the system decreases, and the equivalent tunable state density increases, resulting in a more uniform conductivity increment for each subsequent pulse under a similar carrier background; overall, illumination expands the effective window of modulated conductivity, making the conductivity increase more smoothly with the number of pulses, thereby improving the linearity of the weight update.

[0008] As a preferred method, visible light with a wavelength of 400-800 nm and an illuminance of 100-10000 lux is irradiated in its channel or conductivity modulation region.

[0009] As a preferred method, no fewer than 20 continuous voltage pulses are applied under illumination conditions.

[0010] As a preferred method, the relationship between conductivity and the number of pulses is changed from nonlinear to near linear by adjusting the illumination parameters, and the nonlinearity factor is reduced by at least 40% compared with the dark state.

[0011] As a preferred method, the artificial synaptic transistor is an oxide transistor;

[0012] And / or when fabricating synaptic transistors, ensure that the functional layer channel faces upwards to receive light.

[0013] As a preferred method, the fabrication method of the artificial synaptic transistor is as follows: the synaptic transistor includes a gate, a gate dielectric layer, an amorphous In-Ga-Zn-O channel layer, a source, and a drain. The channel layer is disposed on the gate dielectric layer, and at least one side is exposed to the outside to receive light. The specific fabrication process is as follows:

[0014] (1) Substrate pretreatment: First, the silicon nitride Si3N4 substrate is cleaned, including ultrasonic cleaning with acetone, isopropanol and deionized water in sequence.

[0015] (2) Precursor preparation: Using ethylene glycol methyl ether as solvent, prepare an IGZO precursor solution with a concentration of 0.3 mol / L, In:Ga:Zn = 5:2:1, and add an appropriate amount of ethanolamine as a stabilizer. The precursor solution is fully dissolved under ultrasonic conditions and aged at room temperature for 12 hours.

[0016] (3) IGZO thin film deposition and channel formation: A two-stage spin coating process was adopted, with a precursor concentration of 0.3 mol / L. The spin coating was carried out at 4500 rpm for 50 seconds, followed by pre-annealing at 150°C for 2 minutes to form an IGZO thin film with a thickness of about 60 nm on the substrate. Subsequently, the film was annealed at 370°C for 1 hour to improve the density and stability of the film. Then, the IGZO area was patterned using positive photoresist, and the channel was etched by wet etching with 5 wt% nitric acid solution for 5 seconds. Finally, the photoresist was stripped to complete the channel patterning.

[0017] (4) Source and drain electrode fabrication: The source and drain electrode regions were patterned using a lift-off process with negative photoresist, followed by deposition of a 100 nm thick gold Au electrode by ion beam evaporation; after completion, acetone was removed and annealed at 110°C for 5 minutes to enhance the contact performance between the electrode and the channel interface.

[0018] As a preferred embodiment, the synaptic transistor channel layer is disposed on the gate dielectric layer, the channel layer having a thickness of 30–80 nm, the gate dielectric being a 200–400 nm thick silicon nitride layer, and the source, drain, and gate being made of Au.

[0019] As a preferred method, irradiating with visible light and applying a continuous voltage pulse under illumination conditions includes the following steps:

[0020] (1) Lighting setting steps:

[0021] Visible light is irradiated in the channel layer region, wherein the center wavelength of the visible light is 460–520 nm, preferably 470–500 nm, and the illuminance is 1000–7000 lux, so that the channel is in a predetermined illumination state.

[0022] (2) Pulse modulation steps:

[0023] Under the above illumination conditions, N negative voltage pulses are applied to the gate, where N≥20, preferably 20~40, the amplitude of each negative voltage pulse is -8~-22 V, preferably -10 V, the pulse width is 0.05~0.2 s, and the pulse interval is 0.05~0.5 s; at the same time, a drain voltage of 0.1~1 V is applied between the source and the drain, so that the conductance of the synaptic transistor increases monotonically with the number of pulses;

[0024] (3). Weight reading steps:

[0025] Within 10–200 ms after the last negative voltage pulse ends, the conductance value of the synaptic transistor is read at a preset readout voltage, and this conductance value is used as the weight value for the corresponding number of pulses; as the number of pulses increases from 1 to N, a set of weight value sequences can be obtained.

[0026] (4). Linear metric steps:

[0027] To further quantitatively analyze the regulatory effect of illumination on synaptic linearity, and to characterize the dynamic process of conductance gradually approaching steady state, the conductance-pulse relationship can be fitted using an exponential growth model:

[0028]

[0029] Where p is the number of pulses, G p To correspond to the conductance, B and v are fitting parameters. This model is equivalent to a capacitor charging process, with the nonlinear factor v and the equivalent capacitor charging time being related. ,Right now:

[0030]

[0031] Among them, the reduction of the nonlinear factor v is an important indicator of the improvement of quantization linearity, because When the time constant As the resistance increases, the rate of steady-state evolution of the electrical conduction slows down, and the weight updates become smoother, resulting in higher linearity. In other words, the key to enhancing linearity lies in increasing the equivalent resistance. With equivalent capacitance Thus increase The nonlinear factor v can be obtained by fitting the electrodynamic curve and extracting parameters.

[0032] Therefore, by adjusting the illuminance, the value of the nonlinear factor v can be continuously adjusted within a certain range, thereby achieving the linear reconstruction of the weight update curve.

[0033] The working principle of this invention is as follows:

[0034] The conductance modulation of artificial synaptic transistors is primarily controlled by the occupancy changes of subbandgap defect states within the channel. After a voltage pulse injects electrons, these defect states are gradually filled, increasing the free carrier concentration and resulting in a weak-to-strong conductance modulation. In the dark state, there are numerous empty traps, leading to rapid electron capture initially, followed by slow adjustment due to trap saturation, resulting in typical nonlinear characteristics in weight updates. Under illumination, photogenerated carriers inject electrons into the channel region, pushing the quasi-Fermi level towards the conduction band. This brings some subbandgap states previously located above the Fermi level into the occupancy region, increasing the number of tunable effective states. When photogenerated electrons fill some shallow traps and band tail states, the number of empty defect states decreases, increasing the equivalent tunable state density. This results in a more uniform conductance increment for each subsequent pulse against a similar carrier background. Overall, illumination expands the effective window for modulated conductance, making the conductance increase more smoothly with increasing pulse number, thus significantly improving the linearity of weight updates.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] (1) Reconfigurable linearization

[0037] This invention does not require changes to the material system and hierarchical structure of artificial synaptic transistors. It significantly improves the linearity of the conductance-pulse relationship simply by using visible light of appropriate wavelength and illuminance in conjunction with simple pulse stimulation. This method avoids high-cost solutions such as multi-gate structures, multilayer dielectrics, and complex pulse engineering, offering strong process compatibility and suitability for large-scale integration.

[0038] (2) 5-bit high-fidelity data compression

[0039] Under the photoinduced linear modulation conditions of this invention, the conductivity modulation range is wider and the state distribution is more uniform, enabling the formation of [something] within a finite conductivity window. A highly distinguishable weighted state significantly reduces state overlap and quantization distortion, thereby achieving high-fidelity timing compression of 5-bit or even higher bit widths.

[0040] (3) Dynamic feature extraction of handwriting recognition

[0041] The linearized weight update process of this invention has a lower nonlinearity factor, enabling it to more evenly map key dynamic features such as start and end points and acceleration changes in the writing trajectory. The compressed conductance sequence exhibits better inter-class separability, making it suitable for tasks such as handwriting recognition and handwriting identification, and can effectively improve the recognition accuracy of downstream classifiers or neural networks. Attached Figure Description

[0042] Figure 1This is a structural diagram of the IGZO artificial synaptic transistor device of the present invention.

[0043] Figures 2(a), 2(b), and 2(c) show the conductivity variation curves and optical modulation linearity behavior under wavelengths of 365 nm, 480 nm, and 580 nm, respectively, for conditions ranging from 0 to 7200 lux.

[0044] Figure 3 This invention illustrates the effect of light intensity at different wavelengths on the linearity of the device.

[0045] Figure 4 This is a comparison of the recognition performance of the device of the present invention under 5-bit feature compression in light / dark conditions.

[0046] in

[0047] (a) Schematic diagram of feature extraction and recognition of handwritten digits under raw input, dark state compression and light state compression in MNIST;

[0048] (b) Changes in recognition accuracy during training under different preprocessing conditions;

[0049] (c) Recognition accuracy under different preprocessing methods;

[0050] (d) Comparison of ANN model training time.

[0051] Figure 5 This document presents the preprocessing procedure and classification results for handwriting identification using the device of this invention under light / dark conditions.

[0052] in

[0053] (a) Schematic diagram of handwriting identification principle;

[0054] (b) Extraction results of handwriting brightness distribution and intensity characteristics;

[0055] (c) Template similarity;

[0056] (d) SVM recognition accuracy. Detailed Implementation

[0057] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0058] Example 1

[0059] This embodiment provides a method for realizing a photo-induced linearly reconfigurable artificial synapse. It provides an artificial synapse transistor whose conductance can be adjusted by voltage pulses. Visible light is irradiated in its channel or conductance modulation region. Continuous voltage pulses are applied under illumination conditions, and the conductance is read within a predetermined time window after the last pulse ends, and used as the weight value of the corresponding pulse sequence. By adjusting the illumination parameters, the relationship between conductance and the number of pulses is changed from nonlinear to linear. The nonlinearity factor is reduced compared to the dark state, the linear interval is widened, and the linearity of the weight update process is reconstructed.

[0060] Furthermore, the nonlinearity refers to the fact that the conductance modulation of the artificial synaptic transistor is mainly controlled by the occupancy change of the subbandgap defect states in the channel. After the voltage pulse injects electrons, these defect states are gradually filled, causing the free carrier concentration to increase, thereby generating an electric conduction from weak to strong. In the dark state, there are a large number of empty traps. In the early stage, electrons are quickly captured, and in the later stage, they enter the slow adjustment region due to trap saturation, resulting in the weight update exhibiting typical nonlinear characteristics.

[0061] Furthermore, the linearity reconstruction of the weight update process refers to the following: under visible light illumination, photogenerated carriers inject electrons into the channel region and drive the quasi-Fermi level of the channel to move towards the conduction band, so that some sub-bandgap states originally located above it are included in the occupancy region, thereby increasing the number of tunable effective states; when photogenerated electrons fill some shallow traps and band tail states, the number of empty defect states in the system decreases, and the equivalent tunable state density increases, so that each subsequent pulse produces a more uniform conductivity increment under a similar carrier background; overall, illumination expands the effective window of modulated conductivity, making the conductivity increase more smoothly with the increase of pulse number, thereby improving the linearity of weight update.

[0062] Furthermore, visible light with a wavelength of 400-800 nm and an illuminance of 100-10000 lux is irradiated in its channel or conductivity modulation region.

[0063] Furthermore, no fewer than 20 continuous voltage pulses are applied under illumination conditions.

[0064] Furthermore, by adjusting the illumination parameters, the relationship between conductivity and the number of pulses was changed from nonlinear to near linear, and the nonlinearity factor was reduced by at least 40% compared to the dark state.

[0065] Furthermore, the artificial synaptic transistor is an oxide transistor;

[0066] And / or when fabricating synaptic transistors, ensure that the functional layer channel faces upwards to receive light.

[0067] Example 2

[0068] This embodiment provides a method for realizing a photo-induced linearly reconfigurable artificial synapse, which differs from Embodiment 1 in that: the method for fabricating the artificial synaptic transistor in this invention is as follows:

[0069] The synaptic transistor includes a gate, a gate dielectric layer, an amorphous In-Ga-Zn-O channel layer, a source, and a drain. The channel layer is disposed on the gate dielectric layer, and at least one side is exposed to the outside to receive light. The specific fabrication process is as follows:

[0070] (1) Substrate pretreatment: First, the silicon nitride Si3N4 substrate is cleaned, including ultrasonic cleaning with acetone, isopropanol and deionized water in sequence.

[0071] (2) Precursor preparation: Using ethylene glycol methyl ether as solvent, prepare an IGZO precursor solution with a concentration of 0.3 mol / L, In:Ga:Zn = 5:2:1, and add an appropriate amount of ethanolamine as a stabilizer. The precursor solution is fully dissolved under ultrasonic conditions and aged at room temperature for 12 hours.

[0072] (3) IGZO thin film deposition and channel formation: A two-stage spin coating process was adopted, with a precursor concentration of 0.3 mol / L. The spin coating was carried out at 4500 rpm for 50 seconds, followed by pre-annealing at 150°C for 2 minutes to form an IGZO thin film with a thickness of about 60 nm on the substrate. Subsequently, the film was annealed at 370°C for 1 hour to improve the density and stability of the film. Then, the IGZO area was patterned using positive photoresist, and the channel was etched by wet etching with 5 wt% nitric acid solution for 5 seconds. Finally, the photoresist was stripped to complete the channel patterning.

[0073] (4) Source and drain electrode fabrication: The source and drain electrode regions were patterned using a lift-off process with negative photoresist, followed by deposition of a 100 nm thick gold Au electrode by ion beam evaporation; after completion, acetone was removed and annealed at 110°C for 5 minutes to enhance the contact performance between the electrode and the channel interface.

[0074] Furthermore, the synaptic transistor channel layer is disposed on the gate dielectric layer, the channel layer has a thickness of 30-80 nm, the gate dielectric is a silicon nitride layer with a thickness of 200-400 nm, and the source, drain, and gate are made of Au.

[0075] Example 3

[0076] This embodiment provides a method for realizing a photoinduced linear reconfigurable artificial synapse, which differs from Embodiment 1 in that: irradiating with visible light and applying continuous voltage pulses under illumination conditions includes the following steps:

[0077] (1) Lighting setting steps:

[0078] Visible light is irradiated in the channel layer region, wherein the center wavelength of the visible light is 460–520 nm, preferably 470–500 nm, and the illuminance is 1000–7000 lux, so that the channel is in a predetermined illumination state.

[0079] (2) Pulse modulation steps:

[0080] Under the above illumination conditions, N negative voltage pulses are applied to the gate, where N≥20, preferably 20~40, the amplitude of each negative voltage pulse is -8~-22 V, preferably -10 V, the pulse width is 0.05~0.2 s, and the pulse interval is 0.05~0.5 s; at the same time, a drain voltage of 0.1~1 V is applied between the source and the drain, so that the conductance of the synaptic transistor increases monotonically with the number of pulses;

[0081] (3). Weight reading steps:

[0082] Within 10–200 ms after the last negative voltage pulse ends, the conductance value of the synaptic transistor is read at a preset readout voltage, and this conductance value is used as the weight value for the corresponding number of pulses; as the number of pulses increases from 1 to N, a set of weight value sequences can be obtained.

[0083] (4). Linear metric steps:

[0084] To further quantitatively analyze the regulatory effect of illumination on synaptic linearity, and to characterize the dynamic process of conductance gradually approaching steady state, the conductance-pulse relationship can be fitted using an exponential growth model:

[0085]

[0086] Where p is the number of pulses, G p To correspond to the conductance, B and v are fitting parameters. This model is equivalent to a capacitor charging process, with the nonlinear factor v and the equivalent capacitor charging time being related. ,Right now:

[0087]

[0088] Among them, the reduction of the nonlinear factor v is an important indicator of the improvement of quantization linearity, because When the time constant As the resistance increases, the rate of steady-state evolution of the electrical conduction slows down, and the weight updates become smoother, resulting in higher linearity. In other words, the key to enhancing linearity lies in increasing the equivalent resistance. With equivalent capacitance Thus increase The nonlinear factor v can be obtained by fitting and extracting parameters through electrodynamic curves;

[0089] Therefore, by adjusting the illuminance, the value of the nonlinear factor v can be continuously adjusted within a certain range, thereby achieving the linear reconstruction of the weight update curve.

[0090] Example 4

[0091] This embodiment provides a method for realizing a photoinduced linear reconfigurable artificial synapse, including the following steps:

[0092] 1. Fabrication steps of IGZO synaptic transistors:

[0093] A synaptic transistor is provided. The synaptic transistor of the present invention includes a gate, a gate dielectric layer, an amorphous In-Ga-Zn-O channel layer, a source, and a drain. The channel layer is disposed on the gate dielectric layer, and at least one side is exposed to the outside to receive light. The structure is as follows. Figure 1 As shown. The channel layer thickness of the device of the present invention is preferably 30–80 nm, the gate dielectric is preferably a 200–400 nm thick silicon nitride layer, and the source, drain, and gate are made of Au. The specific fabrication process is as follows:

[0094] (1) Substrate pretreatment: First, the silicon nitride (Si3N4) substrate is cleaned, including ultrasonic cleaning with acetone, isopropanol and deionized water in sequence.

[0095] (2) Precursor preparation: An IGZO precursor solution with a concentration of 0.3 mol / L (In:Ga:Zn = 5:2:1) was prepared using ethylene glycol methyl ether as a solvent, and an appropriate amount of ethanolamine was added as a stabilizer. The precursor solution was fully dissolved under ultrasonic conditions and aged at room temperature for 12 hours.

[0096] (3) IGZO thin film deposition and channel formation: A two-stage spin-coating process (0.3 mol / L precursor concentration) was used, with spin-coating at 4500 rpm for 50 seconds and pre-annealing at 150°C for 2 minutes to form an IGZO thin film with a thickness of approximately 60 nm on the substrate. Subsequently, annealing was carried out at 370°C for 1 hour to improve the film density and stability. Next, the IGZO regions were patterned using positive photoresist, and the channels were etched using a 5 wt% nitric acid solution for 5 seconds. Finally, the photoresist was stripped to complete the channel patterning.

[0097] (4) Source and drain electrode fabrication: The source and drain electrode regions were patterned using a lift-off process with negative photoresist, followed by deposition of 100 nm thick gold (Au) electrodes by ion beam evaporation. After completion, acetone was removed and the electrodes were annealed at 110°C for 5 minutes to enhance the contact performance between the electrodes and the channel interface.

[0098] 2. Lighting settings steps:

[0099] Visible light is irradiated in the channel layer region, with the center wavelength of the visible light being 460–520 nm, preferably 470–500 nm, and the illuminance being 1000–7000 lux, so that the channel is in a predetermined illumination state.

[0100] 3. Pulse modulation steps:

[0101] Under the illumination conditions of step 2, N negative voltage pulses are applied to the gate, where N ≥ 20, preferably 20–40. The amplitude of each negative voltage pulse is -8 to -22 V, preferably -10 V, the pulse width is 0.05–0.2 s, and the pulse interval is 0.05–0.5 s; simultaneously, a drain voltage of 0.1–1 V is applied between the source and drain, so that the conductance of the synaptic transistor increases monotonically with the number of pulses.

[0102] 4. Weight reading steps:

[0103] Within 10–200 ms after the last negative voltage pulse ends, the conductance value of the synaptic transistor is read at a preset readout voltage, and this conductance value is used as the weight value for the corresponding number of pulses; as the number of pulses increases from 1 to N, a set of weight value sequences can be obtained.

[0104] 5. Linearity metric steps:

[0105] To further quantitatively analyze the regulatory effect of illumination on synaptic linearity, and to characterize the dynamic process of conductance gradually approaching steady state, the conductance-pulse relationship can be fitted using an exponential growth model:

[0106]

[0107] in For the number of pulses, For the corresponding conductance, and These are the fitting parameters. This model is equivalent to a capacitor charging process, with a nonlinear factor... With equivalent time capacitor charging time ,Right now:

[0108]

[0109] Among them, nonlinear factors The reduction of is an important indicator of improved quantization linearity. Because When the time constant As the resistance increases, the rate of steady-state evolution of the electrical conduction slows down, and the weight updates become smoother, resulting in higher linearity. In other words, the key to enhancing linearity lies in increasing the equivalent resistance. With equivalent capacitance Thus increase The nonlinear factor can be obtained by fitting and extracting parameters from the electrodynamic curves in Figure 2. .

[0110] Therefore, by adjusting the illuminance, the nonlinear factor can be continuously adjusted within a certain range. The numerical values ​​are used to reconstruct the linear weight update curve.

[0111] Performance testing

[0112] (1) Effect of light intensity on linearity

[0113] like Figure 3 As shown, by changing only the illuminance, the 480 nm illuminance was set to 0, 1800, 3600, 5400, and 7200 lux, respectively, and the conductivity-pulse curves under different light intensities were obtained.

[0114] The nonlinear factors obtained by fitting the exponential model are as follows:

[0115] 0 lux condition: ;

[0116] 1800 lux conditions: ;

[0117] 3600 lux conditions: ;

[0118] 5400 lux conditions: ;

[0119] 7200 lux conditions: .

[0120] Meanwhile, the nonlinear factor decreases monotonically with increasing illuminance. This indicates that light intensity is beneficial for increasing the linearity of device weight updates.

[0121] (2) An example of applying this method to 5-bit timing compression

[0122] like Figure 4 As shown, under both dark and light conditions, a 5-bit binary time-series pulse sequence (each bit corresponding to a "present / absent" pulse within a time window) is mapped to 2... 5=32 conductance states, utilizing short-time plasticity and natural relaxation to achieve temporal compression from 5-bit to 32 modes. In the dark state, due to the nonlinearity of weight updates, the conductance span covered by 5 pulses is limited, and the 32 modes partially overlap. After applying the photo-induced linear modulation of this invention, the conductance increment contributed by each pulse is approximately equal, the conductance span is significantly increased, and the 32 modes are completely separated at the readout time. Further, this 5-bit compressed feature is applied to MNIST handwritten digit recognition. The results show that compared with the uncompressed original input (about 83%) and dark state compression (about 93%), the classification accuracy of the illumination linear compression is improved to about 97%, while the overall training time is reduced by about 77.5%, proving that this method achieves high compression ratio while taking into account feature fidelity and training efficiency.

[0123] (3) Based on the application of this method in handwriting identification scenarios

[0124] like Figure 5 As shown in the embodiment, real and forged handwriting samples from the SVC2004 dataset are selected. The writing trajectory is converted into a grayscale (or pressure) matrix in chronological order and further encoded into a temporal pulse sequence. This sequence is then written into a synaptic transistor array under both dark conditions and the linearized illumination conditions of this invention, resulting in conductivity feature maps containing temporal information. Based on these feature maps, the similarity distribution between the test sample and the real template is calculated. The results show that: the original image relies only on static brightness information, and the real and fake similarity intervals highly overlap, with a gap of approximately 0.161; after device preprocessing, dynamic features such as writing speed, pressure, and rhythm are mapped into the conductivity mode, increasing the real and fake gap to approximately 0.20; under linearized illumination conditions, the temporal features are preserved more uniformly and stably, further increasing the gap to approximately 0.24. The corresponding SVM classification results show that the recognition accuracy of the original input is about 78.5%, and the device preprocessing significantly improves the classification performance. When the photo-induced linear preprocessing of the present invention is used, the recognition accuracy can be increased to about 97%, which proves that the method can amplify the dynamic differences between genuine and fake handwriting and significantly enhance the discrimination ability and robustness of handwriting identification.

[0125] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for realizing a photoinduced linearly reconfigurable artificial synapse, characterized in that: An artificial synaptic transistor with conductance adjustable by voltage pulses is provided. Visible light is irradiated in its channel or conductance modulation region. Continuous voltage pulses are applied under illumination conditions, and the conductance is read within a predetermined time window after the last pulse ends, and used as the weight value of the corresponding pulse sequence. By adjusting the illumination parameters, the relationship between conductivity and the number of pulses is transformed from nonlinear to linear. The nonlinearity factor is reduced compared to the dark state, the linear interval is widened, and the linearity of the weight update process is reconstructed.

2. The method for realizing a photoinduced linearly reconfigurable artificial synapse according to claim 1, characterized in that: The nonlinearity refers to: The conductance modulation of artificial synaptic transistors is mainly controlled by the occupancy change of subbandgap defect states in the channel. After the voltage pulse injects electrons, these defect states are gradually filled, causing the free carrier concentration to increase, thereby generating an electric conduction from weak to strong. In the dark state, there are more empty traps. In the early stage, electrons are captured rapidly, and in the later stage, they enter the slow adjustment region due to trap saturation, resulting in the weight update exhibiting typical nonlinear characteristics.

3. The method for realizing a photoinduced linearly reconfigurable artificial synapse according to claim 1, characterized in that: The linearity reconstruction of the weight update process refers to: Under visible light illumination, photogenerated carriers inject electrons into the channel region, driving the quasi-Fermi level of the channel to shift towards the conduction band. This brings some sub-bandgap states that were originally located above it into the occupied region, thereby increasing the number of tunable effective states. When photogenerated electrons fill some shallow traps and band tail states, the number of empty defect states in the system decreases, and the equivalent tunable state density increases, resulting in a more uniform conductivity increment for each subsequent pulse under a similar carrier background. Overall, illumination expands the effective window of modulated conductivity, making the conductivity increase more smoothly with the number of pulses, thereby improving the linearity of weight updates.

4. The method for realizing a photoinduced linearly reconfigurable artificial synapse according to claim 1, characterized in that: Irradiate its channel or conductivity modulation region with visible light of wavelength 400~800 nm and illuminance of 100~10000 lux.

5. The method for realizing a photoinduced linearly reconfigurable artificial synapse according to claim 1, characterized in that: No fewer than 20 continuous voltage pulses are applied under illumination conditions.

6. The method for realizing a photoinduced linearly reconfigurable artificial synapse according to claim 1, characterized in that: By adjusting the illumination parameters, the relationship between conductivity and the number of pulses is changed from nonlinear to near-linear, and the nonlinearity factor is reduced by at least 40% compared to the dark state.

7. The method for realizing a photoinduced linearly reconfigurable artificial synapse according to claim 1, characterized in that: Artificial synaptic transistors are oxide transistors; And / or when fabricating synaptic transistors, ensure that the functional layer channel faces upwards to receive light.

8. The method for realizing a photoinduced linearly reconfigurable artificial synapse according to claim 1, characterized in that: The method for fabricating artificial synaptic transistors is as follows: The synaptic transistor includes a gate, a gate dielectric layer, an amorphous In-Ga-Zn-O channel layer, a source, and a drain. The channel layer is disposed on the gate dielectric layer, and at least one side is exposed to the outside to receive light. The specific fabrication process is as follows: (1) Substrate pretreatment: First, the silicon nitride Si3N4 substrate is cleaned, including ultrasonic cleaning with acetone, isopropanol and deionized water in sequence; (2) Precursor preparation: Using ethylene glycol methyl ether as solvent, prepare an IGZO precursor solution with a concentration of 0.3 mol / L, In:Ga:Zn = 5:2:1, and add an appropriate amount of ethanolamine as a stabilizer. The precursor solution is fully dissolved under ultrasonic conditions and aged at room temperature for 12 hours. (3) IGZO thin film deposition and channel formation: A two-stage spin coating process was adopted, with a precursor concentration of 0.3 mol / L. The spin coating was carried out at 4500 rpm for 50 seconds, followed by pre-annealing at 150°C for 2 minutes to form an IGZO thin film with a thickness of about 60 nm on the substrate. Subsequently, the film was annealed at 370°C for 1 hour to improve the density and stability of the film. Then, the IGZO area was patterned using positive photoresist, and the channel was etched by wet etching with 5 wt% nitric acid solution for 5 seconds. Finally, the photoresist was stripped to complete the channel patterning. (4) Source and drain electrode fabrication: The source and drain electrode regions were patterned using a lift-off process with negative photoresist, followed by deposition of a 100 nm thick gold Au electrode by ion beam evaporation; after completion, acetone was removed and annealed at 110°C for 5 minutes to enhance the contact performance between the electrode and the channel interface.

9. The method for realizing a photoinduced linearly reconfigurable artificial synapse according to claim 8, characterized in that: The synaptic transistor channel layer is disposed on the gate dielectric layer, the channel layer having a thickness of 30–80 nm, the gate dielectric being a 200–400 nm thick silicon nitride layer, and the source, drain, and gate being made of Au.

10. The method for realizing a photoinduced linearly reconfigurable artificial synapse according to claim 1, characterized in that: Irradiating with visible light and applying continuous voltage pulses under illumination conditions include the following steps: (1) Lighting setting steps: Visible light is irradiated in the channel layer region, wherein the center wavelength of the visible light is 460–520 nm, preferably 470–500 nm, and the illuminance is 1000–7000 lux, so that the channel is in a predetermined illumination state. (2) Pulse modulation steps: Under the above illumination conditions, N negative voltage pulses are applied to the gate, where N≥20, preferably 20~40, the amplitude of each negative voltage pulse is -8~-22 V, preferably -10 V, the pulse width is 0.05~0.2 s, and the pulse interval is 0.05~0.5 s; at the same time, a drain voltage of 0.1~1 V is applied between the source and the drain, so that the conductance of the synaptic transistor increases monotonically with the number of pulses; (3). Weight reading steps: Within 10–200 ms after the last negative voltage pulse ends, the conductance value of the synaptic transistor is read at a preset readout voltage, and this conductance value is used as the weight value for the corresponding number of pulses; as the number of pulses increases from 1 to N, a set of weight value sequences can be obtained. (4). Linear metric steps: To further quantitatively analyze the regulatory effect of illumination on synaptic linearity, and to characterize the dynamic process of conductance gradually approaching steady state, the conductance-pulse relationship can be fitted using an exponential growth model: Where p is the number of pulses, G p To correspond to the conductance, B and v are fitting parameters. This model is equivalent to a capacitor charging process, with the nonlinear factor v and the equivalent capacitor charging time being related. ,Right now: Among them, the reduction of the nonlinear factor v is an important indicator of the improvement of quantization linearity, because When the time constant As the resistance increases, the rate of steady-state evolution of the electrical conduction slows down, and the weight updates become smoother, resulting in higher linearity. In other words, the key to enhancing linearity lies in increasing the equivalent resistance. With equivalent capacitance Thus increase The nonlinear factor v can be obtained by fitting and extracting parameters through electrodynamic curves; Therefore, by adjusting the illuminance, the value of the nonlinear factor v can be continuously adjusted within a certain range, thereby achieving the linear reconstruction of the weight update curve.

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