Chip failure analysis path grading decision and intelligent management and control method

Abstract

The present application relates to the technical field of chip failure analysis, and particularly relates to a chip failure analysis path grading decision and intelligent management and control method, comprising: determining whether to perform data optimization to obtain an optimized target analysis model according to a path abnormal frequency ratio of the target analysis model; in the data optimization, a supplement strategy of associated data supplement is adopted, and whether the supplement strategy includes failure analysis supplement is determined according to a high-frequency associated abnormal chip data proportion; in the failure analysis supplement, whether a parameter is an outlier parameter is determined according to a related reference value or a secondary determination according to a deviation recurrence frequency ratio and a parameter emergence coefficient, data supplement is performed for each outlier parameter, and whether to perform global disturbance analysis supplement is determined according to a global abnormality coefficient. The present application can improve analysis efficiency and result reliability.

Description

Technical Field

[0001] This invention relates to the field of chip failure analysis technology, and in particular to a hierarchical decision-making and intelligent control method for chip failure analysis paths. Background Technology

[0002] As chip integration and circuit complexity continue to increase, chip failure modes are becoming increasingly diverse and complex. Failure analysis, as a core component for improving chip yield, locating the root cause of failures, and optimizing chip design and manufacturing processes, has a crucial impact on cost control and cycle shortening in chip R&D and mass production due to its efficiency and the accuracy of path decision-making. While replacing traditional decision-making methods that rely entirely on the experience of senior engineers with models has improved analysis efficiency, the complexity of chip manufacturing means that model data supplementation lacks targeting, the quantitative characterization of failure features is incomplete, and its adaptability to the systematic characteristics of actual chip failures is insufficient. Therefore, how to improve the reliability of model predictions, thereby improving the overall efficiency of chip failure analysis and reducing the cost of analysis trial and error and sample loss, is a technical problem that urgently needs to be solved by those skilled in the art.

[0003] Chinese Patent Publication No. CN114076881A discloses a method, apparatus, device, and storage medium for semiconductor device failure analysis. The method includes: obtaining target detection parameters of a normal semiconductor device through physical testing. These target detection parameters include detection parameters of the failure point region on the corresponding failed semiconductor device, including surface detection parameters, elemental concentration detection parameters, and cross-sectional detection parameters of the failure point region. The obtained target detection parameters are then used as input parameters for a preset simulation algorithm. The algorithm, combined with predicted failure results, is used to determine the cause of failure in the semiconductor device. However, this approach suffers from the following problems: relying solely on physical testing to obtain normal device parameters and combining them with simulation algorithms to deduce the failure cause lacks dynamic data optimization of the analysis model and targeted supplementary analysis design, resulting in poor analysis efficiency and reliability. Summary of the Invention

[0004] To address this, the present invention provides a hierarchical decision-making and intelligent control method for chip failure analysis paths, which overcomes the problems of poor analysis efficiency and reliability caused by the lack of dynamic data optimization of analysis models and the absence of targeted supplementary analysis design in the prior art.

[0005] To achieve the above objectives, this invention provides a hierarchical decision-making and intelligent control method for chip failure analysis paths, comprising:

[0006] Determine whether to perform data optimization based on the path anomaly frequency ratio of the target analysis model to obtain an optimized target analysis model;

[0007] In data optimization, a supplementary strategy of supplementing related data is adopted, and the supplementary strategy is determined based on the proportion of high-frequency related abnormal chip data, to determine whether failure analysis supplementation is included.

[0008] In the process of supplementing related data, supplementation is based on anomaly detection parameters, and the determination of whether to supplement based on the clustering profile coefficient of the fault probability map is based on the proportion of scattered data.

[0009] In the supplementary failure analysis, outlier parameters are determined directly based on relevant reference values ​​or secondarily based on deviation recurrence frequency ratio and parameter emergence coefficient. Data is supplemented for each outlier parameter, and whether to conduct supplementary global disturbance analysis is determined based on global anomaly coefficient.

[0010] In the supplementary global disturbance analysis, supplementary data are added for each design parameter whose abnormal reference value is greater than the preset abnormal reference value, and it is determined whether to supplement based on the comparison reference mechanism according to the coefficient of variation.

[0011] The chip detection data of the failed chip is input into the optimized target analysis model to output the sampling points and the sampling point order.

[0012] Furthermore, data optimization is performed on the target analysis model where the path anomaly frequency ratio is greater than or equal to the preset path anomaly frequency ratio.

[0013] Furthermore, if the proportion of high-frequency correlated abnormal chip data is greater than or equal to the preset proportion of high-frequency correlated abnormal chip data, the supplementary strategy includes failure analysis supplementation.

[0014] Among them, high-frequency associated abnormal chip data refers to abnormal chip data where the proportion of associated failed chips is greater than the preset proportion of associated failed chips.

[0015] Furthermore, when supplementing based on anomaly detection parameters, the anomaly detection parameters are determined based on the parameter bias coefficient, and the data to be selected is supplemented for each anomaly detection parameter according to the sub-bias coefficient.

[0016] Furthermore, if the proportion of scattered data is greater than or equal to the preset proportion of scattered data, then the clustering contour coefficient based on the fault probability map is used for supplementation.

[0017] Among them, scattered data refers to abnormal chip data whose cluster profile coefficient of the fault probability map is greater than the preset cluster profile coefficient.

[0018] Furthermore, design parameters whose relevant reference values ​​are greater than or equal to preset relevant reference values ​​are directly identified as outlier parameters;

[0019] For design parameters whose relevant reference values ​​are less than preset relevant reference values, a second determination is made based on the deviation recurrence frequency ratio and the parameter emergence coefficient to determine whether they are outliers. Specifically, if the deviation recurrence frequency ratio of the design parameter is greater than or equal to the preset deviation recurrence frequency ratio and the parameter emergence coefficient is greater than or equal to the preset parameter emergence coefficient, then the design parameter is recorded as an outlier.

[0020] Furthermore, the method for confirming the deviation recurrence frequency ratio includes:

[0021] The fitting curve is obtained by fitting the span coefficient and parameter deviation corresponding to each design parameter;

[0022] The fitting deviation of each design parameter under the corresponding abnormal chip data is determined based on the deviation of the parameter corresponding to the span coefficient on the fitting curve and the deviation of the actual parameter of the design parameter.

[0023] The deviation recurrence frequency ratio of the corresponding design parameters is determined by the ratio of the number of abnormal chip data with a fitting deviation less than the preset fitting deviation to the total number of abnormal chip data.

[0024] Furthermore, if the global anomaly coefficient is greater than or equal to the preset global anomaly coefficient, then a global disturbance analysis is performed as a supplement.

[0025] Furthermore, if the coefficient of variation is greater than or equal to the preset coefficient of variation, supplementation is made based on the comparison reference mechanism.

[0026] Furthermore, when supplementing based on the comparison reference mechanism, supplementation is performed for each comparison reference mechanism, and the number of candidate data to be supplemented for a single comparison reference mechanism is positively correlated with the comparison coefficient corresponding to that comparison reference mechanism;

[0027] The comparison reference mechanism is a reference mechanism in which the comparison coefficient is greater than the preset comparison coefficient, and the reference mechanism is the associated failure mechanism corresponding to the data of each abnormal chip.

[0028] Compared with the prior art, the beneficial effects of the present invention are that, in the technical solution of the present invention, the path anomaly frequency ratio effectively reflects the accuracy of the target analysis model in representing chip failure characteristics and the data adaptability. Then, based on the path anomaly frequency ratio of the target analysis model, it is determined whether to perform data optimization. This helps to avoid blind data supplementation without a target, improves the pertinence and efficiency of data optimization of the target analysis model, and ensures the reliability of the optimized model in predicting failure analysis path decisions.

[0029] Furthermore, the supplementary strategy of using associated data in this invention can specifically mine the batch correlation characteristics and systematic failure patterns of abnormal chip data, and then specifically supplement effective training samples with associated failure attributes. When the proportion of high-frequency associated abnormal chip data is greater than or equal to the preset proportion of high-frequency associated abnormal chip data, it indicates that the associated causes of chip failure are significant. The existing model training data is not suitable for systematic failure scenarios. Failure analysis supplementation can provide targeted data supplementation, which is beneficial to improving the efficiency and accuracy of fault location in failure analysis practice.

[0030] Furthermore, the supplementation based on anomaly detection parameters in this invention can accurately locate detection parameters with significant bias characteristics in abnormal chip data, thereby optimizing the model's failure feature capture accuracy from the parameter dimension. When the proportion of scattered data is greater than or equal to the preset proportion of scattered data, the existing data is difficult to support the model in accurately learning the spatial distribution pattern of chip failure. Supplementing based on the clustering contour coefficient of the fault probability map is beneficial for screening and supplementing high-correlation samples with better clustering contour coefficients of the fault probability map and stronger spatial clustering and inter-cluster distinction of failure sub-regions, thus enriching the model's feature learning samples for the spatial distribution pattern of chip failure and improving the rationality of the model's decision-making.

[0031] Furthermore, this invention effectively reflects the linear correlation strength between design parameters and chip batch failure characteristics through relevant reference values, as well as the probability that the design parameters deviate from the linear law during the correlation analysis process. Then, based on the adaptive selection of relevant reference values, outlier parameters can be directly determined, or whether they are outlier parameters can be determined a second time based on the deviation recurrence frequency ratio and parameter emergence coefficient. This helps to improve the accuracy of outlier parameter determination, thereby providing subsequent data supplementation that can directionally cover failure causes at the design parameter level and improve the accuracy of model output.

[0032] Furthermore, when the global anomaly coefficient is greater than or equal to the preset global anomaly coefficient, it indicates that a significant global anomaly has occurred at the chip design parameter level, and the overall level of the design parameter fitting deviation exceeds a reasonable threshold. Conventional failure analysis alone is insufficient to fully cover the failure causes at the design end. Global disturbance analysis can provide targeted supplementary data for design parameters with excessive anomalies. At the same time, the supplementary strategy is improved by combining the discrete characteristics of the detection parameters with the indicative role of the failure mechanism, thereby achieving targeted data supplementation for global anomalies in design parameters and ensuring the high efficiency of failure analysis practice.

[0033] Furthermore, this invention supplements the selection data for each design parameter whose abnormal reference value is greater than the preset abnormal reference value. This is beneficial for targeted enhancement of the model's feature learning of design parameters with significant abnormality. When the coefficient of variation is greater than or equal to the preset coefficient of variation, it indicates that there is significant batch-specific discrete fluctuation in the detection parameters in the production process, poor uniformity of numerical distribution, and prominent global discrete abnormality characteristics. Targeted supplementation of design parameters alone is insufficient to cover the failure causes caused by the discreteness of detection parameters in the production end. Supplementation based on the comparison reference mechanism is beneficial for screening failure mechanisms that are highly indicative of chip failure, and for targeted supplementation of the corresponding adaptive data for such mechanisms, thereby improving the accuracy of failure analysis. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the hierarchical decision-making and intelligent control method for chip failure analysis paths according to the present invention;

[0035] Figure 2 This is a flowchart illustrating how the present invention determines whether to perform data optimization based on the path anomaly frequency ratio of the target analysis model.

[0036] Figure 3 This is a flowchart illustrating the process of determining whether a supplementary strategy includes failure analysis supplementation based on the proportion of high-frequency correlated abnormal chip data in this invention.

[0037] Figure 4 This is a flowchart illustrating the process of determining whether to perform supplementary global disturbance analysis based on the global anomaly coefficient in this invention. Detailed Implementation

[0038] To make the objectives and advantages of the present invention clearer, the present invention will be further described below with reference to embodiments; it should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0039] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0040] Please see Figures 1 to 4 As shown, this invention provides a hierarchical decision-making and intelligent control method for chip failure analysis paths, including:

[0041] Determine whether to perform data optimization based on the path anomaly frequency ratio of the target analysis model to obtain an optimized target analysis model;

[0042] In data optimization, a supplementary strategy of supplementing related data is adopted, and the supplementary strategy is determined based on the proportion of high-frequency related abnormal chip data, to determine whether failure analysis supplementation is included.

[0043] In the process of supplementing related data, supplementation is based on anomaly detection parameters, and the determination of whether to supplement based on the clustering profile coefficient of the fault probability map is based on the proportion of scattered data.

[0044] In the supplementary failure analysis, outlier parameters are determined directly based on relevant reference values ​​or secondarily based on deviation recurrence frequency ratio and parameter emergence coefficient. Data is supplemented for each outlier parameter, and whether to conduct supplementary global disturbance analysis is determined based on global anomaly coefficient.

[0045] In the supplementary global disturbance analysis, supplementary data are added for each design parameter whose abnormal reference value is greater than the preset abnormal reference value, and it is determined whether to supplement based on the comparison reference mechanism according to the coefficient of variation.

[0046] The chip detection data of the failed chip is input into the optimized target analysis model to output the sampling points and the sampling point order.

[0047] The application scenario of this invention is to supplement the training data of the target analysis model to achieve iterative optimization of the model, thereby improving the accuracy of the FA path and sampling point sequence output in the semiconductor chip failure analysis process.

[0048] The training process of the target analysis model includes: dividing the initial training data into a training set, a validation set, and a test set in a 6:2:2 ratio. The training set is used to iteratively update model parameters (such as path decision weights and sampling priority coefficients). The validation set dynamically adjusts hyperparameters (including learning rate 0.001–0.01, batch size 32–128, number of network layers 3–5, and regularization strength 0.001–0.01) by monitoring key indicators (path accuracy and decision efficiency) to optimize model performance and prevent overfitting. Finally, the test set is used to independently evaluate the model's generalization ability on unknown data (requiring a path accuracy ≥90% and a decision latency ≤100ms on the test set) to ensure its stability and reliability in real-world scenarios.

[0049] The target analysis model takes chip detection data as input and outputs sampling points and their order.

[0050] The initial training data is the training data for the target analysis model. This invention includes several selectable data sets, including chip detection data, failure analysis paths, and sampling point sequences corresponding to the chip detection data. The chip detection data contains detection parameters and their corresponding detection values ​​for each sub-region. To ensure that the spatial resolution of the detection data matches the sampling accuracy of the chip failure analysis, the chip is uniformly divided into several 100μm×100μm sub-regions. The detection parameters are the physical and electrical performance parameters obtained from the chip product after testing, used to characterize the actual failure state of the chip. Detection parameters include, but are not limited to, crack length, number of voids, void area, delamination interface area, microcrack extension depth, silicon substrate micro-defect density, hotspot area, maximum hotspot temperature, voltage, and leakage current. X-ray, CT, SAM, infrared hotspot, and non-destructive electrical parameter testing technologies can be used to detect damaged chips to obtain corresponding raw detection data. The raw detection data is then quantitatively analyzed and feature extracted to obtain the detection parameters. The sampling point order is the order in which samples are taken for chip failure analysis, and each sampling point corresponds to a 100μm×100μm sub-region of the chip.

[0051] Users can determine whether a chip is abnormal based on self-defined detection indicators. These indicators can include, but are not limited to, peak operating current and chip operating voltage fluctuation range, which will not be elaborated here. Normal chips are any chips other than abnormal ones.

[0052] Specifically, data optimization is performed on target analysis models where the path anomaly frequency ratio is greater than or equal to the preset path anomaly frequency ratio.

[0053] The present invention sets an intelligent control cycle, the duration of a single intelligent control cycle is 10 days, and at the end of a single intelligent control cycle, a path anomaly frequency ratio is determined.

[0054] In the current intelligent control cycle, when using the target analysis model to output sampling points and sampling order, the input chip detection data is recorded as reference chip detection data. For a single reference chip detection data, if the output result corresponding to that data fails to accurately locate the fault location when opening the chip, then that reference chip detection data is recorded as abnormal chip data. Failure to accurately locate the fault location means that the sampling point cannot find the fault location or that the sampling point cannot find all fault locations.

[0055] If the output results corresponding to this data can accurately locate the fault location when the chip is unpacked, then the reference chip test data is recorded as normal chip data.

[0056] The path anomaly frequency ratio is the ratio of the number of abnormal chip data to the number of reference chip detection data in the current intelligent control cycle.

[0057] The value of the preset path anomaly frequency ratio can be determined by the user based on the actual application scenario. The greater the user's need to improve the sensitivity of path anomaly identification of failed chips and the accuracy of path failure location, the smaller the value of the preset path anomaly frequency ratio will be. In this embodiment, the preset path anomaly frequency ratio is 0.1.

[0058] Specifically, if the proportion of high-frequency correlated abnormal chip data is greater than or equal to the preset proportion of high-frequency correlated abnormal chip data, the supplementary strategy includes failure analysis supplementation.

[0059] Among them, high-frequency associated abnormal chip data refers to abnormal chip data where the proportion of associated failed chips is greater than the preset proportion of associated failed chips.

[0060] Specifically, for a single abnormal chip data, the total number of chips produced by the production line corresponding to the failed chip in the intelligent control cycle where the failed chip was produced is recorded as the first quantity, the number of failed chips is recorded as the second quantity, and the proportion of associated failed chips is the ratio of the second quantity to the first quantity. The proportion of associated failed chips is used to characterize the batch correlation of chip failures. If the proportion is too high, it indicates that the failure is a systemic failure of the production line (such as process parameter deviation or process reasons), rather than a random failure of a single chip.

[0061] The user can determine the value of the preset associated failure chip percentage based on the actual application scenario. It can be understood that the associated failure chip percentage effectively reflects the batch correlation and concentrated occurrence characteristics of chip failures within the corresponding intelligent control cycle. The greater the user's demand for the sensitivity of identifying systemic failures in the production process and the accuracy of tracing batch failures, the smaller the value of the preset associated failure chip percentage. In this embodiment, the preset associated failure chip percentage is 0.37.

[0062] The proportion of high-frequency correlated abnormal chip data is the ratio of the number of high-frequency correlated abnormal chip data to the number of abnormal chip data.

[0063] The preset value of the proportion of high-frequency correlated abnormal chip data can be determined by the user according to the actual application scenario. It can be understood that the proportion of high-frequency correlated abnormal chip data shows the overall proportion level of high-frequency correlated abnormal chips in the current abnormal chip data. The larger the proportion of high-frequency correlated abnormal chip data, the higher the proportion of samples in the current failed chips that show the characteristics of systematic failure in the production process, and the more significant the trend of correlated failure. Supplementing failure analysis can specifically supplement failure analysis samples and data with systematic failure characteristics, and improve the accuracy of path identification of correlated failures. Therefore, the greater the user's demand for improving the adaptability of the target analysis model to systematic failure scenarios, the smaller the preset value of the proportion of high-frequency correlated abnormal chip data. In this embodiment, the preset proportion of high-frequency correlated abnormal chip data is 0.2.

[0064] Specifically, when supplementing based on anomaly detection parameters, the anomaly detection parameters are determined based on the parameter bias coefficient, and the data to be selected is supplemented for each anomaly detection parameter according to the sub-bias coefficient.

[0065] Specifically, the parameter bias coefficient corresponding to a single detection parameter is the average of the sub-bias coefficients corresponding to that detection parameter in the data of each abnormal chip;

[0066] The sub-bias coefficient corresponding to a single detection parameter in the abnormal chip data is the average of the abnormal comparison values ​​of the detection parameter corresponding to the abnormal chip data and each initial training data.

[0067] The abnormal alignment value of the detection parameter corresponding to a single abnormal chip data and a single initial training data is = spatial alignment degree / preset spatial alignment degree × first weight coefficient + deviation alignment degree / preset deviation alignment degree × second weight coefficient, where the first weight coefficient and the second weight coefficient are both 0.5;

[0068] For a single detection parameter, the normal range corresponding to the detection parameter is [the minimum value of the detection parameter corresponding to each sub-region of each normal chip, and the maximum value of the detection parameter corresponding to each sub-region of each normal chip];

[0069] For a single abnormal chip data, detect the sub-regions in the abnormal chip data where the detection parameter is not in the normal range, and record them as the abnormal sub-regions corresponding to the detection parameter;

[0070] The spatial alignment degree between a single anomalous chip data and a single initial training data is calculated as: quantitative difference × quantitative weight coefficient + distribution difference × distribution weight coefficient, where both the quantitative weight coefficient and the distribution weight coefficient are 0.5.

[0071] The difference in quantity between a single abnormal chip data and a single initial training data is equal to the absolute value of the difference in the number of abnormal sub-regions corresponding to the two data points / the larger of the number of abnormal sub-regions corresponding to the two data points. The difference in distribution is equal to the absolute value of the difference in the distribution coefficients of the abnormal sub-regions corresponding to the two data points / the larger of the distribution coefficients of the abnormal sub-regions corresponding to the two data points.

[0072] The distribution coefficient of an outlier subregion corresponding to a single data point is the average of the mean distances of the corresponding outlier subregions. For a single outlier subregion, this outlier subregion is designated as the target outlier subregion, and the other outlier subregions are designated as reference outlier subregions. The mean distance of the target outlier subregion is the average of the lengths of the lines connecting the center points of the target outlier subregion and the center points of the reference outlier subregions. The center point of a single subregion is the intersection of the diagonals of that subregion. If there is only one outlier subregion, the distribution coefficient of the outlier subregion is 0.

[0073] For a single detection parameter, the maximum and minimum values ​​of the parameter corresponding to a single data point are the maximum and minimum values ​​of the detection values ​​corresponding to the detection parameter in each sub-region of the data, respectively. The deviation comparison between a single abnormal chip data point and a single initial training data point = the absolute value of the difference between the maximum values ​​of the parameters corresponding to the two data points / the larger of the maximum values ​​of the parameters corresponding to the two data points × 0.5 + the absolute value of the difference between the minimum values ​​of the parameters corresponding to the two data points / the larger of the minimum values ​​of the parameters corresponding to the two data points × 0.5;

[0074] The preset spatial comparison degree and preset deviation comparison degree can be determined by the user according to the actual application scenario. The spatial comparison degree and deviation comparison degree reflect the spatial distribution characteristics and parameter extreme value deviation characteristics of chip anomalies. The greater the user's need for high-precision identification of spatial differences and parameter extreme value deviations in chip anomaly sub-regions, the smaller the preset spatial comparison degree and preset deviation comparison degree will be. In this embodiment, the preset spatial comparison degree is 0.4 and the preset deviation comparison degree is 0.3.

[0075] When determining anomaly detection parameters based on parameter bias coefficients, detection parameters whose parameter bias coefficients are greater than preset parameter bias coefficients are recorded as anomaly detection parameters.

[0076] When supplementing data for a single anomaly detection parameter based on the sub-bias coefficients, the data is supplemented in descending order of the sub-bias coefficients until the required amount of supplementary data is reached. In this embodiment, the amount of supplementary data is 10% of the initial training data.

[0077] The sub-bias coefficient corresponding to a single candidate data point is the average of the anomaly comparison values ​​of that candidate data point and the anomaly detection parameter corresponding to each of the initial training data points.

[0078] The value of the preset parameter bias coefficient can be determined by the user according to the actual application scenario. The greater the user's requirement for the accuracy of chip detection parameter anomaly identification, the smaller the value of the preset parameter bias coefficient. In this embodiment, the preset parameter bias coefficient is 0.34.

[0079] Specifically, if the proportion of scattered data is greater than or equal to the preset proportion of scattered data, then supplementation is made based on the clustering contour coefficient of the fault probability map.

[0080] Among them, scattered data refers to abnormal chip data whose cluster profile coefficient of the fault probability map is greater than the preset cluster profile coefficient.

[0081] Specifically, if the proportion of scattered data is less than the preset proportion of scattered data, then there is no need to supplement it based on the clustering contour coefficient of the fault probability map.

[0082] The failure probability map for a single failed chip contains the failure probability for each sub-region, and the failure probability for a single sub-region is the maximum value of the anomaly coefficients for each detection parameter.

[0083] For a single sub-region, the anomaly coefficient corresponding to a single detection parameter is calculated as follows: If the detection parameter is within its corresponding normal range, the anomaly coefficient for that sub-region is 0. If the detection parameter is not within its corresponding normal range, the anomaly coefficient for that sub-region is calculated as follows: If the detection value of the detection parameter is greater than any value within the normal range, the anomaly coefficient = (the detection value of the detection parameter - the maximum value of the detection parameter in each sub-region of each normal chip) / the maximum value of the detection parameter in each sub-region of each normal chip; if the detection value of the detection parameter is less than any value within the normal range, the anomaly coefficient = (the minimum value of the detection parameter in each sub-region of each normal chip - the detection value of the detection parameter) / the minimum value of the detection parameter in each sub-region of each normal chip.

[0084] For a single fault probability map, abnormal sub-regions in the fault probability map with fault probabilities greater than or equal to preset fault probabilities are categorized as high-probability sub-regions, while abnormal sub-regions in the fault probability map with fault probabilities less than preset fault probabilities are categorized as low-probability sub-regions.

[0085] The value of the preset failure probability can be determined by the user based on the accuracy requirements of failure analysis and the actual production failure scenario. The failure probability reflects the critical probability level of a sub-region being judged as a high-probability failure sub-region. The greater the user's demand for the sensitivity of failure core area identification, the smaller the value of the preset failure probability. In this embodiment, the preset failure probability is 0.4.

[0086] Intra-cluster average distance = (standard deviation of failure probability corresponding to each high-probability sub-region + standard deviation of failure probability corresponding to each low-probability sub-region) / 2;

[0087] Average inter-cluster distance = average of the failure probabilities corresponding to each high-probability sub-region - average of the failure probabilities corresponding to each low-probability sub-region;

[0088] Cluster silhouette coefficient = (average distance between clusters - average distance within clusters) / max(average distance between clusters, average distance within clusters);

[0089] Understandably, the statistical characteristics of failure probability are used to quantify intra-cluster compactness and inter-cluster separation. The average distance within a cluster represents the overall dispersion level of the failure probability within the cluster; the smaller the dispersion, the stronger the compactness. The average distance between clusters represents the degree of deviation between the centers of the probability distributions of the two clusters; the larger the difference, the higher the separation. Therefore, the cluster profile coefficient can reflect the intra-cluster clustering and inter-cluster differentiation of the failed sub-regions in the failure probability map. The smaller the cluster profile coefficient, the smaller the dispersion of the failure probability within the cluster, the stronger the compactness, and the more significant the spatial clustering of the failed sub-regions.

[0090] The value of the preset clustering profile coefficient can be determined by the user according to the actual application scenario. The greater the user's need for accurate identification of the clustering of failed sub-regions and the distinguishability between clusters, the smaller the value of the preset clustering profile coefficient. In this embodiment, the preset clustering profile coefficient is 0.3.

[0091] When supplementing based on the cluster profile coefficients of the fault probability map, select the data to be supplemented in ascending order of the cluster profile coefficients of the fault probability map until the number of supplemented data reaches 10% of the initial training data.

[0092] The proportion of scattered data is the ratio of the number of scattered data to the number of abnormal chip data.

[0093] The preset value of the scattered data proportion can be determined by the user based on the accuracy requirements of the failure analysis results. The scattered data proportion effectively reflects the overall proportion of scattered samples with poor clustering and low inter-cluster discrimination in the failure probability map of the current abnormal chip data. The larger the scattered data proportion, the higher the proportion of samples with poor clustering and scattered probability distribution in the failure probability map of the current abnormal chip. Its failure probability map cannot effectively capture the spatial correlation characteristics of chip failure, and it is difficult to accurately represent the distribution pattern of failure sub-regions through clustering contour coefficients. Supplementing with clustering contour coefficients based on the failure probability map can weaken the interference of scattered samples on the model by supplementing highly correlated samples, making the model more consistent with the actual spatial distribution pattern of chip failure. Therefore, the greater the user's demand for the effectiveness of the correlation feature representation of the failure probability map and the accuracy of the failure analysis results, the smaller the preset scattered data proportion should be. In this embodiment, the preset scattered data proportion is 0.6.

[0094] Specifically, design parameters whose relevant reference values ​​are greater than or equal to preset relevant reference values ​​are directly identified as outliers.

[0095] For design parameters whose relevant reference values ​​are less than preset relevant reference values, a second determination is made based on the deviation recurrence frequency ratio and the parameter emergence coefficient to determine whether they are outliers. Specifically, if the deviation recurrence frequency ratio of the design parameter is greater than or equal to the preset deviation recurrence frequency ratio and the parameter emergence coefficient is greater than or equal to the preset parameter emergence coefficient, then the design parameter is recorded as an outlier.

[0096] Specifically, if the deviation frequency ratio of the design parameter is less than the preset deviation frequency ratio or the parameter occurrence coefficient is less than the preset parameter occurrence coefficient, then there is no need to record the design parameter as an outlier parameter.

[0097] This invention utilizes a failure mechanism library, which includes several chip detection data and their corresponding failure mechanisms. The failure mechanisms include, but are not limited to, photoresist residue failure, over-etching failure, under-etching failure, excessive leakage current failure due to uneven oxide layer thickness, device switching characteristic degradation failure due to gate length deviation, metal wiring micro-short circuit / open circuit failure, interconnect resistance increase failure due to via diameter deviation, and photolithography overlay failure due to array spacing deviation. The design parameters are preset design indicators during chip manufacturing, used to control the manufacturing process and directly affect chip performance. The design parameters include, but are not limited to, oxide layer thickness, gate length, via diameter, and array spacing.

[0098] For each abnormal chip data, obtain the design parameters and corresponding values ​​of the failed chip corresponding to each abnormal chip data;

[0099] The relevant reference value is determined as follows: for a single design parameter, the abnormal chip data is sorted in the order of the sampling points output by the target analysis model from earliest to latest time. The span coefficient of the design parameter corresponding to each abnormal chip data is recorded as the first sequence, the proportion of associated failed chips corresponding to each abnormal chip data is recorded as the second sequence, and the absolute value of the Pearson correlation coefficient between the first sequence and the second sequence is recorded as the relevant reference value corresponding to the design parameter.

[0100] The design threshold for a single design parameter is the average value of that design parameter for each normal chip; for a single abnormal chip data, the span coefficient of a single design parameter in that abnormal chip data = (the value of the design parameter - the design threshold corresponding to the design parameter) / the design threshold corresponding to the design parameter.

[0101] The user can determine the value of the preset relevant reference value according to the actual application scenario. The relevant reference value is used to characterize the degree of linear correlation between the design parameters and the chip batch failure. The higher the degree of correlation, the more likely the design parameter is to cause batch or systemic failure. The greater the user's need for efficiently screening design parameters that deviate from the linear law of the cause attribute, the larger the value of the preset relevant reference value. In this embodiment, the preset relevant reference value is 0.6.

[0102] The parameter emergence coefficient corresponding to a single design parameter = the number of abnormal chip data with the same design parameter name appearing in the associated failure mechanism corresponding to the abnormal chip data / the total number of abnormal chip data.

[0103] The values ​​of the preset deviation recurrence frequency ratio and the preset parameter emergence coefficient can be determined by the user according to the actual application scenario. The deviation recurrence frequency ratio and the parameter emergence coefficient effectively reflect the reproducibility of the deviation characteristics of the design parameters and the correlation emergence characteristics of the parameters in the failure mechanism. The greater the user's need for accurately identifying design outliers with low reproducibility deviation characteristics and high correlation with failure mechanisms, and to improve the mechanism adaptability and data accuracy of outlier parameter judgment, the smaller the values ​​of the preset deviation recurrence frequency ratio and the preset parameter emergence coefficient should be. In this embodiment, the preset deviation recurrence frequency ratio is 0.4 and the preset parameter emergence coefficient is 0.35.

[0104] Specifically, the methods for confirming the deviation from the recurrence frequency ratio include:

[0105] The fitting curve is obtained by fitting the span coefficient and parameter deviation corresponding to each design parameter;

[0106] The fitting deviation of each design parameter under the corresponding abnormal chip data is determined based on the deviation of the parameter corresponding to the span coefficient on the fitting curve and the deviation of the actual parameter of the design parameter.

[0107] The deviation recurrence frequency ratio of the corresponding design parameters is determined by the ratio of the number of abnormal chip data with a fitting deviation less than the preset fitting deviation to the total number of abnormal chip data.

[0108] Specifically, the deviation recurrence frequency ratio for a single design parameter = the number of abnormal chip data whose fitting deviation of the design parameter is less than the preset fitting deviation / the total number of abnormal chip data.

[0109] For a single abnormal chip data, the production line corresponding to the abnormal chip data is identified as producing the failed chips within the intelligent control cycle of the same production time as the failed chip, and these are recorded as production failed chips. The abnormal reference frequency for a single design parameter is the number of production failed chips that use that design parameter as an associated design parameter. Each production failed chip corresponds to several failure design parameters. For a single production failed chip, the name of the design parameter appears in the associated failure mechanism of the chip detection data of that production failed chip, and the corresponding design parameter is recorded as a failure design parameter. The parameter deviation corresponding to a single design parameter = the number of production failed chips that use that design parameter as a failure design parameter / the total number of production failed chips.

[0110] For a single abnormal chip data, a two-dimensional coordinate system is constructed with the span coefficient as the abscissa and the parameter deviation as the ordinate. The corresponding data of the span coefficient and parameter deviation of each design parameter are marked as discrete data points in the coordinate system according to the ascending order of the span coefficient. The discrete data points are fitted and calculated based on the least squares linear fitting algorithm to generate the fitting curve corresponding to the abnormal chip data.

[0111] The fitting deviation of a single design parameter = |the parameter deviation of the design parameter in the fitting curve - the actual parameter deviation of the design parameter| / the actual parameter deviation of the design parameter; the actual parameter deviation of a single design parameter is the parameter deviation corresponding to the discrete data point.

[0112] The preset fitting deviation value can be determined by the user according to the actual application scenario. The fitting deviation value effectively reflects the actual matching relationship between the design parameter span coefficient and the parameter deviation, as well as the degree of deviation from the linear fitting law. The smaller the fitting deviation value, the more likely it is that the design parameter deviates from the linear law. The greater the user's demand for improving the substance and effectiveness of outlier parameter identification, the smaller the preset fitting deviation value. In this embodiment, the preset fitting deviation value is 0.2.

[0113] For a single chip detection data, the failure mechanism corresponding to the chip detection data in the failure mechanism library that has a feature matching degree greater than a preset feature matching degree and a failure probability map adaptation coefficient greater than a preset failure probability map adaptation coefficient is recorded as the associated failure mechanism.

[0114] The feature matching degree of any two chip detection data = 1 - the maximum value of the abnormal comparison values ​​corresponding to each detection parameter;

[0115] The fault probability map adaptation coefficient for any two chip detection data is calculated as follows: 1 - the absolute value of the difference between the cluster profile coefficients of the fault probability maps corresponding to the two data points / (the larger value of the cluster profile coefficients of the fault probability maps corresponding to the two data points + 0.001).

[0116] The values ​​of the preset feature matching degree and the preset fault probability map adaptation coefficient can be determined by the user according to the actual application scenario. The feature matching degree and the fault probability map adaptation coefficient effectively reflect the feature similarity between the detection features of the chip to be analyzed and the features of the samples in the failure mechanism library, as well as the adaptability of the fault probability spatial distribution. The greater the user's need to improve the accuracy of failure mechanism matching and strengthen the correlation and fit between detection features and fault spatial distribution, the larger the values ​​of the preset feature matching degree and the preset fault probability map adaptation coefficient will be. In this embodiment, the preset feature matching degree is 0.8 and the preset fault probability map adaptation coefficient is 0.75.

[0117] When supplementing data for each outlier parameter, supplement the data to be selected for each outlier parameter. When supplementing the data to be selected for a single outlier parameter, supplement the data with the corresponding related data for that outlier parameter, until the number of supplemented related data for that outlier parameter reaches 10% of the initial training data.

[0118] For a single candidate data and a single outlier parameter, if the name of the outlier parameter appears in the association failure mechanism of the candidate data and the fitting deviation of the outlier parameter in the candidate data is less than the preset fitting deviation, then the candidate data is recorded as the association supplementary data of the outlier parameter.

[0119] Specifically, if the global anomaly coefficient is greater than or equal to the preset global anomaly coefficient, then a global disturbance analysis is performed to supplement it.

[0120] Specifically, if the global anomaly coefficient is less than the preset global anomaly coefficient, then there is no need to perform supplementary global disturbance analysis.

[0121] The global anomaly coefficient is the maximum value among the anomaly reference values ​​of each design parameter; the anomaly reference value for a single design parameter is the average of the fitting deviation of that design parameter corresponding to the data of each anomaly chip.

[0122] The value of the preset global anomaly coefficient can be determined by the user according to the actual application scenario. The global anomaly coefficient effectively reflects the overall anomaly level of the fitting deviation of each design parameter and quantifies the intensity of global anomaly features at the chip design parameter level. The greater the user's need for accurate identification of chip global design parameter anomalies and to improve the pertinence and effectiveness of global disturbance analysis, the smaller the value of the preset global anomaly coefficient should be. In this embodiment, the preset global anomaly coefficient is 0.3.

[0123] Specifically, if the coefficient of variation is greater than or equal to the preset coefficient of variation, then supplementation is made based on the comparison reference mechanism.

[0124] If the coefficient of variation is less than the preset coefficient of variation, then no supplementation based on the comparison reference mechanism is required.

[0125] The coefficient of variation is the average of the sub-coefficients of variation corresponding to each abnormal chip data, and the sub-coefficient of variation corresponding to a single abnormal chip data is the average of the discrete reference values ​​corresponding to each detection parameter.

[0126] The discrete reference value corresponding to a single detection parameter = the standard deviation of the detection values ​​of the detection parameters of each abnormal chip produced by the production line corresponding to the failed chip in the intelligent control cycle where the failed chip was produced, and the average value of the detection parameters of each abnormal chip produced by the production line corresponding to the failed chip in the intelligent control cycle where the failed chip was produced.

[0127] The value of the preset dispersion coefficient can be determined by the user according to the actual application scenario. The dispersion coefficient effectively reflects the overall dispersion of the detection parameters of each abnormal chip, and quantitatively characterizes the batch fluctuation and numerical heterogeneity of the detection parameters in the production process. The larger the dispersion coefficient, the more obvious the numerical dispersion fluctuation of the detection parameters in the production batch, the worse the distribution uniformity, and the more prominent the global dispersion anomaly. The greater the user's need for accurate identification of global dispersion anomalies of detection parameters and improved targeted supplementation of comparison reference mechanisms, the smaller the value of the preset dispersion coefficient. In this embodiment, the preset dispersion coefficient is 0.25.

[0128] Specifically, when supplementing based on comparison reference mechanisms, supplementation is carried out for each comparison reference mechanism, and the number of candidate data to be supplemented for a single comparison reference mechanism is positively correlated with the comparison coefficient corresponding to that comparison reference mechanism;

[0129] The comparison reference mechanism is a reference mechanism in which the comparison coefficient is greater than the preset comparison coefficient, and the reference mechanism is the associated failure mechanism corresponding to the data of each abnormal chip.

[0130] The comparison coefficient corresponding to a single reference mechanism = the number of abnormal chip data with the associated failure mechanism as the reference mechanism / the number of abnormal chip data - the number of normal chip data with the associated failure mechanism as the reference mechanism / the number of normal chip data;

[0131] When supplementing based on mechanism matching degree, supplementation is performed for each reference mechanism whose comparison coefficient is greater than the preset comparison coefficient. When supplementing a single reference mechanism whose comparison coefficient is greater than the preset comparison coefficient, the supplemented associated failure mechanism is the candidate data of that reference mechanism until the number of candidate data supplemented reaches n, where n = 10% of the initial training data quantity × (comparison coefficient / preset comparison coefficient).

[0132] The value of the preset comparison coefficient can be determined by the user according to the actual application scenario. The comparison coefficient effectively reflects the difference between the proportion of each reference mechanism in the abnormal chip data and the proportion in the normal chip data, and characterizes the strength of the indicative power of the reference mechanism for chip failure. The greater the user's need for efficient identification of reference mechanisms with strong indicative power for failure and to enhance the effectiveness of supplementing the comparison reference mechanisms, the smaller the value of the preset comparison coefficient. In this embodiment, the preset comparison coefficient is 0.25.

[0133] For each design parameter whose abnormal reference value is greater than the preset abnormal reference value, supplement the selection data. When supplementing the selection data for a single design parameter whose abnormal reference value is greater than the preset abnormal reference value, supplement the selection data with the design parameter whose fitting deviation in the corresponding selection data is greater than the preset fitting deviation, until the number of selection data corresponding to the design parameter reaches 10% of the initial training data.

[0134] The user can determine the value of the preset anomaly reference value based on the sensitivity of identifying global anomalies in chip design parameters and the targeted needs of global disturbance analysis supplementation. The greater the user's need for accurately identifying global anomaly features at the design parameter level and improving the targeting of global disturbance analysis supplementation for high-anomaly design parameters, the smaller the value of the preset anomaly reference value. In this embodiment, the preset anomaly reference value is 0.5.

[0135] The supplementary candidate data and initial training data are used as training data. The training / validation / test sets are re-divided into a 6:2:2 ratio, and the target analysis model is retrained to obtain an optimized target analysis model.

[0136] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of the present invention.

Claims

1. A hierarchical decision-making and intelligent control method for chip failure analysis paths, characterized in that, include: Determine whether to perform data optimization based on the path anomaly frequency ratio of the target analysis model to obtain an optimized target analysis model; In data optimization, a supplementary strategy of supplementing related data is adopted, and the supplementary strategy is determined based on the proportion of high-frequency related abnormal chip data, to determine whether failure analysis supplementation is included. In the process of supplementing related data, supplementation is based on anomaly detection parameters, and the determination of whether to supplement based on the clustering profile coefficient of the fault probability map is based on the proportion of scattered data. In the supplementary failure analysis, outlier parameters are determined directly based on relevant reference values ​​or secondarily based on deviation recurrence frequency ratio and parameter emergence coefficient. Data is supplemented for each outlier parameter, and whether to conduct supplementary global disturbance analysis is determined based on global anomaly coefficient. In the supplementary global disturbance analysis, supplementary data are added for each design parameter whose abnormal reference value is greater than the preset abnormal reference value, and it is determined whether to supplement based on the comparison reference mechanism according to the coefficient of variation. The chip detection data of the failed chip is input into the optimized target analysis model to output the sampling points and the sampling point order.

2. The hierarchical decision-making and intelligent control method for chip failure analysis paths according to claim 1, characterized in that, Data optimization is performed on target analysis models where the path anomaly frequency ratio is greater than or equal to the preset path anomaly frequency ratio.

3. The hierarchical decision-making and intelligent control method for chip failure analysis paths according to claim 2, characterized in that, If the proportion of high-frequency correlated abnormal chip data is greater than or equal to the preset proportion of high-frequency correlated abnormal chip data, the supplementary strategy includes failure analysis supplementation. Among them, high-frequency associated abnormal chip data refers to abnormal chip data where the proportion of associated failed chips is greater than the preset proportion of associated failed chips.

4. The hierarchical decision-making and intelligent control method for chip failure analysis paths according to claim 2, characterized in that, When supplementing based on anomaly detection parameters, the anomaly detection parameters are determined based on the parameter bias coefficient, and the data to be selected is supplemented for each anomaly detection parameter according to the sub-bias coefficient.

5. The hierarchical decision-making and intelligent control method for chip failure analysis paths according to claim 4, characterized in that, If the proportion of scattered data is greater than or equal to the preset proportion of scattered data, then supplementation is made based on the clustering profile coefficient of the fault probability map. Among them, scattered data refers to abnormal chip data whose cluster profile coefficient of the fault probability map is greater than the preset cluster profile coefficient.

6. The hierarchical decision-making and intelligent control method for chip failure analysis paths according to claim 2, characterized in that, Design parameters whose relevant reference values ​​are greater than or equal to preset relevant reference values ​​are directly identified as outliers. For design parameters whose relevant reference values ​​are less than preset relevant reference values, a second determination is made based on the deviation recurrence frequency ratio and the parameter emergence coefficient to determine whether they are outliers. Specifically, if the deviation recurrence frequency ratio of the design parameter is greater than or equal to the preset deviation recurrence frequency ratio and the parameter emergence coefficient is greater than or equal to the preset parameter emergence coefficient, then the design parameter is recorded as an outlier.

7. The hierarchical decision-making and intelligent control method for chip failure analysis paths according to claim 6, characterized in that, The methods for confirming the deviation recurrence frequency ratio include: The fitting curve is obtained by fitting the span coefficient and parameter deviation corresponding to each design parameter; The fitting deviation of each design parameter under the corresponding abnormal chip data is determined based on the deviation of the parameter corresponding to the span coefficient on the fitting curve and the deviation of the actual parameter of the design parameter. The deviation recurrence frequency ratio of the corresponding design parameters is determined by the ratio of the number of abnormal chip data with a fitting deviation less than the preset fitting deviation to the total number of abnormal chip data.

8. The hierarchical decision-making and intelligent control method for chip failure analysis paths according to claim 1, characterized in that, If the global anomaly coefficient is greater than or equal to the preset global anomaly coefficient, then a global disturbance analysis is performed to supplement it.

9. The hierarchical decision-making and intelligent control method for chip failure analysis paths according to claim 8, characterized in that, If the coefficient of variation is greater than or equal to the preset coefficient of variation, then supplementation is made based on the comparison reference mechanism.

10. The hierarchical decision-making and intelligent control method for chip failure analysis paths according to claim 9, characterized in that, When supplementing based on comparison reference mechanisms, the supplementation is performed for each comparison reference mechanism. The number of candidate data to be supplemented for a single comparison reference mechanism is positively correlated with the comparison coefficient corresponding to that comparison reference mechanism. The comparison reference mechanism is a reference mechanism in which the comparison coefficient is greater than the preset comparison coefficient, and the reference mechanism is the associated failure mechanism corresponding to the data of each abnormal chip.

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