Reliability analysis integrated application method of carrier rocket control system

Abstract

The invention discloses a reliability analysis integrated application method of a carrier rocket control system, and the method combines the technologies of state simulation modeling, path traversal searching, reliability block diagram modeling and the like, and builds a reliability analysis system facing a complex system. The method can effectively solve the problems of a traditional method in the aspects of component state modeling, sequential logic processing, system-level netlist data analysis and the like, and powerful technical support is provided for development of a high-reliability system.

Description

Technical Field

[0001] This invention belongs to the field of aerospace reliability analysis technology, specifically relating to an integrated application method for reliability analysis of launch vehicle control systems. Background Technology

[0002] With the increasing development of modern complex system design, especially in high-reliability fields such as aerospace, aviation, and military, the functional complexity and integration of systems are constantly increasing, placing higher demands on system reliability. Traditional reliability analysis methods mainly rely on numerical simulation or physical experiments, but in practical applications, they suffer from problems such as high cost, long cycle time, and difficulty in controlling risks. These problems are particularly prominent in the early design stages of complex systems.

[0003] In recent years, simulation-based reliability analysis techniques have gradually gained attention. Through state simulation modeling, systems can be analyzed and verified early in the design process, allowing for the identification and correction of potential problems at a lower cost. However, existing simulation methods still have limitations in handling complex component functional control relationships, timing logic, and path traversal, making it difficult to meet the comprehensive requirements of high-reliability systems.

[0004] Specifically, traditional numerical simulation requires detailed component parameter information, but in many real-world scenarios, detailed information about components may not be fully available, limiting its application scope. Furthermore, the functional control relationships and timing logic of components in complex systems are often quite intricate, and existing methods lack efficient modeling and analysis tools to address these issues. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide an integrated application method for reliability analysis of launch vehicle control systems.

[0006] A reliability analysis and integrated application method for a launch vehicle control system includes the following steps: Step 1: Model building, specifically including: S1. Construct an integrated connectivity model for the control system, wherein the integrated connectivity model integrates instruction paths and energy paths; wherein, the instruction path is the execution logic path of programmable integrated circuits or system-on-a-chip software, and the energy path is the current or voltage transmission path in the hardware circuit. Step 2, simulation testing, specifically includes: S2. Establish a qualitative state model based on the functional characteristics of the components. The qualitative state model only characterizes the on / off state and current direction of the components and does not depend on specific electrical parameter values. S3. Use a depth-first search algorithm to traverse the energy path and combine it with the qualitative state model to generate all possible current connection paths; S4. Define the priority of component actions according to the system task timing, configure the timing state input of key points, and identify potential timing conflict paths by traversing legal state combinations through state simulation. Step 3, reliability analysis, specifically including: S5. Based on the integrated connectivity model and simulation test results, construct a reliability block diagram model of the instruction task, and calculate the task reliability index by combining the basic reliability data of the components.

[0007] Preferably, in step S2: The cable is modeled as an ideal conductor or a conductor with impedance. The capacitor is modeled as a short circuit at the moment of power-on and as an open circuit in steady state. The inductor is modeled as an open circuit at the moment of power-on and as a short circuit in steady state. A diode is modeled as a short circuit when it is forward-biased and as an open circuit when it is reverse-biased. Transistors are modeled as saturation, amplification, or cutoff modes based on their bias states.

[0008] Preferably, in step S4: Uncertain combinations of the separation sequence of electrical connectors; Timing of busbar energization or de-energization operations at different stages; The relative sequence of action of multiple relay contacts; The path analysis data is filtered by combining forward filtering and reverse search.

[0009] Preferably, the reliability block diagram model described in step S5 adopts one or a combination of series model, parallel model, voting model, bridging model or side model, and is divided into working reserve, non-working reserve or non-reserve model. The reliability index of the task is calculated based on the connectivity probability from the instruction source to the destination, and satisfies the following conditions: the specified task, the specified working conditions, and the specified task time.

[0010] Furthermore, it also includes fault deduction steps, specifically: Open-circuit or short-circuit faults are injected into analog devices using parameter modification or series-parallel connection methods. Open-circuit faults are achieved by setting the resistor to 1000MΩ or the capacitor to 0.001nF, while short-circuit faults are achieved by setting the resistor to 1mΩ or the capacitor to 1000F. Inject one of five fault modes into the output pin of a digital device: normally high, normally low, open circuit, inverted, or short circuit. Based on the simulation results after fault injection, a qualitative analysis is first performed to determine the impact range of the fault on the main and backup circuits, and then a quantitative analysis is performed to assess whether it will cause overstress, signal interference or mission failure.

[0011] Preferably, the state simulation algorithm includes: Functional network tree search: Traverse components starting from the power supply; Component replacement: Replace the actual component with the corresponding qualitative state model; Initial state settings: Set the initial states of the switches and capacitors according to the design intent; Shortest path search: Determines the connectivity from the power source to the target port; Output results: Generate resistor network topology, component connection relationships, equivalent resistance values, and operating status information.

[0012] The present invention has the following beneficial effects: To address the aforementioned problems, this invention proposes an integrated application method for reliability analysis of launch vehicle control systems. By combining techniques such as state simulation modeling, path traversal search, and reliability block diagram modeling, a reliability analysis framework for complex systems is constructed. This method effectively solves the difficulties of traditional methods in component state modeling, timing logic processing, and system-level netlist data parsing, providing strong technical support for the development of highly reliable systems. Attached Figure Description

[0013] Figure 1 This is the overall roadmap of the present invention; Figure 2 Modeling process for instruction path connectivity reliability; Figure 3 This is a commonly used reliability model; Figure 4 This refers to the sequential relationship of the main workflow; Figure 5 Modeling process for instruction path connectivity reliability; Figure 6 Modeling component failures; Figure 7 This is a schematic diagram of a typical failure mode; Figure 8 This is a flowchart of a method for predicting the reliability of instruction tasks based on simulation testing. Detailed Implementation

[0014] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0015] This invention provides an integrated application method for reliability analysis of a launch vehicle control system, which mainly includes three steps: model establishment, simulation testing, and reliability analysis, as detailed below: (I) Model Establishment This section primarily includes instruction path modeling and simulation, energy path modeling and simulation, and integrated path modeling and simulation. Instruction paths mainly refer to the functional logic paths in programmable integrated circuits and the execution paths of on-chip system software. These paths are primarily defined by hardware description languages ​​or software programming languages ​​and are implicit paths at the control system level. Energy paths mainly refer to the current and voltage paths in the individual hardware circuits of the control system. These paths mainly realize power transmission or signal transmission and are explicit paths at the control system level. Integrating implicit and explicit paths to construct an integrated connectivity model of the control system and performing integrated path modeling and simulation forms the model foundation for conducting reliability integrated simulation testing.

[0016] The integrated application method of reliability analysis based on simulation testing involves modeling and simulating command paths, energy paths, and their combined paths. By constructing state simulation models, a comprehensive verification of system functions and timing logic can be achieved, ensuring that potential problems can be detected and corrected at an early stage of the design process.

[0017] (1) When conducting instruction path modeling and simulation, the task flowchart and timing diagram should be clearly defined first, and the internal logic and peripheral circuits of digital devices such as FPGA and SRAM in the system should be analyzed. The instruction path model is established by integrating functional simulation and timing simulation.

[0018] Functional simulation uses HDL (Hardware Description Language) to describe the integrated circuit and utilizes tools such as ModelSim to verify the accuracy of the functions. Timing simulation adds time delay analysis to the functional simulation to ensure that the system meets the design requirements under specified conditions.

[0019] During the simulation, project files are built in the ModelSim environment, and the test platform and the design under test are compiled. By setting simulation parameters, monitoring signal waveforms, and exporting results, the connectivity of functions such as bus control and serial port transmission and reception is verified.

[0020] (2) When conducting energy path modeling and simulation, an energy path model is established based on the concept of reverse resistance, while also considering the input-output logic relationships of digital devices. Components can be classified according to their logic relationships: One-to-one correspondence type: Directly use qualitative resistors to simulate input and output.

[0021] Many-to-one type: A resistor network is established between multiple inputs and a single output.

[0022] One-to-one multi-type: Resistors are set between each input and multiple outputs.

[0023] During energy path modeling, to ensure the correctness of the logical relationships, output interference can be addressed by adding a reverse resistor, and power paths that have no impact on the analysis can be ignored.

[0024] (3) When conducting integrated path modeling and simulation, the integrated model combines command and energy paths to analyze the occurrence, transmission, and execution of timing actions. The key points are: Interface interaction research: describing the conversion process between commands and energy.

[0025] Link analysis: statistical analysis of energy paths at the component level and instruction paths at the functional module level.

[0026] Impact assessment: For characteristic events, decompose the execution chain, check the interface and software status, and analyze the impact of the results on subsequent actions.

[0027] By using the above methods, we can ensure that the system design achieves comprehensive reliability verification in the early stages, reduce development costs, and improve product performance.

[0028] (ii) Simulation Testing (1) Component state modeling and simulation Component state modeling is the foundation of reliability analysis based on simulation testing. When establishing a component's state model based on its functional characteristics, the focus is on the component's on / off state and current flow, without considering specific voltage or current values. This method effectively simplifies the circuit analysis process while ensuring the accurate capture of key functional characteristics.

[0029] In DC circuits, the state models of common components are as follows: Cables: Based on their length, they are divided into ideal wires (without resistance) and cables with impedance.

[0030] Capacitors are defined as short-circuited at the moment of power-on and open-circuited after the circuit stabilizes.

[0031] Inductance: It is defined as an open circuit at the moment of power-on and as a short circuit after the circuit stabilizes.

[0032] Diode: When forward-biased, it is defined as a short-circuit state; when reverse voltage is present, it is defined as an open-circuit state.

[0033] Transistor: Depending on the energized state of each electrode, it operates in one of the following modes: saturation mode, amplification mode, or cutoff mode.

[0034] In this way, the state model of the components can effectively reflect the actual operating characteristics of the circuit, while avoiding dependence on specific numerical analysis, thereby reducing the complexity of simulation.

[0035] (2) Circuit path traversal search To comprehensively analyze the function and reliability of a circuit, a depth-first search algorithm is needed to find all possible current paths in the circuit. This method uses recursive conditions to determine the current direction and the operating state of the devices, ensuring the accuracy of the path analysis. Specifically: First, start with the power supply and gradually go through each component in the circuit; Based on the state model of the component, determine whether it is on or off under specific operating conditions; By recursively enumerating all possible current paths, the connectivity and related state information of each path are recorded.

[0036] This method can effectively identify potential functional problems, such as short circuits, open circuits, and unreasonable current flow.

[0037] (3) Timing input configuration and priority definition Timing problems are one of the key challenges in circuit design. To analyze and solve timing problems, it is necessary to configure the order of component actions according to the design intent and define the priority of each pair of component actions. For example, during a rocket launch, operations such as power distribution, power transfer, power release, and ignition must be performed strictly according to a specific timing sequence.

[0038] By predefining the priority of component state outcomes, potential problem paths can be effectively located. For example, state changes of certain critical components may require specific conditions to trigger, and violations of timing logic could lead to system failure. Therefore, these priorities need to be strictly controlled during simulation to ensure that each operation conforms to the design intent.

[0039] (4) Key point timing state analysis Building upon the standard configuration, it's necessary to add timing state inputs for key areas of concern, such as the actual order in which multiple plugs are disconnected. By automatically traversing all possible state combinations through simulation, potential problem paths can be identified. This method is particularly suitable for problems arising from uncertain timing sequences during actual operation.

[0040] For example, in a multi-power supply system, the ground definitions of different power supplies may differ, requiring special definitions for key electronic components to automatically traverse all possible state inputs during simulation, thereby ensuring the reliability and robustness of the system.

[0041] (5) Circuit path analysis and data screening To improve simulation efficiency and accuracy, two methods can be used to filter path analysis data based on input status and output results: Forward filtering: Starting from the input state, filtering path results under specific conditions; Reverse search: Search for the corresponding input state from the output result.

[0042] By nesting these two methods, comprehensive path analysis can be achieved, thereby effectively reducing the number of useless paths and improving simulation efficiency.

[0043] (6) State simulation algorithm State simulation algorithms are the core tool for implementing the above analysis. The specific steps are as follows: Functional network tree search: Starting from the power supply, it traverses each component in the circuit step by step; Component replacement: Replace the actual component with the corresponding state model; Initial state settings: Set the initial state of the switches and capacitors according to the design intent; Shortest path search: Determine the connectivity from the power source to the target port using the shortest path algorithm, and analyze the state changes of key points; Output results: Resistor network, component connection relationships, resistance value information, and operating status of each component.

[0044] (III) Reliability Analysis This section mainly includes reliability modeling, fault injection, and reliability prediction.

[0045] (1) Construction of instruction connectivity reliability model This section mainly studies the conversion relationship between the connectivity simulation test model and the reliability model of the execution instructions of each test process in the project, analyzes the logical relationship of each instruction execution path, and can construct an instruction connectivity reliability model according to the timing of the test task instructions.

[0046] The logical relationships of tasks are expressed using reliability block diagrams. Major reliability models include: parallel reliability model, serial reliability model, Markov model, Bayesian network model, and fault tree model. The underlying idea of ​​this invention is as follows: Figure 2 As shown.

[0047] 1) Define the reliability modeling method based on the system characteristics; 2) Determine the instruction task path and the operating mode of the relevant driving devices; 3) Analyze the logical relationships and connectivity simulation test results between instructions; 4) Construct a task reliability model.

[0048] Commonly used reliability models include series models, parallel models, voting models, bridging models, and side-connection models. These models can be further divided into three categories: working reserve models, non-working reserve models, and non-reserve models. For example... Figure 3 As shown.

[0049] By analyzing the constructed command task state path, the topology of the path and the series and parallel relationships between various components can be further clarified. Further connectivity-based simulation tests combined with specific flight timing can generate the state path for a single command task.

[0050] When conducting simulation tests, the following three combinations of states need to be considered: 1. Possible different sequences and states of the main workflow. To address this issue, it's necessary to first streamline workflows with relatively fixed sequences. For example, the main timing sequences of power distribution commands, power transfer commands, ignition commands, emergency shutdown commands, and timed shutdown commands are generally fixed, while the order of power-off commands, reset commands, single-unit reset commands, and reset lockout commands can be adjusted. A workflow with a fixed sequence is as follows: Figure 4 As shown.

[0051] Based on the above analysis, the following special states of the workflow also need to be considered, specifically including: (1) During power distribution, the bus energization sequence is different; (2) In the power distribution process, only one or two busbars are energized; (3) When a power-off operation is performed before the busbar has been energized; (4) When a power-off operation is performed after the busbar has been energized; (5) When the power transfer operation is completed and all equipment on the rocket is powered by the rocket battery, the power-off operation is performed.

[0052] 2. The arrangement and combination of different relay operation sequences and states under the same working process state. To address this issue, the first step is to analyze the simultaneous operation of relay contacts with different functions. For example, after a power transfer command is issued, the simultaneous operation of the power transfer relay contacts typically involves other sequential functions, including: power transfer self-holding, power transfer signal output, switching from ground power to independent battery power, and energizing the relay coil upon receiving the "power transfer complete" signal. Furthermore, it is necessary to analyze whether there are busbars on the negative return lines of each command execution and whether there are disconnectable connectors in each functional branch. The presence of busbars or disconnectable connectors may affect the topology of the command task path and cause system failures.

[0053] 3. Combination states of different electrical connector disconnection sequences The combination states of connector separation sequence are generally divided into two levels: one is to analyze the separation action using the disconnect plug as the basic analysis unit; the other is to analyze the separation action using the pins of the disconnect plug as the basic analysis unit.

[0054] After completing the system operation process and instruction timing analysis, a single instruction task path is formed. Combining the component connection relationships within this instruction path, a single instruction task reliability model can be further developed.

[0055] (2) Fault inference technology based on simulation test Failure Mode and Effects Analysis (FMEA) is based on faults discovered during current testing. By analyzing faults related to instruction transmission, the scope of faults is further narrowed. Connectivity simulation analysis results are used to identify instruction paths with potential faults. The components related to the instruction paths are analyzed, examining both the impact of each execution unit on the instruction paths under fault conditions and the system-level impact of the paths on the task. The research plan is as follows: Figure 5 As shown: Failure modes are the manifestations of failures, such as short circuits, open circuits, fractures, and excessive wear. Failure mode identification (FMEA) is the foundation of failure mode analysis. The purpose of failure mode identification is to investigate and anticipate failures, which involves using the designer's professional knowledge and experience to perform logical analysis and reasoning to identify failure modes. Failure mode identification should strive to cover all failure modes, especially critical ones. Failure mode analysis should systematically analyze the most concerning failures of the product and consider the necessary actions to take should these failure modes occur.

[0056] Based on the different characteristics of failure modes, state path failure state models can be classified and modeled according to analog devices and digital devices. Failures occurring in analog devices are classified as analog failures, and failures occurring in digital devices are classified as digital failures. Figure 6 As shown: Depending on the method of component fault injection, the simulated devices in the state path can be modeled for component fault states using the following two methods: (1) Parameter modification method Fault modeling of components, such as resistors and capacitors, is achieved by modifying specific parameters of normally functioning circuit components. This type of fault model is implemented through parameter modification; for example, to simulate an open-circuit fault, the resistance value is set to a very large value or the capacitance value to a very small value; conversely, to simulate a short-circuit fault, the resistance value is set to a very small value or the capacitance value to a very large value. Specific values ​​are shown in Table 1.

[0057] Table 1 Resistor and Capacitor Parameter Values

[0058] (2) Series and parallel connection method To simulate a fault, connect a normal component in parallel or series with another normal component. For example, connecting a very large resistor in series with an analog component is equivalent to making the analog component open-circuited, while connecting a very small resistor in parallel is equivalent to making the analog component short-circuited. For digital components, a gate circuit is typically connected in parallel or series. Fault modes for digital components are specific to each output pin. Each pin has five fault modes: open-circuit, normally high, normally low, inverted, and short-circuit. Fault injection in digital components involves connecting a corresponding fault mode in series at the original pin location. Figure 7 As shown.

[0059] For digital devices in the state path, fault state modeling of digital devices is mainly achieved by combining logic state transition truth tables with port electrical characteristics.

[0060] When conducting fault deduction and impact analysis of control systems based on simulation testing, the first step is to analyze the working process and command timing of the control system. After completing the system instruction action state traversal and simulation test, fault inference and impact analysis are carried out based on the generated state path. On the one hand, the impact of each execution component on instruction actions under fault conditions is analyzed; on the other hand, from the system level, the impact of the path on the task is analyzed.

[0061] The various state paths of a control system are basically composed of components; therefore, the main considerations are open-circuit and short-circuit fault modes. The analysis employs a combination of qualitative and quantitative approaches: after identifying a fault mode, a qualitative analysis is first conducted on the potential impact of the fault on the entire main and backup circuits, identifying which functions might be affected; after determining the potentially affected functional branches, quantitative analysis is used to further determine whether the fault will cause overstress, signal interference, voltage clamping, or other effects on these functional branches, and whether it will affect the execution of system tasks.

[0062] First, a qualitative analysis is conducted, and then a quantitative analysis is performed based on this qualitative analysis. Subsequent analysis can then be tailored to the key points and areas of uncertainty identified above, thus improving both efficiency and effectiveness.

[0063] (3) Reliability prediction of instruction tasks based on simulation test This section mainly studies the task reliability calculation of the control system command path based on the constructed command path connectivity reliability model and the basic reliability data of related products on the command path.

[0064] According to the definition of reliability, the following conditions must be clearly defined to complete the reliability calculation of a task: 1) Defined task: Can all instructions in a single task ensure connectivity between the source and destination? 2) Specified conditions: normal working mode and extreme working conditions; 3) Specify the task time: that is, the specified instruction transmission time.

[0065] The overall approach of this section is as follows: Figure 8 As shown.

[0066] Command mission analysis needs to make full use of the test data and results obtained from design, acceptance, simulation, ground tests and previous flight tests to analyze and confirm each flight sequence action and its support measures in the technical preparation phase, launch preparation phase and actual flight phase.

[0067] During the command and mission analysis, the focus is on the sequence of events during launch and flight. Following the process of each timing action's occurrence → transmission → execution → result confirmation → impact analysis, statistical analysis is performed on all flight timing actions of the model (energy path analysis down to the component level, command path analysis down to the functional module level) to comprehensively ensure the correctness and accuracy of the control system's execution of each flight timing action after ignition.

[0068] Meanwhile, for characteristic events, the related products in the action execution chain are decomposed layer by layer, the interfaces and software involved in the event are examined, the conditions under which the event occurs and the accuracy of the action under those conditions are analyzed, and the various possible results of the event are analyzed, and the impact of the result on subsequent actions is analyzed.

[0069] In practice, based on the product design characteristics, and taking the baseline time 0 of the technical state / test phase as the starting point, the system's workflow and processes are divided into time periods. Using work actions as the main thread, and according to the temporal transmission relationship of each action, each time period is decomposed into specific key actions, instruction actions (including hardware and software), and non-instruction actions (including software). Each action is taken as the top-level analysis object, analyzing and decomposing the specific link links of its generation, transmission, processing, execution, and result confirmation. Specific energy paths are decomposed to the component level, and instruction paths can be decomposed to the specific functional module level. Finally, an action link analysis and confirmation checklist is formed for each process.

[0070] All relevant design parameters, performance parameters, test data, fault information, historical lifespan and reliability data, and simulation data of the product during its production, research and development, testing, and application should be collected for reliability verification and evaluation. In addition, data inferred and estimated by experts in the relevant field, as well as data available for reference in domestic and international standards and specifications, should also be collected and organized to comprehensively and accurately reflect the product's reliability status and level.

[0071] After establishing the instruction reliability block diagram and clarifying its mathematical model, the indicators can be calculated based on the collected reliability data.

[0072] In summary, the above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A reliability analysis and integrated application method for a launch vehicle control system, characterized in that, Includes the following steps: Step 1: Model building, which specifically includes: S1. Construct an integrated connectivity model for the control system, wherein the integrated connectivity model integrates instruction paths and energy paths; wherein, the instruction path is the execution logic path of programmable integrated circuits or system-on-a-chip software, and the energy path is the current or voltage transmission path in the hardware circuit. Step 2, simulation testing, specifically includes: S2. Establish a qualitative state model based on the functional characteristics of the components. The qualitative state model only characterizes the on / off state and current direction of the components and does not depend on specific electrical parameter values. S3. Use a depth-first search algorithm to traverse the energy path and combine it with the qualitative state model to generate all possible current connection paths; S4. Define the priority of component actions according to the system task timing, configure the timing state input of key points, and identify potential timing conflict paths by traversing legal state combinations through state simulation. Step 3, reliability analysis, specifically including: S5. Based on the integrated connectivity model and simulation test results, construct a reliability block diagram model of the instruction task, and calculate the task reliability index by combining the basic reliability data of the components.

2. The reliability analysis and integrated application method for a launch vehicle control system as described in claim 1, characterized in that, In step S2: The cable is modeled as an ideal conductor or a conductor with impedance. The capacitor is modeled as a short circuit at the moment of power-on and as an open circuit in steady state. The inductor is modeled as an open circuit at the moment of power-on and as a short circuit in steady state. A diode is modeled as a short circuit when it is forward-biased and as an open circuit when it is reverse-biased. Transistors are modeled as saturation, amplification, or cutoff modes based on their bias states.

3. The reliability analysis and integrated application method for a launch vehicle control system as described in claim 1, characterized in that, In step S4: Uncertain combinations of the separation sequence of electrical connectors; Timing of busbar energization or de-energization operations at different stages; The relative sequence of action of multiple relay contacts; The path analysis data is filtered by combining forward filtering and reverse search.

4. The reliability analysis and integrated application method for a launch vehicle control system as described in claim 1, characterized in that, The reliability block diagram model described in step S5 adopts one or a combination of series model, parallel model, voting model, bridging model or side model, and is divided into working reserve, non-working reserve or non-reserve model; The reliability index of the task is calculated based on the connectivity probability from the instruction source to the destination, and satisfies the following conditions: the specified task, the specified working conditions, and the specified task time.

5. The reliability analysis and integrated application method for a launch vehicle control system as described in claim 1, characterized in that, It also includes fault deduction steps, specifically: Open-circuit or short-circuit faults are injected into analog devices using parameter modification or series-parallel connection methods. Open-circuit faults are achieved by setting the resistor to 1000MΩ or the capacitor to 0.001nF, while short-circuit faults are achieved by setting the resistor to 1mΩ or the capacitor to 1000F. Inject one of five fault modes into the output pin of a digital device: normally high, normally low, open circuit, inverted, or short circuit. Based on the simulation results after fault injection, a qualitative analysis is first performed to determine the impact range of the fault on the main and backup circuits, and then a quantitative analysis is performed to assess whether it will cause overstress, signal interference or mission failure.

6. The reliability analysis and integrated application method for a launch vehicle control system as described in claim 1, characterized in that, The state simulation algorithm includes: Functional network tree search: Traverse components starting from the power supply; Component replacement: Replace the actual component with the corresponding qualitative state model; Initial state settings: Set the initial states of the switches and capacitors according to the design intent; Shortest path search: Determines the connectivity from the power source to the target port; Output results: Generate resistor network topology, component connection relationships, equivalent resistance values, and operating status information.

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