BMC, BMC resetting method and device and storage medium

Abstract

The embodiment of the invention provides a BMC, a resetting method and device of the BMC and a storage medium. The BMC comprises a processor, a clock resetting module and functional modules except the clock resetting module. The clock reset module is respectively connected with reset pins of the functional modules; the clock reset module comprises a first register used for recording reset source information; when the clock reset module is triggered to carry out reset control, reset source information is recorded in the first register, and a function module which corresponds to the reset source information and needs to be reset is triggered through a reset pin connected with the clock reset module to carry out reset; and the processor reads the reset source information from the first register after self-resetting, determines the configuration information corresponding to the read reset source information as target configuration information, and initializes the function module recorded in the target configuration information. Through the scheme, the BMC resetting flexibility can be improved.

Description

Technical Field

[0001] This invention relates to the field of baseboard management controller technology, and in particular to a baseboard management controller (BMC), a BMC reset method, an apparatus, and a storage medium. Background Technology

[0002] The Baseboard Manager Controller (BMC) is a dedicated microcontroller in a server. Utilizing the BMC firmware running on its various hardware interfaces, it enables remote management and monitoring of the server. Local display is also a crucial function of the BMC. The server's main CPU can recognize the BMC chip as a standard compatible graphics card via the PCIe (Peripheral Component Interconnect Express) interface, transmitting display data to the BMC. The BMC then transmits this data to a monitor via its VGA (Video Graphic Array), DP (Display Port), or HDMI (High Definition Multimedia Interface) ports for display.

[0003] When resetting the BMC, apart from a full chip power-down reset, other resets must not affect the server's normal operations. For example, the BMC must maintain uninterrupted local display functionality during a reset. Related technologies require designing complex local reset circuits within the BMC to isolate the modules requiring reset from other modules. However, this circuit-based reset method can only reset a fixed number of modules. In different scenarios, the modules requiring reset are often not fixed, and related technologies cannot flexibly adjust the modules performing the reset in different situations. Summary of the Invention

[0004] The purpose of this invention is to provide a BMC, a BMC reset method, an apparatus, and a storage medium to improve the flexibility of BMC reset. The specific technical solution is as follows:

[0005] This invention first provides a BMC, which includes: a processor, a clock reset module, and functional modules other than the clock reset module; the clock reset module is connected to the reset pins of each functional module; the clock reset module includes: a first register for recording reset source information;

[0006] When the clock reset module is triggered to perform reset control, it records the reset source information in the first register and triggers the functional module that needs to be reset to perform the reset through the connected reset pin.

[0007] After resetting itself, the processor reads reset source information from the first register and determines the configuration information corresponding to the read reset source information as the target configuration information; wherein, the configuration information corresponding to each reset source information records the functional module that needs to be reset corresponding to that reset source information;

[0008] The processor initializes the functional modules recorded in the target configuration information.

[0009] In one embodiment of the present invention, the clock reset module further includes: a second register;

[0010] When the first reset condition is met, the processor determines the functional module that needs to be reset recorded in the configuration information corresponding to the reset source information, and writes the reset control information of the functional module that needs to be reset into the second register.

[0011] The clock reset module triggers the corresponding functional module that needs to be reset to perform a reset via the connected reset pin, including:

[0012] After the clock reset module writes reset control information into the second register, it triggers the functional module to which the target reset pin belongs to perform a reset by outputting a reset signal to the connected target reset pin; the target reset pin is the reset pin of the functional module represented by the written reset control information.

[0013] In one embodiment of the present invention, the first reset condition includes: the processor receiving a reset interrupt signal; the reset interrupt signal is generated by the clock reset module after receiving a key reset signal;

[0014] When the clock reset module receives a button reset signal, it triggers a reset interrupt signal to the processor.

[0015] When the clock reset module is triggered to perform reset control, it records reset source information in the first register, including:

[0016] When the clock reset module receives a button reset signal, it records the reset source information indicating that the reset was triggered by the button in the first register.

[0017] In one embodiment of the present invention, the first reset condition includes: a software-triggered reset running by the processor;

[0018] In the event of a software-triggered reset, the processor transmits reset source information indicating that the reset was triggered by software to the clock reset module.

[0019] When the clock reset module is triggered to perform a reset, it records reset source information in the first register, including:

[0020] When the clock reset module receives the reset source information transmitted by the processor, it records the reset source information in the first register.

[0021] In one embodiment of the present invention, the processor writes reset control information indicating a functional module requiring reset into the second register, including:

[0022] The processor controls the process corresponding to the functional module that needs to be reset to stop running, and after receiving a signal from the functional module that needs to be reset indicating that the current task has been completed, it writes the reset control information of the functional module that needs to be reset into the second register.

[0023] In one embodiment of the present invention, the clock reset module is provided with a reset control circuit, and the reset control circuit is connected to the reset pin of a designated functional module in the BMC;

[0024] When the clock reset module is triggered to perform a reset, it records reset source information in the first register, including:

[0025] When the clock reset module receives a reset signal triggered by the watchdog timer, it records the reset source information indicating that the watchdog timer triggered the reset in the first register.

[0026] The clock reset module triggers the corresponding functional module that needs to be reset to perform a reset via the connected reset pin, including:

[0027] The clock reset module triggers the designated functional module to perform a reset through the reset control circuit.

[0028] In the configuration information, the watchdog trigger reset corresponds to the specified functional module.

[0029] In one embodiment of the present invention, after the processor resets itself, it reads the reset source information from the first register and then clears the reset source information recorded in the first register.

[0030] This invention also provides a BMC reset method, applied to the processor of a Baseboard Management Controller (BMC). The BMC further includes: a clock reset module and functional modules other than the clock reset module; the clock reset module is connected to the reset pins of each functional module; the clock reset module includes: a first register for recording reset source information; the clock reset module is used to: record the reset source information in the first register when triggered for reset control, and trigger the functional module corresponding to the reset source information to perform a reset through the connected reset pins; the method includes:

[0031] After the processor is reset, the reset source information is read from the first register;

[0032] The configuration information corresponding to the read reset source information is determined as the target configuration information; wherein, the configuration information corresponding to each reset source information records the functional module that needs to be reset corresponding to that reset source information;

[0033] The functional modules recorded in the target configuration information are initialized.

[0034] In one embodiment of the present invention, the clock reset module further includes: a second register; the method further includes:

[0035] When the first reset condition is met, determine the functional module that needs to be reset, which is recorded in the configuration information corresponding to the reset source information.

[0036] Write reset control information for the functional module that needs to be reset into the second register, so that after the reset control information is written into the second register, the clock reset module can trigger the functional module to which the target reset pin belongs to perform a reset by outputting a reset signal to the connected target reset pin; the target reset pin is the reset pin of the functional module represented by the written reset control information.

[0037] In one embodiment of the present invention, the first reset condition includes: the processor receiving a reset interrupt signal; the reset interrupt signal is generated by the clock reset module after receiving a key reset signal.

[0038] In one embodiment of the present invention, the first reset condition includes: a software-triggered reset running by the processor; the method further includes:

[0039] In the event of a software-triggered reset, reset source information indicating a software-triggered reset is transmitted to the clock reset module, so that the clock reset module records the reset source information in the first register.

[0040] In one embodiment of the present invention, reset control information indicating a functional module requiring reset is written into the second register, including:

[0041] The process corresponding to the functional module that needs to be reset is stopped from running. After receiving a signal from the functional module that needs to be reset indicating that the current task has been completed, the reset control information of the functional module that needs to be reset is written into the second register.

[0042] In one embodiment of the present invention, the clock reset module is provided with a reset control circuit, which is connected to the reset pin of a designated functional module in the BMC; the clock reset module is specifically used to: when a watchdog-triggered reset signal is received, record reset source information indicating watchdog-triggered reset in the first register, and trigger the designated functional module to perform reset through the reset control circuit; in the configuration information, watchdog-triggered reset corresponds to the designated functional module.

[0043] In one embodiment of the present invention, after reading the reset source information from the first register after the processor is reset, the method further includes:

[0044] Clear the reset source information recorded in the first register.

[0045] This invention also provides a reset device for a Baseboard Management Controller (BMC), applied to the processor of the BMC. The BMC further includes: a clock reset module and functional modules other than the clock reset module; the clock reset module is connected to the reset pins of each functional module; the clock reset module includes: a first register for recording reset source information; the clock reset module is used to: record reset source information in the first register when triggered for reset control, and trigger the corresponding functional module requiring reset to perform a reset via the connected reset pins; the device includes:

[0046] A reset source information reading unit is used to read reset source information from the first register after the processor is reset;

[0047] The first module determining unit is used to determine the configuration information corresponding to the read reset source information as the target configuration information; wherein, the configuration information corresponding to each reset source information records the functional module that needs to be reset corresponding to the reset source information;

[0048] An initialization unit is used to initialize the functional modules recorded in the target configuration information.

[0049] This invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements any of the above-described BMC reset methods.

[0050] This invention also provides a computer program product containing instructions that, when run on a computer, cause the computer to execute any of the BMC reset methods described above.

[0051] Beneficial effects of the embodiments of the present invention:

[0052] The BMC provided in this embodiment of the invention includes: a processor, a clock reset module, and functional modules other than the clock reset module; the clock reset module is connected to the reset pins of each functional module; the clock reset module includes: a first register for storing reset source information; the clock reset module is connected to the reset pins of the functional modules, enabling different functional modules to be reset for different reset sources, and the clock reset module can also record reset source information in its own first register. Thus, when the processor performs a reset, it can read the reset source information from the first register and determine the functional module that performed the reset based on the configuration information corresponding to the reset source information, so as to initialize the functional module that performed the reset. It can be seen that this solution, by recording reset source information in the register of the clock reset module and pre-setting configuration information, enables the BMC to control the corresponding functional modules to perform resets according to different reset sources, rather than only controlling fixed functional modules to perform resets, thereby improving the flexibility of BMC reset. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0054] Figure 1 This is a schematic diagram of a BMC structure;

[0055] Figure 2 This is a schematic diagram of the structure of the first type of BMC provided in an embodiment of the present invention;

[0056] Figure 3 This is a schematic diagram of the structure of the second type of BMC provided in an embodiment of the present invention;

[0057] Figure 4 This is a schematic diagram of the third type of BMC provided in an embodiment of the present invention;

[0058] Figure 5This is a schematic diagram of the first process of the BMC reset method provided in an embodiment of the present invention;

[0059] Figure 6 This is a schematic diagram of a second process for resetting the BMC provided in an embodiment of the present invention;

[0060] Figure 7 This is a schematic diagram of the BMC reset device provided in an embodiment of the present invention. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art based on the present invention are within the scope of protection of the present invention.

[0062] The BMC has various reset sources, including external buttons, watchdog timers, and software resets. As the server's manager, apart from a full-chip power-down reset, other resets must not affect server-side services and must maintain uninterrupted local display. Therefore, the BMC needs to support flexible partial reset functionality, such as... Figure 1 As shown, when a partial reset occurs in the BMC, it should not affect multiple modules such as PCIe, Video, GPU (Graphics Processing Unit), DDR (Double Data Rate Synchronous Dynamic Random Access Memory), VGA, DP, and HDMI, but should reset other modules and the CPU to ensure normal local display functionality. Since BMC resets can occur at any time, especially button resets, it is necessary to ensure that resets during data transmission do not affect the system bus. However, current BMC reset mechanisms are relatively inflexible.

[0063] To improve the flexibility of BMC reset, embodiments of the present invention provide a BMC, a BMC reset method, an apparatus, and a storage medium. The BMC provided in these embodiments is described below. Figure 2 As shown, the BMC includes: a processor 101, a clock reset module 102, and functional modules 103 other than the clock reset module 102; the clock reset module 102 is connected to the reset pins of each functional module 103; the clock reset module 102 includes: a first register for recording reset source information;

[0064] The processor 101 mentioned above can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. There can be multiple functional modules 103, and each functional module 103 is used to implement a specific business function.

[0065] When the clock reset module 102 is triggered to perform reset control, it records the reset source information in the first register and triggers the corresponding function module 103 that needs to be reset to perform the reset through the connected reset pin.

[0066] After resetting itself, the processor 101 reads the reset source information from the first register and determines the configuration information corresponding to the read reset source information as the target configuration information; wherein, the configuration information corresponding to each reset source information records the functional module that needs to be reset.

[0067] The above reset source information indicates the source that triggered the BMC to perform a reset. For example, when a reset is triggered by a button, 01 can be recorded in the first register; when a reset is triggered by a watchdog timer, 10 can be recorded in the first register; and when a reset is triggered by software, 11 can be recorded in the first register.

[0068] Furthermore, after resetting itself, the processor 101 can read the reset source information from the first register and then clear the reset source information recorded in the first register to save storage space in the registers of the clock reset module 102. Afterward, the processor 101 can begin normal business processing.

[0069] In one implementation, the clock reset module 102 further includes a second register. When the first reset condition is met, the processor 101 can determine the functional module requiring reset recorded in the configuration information corresponding to the reset source information, and write reset control information indicating the functional module 103 requiring reset into the second register. After the reset control information is written into the second register, the clock reset module 102 can trigger the functional module 103 to perform a reset by outputting a reset signal to the connected target reset pin; the target reset pin is the reset pin of the functional module 103 indicated by the written reset control information.

[0070] For example, the second register can be a 32-bit register, with each bit corresponding to a functional module 103. When any bit is changed from 0 to 1, the clock reset module 102 triggers the corresponding functional module 103 to perform a reset. Understandably, when there are more than 32 functional modules 103 that need to be controlled, multiple second registers can be set in the clock reset module 102.

[0071] This implementation requires the processor 101 to initiate the BMC reset. Specifically, the process can be executed by software running on the processor 101. This reset method can be performed in any situation except when the processor 101 is stuck. Furthermore, this implementation allows for flexible configuration of the modules that need to be reset in the configuration information, thereby further improving the flexibility of the BMC reset.

[0072] Processor 101 writes reset control information indicating that functional module 103 needs to be reset into the second register, which may specifically include:

[0073] The processor 101 controls the process corresponding to the functional module 103 that needs to be reset to stop running, and after receiving a signal from the functional module 103 that the current task has been completed, it writes the reset control information of the functional module 103 that needs to be reset into the second register.

[0074] Understandably, the processor 101 runs the process corresponding to the functional module 103. This process interacts with the corresponding functional module 103 through the processor 101 to enable the functional module 103 to process the corresponding data. When a reset is required, the processor 101 can first stop the process corresponding to the functional module 103 that needs to be reset. After receiving a signal from the functional module 103 indicating that the current task processing is complete, indicating that there is no residual data in the functional module 103, reset control information is written to the second register to trigger a reset of the functional module 103. The above process of the processor 101 can be implemented by the running software. In this way, the software running in the processor 101 can be responsible for clearing the residual data of each bus and each IP (intellectual property) hardware before resetting. This eliminates the need to design complex residual data processing circuits for the buses and each functional module 103 in the BMC chip, thereby reducing the logic complexity of the BMC chip and the development difficulty of the BMC chip.

[0075] In this embodiment, the clock reset module 102 is connected to the reset pins of each functional module 103, enabling it to trigger different functional modules 103 to perform resets for different reset sources. Furthermore, the clock reset module 102 can record reset source information in its first register. Thus, when the processor 101 performs a reset, it can read the reset source information from the first register and determine the functional module 103 that performed the reset based on preset configuration information, thereby initializing the reset functional module 103. It is evident that the hardware and software in this solution work together. By recording reset source information in the register of the clock reset module 102 and pre-setting configuration information, the BMC can control the corresponding functional module 103 to perform a reset based on different reset sources, rather than only controlling a fixed functional module 103 to perform a reset, thus improving the flexibility of BMC reset.

[0076] In one embodiment of the present invention, the first reset condition includes: the processor 101 receiving a reset interrupt signal; the reset interrupt signal is generated by the clock reset module 102 after receiving a button reset signal;

[0077] When the clock reset module 102 receives the button reset signal, it triggers a reset interrupt signal to the processor 101.

[0078] The button reset signal can be triggered by the user pressing and holding the reset button on the BMC. The reset interrupt signal triggered by the clock reset module 102 can be a high-priority interrupt.

[0079] When the aforementioned clock reset module 102 is triggered to perform reset control, it records reset source information in the first register, including:

[0080] The clock reset module 102, upon receiving a button reset signal, records reset source information indicating that the reset was triggered by the button in a first register. Specifically, a specific logic circuit can be configured in the clock reset module 102 to write reset source information indicating that the reset was triggered by the button into the first register after receiving the button reset signal.

[0081] When processor 101 receives a reset interrupt signal triggered by clock reset module 102, it can determine that the current reset source is a button. Then, based on the configuration information, it can determine the functional module 103 that needs to be reset and write reset control information for the functional module 103 into the second register to trigger it to perform a reset. After resetting itself, it reads the reset source information from the first register, determines the module that performed the reset based on the preset configuration information and the read reset source information, and initializes the module that performed the reset. Specifically, the above process can be executed using software within processor 101.

[0082] In one specific implementation, such as Figure 3 As shown, this embodiment is different from... Figure 1 As shown in the BMC, by setting the configuration information, the reset domain can be defined, and the modules related to the local display function can be isolated from other modules. Thus, when the reset is triggered by the button, the software running in the CPU writes the reset control information of the functional module that needs to be reset into the second register, which can also achieve the purpose of keeping the local display of the server uninterrupted when the BMC is reset.

[0083] In this embodiment, when the clock reset module 102 receives a button reset signal, it triggers a reset interrupt signal to the processor 101 and records reset source information indicating that the reset was triggered by the button in the first register. After the processor 101 performs a reset, it can read the reset source information from the first register and determine the function module 103 that was triggered by the button reset according to the preset configuration information, so as to initialize the function module 103 that performed the reset. Therefore, this embodiment enables the BMC to be reset by button, and also allows for flexible configuration of the modules that need to be reset in the configuration information, thereby further improving the flexibility of resetting the BMC by button.

[0084] In one embodiment of the present invention, the first reset condition includes: a software-triggered reset running by the processor 101;

[0085] In the event of a software-triggered reset, the processor 101 transmits reset source information indicating that the reset was triggered by the software to the clock reset module 102.

[0086] For example, when a firmware upgrade of the BMC or a service malfunction occurs in the processor 101, the software running on the processor 101 can initiate a BMC service reset and transmit reset source information indicating that the reset was triggered by the software to the clock reset module 102.

[0087] When the clock reset module 102 is triggered to perform a reset, it records the reset source information in the first register, which may specifically include:

[0088] When the clock reset module 102 receives the reset source information transmitted by the processor 101, it records the reset source information in the first register.

[0089] For example, processor 101 can directly write reset source information indicating a software-triggered reset into the first register.

[0090] Then, the processor 101 can determine the functional module 103 that needs to be reset based on the configuration information and the reset source. Then, when it is determined that there is no residual data in the module that needs to be reset, the processor 101 writes the reset control information of the functional module 103 that needs to be reset into the second register to trigger the functional module 103 that needs to be reset to perform the reset. After resetting itself, the processor 101 reads the reset source information from the first register, determines the module that has been reset based on the preset configuration information and the read reset source information, and initializes the module that has been reset.

[0091] In this embodiment, when a software-triggered reset is initiated, reset source information indicating a software-triggered reset is transmitted to the clock reset module 102. Upon receiving the reset source information from the processor 101, the clock reset module 102 records the reset source information in a first register. After the processor 101 performs a reset, it can read the reset source information from the first register and determine the software-triggered reset function module 103 based on preset configuration information, thereby initializing the reset function module 103. Therefore, this embodiment enables BMC reset via buttons and allows flexible configuration of the modules requiring reset in the configuration information, further improving the flexibility of BMC reset via buttons. By setting the configuration information, it is also possible to maintain uninterrupted local display on the server during BMC reset.

[0092] In one embodiment of the present invention, the clock reset module 102 is provided with a reset control circuit, which is connected to the reset pin of the designated functional module 103 in the BMC.

[0093] When the clock reset module 102 is triggered to perform a reset, it records the reset source information in the first register, which may specifically include:

[0094] When the clock reset module 102 receives a reset signal triggered by the watchdog timer, it records the reset source information indicating that the watchdog timer triggered the reset in the first register.

[0095] When the processor 101 is in a suspended state, the watchdog can trigger a reset signal to the clock reset module 102. Since the processor 101 is suspended, the bus service data transmission is interrupted, so no software intervention is required before the reset.

[0096] The clock reset module 102 triggers the corresponding function module 103 that needs to be reset via the connected reset pin to perform the reset, including:

[0097] The clock reset module 102 triggers the designated function module 103 to perform a reset via the reset control circuit.

[0098] In the configuration information, watchdog-triggered reset corresponds to designated functional module 103. That is, the correspondence between functional modules 103 and watchdog-triggered reset needs to be recorded in the configuration information beforehand, based on the functional modules 103 controlled by the reset control circuit. This way, after the processor 101 performs a reset, it can read the reset source information from the first register and determine the functional module 103 triggered by the watchdog reset according to the preset configuration information, thus initializing the reset functional module 103.

[0099] In order to ensure that the local display of the server is not interrupted when the BMC is reset, the specified functional module 103 may not include modules related to the local display function.

[0100] In this embodiment, the flexibility of BMC reset is improved. Furthermore, the clock reset module 102 is equipped with a reset control circuit, which is connected to the reset pin of the designated functional module 103 in the BMC. When the clock reset module 102 receives a watchdog-triggered reset signal, it records the reset source information indicating the watchdog-triggered reset in the first register, and triggers the designated functional module 103 to perform the reset through the reset control circuit, thereby realizing watchdog-triggered BMC reset.

[0101] Figure 4 This is a schematic diagram of a BMC provided in an embodiment of the present invention. The BMC can include a CPU, a reset button, a clock reset module, a watchdog timer, a display module related to local display functions, and other functional modules besides the display module. The clock reset module includes a first register, a second register, and a reset control circuit. The first register is used to record reset source information, including button triggering, watchdog triggering, and software triggering.

[0102] The reset signal output by the reset control circuit is triggered by the watchdog timer. To ensure uninterrupted local display during BMC reset, the reset control circuit in the clock reset module can be used only to control the reset of functional modules other than the display module. Therefore, the server's local display function will not be interrupted throughout the entire reset process.

[0103] When the reset source is a button trigger or a software trigger, the CPU can write reset control information for the functional module that needs to be reset into the second register according to preset configuration information, thereby triggering the relevant functional module to perform the reset, such as triggering the reset of modules other than the display module. After resetting itself, the CPU can read the reset source information from the first register, determine the module that performed the reset according to the preset configuration information and the read reset source information, and initialize the module that performed the reset. For example, it can initialize functional modules other than the display module without re-initializing the display module. The above process performed by the CPU can be implemented using software running in the CPU.

[0104] As can be seen, the BMC provided by this invention can control the corresponding functional module to perform reset according to different reset sources, rather than only controlling a fixed functional module to perform reset, thus improving the flexibility of BMC reset. Furthermore, since the functional module is controlled by software running in the CPU to perform reset when there is no residual data, there is no need to design residual data processing circuitry in the BMC chip, which greatly simplifies the BMC chip hardware design, solves the problem of complex hardware implementation related to partial reset in BMC chips, shortens the chip development cycle, reduces chip area, and lowers chip cost.

[0105] Based on the same inventive concept, this embodiment of the invention also provides a BMC reset method, applied to the processor of a Baseboard Management Controller (BMC). The BMC further includes: a clock reset module and functional modules other than the clock reset module; the clock reset module is connected to the reset pins of each functional module; the clock reset module includes: a first register for recording reset source information; the clock reset module is used to: record reset source information in the first register when triggered for reset control, and trigger the functional module corresponding to the reset source information to perform a reset through the connected reset pins; for example... Figure 5 As shown, the method includes:

[0106] S501 reads the reset source information from the first register after the processor is reset;

[0107] S502, determine the configuration information corresponding to the read reset source information as the target configuration information; wherein, the configuration information corresponding to each reset source information records the functional module that needs to be reset corresponding to the reset source information;

[0108] S503 initializes the functional modules recorded in the target configuration information.

[0109] In one embodiment of the present invention, the clock reset module further includes: a second register; as shown below. Figure 6 As shown, the method also includes:

[0110] S601, when the first reset condition is met, determine the functional module that needs to be reset recorded in the configuration information corresponding to the reset source information;

[0111] S602, write the reset control information of the functional module that needs to be reset into the second register, so that after the clock reset module writes the reset control information into the second register, it can trigger the functional module to perform the reset by outputting a reset signal to the connected target reset pin; wherein, the target reset pin is: the reset pin of the functional module represented by the written reset control information.

[0112] In one embodiment of the present invention, the first reset condition includes: the processor receiving a reset interrupt signal; the reset interrupt signal is generated by the clock reset module after receiving a key reset signal.

[0113] In one embodiment of the present invention, the first reset condition includes: a software-triggered reset running by the processor; the method further includes:

[0114] In the event of a software-triggered reset, reset source information indicating a software-triggered reset is transmitted to the clock reset module, so that the clock reset module records the reset source information in the first register.

[0115] In one embodiment of the present invention, reset control information indicating a functional module requiring reset is written into the second register, including:

[0116] The process corresponding to the functional module that needs to be reset is stopped from running. After receiving a signal from the functional module that needs to be reset indicating that the current task has been completed, the reset control information of the functional module that needs to be reset is written into the second register.

[0117] In one embodiment of the present invention, the clock reset module is provided with a reset control circuit, which is connected to the reset pin of a designated functional module in the BMC; the clock reset module is specifically used to: when a watchdog-triggered reset signal is received, record reset source information indicating watchdog-triggered reset in the first register, and trigger the designated functional module to perform reset through the reset control circuit; in the configuration information, watchdog-triggered reset corresponds to the designated functional module.

[0118] In one embodiment of the present invention, after reading the reset source information from the first register after the processor is reset, the method further includes:

[0119] Clear the reset source information recorded in the first register.

[0120] This invention also provides a reset device for a Baseboard Management Controller (BMC), applied to the processor of the BMC. The BMC further includes a clock reset module and functional modules other than the clock reset module. The clock reset module is connected to the reset pins of each functional module. The clock reset module includes a first register for recording reset source information. The clock reset module is used to: record the reset source information in the first register when triggered for reset control, and trigger the corresponding functional module requiring reset to perform a reset via the connected reset pins. Figure 7 As shown, the device includes:

[0121] The reset source information reading unit 701 is used to read reset source information from the first register after the processor is reset;

[0122] The first module determining unit 702 is used to determine the configuration information corresponding to the read reset source information as the target configuration information; wherein, the configuration information corresponding to each reset source information records the functional module that needs to be reset corresponding to the reset source information;

[0123] The initialization unit 703 is used to initialize the functional modules recorded in the target configuration information.

[0124] In one embodiment of the present invention, the clock reset module further includes: a second register; the device further includes:

[0125] The second module determination unit is used to determine the functional module that needs to be reset recorded in the configuration information corresponding to the reset source information when the first reset condition is met.

[0126] The control information writing unit is used to write reset control information representing the functional module that needs to be reset into the second register, so that after the clock reset module writes the reset control information into the second register, it can trigger the functional module to perform a reset by outputting a reset signal to the connected target reset pin; the target reset pin is the reset pin of the functional module represented by the written reset control information.

[0127] In one embodiment of the present invention, the first reset condition includes: the processor receiving a reset interrupt signal; the reset interrupt signal is generated by the clock reset module after receiving a key reset signal.

[0128] In one embodiment of the present invention, the first reset condition includes: a software-triggered reset executed by the processor; the device further includes:

[0129] The reset source information writing unit is used to transmit reset source information indicating that the reset was triggered by software to the clock reset module when the running software triggers a reset, so that the clock reset module records the reset source information in the first register.

[0130] In one embodiment of the present invention, the control information writing unit is specifically used for:

[0131] The process corresponding to the functional module that needs to be reset is stopped from running. After receiving a signal from the functional module that needs to be reset indicating that the current task has been completed, the reset control information of the functional module that needs to be reset is written into the second register.

[0132] In one embodiment of the present invention, the clock reset module is provided with a reset control circuit, which is connected to the reset pin of a designated functional module in the BMC; the clock reset module is specifically used to: when a watchdog-triggered reset signal is received, record reset source information indicating watchdog-triggered reset in the first register, and trigger the designated functional module to perform reset through the reset control circuit; in the configuration information, watchdog-triggered reset corresponds to the designated functional module.

[0133] In one embodiment of the present invention, the device further includes:

[0134] The reset source information clearing module is used to clear the reset source information recorded in the first register after the processor is reset and the reset source information is read from the first register.

[0135] In another embodiment of the present invention, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements the steps of any of the above-described BMC reset methods.

[0136] In another embodiment of the present invention, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute the reset method of any BMC in the above embodiments.

[0137] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0138] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0139] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of methods, apparatus, readable storage media, and computer program products are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0140] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A BMC, characterized in that, The BMC includes: a processor, a clock reset module, and functional modules other than the clock reset module; the clock reset module is connected to the reset pin of each functional module; the clock reset module includes: a first register for recording reset source information; When the clock reset module is triggered to perform reset control, it records the reset source information in the first register and triggers the functional module that needs to be reset to perform the reset through the connected reset pin. After resetting itself, the processor reads reset source information from the first register and determines the configuration information corresponding to the read reset source information as the target configuration information; wherein, the configuration information corresponding to each reset source information records the functional module that needs to be reset corresponding to that reset source information; The processor initializes the functional modules recorded in the target configuration information.

2. The BMC according to claim 1, characterized in that, The clock reset module further includes: a second register; When the first reset condition is met, the processor determines the functional module that needs to be reset recorded in the configuration information corresponding to the reset source information, and writes the reset control information of the functional module that needs to be reset into the second register. The clock reset module triggers the corresponding functional module that needs to be reset to perform a reset via the connected reset pin, including: After the clock reset module writes reset control information into the second register, it triggers the functional module to which the target reset pin belongs to perform a reset by outputting a reset signal to the connected target reset pin; the target reset pin is the reset pin of the functional module represented by the written reset control information.

3. The BMC according to claim 2, characterized in that, The first reset condition includes: the processor receiving a reset interrupt signal; the reset interrupt signal is generated by the clock reset module after receiving a button reset signal; When the clock reset module receives a button reset signal, it triggers a reset interrupt signal to the processor. When the clock reset module is triggered to perform reset control, it records reset source information in the first register, including: When the clock reset module receives a button reset signal, it records the reset source information indicating that the reset was triggered by the button in the first register.

4. The BMC according to claim 2, characterized in that, The first reset condition includes: a software-triggered reset running by the processor; In the event of a software-triggered reset, the processor transmits reset source information indicating that the reset was triggered by software to the clock reset module. When the clock reset module is triggered to perform a reset, it records reset source information in the first register, including: When the clock reset module receives the reset source information transmitted by the processor, it records the reset source information in the first register.

5. The BMC according to any one of claims 2-4, characterized in that, The processor writes reset control information, indicating the functional module that needs to be reset, into the second register, including: The processor controls the process corresponding to the functional module that needs to be reset to stop running, and after receiving a signal from the functional module that needs to be reset indicating that the current task has been completed, it writes the reset control information of the functional module that needs to be reset into the second register.

6. The BMC according to claim 1, characterized in that, The clock reset module is equipped with a reset control circuit, which is connected to the reset pin of a designated functional module in the BMC. When the clock reset module is triggered to perform a reset, it records reset source information in the first register, including: When the clock reset module receives a reset signal triggered by the watchdog timer, it records the reset source information indicating that the watchdog timer triggered the reset in the first register. The clock reset module triggers the corresponding functional module that needs to be reset to perform a reset via the connected reset pin, including: The clock reset module triggers the designated functional module to perform a reset through the reset control circuit. In the configuration information, the watchdog trigger reset corresponds to the specified functional module.

7. The BMC according to claim 1, characterized in that, After resetting itself, the processor reads the reset source information from the first register and then clears the reset source information recorded in the first register.

8. A method for resetting a BMC, characterized in that, A processor applied to a baseboard management controller (BMC), the BMC further comprising: a clock reset module and functional modules other than the clock reset module; the clock reset module is connected to the reset pins of each functional module; the clock reset module includes: a first register for recording reset source information; the clock reset module is used to: record the reset source information in the first register when triggered for reset control, and trigger the functional module corresponding to the reset source information to perform a reset through the connected reset pins; the method includes: After the processor is reset, the reset source information is read from the first register; The configuration information corresponding to the read reset source information is determined as the target configuration information; wherein, the configuration information corresponding to each reset source information records the functional module that needs to be reset corresponding to that reset source information; The functional modules recorded in the target configuration information are initialized.

9. The method according to claim 8, characterized in that, The clock reset module further includes: a second register; the method further includes: When the first reset condition is met, determine the functional module that needs to be reset, which is recorded in the configuration information corresponding to the reset source information. Write reset control information for the functional module that needs to be reset into the second register, so that after the reset control information is written into the second register, the clock reset module can trigger the functional module to which the target reset pin belongs to perform a reset by outputting a reset signal to the connected target reset pin; the target reset pin is the reset pin of the functional module represented by the written reset control information.

10. The method according to claim 9, characterized in that, The first reset condition includes: the processor receiving a reset interrupt signal; the reset interrupt signal is generated by the clock reset module after receiving a button reset signal.

11. The method according to claim 9, characterized in that, The first reset condition includes: a software-triggered reset running by the processor; the method further includes: In the event of a software-triggered reset, reset source information indicating a software-triggered reset is transmitted to the clock reset module, so that the clock reset module records the reset source information in the first register.

12. The method according to any one of claims 9-11, characterized in that, Write reset control information indicating the functional module that needs to be reset into the second register, including: The process corresponding to the functional module that needs to be reset is stopped from running. After receiving a signal from the functional module that needs to be reset indicating that the current task has been completed, the reset control information of the functional module that needs to be reset is written into the second register.

13. The method according to claim 8, characterized in that, The clock reset module is equipped with a reset control circuit, which is connected to the reset pin of the designated functional module in the BMC. Specifically, the clock reset module is used to: when a watchdog-triggered reset signal is received, record the reset source information indicating the watchdog-triggered reset in the first register, and trigger the designated functional module to perform a reset through the reset control circuit; in the configuration information, the watchdog-triggered reset corresponds to the designated functional module.

14. The method according to claim 8, characterized in that, After reading the reset source information from the first register after the processor is reset, the method further includes: Clear the reset source information recorded in the first register.

15. A BMC reset device, characterized in that, A processor applied to a baseboard management controller (BMC), the BMC further comprising: a clock reset module and functional modules other than the clock reset module; the clock reset module is connected to the reset pins of each functional module; the clock reset module includes: a first register for recording reset source information; the clock reset module is used to: record the reset source information in the first register when triggered for reset control, and trigger the functional module corresponding to the reset source information to perform a reset through the connected reset pins; the device includes: A reset source information reading unit is used to read reset source information from the first register after the processor is reset; The first module determining unit is used to determine the configuration information corresponding to the read reset source information as the target configuration information; wherein, the configuration information corresponding to each reset source information records the functional module that needs to be reset corresponding to the reset source information; An initialization unit is used to initialize the functional modules recorded in the target configuration information.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 8-14.

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