PSRAM-based controller, control method and integrated circuit
By using a PSRAM-based controller, the AHB bus and PSRAM chips can interact efficiently through a locking signal and an arbitration unit, which solves the problem of low system execution efficiency and improves the data interaction efficiency and controller stability of RGB screen display.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-23
- Publication Date
- 2026-04-07
AI Technical Summary
In existing technologies, the interaction between the AHB bus and the PSRAM chip results in low system execution efficiency, which cannot efficiently meet the display requirements of RGB screens.
A PSRAM-based controller is adopted, including a data receiving unit, a first asynchronous FIFO unit, a PSRAM write unit, a PSRAM read unit, and a second asynchronous FIFO unit. The read and write operations are autonomously judged and executed through locking signals and arbitration units, reducing the time occupied on the AHB bus.
It improves system execution efficiency, reduces software configuration requirements, ensures data sampling accuracy and controller stability, and optimizes the interaction process between the AHB bus and PSRAM chips.
Smart Images
Figure CN121807227A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of PSRAM technology, and specifically relates to a PSRAM-based controller, control method, and integrated circuit. Background Technology
[0002] like Figure 1 As shown, the AHB bus currently interacts with PSRAM chips through DWC_SSI (DesignWare Core Synchronous Serial Interface, a synchronous serial interface IP core from DesignWare). The DWC_SSI IP core was acquired by Synopsys through its acquisition of DesignWare. The DWC_SSI IP core is specifically designed for handling high-speed serial interface communication, including applications such as PSRAM interfaces. The DWC_SSI IP core has multiple functions and can be configured via software to perform write or read operations. For RGB screens, since they do not have built-in RAM, the PSRAM chips need to be used as external RAM to store image data. To display various images on an RGB screen, the data in the PSRAM chips needs to be constantly changed, meaning that PSRAM read / write functions need to be continuously interleaved. Therefore, the parameters in the DWC_SSI controller need to be repeatedly configured. Because the PSRAM read / write functions need to be continuously interleaved, this leads to long-term occupation of the AHB bus, causing other modules to wait when they want to use the AHB bus, resulting in very low system efficiency. How to provide an effective, reliable, convenient, and efficient controller and control method to achieve efficient interaction between the AHB bus and PSRAM chips to meet the display requirements of RGB screens is a problem that urgently needs to be solved. Summary of the Invention
[0003] In view of this, the present invention provides a PSRAM-based controller and control method to overcome the shortcomings of the prior art.
[0004] To achieve the above objectives, the present invention adopts the following technical solution:
[0005] This invention provides a PSRAM-based controller for data interaction between an AHB bus and PSRAM chips, comprising:
[0006] Data receiving unit, first asynchronous FIFO unit, PSRAM write unit, PSRAM read unit, second asynchronous FIFO unit;
[0007] The data receiving unit is responsible for acquiring data from external RAM via the AHB bus and storing the data in the first asynchronous FIFO unit;
[0008] The first asynchronous FIFO unit is used to buffer the data received by the data receiving unit;
[0009] The PSRAM write unit is used to retrieve the data from the first asynchronous FIFO unit in a timely manner according to the acquired signal and store it into the PSRAM chip in a parallel-to-serial conversion manner;
[0010] The PSRAM read unit is used to retrieve the data from the PSRAM chip in a timely manner according to the acquired signal and store it into the second asynchronous FIFO unit in a serial-to-parallel conversion manner.
[0011] The second asynchronous FIFO unit is used to cache data read from the PSRAM particle for external use.
[0012] Furthermore, the PSRAM write unit and PSRAM read unit use the empty signal provided by the first asynchronous FIFO unit, the half-full signal provided by the second asynchronous FIFO unit, the write lock signal wr_lock provided by the PSRAM write unit, and the read lock signal rd_lock provided by the PSRAM read unit to determine whether to perform a read or write operation;
[0013] When the PSRAM write unit detects that the empty signal provided by the first asynchronous FIFO unit is valid and the read lock signal rd_lock provided by the PSRAM read unit is invalid, it starts to execute the write operation and sets the write lock signal wr_lock to valid.
[0014] When the PSRAM read unit detects that the half-full signal provided by the second asynchronous FIFO unit is valid and the write lock signal wr_lock provided by the PSRAM write unit is invalid, it starts to perform a read operation and sets the read lock signal rd_lock to valid.
[0015] Furthermore, both the read lock signal rd_lock and the write lock signal wr_lock are active high, and both the empty signal and the half-full signal are active low.
[0016] Furthermore, both the PSRAM read unit and the PSRAM write unit can use the internal fast clock to sample data. However, the sampling conditions of the phase and the number of waiting cycles need to be adjusted to accurately sample the data.
[0017] Furthermore, the waiting period generated by the internal fast clock can be configured and adjusted. By adjusting the default waiting period of acquiring one high level and one low level of the clock signal to acquiring only one high level or one low level of the clock signal, the counting method of the waiting period is changed from one to half a period. By adjusting the waiting period, the requirement for accurate data sampling can be met even under the conditions of device function delay and path delay.
[0018] Furthermore, the PSRAM read unit can also use the DM signal provided by the PSRAM chip as a clock for sampling; by using the DM signal provided by the PSRAM chip, data can be accurately sampled without adjusting the sampling conditions of the phase and the number of waiting cycles.
[0019] Furthermore, it also includes: a PSRAM arbitration unit;
[0020] The PSRAM arbitration unit is used to replace the PSRAM write unit and PSRAM read unit to complete the arbitration judgment and output the corresponding response signal to the PSRAM write unit and PSRAM read unit; specifically as follows: when the empty signal provided by the first asynchronous FIFO unit is detected to be valid and the read lock signal rd_lock provided by the PSRAM read unit is invalid, a valid write request signal wr_req is output to the PSRAM write unit; when the half-full signal provided by the second asynchronous FIFO unit is detected to be valid and the write lock signal wr_lock provided by the PSRAM write unit is invalid, a valid read request signal rd_req is output to the PSRAM read unit.
[0021] The PSRAM write unit is used to retrieve the data from the first asynchronous FIFO unit and store it into the PSRAM chip in a parallel-to-serial manner when a valid write request signal wr_req is detected.
[0022] When a valid read request signal rd_req is detected, the PSRAM read unit retrieves the data from the PSRAM chip and stores it in the second asynchronous FIFO unit in a serial-to-parallel conversion manner.
[0023] This invention also provides a PSRAM-based control method applied to the PSRAM-based controller described above, the method comprising:
[0024] When the empty signal provided by the first asynchronous FIFO unit is detected to be valid and the read lock signal rd_lock provided by the PSRAM read unit is invalid, the PSRAM write unit starts to perform a write operation, retrieves the data from the first asynchronous FIFO unit and stores it into the PSRAM chip in a parallel-to-serial conversion manner; and sets the write lock signal wr_lock to valid.
[0025] When the half-full signal provided by the second asynchronous FIFO unit is detected to be valid and the write lock signal wr_lock provided by the PSRAM write unit is invalid, the PSRAM read unit starts to perform a read operation. The data in the PSRAM chip is retrieved and stored in the second asynchronous FIFO unit in a serial-to-parallel manner, and the read lock signal rd_lock is set to valid.
[0026] Furthermore, it also includes: when the half_full signal provided by the first asynchronous FIFO unit is detected to be invalid, data is obtained from the external RAM through the AHB bus and stored in the first asynchronous FIFO unit for external use.
[0027] This invention also provides an integrated circuit including the PSRAM-based controller described above, which is used to replace the DesignWare Synchronous Serial Interface core to realize data interaction between the AHB bus and the PSRAM chip.
[0028] The controller provided in this application eliminates the need for repeated software configuration of read and write enable during operation. The controller's internal logic automatically determines whether to perform a write or read operation, thus reducing AHB bus usage time and improving system efficiency. The PSRAM read unit also provides a DM sampling mode, which accurately samples data using the DM signal provided by the PSRAM chip without adjusting the phase sampling conditions or the number of waiting cycles. This allows for accurate data sampling without changing the phase sampling conditions or waiting cycles while the PSRAM read unit is operating, reducing software intervention and improving overall efficiency.
[0029] The wait period is generated by a fast clock and can be configured and adjusted. The advantage of this configuration and adjustment is that even if there are delays in device function and path, the usage requirements can still be met by configuring the phase sampling conditions and the number of wait periods. There will be no situation where the phase sampling conditions are changed or the data cannot be sampled correctly after the wait period, which can ensure the stability of the controller. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a schematic diagram of the interaction between the AHB bus and PSRAM chips in the prior art;
[0032] Figure 2 This is a schematic diagram of a controller implementing interaction between the AHB bus and PSRAM chips according to an embodiment of the present invention;
[0033] Figure 3 This is a schematic diagram of a controller that implements interaction between the AHB bus and PSRAM chips, provided by another embodiment of the present invention. Detailed Implementation
[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0035] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
[0036] like Figure 2As shown, this embodiment of the invention provides a PSRAM-based controller for data interaction between an AHB bus and PSRAM chips, including: a data receiving unit, a first asynchronous FIFO unit, a PSRAM write unit, a PSRAM read unit, and a second asynchronous FIFO unit. The data receiving unit is responsible for acquiring data from external RAM via the AHB bus and storing the data in the first asynchronous FIFO unit. The first asynchronous FIFO unit is used to buffer the data received by the data receiving unit. The PSRAM write unit is used to retrieve the data from the first asynchronous FIFO unit in a timely manner according to the acquired signal and store it in the PSRAM chip in a parallel-to-serial conversion. The PSRAM read unit is used to retrieve the data from the PSRAM chip in a timely manner according to the acquired signal and store it in the second asynchronous FIFO unit in a serial-to-parallel conversion. The second asynchronous FIFO unit is used to buffer the data read from the PSRAM chip for external use. The PSRAM write unit and PSRAM read unit use the empty signal provided by the first asynchronous FIFO unit, the half-full signal provided by the second asynchronous FIFO unit, the write lock signal wr_lock provided by the PSRAM write unit, and the read lock signal rd_lock provided by the PSRAM read unit to determine whether to perform a read or write operation. When the PSRAM write unit detects that the empty signal provided by the first asynchronous FIFO unit is valid (low level) and the read lock signal rd_lock provided by the PSRAM read unit is low level (invalid), it starts the write operation and sets the write lock signal wr_lock high level (valid). When the PSRAM read unit detects that the half-full signal provided by the second asynchronous FIFO unit is valid (low level) and the write lock signal wr_lock provided by the PSRAM write unit is low level (invalid), it starts the read operation and sets the read lock signal rd_lock high level (valid). Both the read lock signal rd_lock and the write lock signal wr_lock are valid high level, and both the empty signal and the half-full signal are valid low level. The PSRAM write unit and PSRAM read unit generate wr_lock and rd_lock signals respectively when performing write or read operations. By judging the wr_lock signal or rd_lock signal, other functions can be prohibited from being executed.
[0037] PSRAM read cells offer two data sampling methods: one utilizes an internal fast clock, and the other uses the DM (Data Mask) signal provided by the PSRAM chip as a clock signal. Since PSRAM chips use dual-edge sampling, the sampling clock frequency must be at least twice the PSRAM clock frequency. Only by using a fast clock can dual-edge sampling be achieved, and because it's dual-edge sampling, the sampling efficiency is also higher.
[0038] Using the internal fast clock to sample data requires adjusting the phase sampling conditions and the number of waiting periods to accurately sample the data. Using the DM signal provided by the PSRAM chip, however, does not require adjusting the phase sampling conditions and the number of waiting periods to accurately sample the data.
[0039] Since there is no dedicated arbitration unit, the PSRAM write unit and PSRAM read unit independently determine the empty signal in the first asynchronous FIFO unit and the half_full signal in the second asynchronous FIFO unit to control read and write operations. Specifically, when the PSRAM write unit detects that the empty signal in the first asynchronous FIFO unit is valid and the rd_lock signal from the PSRAM read unit is low, it starts the write operation and sets the wr_lock signal high. When the PSRAM read unit detects that the half_full signal in the second asynchronous FIFO unit is valid and the wr_lock signal from the PSRAM write unit is low, it starts the read operation and sets the rd_lock signal high.
[0040] The data receiving unit will retrieve data of a preset bit width from RAM via the AHB bus according to the request signal, and store the data in the first asynchronous FIFO unit via the write signal. Then, it will continuously check the half_full signal of the first asynchronous FIFO unit. Once it detects that the half_full signal is not satisfied, it will again use the AHB bus to retrieve data from RAM and store it in the first asynchronous FIFO unit.
[0041] The PSRAM read unit can eliminate the internal fast clock sampling data function, and only use the DM signal provided by the PSRAM chip to sample data, thus reducing the chip area without affecting the actual application requirements.
[0042] like Figure 3 As shown, this embodiment of the invention provides a PSRAM-based controller, and... Figure 2In comparison, only one PSRAM arbitration unit is added. This unit detects signals and controls the operations of the PSRAM read and write units. Having a dedicated PSRAM arbitration unit to detect and determine when read / write operations can be performed effectively reduces the multitasking load on the PSRAM read and write units, thus significantly improving their read / write efficiency.
[0043] The data receiving unit retrieves data from RAM via the AHB bus and stores it in the first asynchronous FIFO unit. The width and depth of the first asynchronous FIFO unit can be 32 and 64, respectively. When the sampling enable signal is valid, since the first asynchronous FIFO unit is empty before the first data is stored, the number of data transmitted in the first transmission is 64. Subsequent transmission of the remaining data from RAM to the first asynchronous FIFO unit depends on the half_full signal in the first asynchronous FIFO unit; the number of data to be transmitted is calculated internally by the logic. When the half_full signal is detected to be low, it indicates that less than half of the data remains in the first asynchronous FIFO unit. At this point, the internal logic begins calculation. Since the number of rows to be transmitted and the number of data items per row have been configured during initialization, the number of data items to be transmitted per row is subtracted from the number of data items already transmitted. If the remaining number is greater than or equal to 32, then 32 data items are retrieved from RAM and stored in the first asynchronous FIFO unit. If the remaining number is less than 32, then the actual number of remaining data items is retrieved from RAM and stored in the first asynchronous FIFO unit. The number of data items to be transmitted for the next row is calculated in the same way, until all data has been transmitted. When the sampling enable signal becomes valid again, the next round of transmission begins, and so on.
[0044] The function of the first asynchronous FIFO unit is to store and retrieve data. The data receiving unit uses the AHB bus to retrieve data from the RAM and stores the data into the first asynchronous FIFO unit. The PSRAM writing unit retrieves data from the first asynchronous FIFO unit and stores the retrieved data into the PSRAM chip in a parallel-to-serial conversion manner.
[0045] The PSRAM arbitration unit uses the empty signal provided by the first asynchronous FIFO unit, the half_full signal provided by the second asynchronous FIFO unit, the wr_lock signal provided by the PSRAM write unit, and the rd_lock signal provided by the PSRAM read unit to determine the internal logic, and drives the PSRAM write unit and PSRAM read unit by outputting the wr_req signal or the rd_req signal.
[0046] If both the empty and half_full signals are valid, a valid rd_req signal is output to the PSRAM read unit first. Subsequent operations involve continuously checking the rd_lock signal sent by the PSRAM read unit. When the rd_lock signal is 1, it indicates that the PSRAM read unit has not yet finished executing; when the rd_lock signal is 0, it indicates that the PSRAM read unit has finished executing, and a valid wr_req signal can then be output to the PSRAM write unit.
[0047] When the empty signal is valid, the PSRAM arbitration unit will generate a wr_req signal to the PSRAM write unit. The PSRAM write unit will execute operations such as commands, addresses, and wait cycles to the PSRAM chip, and use the internally generated read signal to obtain data from the first asynchronous FIFO unit, and store the data into the PSRAM chip in a parallel-to-serial format.
[0048] When the half_full signal is valid, the PSRAM arbitration unit will generate the rd_req signal to the PSRAM read unit. The PSRAM read unit will execute operations such as commands, addresses, and wait cycles to the PSRAM chip, and store the data sent by the PSRAM chip into the second asynchronous FIFO unit in serial-to-parallel format for other functional units to read and use.
[0049] The empty signal in the second asynchronous FIFO unit does not need to be monitored because write operations to the second asynchronous FIFO unit are faster than read operations, and the number of data items that subsequent modules read from the second asynchronous FIFO unit is pre-configured. As long as the configuration is correct, the data in the second asynchronous FIFO unit will not be empty, so there is no need to monitor the empty signal in the second asynchronous unit. The second asynchronous FIFO unit simply caches the data read from the PSRAM chip for other subsequent modules to read and use.
[0050] When the empty signal provided by the first asynchronous FIFO unit is low and the half_full signal provided by the second asynchronous FIFO unit is low, if the wr_lock signal provided by the PSRAM write unit and the rd_lock signal provided by the PSRAM read unit are both low, it indicates that neither the PSRAM write unit nor the PSRAM read unit is working. At this time, the PSRAM read unit is driven first, and a high-level rd_req signal is output to the PSRAM read unit to drive it to start working. A valid high-level rd_lock signal will be received from the PSRAM read unit, indicating that the PSRAM read unit has started working.
[0051] When only the empty signal provided by the first asynchronous FIFO unit is low and the half_full signal provided by the second asynchronous FIFO unit is high, if both the wr_lock signal provided by the PSRAM write unit and the rd_lock signal provided by the PSRAM read unit are low, it indicates that neither the PSRAM write unit nor the PSRAM read unit is working. In this case, the PSRAM write unit will be driven to output a high-level wr_req signal to the PSRAM write unit to start working, and the high-level wr_lock signal output by the PSRAM write unit will be received. If the rd_lock signal provided by the PSRAM read unit is high, it indicates that the PSRAM read unit is working. In this case, it should wait for the PSRAM read unit to complete its current operation and for the rd_lock signal to return to low before driving the PSRAM write unit to output a high-level wr_req signal to the PSRAM write unit to start working.
[0052] When only the half_full signal provided by the second asynchronous FIFO unit is low and the empty signal provided by the first asynchronous FIFO unit is high, if the wr_lock signal provided by the PSRAM write unit is high at this time, it indicates that the PSRAM write unit is working. Therefore, we should wait for the PSRAM write unit to complete its current round of work and for the wr_lock signal to return to low before driving the PSRAM read unit to output the high-level rd_req signal to the PSRAM read unit and start it working.
[0053] For the PSRAM write unit, it mainly receives the wr_req signal from the arbitration unit and then outputs a high-level wr_lock signal to the arbitration unit. It retrieves data from the first asynchronous FIFO unit, first sending commands, addresses, and wait cycles to the PSRAM chip, and then writing the received data into the PSRAM chip using a parallel-to-serial conversion method. Since its internal configuration pre-determines the number of rows to be transmitted in this round and the number of data items per row, the internal logic calculates and retrieves the calculated number from the first asynchronous FIFO unit.
[0054] For the PSRAM read unit, it mainly receives the rd_req signal from the arbitration unit and then outputs a high-level rd_lock signal to the arbitration unit. First, it sends a command, address, and wait cycle to the PSRAM chip. Then, the data in the PSRAM chip is stored in the second asynchronous FIFO unit in a serial-to-parallel conversion manner. Since its internal configuration pre-determines how many rows to be transmitted in this round and how many data items per row, the internal logic calculates how much data to transmit to the second asynchronous FIFO unit each time.
[0055] The PSRAM write and read units generate wr_lock and rd_lock signals respectively during write and read operations. The PSRAM arbitration unit uses these signals to disable other functions. Specifically, when the PSRAM arbitration unit detects a high wr_lock signal, even if the half_full signal of the second asynchronous FIFO unit is valid, it will not immediately output a valid rd_req signal to the PSRAM read unit. Instead, it will wait until the wr_lock signal returns to a low level before outputting the valid rd_req signal. Similarly, when the PSRAM arbitration unit detects a high rd_lock signal, even if the empty signal of the first asynchronous FIFO unit is valid, it will not immediately output a valid wr_req signal to the PSRAM write unit. Instead, it will wait until the rd_lock signal returns to a low level before outputting the valid wr_req signal.
[0056] The second asynchronous FIFO unit is used to store and retrieve data. The PSRAM read unit retrieves the data from the PSRAM chip and stores the serial-to-parallel converted data into the second asynchronous FIFO unit for use by other functional units.
[0057] This invention also provides a PSRAM-based control method applied to the PSRAM-based controller described above, the method comprising:
[0058] When the first asynchronous FIFO unit detects that the empty signal (low level) is valid and the read lock signal (rd_lock) provided by the PSRAM read unit is low (invalid), the PSRAM write unit starts to perform a write operation, retrieves the data from the first asynchronous FIFO unit and stores it into the PSRAM chip in a parallel-to-serial conversion manner; and sets the write lock signal (wr_lock) high (valid). When the second asynchronous FIFO unit detects that the half-full signal (low level) is valid and the write lock signal (wr_lock) provided by the PSRAM write unit is low (invalid), the PSRAM read unit starts to perform a read operation, retrieves the data from the PSRAM chip and stores it into the second asynchronous FIFO unit in a serial-to-parallel conversion manner, and sets the read lock signal (rd_lock) high (valid).
[0059] The method further includes: when the half_full signal provided by the first asynchronous FIFO unit is detected to be invalid (high level), data is obtained from the external RAM through the AHB bus and stored in the first asynchronous FIFO unit for external use.
[0060] This invention also provides an integrated circuit including the PSRAM-based controller described above, which is used to replace the DesignWare Synchronous Serial Interface core to realize data interaction between the AHB bus and the PSRAM chip.
[0061] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A PSRAM-based controller for data interaction between an AHB bus and PSRAM chips, characterized in that, include: Data receiving unit, first asynchronous FIFO unit, PSRAM write unit, PSRAM read unit, second asynchronous FIFO unit; The data receiving unit is responsible for acquiring data from external RAM via the AHB bus and storing the data in the first asynchronous FIFO unit; The first asynchronous FIFO unit is used to buffer the data received by the data receiving unit; The PSRAM write unit is used to retrieve the data from the first asynchronous FIFO unit in a timely manner according to the acquired signal and store it into the PSRAM chip in a parallel-to-serial conversion manner; The PSRAM read unit is used to retrieve the data from the PSRAM chip in a timely manner according to the acquired signal and store it into the second asynchronous FIFO unit in a serial-to-parallel conversion manner. The second asynchronous FIFO unit is used to cache data read from the PSRAM particle for external use.
2. The controller according to claim 1, characterized in that, The PSRAM write unit and PSRAM read unit use the empty signal provided by the first asynchronous FIFO unit, the half-full signal provided by the second asynchronous FIFO unit, the write lock signal wr_lock provided by the PSRAM write unit, and the read lock signal rd_lock provided by the PSRAM read unit to determine whether to perform a read or write operation. When the PSRAM write unit detects that the empty signal provided by the first asynchronous FIFO unit is valid and the read lock signal rd_lock provided by the PSRAM read unit is invalid, it starts to execute the write operation and sets the write lock signal wr_lock to valid. When the PSRAM read unit detects that the half-full signal provided by the second asynchronous FIFO unit is valid and the write lock signal wr_lock provided by the PSRAM write unit is invalid, it starts to perform a read operation and sets the read lock signal rd_lock to valid.
3. The controller according to claim 2, characterized in that, Both the read lock signal rd_lock and the write lock signal wr_lock are active high, and both the empty signal and the half-full signal are active low.
4. The controller according to claim 1, characterized in that, Both the PSRAM read unit and the PSRAM write unit can use the internal fast clock to sample data. To accurately sample data using the internal fast clock, the sampling conditions of the phase and the number of waiting periods need to be adjusted. When the data is sampled in advance, the phase or the waiting period will be increased. When the data is sampled in a delayed manner, the phase or the waiting period will be decreased.
5. The controller according to claim 4, characterized in that, The waiting period generated by the internal fast clock can be configured and adjusted; by adjusting the waiting period, the requirement for accurate data sampling can be met even under the conditions of device function delay and path delay.
6. The controller according to claim 1, characterized in that, The PSRAM read unit can also use the DM signal provided by the PSRAM chip as a clock for sampling; by using the DM signal provided by the PSRAM chip, data can be accurately sampled without adjusting the sampling conditions of the phase and the number of waiting cycles.
7. The controller according to claim 1, characterized in that, Also includes: PSRAM arbitration unit; The PSRAM arbitration unit is used to replace the PSRAM write unit and PSRAM read unit to complete arbitration judgment and output corresponding response signals to the PSRAM write unit and PSRAM read unit, specifically as follows: when the empty signal provided by the first asynchronous FIFO unit is valid and the read lock signal rd_lock provided by the PSRAM read unit is invalid, a valid write request signal wr_req is output to the PSRAM write unit; when the half-full signal provided by the second asynchronous FIFO unit is valid and the write lock signal wr_lock provided by the PSRAM write unit is invalid, a valid read request signal rd_req is output to the PSRAM read unit. The PSRAM write unit is used to retrieve the data from the first asynchronous FIFO unit and store it into the PSRAM chip in a parallel-to-serial manner when a valid write request signal wr_req is detected. When a valid read request signal rd_req is detected, the PSRAM read unit retrieves the data from the PSRAM chip and stores it in the second asynchronous FIFO unit in a serial-to-parallel conversion manner.
8. A PSRAM-based control method, applied to the PSRAM-based controller according to any one of claims 1-7, characterized in that, The method includes: When the empty signal provided by the first asynchronous FIFO unit is detected to be valid and the read lock signal rd_lock provided by the PSRAM read unit is invalid, the PSRAM write unit starts to perform a write operation, retrieves the data from the first asynchronous FIFO unit and stores it into the PSRAM chip in a parallel-to-serial conversion manner; and sets the write lock signal wr_lock to valid. When the half-full signal provided by the second asynchronous FIFO unit is detected to be valid and the write lock signal wr_lock provided by the PSRAM write unit is invalid, the PSRAM read unit starts to perform a read operation. The data in the PSRAM chip is retrieved and stored in the second asynchronous FIFO unit in a serial-to-parallel manner, and the read lock signal rd_lock is set to valid.
9. The method according to claim 8, characterized in that, Also includes: When the half_full signal provided by the first asynchronous FIFO unit is detected to be invalid, data is obtained from the external RAM via the AHB bus and stored in the first asynchronous FIFO unit for external use.
10. An integrated circuit, characterized in that, Includes the PSRAM-based controller as described in any one of claims 1-7, the controller being used to replace the DesignWare Synchronous Serial Interface core to implement data interaction between the AHB bus and the PSRAM chip.