Capacity configuration method of multi-layer unit memory chip, controller mainboard, controller and vehicle

Abstract

The invention provides a capacity configuration method of a multi-layer unit memory chip, a controller and a vehicle, which are used for prolonging the service life of the memory chip. Wherein in the production process of the controller mainboard, the multi-layer unit storage chip is embedded into the controller mainboard in a standard packaging state, and establishes communication with a control chip on the controller mainboard; the capacity configuration method of the multi-layer unit storage chip comprises the steps that the multi-layer unit storage chip receives a capacity partition configuration instruction sent by a control chip; according to the capacity partition configuration instruction, NAND flash memory partition operation is executed, so that the capacity of the multi-layer unit storage chip is permanently divided into a pseudo single-layer unit partition and a multi-layer unit partition; wherein one unit in the pseudo single-layer unit partition stores information of one bit, and one unit in the multi-layer unit partition stores information of a plurality of bits.

Description

Technical Field

[0001] This application relates to the field of chip storage, specifically to a method for configuring the capacity of a multi-layer cell storage chip, a controller motherboard, a controller, and a vehicle. Background Technology

[0002] In the automotive, industrial, and consumer electronics fields, eMMC (Embedded MultiMediaCard, a package consisting of flash memory and a flash memory controller integrated on the same silicon chip) chips are often used as system drives, requiring continuous recording of logs, OTA packages, event black boxes, and other cyclically erased and rewritten data. The lifespan of an eMMC chip is determined by the number of program / erase (P / E) cycles of the NAND flash memory chips: a short lifespan will lead to premature bad blocks, causing bit errors, read-only lockouts, or even the failure of the entire eMMC chip, resulting in controller failure; a longer lifespan can cover the 10-15 year lifespan of the entire vehicle, significantly reducing the risk of after-sales maintenance and data loss. Therefore, improving the lifespan of eMMC chips is a consensus pursued within the industry. Summary of the Invention

[0003] This application provides a capacity configuration method for a multi-layer cell memory chip, a controller motherboard, a controller, and a vehicle, which are used to extend the service life of the memory chip.

[0004] The technical solution of this invention is as follows:

[0005] In a first aspect, this application provides a capacity configuration method for a multi-layer cell memory chip, the method comprising:

[0006] Receive capacity partition configuration instructions sent by the control chip;

[0007] The NAND flash memory partitioning operation is executed according to the capacity partitioning configuration instruction, so that the capacity of the multi-level cell storage chip is permanently divided into pseudo single-level cell partitions and multi-level cell partitions.

[0008] In this configuration, one cell in the pseudo-single-layer cell partition stores one bit of information, while one cell in the multi-layer cell partition stores multiple bits of information.

[0009] Since the lifespan of a multi-cell memory chip is determined by the number of program / erase (P / E) cycles of the NAND flash memory chip, repartitioning a standard packaged multi-cell memory chip into pseudo-single-cell partitions and multi-cell partitions results in a pseudo-single-cell partition where a single physical cell stores only one bit of information, increasing the number of program / erase (P / E) cycles from thousands to tens of thousands. Each time data is stored, the wear of the insulating oxide layer in a single physical cell in a pseudo-single-cell partition is significantly reduced compared to a single physical cell in a multi-cell partition, making its erase / write lifespan much longer than that of a multi-cell partition, thus extending the overall lifespan of the memory chip.

[0010] In one possible embodiment, the method further includes:

[0011] The multi-layer cell storage chip feeds back the capacity partitioning configuration results to the control chip.

[0012] The capacity partitioning configuration result indicates whether the partition formatting is complete or incomplete, informing the control chip whether the partitioning was successful and facilitating the control chip to execute the next production operation. When the partitioning configuration result for the multi-level cell storage chip is "formatting complete," the control chip can smoothly execute the next production operation; when the partitioning configuration result for the multi-level cell storage chip is "formatting incomplete," it indicates that at least one of the control chip and the multi-level cell storage chip has failed, requiring manual assessment to determine whether the control chip and the multi-level cell storage chip can continue to be used.

[0013] In some embodiments, the pseudo-single-layer cell partition is used to store one type of cyclic erase / write data and non-cyclic erase / write data in the whole vehicle, and the multi-layer cell partition is used to store the other type of cyclic erase / write data and non-cyclic erase / write data in the whole vehicle.

[0014] Based on the data storage requirements, the standard packaged multi-cell memory chip can be repartitioned to meet the storage capacity requirements of cyclically erased and non-cyclically erased data for the multi-cell memory chip.

[0015] By configuring pseudo-single-level cell partitions to handle either cyclic or non-cyclic data, optimal scheduling of the physical characteristics of multi-level cell memory chips and targeted avoidance of functional safety risks can be achieved. Specifically, frequently updated cyclic data is directed to the pseudo-single-level cell partition, directly utilizing its ultra-high durability to withstand the majority of write wear, thereby delaying the overall chip's lifespan degradation. Conversely, storing non-cyclic data in the pseudo-single-level cell partition fully utilizes its higher read reliability and data retention capabilities, ensuring the integrity of the core code and a high boot success rate.

[0016] In an exemplary embodiment, the pseudo-single-layer unit partition stores the cyclic write data of the entire vehicle, while the multi-layer unit partition stores the non-cyclic write data of the entire vehicle.

[0017] As data that needs to be written frequently, erasing cyclically written data in pseudo-single-layer partitions with longer wear life can reduce wear on the insulating oxide layer of multi-layer cell partitions, thereby further improving the overall lifespan of the memory chip.

[0018] In an exemplary embodiment, the multi-layer unit partitioning is a two-layer unit partitioning or a three-layer unit partitioning.

[0019] Whether the multi-level cell partitioning is two-level or three-level depends on the type of multi-level cell storage chip selected: a two-level cell storage chip (Multi-Level Cell Embedded MultiMediaCard, MLC EMMC chip) or a three-level cell storage chip (Triple-Level Cell Embedded MultiMediaCard, TLC EMMC chip). Regardless of the type of storage chip chosen, the lifespan of the multi-level cell storage chip on the controller can be extended, facilitating flexible selection of multi-level cell storage chips in the early stages.

[0020] In an exemplary embodiment, the storage capacity of the pseudo-single-layer cell partition is a set multiple of the maximum capacity of its stored data, and the set multiple is related to the selection of the multi-layer cell storage chip.

[0021] By associating the set multiplier with the selection of the multi-layer cell memory chip, it can be ensured that the multi-layer cell configured as a pseudo-single-layer cell has sufficient storage capacity to fully store the data that needs to be stored.

[0022] When a multi-level cell (MLC) memory chip has two cell layers, the storage capacity of a pseudo-single-level cell partition is greater than twice its maximum data storage capacity. When a MLC memory chip has three cell layers, the storage capacity of a pseudo-single-level cell partition is greater than three times its maximum data storage capacity.

[0023] In an exemplary embodiment, the multi-layer cell memory chip establishes communication with the control chip through its built-in standard hardware interface.

[0024] By utilizing the existing standard hardware interface of multi-cell memory chips, it is easy to perform secondary configuration of standard packaged multi-cell memory chips, thereby reducing hardware R&D costs.

[0025] Secondly, this application also provides a controller motherboard, on which a multi-level cell storage chip and a control chip are embedded, and the multi-level cell storage chip and the control chip are electrically connected; wherein, the capacity of the multi-level cell storage chip is permanently divided into pseudo-single-level cell partitions and multi-level cell partitions under the capacity partition configuration instruction sent by the control chip; the pseudo-single-level cell partition is configured to store one bit of information in each storage cell, and the multi-level cell partition is configured to store multiple bits of information in each storage cell.

[0026] Preferably, the pseudo-single-layer cell partition is used to store one type of cyclic erase / write data and non-cyclic erase / write data in the whole vehicle, and the multi-layer cell partition is used to store the other type of cyclic erase / write data and non-cyclic erase / write data in the whole vehicle.

[0027] Thirdly, this application provides a controller, which includes a controller motherboard, on which a multi-level cell storage chip and a control chip are embedded, and the multi-level cell storage chip and the control chip are electrically connected; wherein, the capacity of the multi-level cell storage chip is permanently divided into pseudo-single-level cell partitions and multi-level cell partitions under the capacity partition configuration instruction sent by the control chip; the pseudo-single-level cell partition is configured to store one bit of information in each storage cell, and the multi-level cell partition is configured to store multiple bits of information in each storage cell.

[0028] Preferably, the pseudo-single-layer cell partition is used to store one type of cyclic erase / write data and non-cyclic erase / write data in the whole vehicle, and the multi-layer cell partition is used to store the other type of cyclic erase / write data and non-cyclic erase / write data in the whole vehicle.

[0029] Fourthly, this application also provides a vehicle on which the aforementioned controller is installed.

[0030] The beneficial effects of this application are as follows:

[0031] By embedding the standard packaged EMMC chip into the controller motherboard during the manufacturing process and establishing communication with the control chip on the controller motherboard, the control chip performs secondary partitioning configuration on the EMMC chip, dividing the EMMC chip into pseudo-single-layer cell partitions and multi-layer cell partitions. The wear of the insulating oxide layer in a single physical cell within the pseudo-single-layer cell partition is greatly reduced, thereby extending the service life of the EMMC chip. Attached Figure Description

[0032] Figure 1 This is a structural block diagram of the vehicle in Embodiment 1 of this application;

[0033] Figure 2This is a structural block diagram of the first controller in Embodiment 2 of this application;

[0034] Figure 3 This is a flowchart illustrating the capacity configuration method of a multi-layer cell memory chip in Embodiment 3 of this application;

[0035] Figure 4 This is a flowchart illustrating the capacity configuration method for the MLC EMMC chip in Embodiment 4 of this application;

[0036] Figure 5 This is a flowchart illustrating the capacity configuration method for the TLC EMMC chip in Embodiment 5 of this application;

[0037] Explanation of reference numerals in the attached diagram: 100-Vehicle; 1-First controller; 11-Controller motherboard; 12-Control chip; 13-EMMC chip; 2-Second controller. Detailed Implementation

[0038] Please see Figure 1 , Figure 1 This is a schematic diagram of the vehicle structure disclosed in Embodiment 1 of this application. The vehicle can be, but is not limited to, a pure electric vehicle (PEV / BEV), a hybrid electric vehicle (HEV), a range-extended electric vehicle (REEV), a plug-in hybrid electric vehicle (PHEV), a new energy vehicle, or a fuel vehicle.

[0039] Reference Figure 1 In this embodiment of the application, the vehicle 100 includes multiple controllers, including a first controller 1, a second controller 2, and so on. The controllers are connected and communicate with each other through relevant wiring harnesses. The first controller 1 and the second controller 2 are, for example, a vehicle controller, a body controller, etc.

[0040] These controllers all contain a controller motherboard, on which control chips and multi-level cell memory chips are installed. These two are connected through the standard hardware interface of the multi-level cell memory chip and communicate directly through the JEDEC EMMC protocol.

[0041] In the embodiments of this application, the controller can be various controllers used in the vehicle, such as vehicle controller, gateway controller, cockpit domain controller, battery management system controller, and other related controllers.

[0042] Taking multi-level cell memory chips (EMMC chips) as an example, for controller manufacturers, the products purchased from EMC chip manufacturers are standardly packaged using the manufacturers' regular production processes. This eliminates the need for manufacturers to adjust the EMC chip products to meet the needs of OEMs, significantly reducing the purchase cost of EMC chips. However, the actual usable storage capacity of these directly purchased EMC chips is usually fixed, and their lifespan cannot be extended. For example, the usable storage capacity of a TLC EMC chip is in TLC mode; and for an MLC EMC chip, it is in MLC mode. The write / erase cycle life of both types of EMC chips is only a few thousand cycles, which cannot meet the long lifespan requirements of OEMs.

[0043] For the reasons mentioned above, in order to extend the lifespan of the EMMC chip without increasing its purchase cost, a controller is provided in Embodiment 2 of this application; please refer to... Figure 2 Taking the aforementioned first controller 1 as an example, the first controller 1 includes a controller motherboard 11.

[0044] In the second embodiment of this application, the controller motherboard 11 is equipped with a control chip 12 and an EMMC chip 13. The EMMC chip 13 is embedded in the controller motherboard 11 during its production process and is configured by the control chip 12 into a pseudo-single-layer unit partition 131 and a multi-layer unit partition 132. After the controller is produced, the EMMC chip 13, which is configured by secondary partitioning, can store each data to be stored into the corresponding partition according to the target storage area information carried in the storage data sent by the control chip 12.

[0045] In this partition, one cell in the pseudo-single-layer cell partition 131 stores one bit of information, and one cell in the multi-layer cell partition 132 stores multiple bits of information. Specifically, the multi-layer cell partition 132 can store 2 bits, 3 bits, or 4 bits of information.

[0046] Since the lifespan of the EMMC chip 13 is determined by the number of programming / erasing (P / E) cycles of the NAND flash memory cells, after repartitioning the standard-packaged EMMC chip 13 into a pseudo single-level cell partition 131 and a multi-level cell partition 132, one physical cell in the obtained pseudo single-level cell partition 131 stores only one bit of information, resulting in an increase in its programming / erasing (P / E) cycles from thousands to tens of thousands; each time data is stored, compared to a single physical cell in the multi-level cell partition 132, the wear of the insulating oxide layer in a single physical cell in the pseudo single-level cell partition 131 is much reduced, making its write / erase lifespan much higher than that of the multi-level cell partition 132, thereby extending the overall lifespan of the EMMC chip 13.

[0047] It should be noted that the storage capacity of the standard-packaged EMMC chip 13 embedded on the controller mainboard 11 should meet the data capacity requirements of the controller. That is, in the early stage, it is necessary to determine the storage amount of various types of data according to the data sources to be stored in the specific controller, and generally, it needs to satisfy the maximum capacity of cyclic write / erase data * N + the maximum capacity of non-cyclic write / erase data < the actual user available capacity of the EMMC chip 13, where N is determined according to the type of the selected EMMC chip 13.

[0048] Generally speaking, the data to be stored in the controller is classified into two categories: cyclic write / erase data and non-cyclic write / erase data. Cyclic write / erase data (i.e., data that needs to be periodically and repeatedly written, read, erased, and rewritten) is generally collected by external sensors and transmitted to the control chip. The control chip 13 processes the cyclic write / erase data and sends it to the EMMC chip 13 for storage, and overwrites the data cyclically according to preset conditions; non-cyclic write / erase data (i.e., data other than cyclic write / erase data) is generally data pre-stored in the EMMC chip 13 through the control chip 13 or data generated according to specific conditions. The number of data sources of cyclic write / erase data and non-cyclic write / erase data depends on the application of the electronic product to which they belong, and the number of data sources can be many or few.

[0049] In the second embodiment of this application, the cyclic write / erase data is, for example, log data, CAN data, etc., and the non-cyclic write / erase data is, for example, the fault log of the controller, OTA data packets, data stored by end users, etc.

[0050] When specifically selecting the EMMC chip 13, the actual user available storage capacity of the EMMC chip 13 will be compared with the maximum capacity of the above cyclic write / erase data * N + the maximum capacity of non-cyclic write / erase data to select a suitable type of EMMC chip.

[0051] In Embodiment 2 of this application, the standard packaged EMMC chip type is, for example, one of MLC EMMC chip, TLC EMMC chip and QLC EMMC chip.

[0052] Reference Figure 3 Embodiment 3 of this application provides a method for configuring the capacity of a multi-layer cell memory chip, including:

[0053] S101 receives the capacity partition configuration command sent by the control chip;

[0054] S102, execute NAND flash memory partitioning operation according to the capacity partitioning configuration instruction, so that the capacity of the multi-layer cell storage chip is permanently divided into pseudo single-layer cell partition and multi-layer cell partition;

[0055] In this configuration, one cell in the pseudo-single-layer cell partition stores one bit of information, while one cell in the multi-layer cell partition stores multiple bits of information.

[0056] The method in this embodiment three involves embedding a standard packaged multi-cell memory chip into the controller motherboard during the manufacturing process and establishing communication with the control chip on the controller motherboard. The control chip performs secondary partitioning configuration on the multi-cell memory chip, dividing it into pseudo-single-cell partitions and multi-cell partitions. The wear of the insulating oxide layer within a single physical cell in the pseudo-single-cell partition is greatly reduced, thereby extending the service life of the multi-cell memory chip.

[0057] Reference Figure 3 In Embodiment 3 of this application, the method further includes:

[0058] S103 feeds back the capacity partitioning configuration results to the control chip.

[0059] The capacity partition configuration result indicates whether the partition formatting is complete or incomplete, informing the control chip whether the partitioning was successful and facilitating the control chip to execute the next production operation.

[0060] Reference Figure 4 In Embodiment 4 of this application, taking the multi-layer cell memory chip as an example, a method for configuring the capacity of an MLC EMMC chip is provided, including:

[0061] S201, the MLC EMMC chip receives capacity partition configuration instructions sent by the control chip;

[0062] S202, executes NAND flash memory partitioning operation according to capacity partitioning configuration instruction, so that the capacity of MLC EMMC chip is permanently divided into PSLC partition and MLC partition;

[0063] In the PSLC partition, one cell stores one bit of information, while in the MLC partition, one cell stores two bits of information.

[0064] In Embodiment 4 of this application, the capacity partition configuration command sent by the control chip is generated based on the configuration requirements using the interface built into the JEDEC eMMC protocol and the partition command set provided by the MLC eMMC supplier. The configuration requirements refer to the pre-determined storage capacity of each partition in the PSLC and MLC partitions, based on the required data storage volume. For example, for the MLC eMMC chip, the required storage capacity for the PSLC partition is determined to be 12GB, and the required storage capacity for the MLC partition is determined to be 2GB. The control chip first obtains the physical capacity, factory partition table, and configurable segment range of the current MLC eMMC chip through the JEDEC eMMC standard interface; then, according to the vehicle manufacturer's configuration requirement table (defining the capacity of boot, log, user areas, etc.), it calls the protocol's inherent SWITCH command (CMD6) format, filling the corresponding bytes (BOOT_SIZE_MULT, GP_SIZE_MULT_x, ENH_START_ADDR, ENH_SIZE_MULT, etc.) with the target values ​​to form a complete capacity partition configuration command.

[0065] In step S202, for the MLC EMMC chip, the MLC EMMC chip responds to a single partition configuration command, automatically completes the partitioning operation of its user data area, and divides it into PSLC partition and MLC partition.

[0066] Since the lifespan of an MLC EMMC chip is determined by the number of program / erase (P / E) cycles of the MLC chip, after repartitioning a standard packaged MLC EMMC chip into PSLC partitions and MLC partitions, each physical unit in the resulting PSLC partition stores only one bit of information. The wear on the insulating oxide layer caused by each write to the PSLC partition is much less than that of the MLC partition. Therefore, before the insulating oxide layer is completely damaged, it can withstand a much larger total number of writes (i.e., P / E cycles) than the MLC partition, thus achieving a longer lifespan.

[0067] Reference Figure 4 In Embodiment 4 of this application, the method further includes:

[0068] S203, the MLC EMMC chip feeds back the capacity partitioning configuration results to the control chip.

[0069] The capacity partition configuration result indicates whether the partition formatting is complete or incomplete, informing the control chip whether the partitioning was successful and facilitating the next production operation. Once the capacity partition is successfully programmed, the MLC EMMC chip immediately returns a formatting completion flag. If the control chip determines the formatting completion flag is valid, it continues subsequent production processes. If the formatting completion flag is missing or verification fails, it automatically rolls back and re-executes the partition programming, retrying a maximum of N times (e.g., N=3). Only when a valid flag cannot be obtained after N consecutive attempts is the partition deemed invalid, the production line is stopped, and a fault is reported. A manual decision is then made regarding whether to replace the controller motherboard or the MLC EMMC chip.

[0070] In Embodiment 4 of this application, the PSLC partition is used to store one of the cyclic write data and non-cyclic write data in the whole vehicle, and the MLC partition is used to store the other of the cyclic write data and non-cyclic write data in the whole vehicle.

[0071] By configuring the PSLC partition to handle either cyclic or non-cyclic data, optimal scheduling of the physical characteristics of the MLC / EMMC chip and targeted avoidance of functional safety risks can be achieved. Specifically, the frequently updated cyclic data is directed to the PSLC partition, directly utilizing its ultra-high durability to withstand the majority of write wear, thereby delaying the lifespan degradation of the entire MLC / EMMC chip. Conversely, storing non-cyclic data in the PSLC partition fully utilizes its higher read reliability and data retention capabilities, ensuring the integrity of the core code and a high boot success rate.

[0072] For example, the PSLC partition stores the cyclic write data of the entire vehicle, and the MLC partition stores the non-cyclic write data of the entire vehicle.

[0073] As data that needs to be written frequently, erasing cyclically written data in the PSLC partition with a longer wear life can reduce wear on the insulating oxide layer of the MLC partition, thereby further improving the overall lifespan of the memory chip.

[0074] Since a physical unit in an MLC partition stores 2 bits of information, configuring a portion of the storage capacity of an MLC EMMC chip as a PSLC partition will result in the capacity of some MLC storage particles being halved. Therefore, for an MLC EMMC chip, the storage capacity of a PSLC partition is twice the maximum capacity of its stored data.

[0075] By configuring a portion of the storage capacity of the MLC EMMC chip as a PSLC partition with a capacity more than twice that of the cyclic write data storage capacity, although the capacity of the MLC storage chips in this PSLC partition is halved, its erase lifespan increases from 3,000 times to 30,000 times, the number of erase / write cycles increases to 10 times, the capacity decreases by 0.5 times, but the overall lifespan increases to 5 times; non-cyclic write data uses the MLC storage capacity, the capacity is not reduced, and the number of erase / write cycles is not increased.

[0076] Based on the above, let's take the solution in Example 4 as an example. Suppose that for the vehicle controller, the maximum capacity of the cyclic write data that needs to be stored in the MLC EMMC chip is 6GB, and the maximum capacity of the non-cyclic write data is 2GB, that is, the total actual capacity requirement is 8GB; then a 16GB capacity MLC EMMC chip needs to be selected (its actual user-available storage capacity is about 14.5GB).

[0077] The total data storage capacity of the MLC EMMC chip in existing applications during its lifespan = 14.5 × 3000 ÷ Write Amplification (WAF); The total data storage capacity of the MLC EMMC chip obtained by the method in Embodiment 4 of this application during its lifespan = {(14.5-2) / 2 × 30000 + 2 × 3000} ÷ Write Amplification (WAF); The lifespan extension factor of the MLC EMMC chip = {(14.5-2) / 2 × 30000 + 2 × 3000} ÷ Write Amplification (WAF) / 14.5 × 3000 ÷ Write Amplification (WAF) = 4.45.

[0078] That is, by using the method in Embodiment 4 of this application, the lifespan of the MLC EMMC chip can be extended to 4.45 times the original lifespan while meeting the storage capacity requirements.

[0079] Reference Figure 5 In Embodiment 5 of this application, taking the multi-layer cell memory chip as a TLC EMMC chip as an example, a method for configuring the capacity of a TLC EMMC chip is provided, including:

[0080] S301, the TLC EMMC chip receives capacity partitioning configuration instructions sent by the control chip;

[0081] S302 executes NAND flash memory partitioning operations according to the capacity partitioning configuration instructions, so that the capacity of the TLC EMMC chip is permanently divided into PSLC partition and TLC partition;

[0082] In a PSLC partition, one cell stores one bit of information, while in a TLC partition, one cell stores three bits of information.

[0083] Similar to Example 4, since a cell in a PSLC partition stores only one bit of information, while a cell in a TLC partition stores three bits of information, the wear on the insulating oxide layer caused by each write to a PSLC partition is less than that of a TLC partition. Therefore, before the insulating oxide layer is completely damaged, it can withstand a much larger total number of writes (i.e., P / E cycles) than a TLC partition, thus achieving a longer lifespan.

[0084] Similar to Embodiment 4, in Embodiment 5 of this application, reference is made to... Figure 5 The method also includes:

[0085] The S303 TLC EMMC chip feeds back the capacity partitioning configuration results to the control chip.

[0086] The capacity partitioning configuration result indicates whether the partition formatting is complete or incomplete, informing the control chip whether the partitioning was successful and facilitating the control chip's execution of the next production operation. When the partitioning configuration result for the TLC EMMC chip is "formatting complete," the control chip can smoothly execute the next production operation. If the partitioning configuration result for the TLC EMMC chip is "formatting incomplete," it indicates that at least one of the control chip and the TLC EMMC chip has malfunctioned, requiring manual assessment to determine whether the control chip and the TLC EMMC chip can continue to be used.

[0087] In Embodiment 5 of this application, the PSLC partition is used to store one of the cyclic write data and non-cyclic write data in the whole vehicle, and the TLC partition is used to store the other of the cyclic write data and non-cyclic write data in the whole vehicle.

[0088] By configuring the PSLC partition to handle either cyclic or non-cyclic data, optimal scheduling of the TLCEMMC chip's physical characteristics and targeted avoidance of functional safety risks can be achieved. Specifically, frequently updated cyclic data is routed to the PSLC partition, directly utilizing its ultra-high durability to withstand the majority of write wear, thereby delaying the overall chip's lifespan degradation. Conversely, storing non-cyclic data in the PSLC partition fully leverages its higher read reliability and data retention capabilities, ensuring the integrity of the core code and a high boot success rate.

[0089] For example, the PSLC partition stores the cyclic write data of the entire vehicle, and the TLC partition stores the non-cyclic write data of the entire vehicle.

[0090] As data that needs to be written frequently, erasing cyclically written data in the PSLC partition, which has a longer wear life, can reduce wear on the insulating oxide layer of the TLC partition, thereby further improving the overall lifespan of the memory chip.

[0091] Since a physical unit in a TLC partition stores 3 bits of information, configuring a portion of the storage capacity of a TLC EMMC chip as a PSLC partition will reduce the capacity of some TLC storage particles by 2 / 3. Therefore, for a TLC EMMC chip, the storage capacity of a PSLC partition is 3 times its maximum storage capacity.

[0092] By configuring a portion of the TLC EMMC chip's storage capacity as a PSLC partition with a capacity three times greater than the cyclic write data storage capacity, although the TLC storage chip capacity in this PSLC partition is halved, its erase lifespan increases from 3,000 cycles to 30,000 cycles, the number of erase / write cycles increases tenfold, the capacity decreases by two-thirds, but the overall lifespan increases by 3.33 times; non-cyclic write data uses the TLC storage capacity, with no reduction in capacity and no increase in the number of erase / write cycles.

[0093] Based on the above, let's take the solution in Example 5 as an example. Suppose that for the vehicle controller, the maximum capacity of the cyclic write data to be stored by the TLC EMMC chip is 6GB, and the maximum capacity of the non-cyclic write data is 9GB, that is, the total actual capacity requirement is 15GB; then a TLC EMMC chip with a capacity of 32GB needs to be selected (its actual user-available storage capacity is about 29GB).

[0094] The total data storage capacity of a TLC EMMC chip in existing applications during its lifecycle is 29 × 3000 ÷ Write Amplification (WAF); the total data storage capacity of a TLC EMMC chip obtained by the method in Embodiment 5 of this application during its lifecycle is {(29-9) / 3 × 30000 + 9 × 3000} ÷ Write Amplification (WAF); the lifecycle extension factor of the TLC EMMC chip is {(29-9) / 3 × 30000 + 9 × 3000} ÷ Write Amplification (WAF) / 29 × 3000 ÷ Write Amplification (WAF) = 2.61.

[0095] That is, by using the method in Embodiment 5 of this application, the lifespan of the TLC EMMC chip can be extended to 2.61 times the original lifespan while meeting the storage capacity requirements.

[0096] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims. Those skilled in the art can understand that implementing all or part of the processes of the above embodiments and making equivalent changes according to the claims of this application still fall within the scope of this application.

Claims

1. A method for configuring the capacity of a multi-layer cell memory chip, characterized in that, The method includes: Receive capacity partition configuration instructions sent by the control chip; The NAND flash memory partitioning operation is executed according to the capacity partitioning configuration instruction, so that the capacity of the multi-level cell storage chip is permanently divided into pseudo single-level cell partitions and multi-level cell partitions. In this configuration, one cell in the pseudo-single-layer cell partition stores one bit of information, while one cell in the multi-layer cell partition stores multiple bits of information.

2. The capacity configuration method for a multi-layer cell memory chip according to claim 1, characterized in that, The method further includes: The capacity partition configuration results are fed back to the control chip.

3. The capacity configuration method for a multi-layer cell memory chip according to claim 1, characterized in that, The pseudo-single-layer cell partition is used to store one type of cyclic write data and non-cyclic write data in the whole vehicle, and the multi-layer cell partition is used to store the other type of cyclic write data and non-cyclic write data in the whole vehicle.

4. The capacity configuration method for a multi-layer cell memory chip according to claim 3, characterized in that, The pseudo-single-layer unit partition stores the cyclic write data of the entire vehicle, while the multi-layer unit partition stores the non-cyclic write data of the entire vehicle.

5. The capacity configuration method for a multi-layer cell memory chip according to claim 1, characterized in that, The storage capacity of the pseudo-single-layer cell partition is a set multiple of the maximum capacity of its stored data, and the set multiple is related to the selection of the multi-layer cell storage chip.

6. A controller motherboard, characterized in that, The controller motherboard has a multi-level cell storage chip and a control chip embedded on it, and the multi-level cell storage chip and the control chip are electrically connected. The capacity of the multi-level cell storage chip is permanently divided into pseudo-single-level cell partitions and multi-level cell partitions under the capacity partition configuration command sent by the control chip. The pseudo-single-level cell partition is configured to store one bit of information in each storage cell, and the multi-level cell partition is configured to store multiple bits of information in each storage cell.

7. The controller motherboard according to claim 6, characterized in that, The pseudo-single-layer cell partition is used to store one type of cyclic write data and non-cyclic write data in the whole vehicle, and the multi-layer cell partition is used to store the other type of cyclic write data and non-cyclic write data in the whole vehicle.

8. A controller, characterized in that, The controller includes a controller motherboard, on which a multi-level cell storage chip and a control chip are embedded, and the multi-level cell storage chip and the control chip are electrically connected; wherein, the capacity of the multi-level cell storage chip is permanently divided into pseudo-single-level cell partitions and multi-level cell partitions under the capacity partition configuration command sent by the control chip; the pseudo-single-level cell partition is configured to store one bit of information in each storage cell, and the multi-level cell partition is configured to store multiple bits of information in each storage cell.

9. The controller according to claim 8, characterized in that, The pseudo-single-layer cell partition is used to store one type of cyclic write data and non-cyclic write data in the whole vehicle, and the multi-layer cell partition is used to store the other type of cyclic write data and non-cyclic write data in the whole vehicle.

10. A vehicle, characterized in that, The vehicle is equipped with the controller as described in claim 8 or 9.

Images