Instruction data packet generation method and device and electronic equipment

Abstract

The invention provides an instruction data packet generation method and apparatus, and an electronic device. The method comprises the steps of obtaining a processing instruction; determining a source operand for processing the instruction according to a pre-configured instruction configuration file; determining a definition of a source operand and a register corresponding to the source operand according to a pre-configured source operand configuration file; determining the definition of the register according to a pre-configured register configuration file; and according to the definition of the source operand and the definition of the register, binding the processing instruction, the source operand and the register, and generating a data packet for calling the processing instruction. According to the instruction data packet generation method provided by the invention, during modification each time, instruction modification can be realized through the configured instruction configuration file, the configured source operand configuration file and the configured register configuration file, so that instruction configuration modification is completed without changing scripts, the period of instruction configuration modification each time is shortened, and the modification efficiency is improved. And development cycle lag is avoided.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, and electronic device for generating instruction data packets. Background Technology

[0002] Currently, the ISG (Instruction Set Group) for VLIW (Very Long Instruction Word) instructions is mainly defined separately using formats such as JSON and XML. That is, in the code implementation, each instruction is defined separately.

[0003] In custom-designed dedicated chips, the instruction set is often not defined at the beginning and needs to be modified as the project develops.

[0004] For VLIW instructions, the format of the instruction word is defined, including multiple operation slots, each corresponding to a functional unit (such as an integer unit, a floating-point unit, a load / store unit, etc.). This makes each modification cycle long and delays the development cycle. Summary of the Invention

[0005] To address one of the aforementioned technical deficiencies, this application provides a method, apparatus, and electronic device for generating instruction data packets.

[0006] The first aspect of this application provides a method for generating instruction data packets, the method comprising: Get a processing instruction; The source operands of the processing instructions are determined based on the pre-configured instruction configuration file. Based on the pre-configured source operand configuration file, determine the definition of the source operand and the register corresponding to the source operand; The register definitions are determined based on the pre-configured register configuration file; Based on the definitions of the source operand and the register, the processing instruction, source operand, and register are bound together to generate a data packet that calls the processing instruction; The registers are located within the vector processor, which also includes: a vector program control unit, multiple functional units, a private vector register for the vector interleaving unit, and a private vector register for the vector access unit. The registers include: register file stack and scalar registers; The vector program control unit is used for instruction fetching and instruction issuing; the vector program control unit interacts with the scalar register. Functional units are used to perform functional processing according to instructions; The register file is used to receive read / write requests and return data; rearrange data and return it; interact with functional units for read / write operations; and configure the configuration registers of the vector program control unit using data in the register file. Among them, the private vector register of the vector interleaving unit corresponds one-to-one with the vector interleaving unit; The private vector register of a vector access unit is shared by multiple vector access units.

[0007] Optionally, the instruction configuration file includes information about the instructions for each functional unit; The information for any instruction includes: the name of any instruction, the template of any instruction, the fields of any instruction, and the general constraints of any instruction template.

[0008] Optionally, the source operand configuration file includes information about the source operands; The information for any source operand includes: the register name corresponding to the source operand, the offset address of the source operand, the number of bits of the source operand, the type of the source operand, the registers involved in the source operand, the associated fields of the source operand, and the general constraints of the source operand.

[0009] Optionally, the register configuration file includes information about all shared registers; The information for any register includes: the name of any register, the format for writing to any register, the number of registers in the group to which any register belongs, and the general constraints of any register.

[0010] Optionally, the information of any instruction may also include: the constraints of any instruction; The constraints include one or more of the following: the name of the destination register not supported by any instruction; the name of the module not used by any instruction; the constraints added when any instruction is used by a module; the constraints on the parameters of any instruction; random order constraints; the constraints passed by any instruction to the destination register; the number of consecutive lock cycles of the destination register; slot occupancy constraints; the constraint to add an instruction before any instruction; the constraint to add an instruction after any instruction; the constraint to prohibit adding an instruction before any instruction; the constraint to prohibit adding an instruction after any instruction; the write operation time constraint of any instruction; and the binding constraint of any instruction.

[0011] Optionally, the variables in the data packet satisfy the constraint relationship; The constraint relationships are determined through the following steps: Form a first sequence from all variables in the data packet; A second sequence is formed based on random order constraints; The random order of all variables is obtained based on the first and second sequences, and the random order is determined as a constraint relationship.

[0012] Optionally, after binding the processing instruction, source operand, and register according to the definitions of the source operand and register, and generating the data packet for invoking the processing instruction, the process further includes: The simulator is used to perform register access statistics on data packets; Determine if there are any problems with the data packets based on the statistical access data.

[0013] Optionally, processing instructions are obtained, including: Obtain processing instructions based on the input command.

[0014] A second aspect of this application provides an instruction data packet generation apparatus, the apparatus comprising: The acquisition module is used to acquire processing instructions; The first determining module is used to determine the source operands of the processing instruction based on the pre-configured instruction configuration file. The second determining module is used to determine the definition of the source operand and the register corresponding to the source operand based on the pre-configured source operand configuration file. The third determining module is used to determine the definition of the registers based on the pre-configured register configuration file; The generation module is used to bind the processing instruction, source operand, and register according to the definitions of the source operand and register, and generate a data packet that calls the processing instruction; The registers are located within the vector processor, which also includes: a vector program control unit, multiple functional units, a private vector register for the vector interleaving unit, and a private vector register for the vector access unit. The registers include: register file stack and scalar registers; The vector program control unit is used for instruction fetching and instruction issuing; the vector program control unit interacts with the scalar register. Functional units are used to perform functional processing according to instructions; The register file is used to receive read / write requests and return data; rearrange data and return it; interact with functional units for read / write operations; and configure the configuration registers of the vector program control unit using data in the register file. Among them, the private vector register of the vector interleaving unit corresponds one-to-one with the vector interleaving unit; The private vector register of a vector access unit is shared by multiple vector access units.

[0015] A third aspect of this application provides an electronic device, comprising: Memory; High-performance processors; and Computer programs; Among them, high-performance processors include: vector processors; The vector processor includes: a vector program control unit, multiple functional units, a private vector register for the vector interleaving unit, a private vector register for the vector access unit, and registers; The registers include: register file stack and scalar registers; The computer program is stored in memory and configured to be executed by a high-performance processor to implement the method described in the first aspect above.

[0016] This application provides a method, apparatus, and electronic device for generating instruction data packets. The method obtains a processing instruction; determines the source operands of the processing instruction according to a pre-configured instruction configuration file; determines the definition of the source operands and the corresponding registers according to a pre-configured source operand configuration file; determines the definition of the registers according to a pre-configured register configuration file; and binds the processing instruction, source operands, and registers according to the definitions of the source operands and registers to generate a data packet invoking the processing instruction. This method allows for instruction modification each time a change is made, using the configured instruction configuration file, source operand configuration file, and register configuration file. This eliminates the need to modify the script to change the instruction configuration, shortening the cycle of each instruction configuration modification and avoiding development cycle delays. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A flowchart illustrating a method for generating instruction data packets provided in an embodiment of this application; Figure 2 A schematic diagram of the architecture of a vector processor provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a vector operation unit provided in an embodiment of this application; Figure 4 A schematic diagram of another vector processor architecture provided in an embodiment of this application; Figure 5 A schematic diagram of the structure of an instruction data packet generation apparatus provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a high-performance processor provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a scalar processor provided in an embodiment of this application; Figure 8This is a schematic diagram of the structure of a synchronization unit for a scalar processor provided in an embodiment of this application. Detailed Implementation

[0018] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0019] In developing this application, the inventors discovered that current ISGs (Instruction Set Groups) for VLIW (Very Long Instruction Word) instructions are primarily defined separately using formats such as JSON and XML. This means that each instruction is defined individually in the code implementation. In custom-designed chips, the instruction set is often not defined at the outset and requires modification as the project develops. For VLIW instructions, defining the instruction word format includes multiple operation slots, each corresponding to a functional unit (such as an integer unit, floating-point unit, load / store unit, etc.). This results in long modification cycles and delays in the development cycle.

[0020] To address the aforementioned issues, this application provides a method, apparatus, and electronic device for generating instruction data packets. The method involves: acquiring a processing instruction; determining the source operands of the processing instruction based on a pre-configured instruction configuration file; determining the definitions of the source operands and their corresponding registers based on a pre-configured source operand configuration file; determining the definitions of the registers based on a pre-configured register configuration file; and binding the processing instruction, source operands, and registers based on the definitions of the source operands and registers to generate a data packet invoking the processing instruction. This method allows for instruction modification each time a change is made, using the configured instruction configuration file, source operand configuration file, and register configuration file. This eliminates the need to modify the script to change the instruction configuration, shortening the cycle of each instruction configuration modification and avoiding development cycle delays.

[0021] This embodiment provides a method for generating instruction data packets. Since VLIW instructions have many functional units, and each functional unit may correspond to different fields, relevant personnel will configure multiple configuration files before executing this method. The instruction data packet generation method provided in this embodiment can generate instructions based on configuration files, without defining them separately through code. This avoids the problem in the prior art where each instruction is defined separately in the code implementation, resulting in a long modification cycle and delaying the development cycle.

[0022] For example, the configuration file includes the following three: 1. Register configuration file The register configuration file includes information on all common registers (Reg) (such as registers of all functional units) to provide general constraints on the registers.

[0023] Information for any register includes: the name of any register (Reg_name), the write format of any register (Write_temp), the number of registers in the group to which any register belongs (Reg_map), and the general constraints of any register (Const).

[0024] in, Register name (Reg_name): Used to define the register; each register has a unique name.

[0025] Register write format (Write_temp): Used to define the write type of registers, such as T5, or latch0, etc.

[0026] The number of registers in the register group (Reg_map): The format is ab, where a represents the number of registers in the register group and b represents the number of modules.

[0027] Table 1 shows a feasible example of a register configuration file.

[0028] Table 1

[0029] In addition, the information in any register may also include Link_conflict, Link_out_conflict, Link_model, etc.

[0030] in, Link_conflict indicates which columns of the conflict register will be used when the register is actually used.

[0031] Link_out_conflict indicates which columns in out_conflict this register will occupy during actual use, with none indicating that it will not occupy an exit point.

[0032] Link_model indicates which register this register belongs to.

[0033] Register configuration files are used for decentralized processing. They are mainly used because the relationship between registers between instructions can occur in the ISG (Instruction Set Group), so registers are treated as variables.

[0034] 2. Command configuration file The instruction configuration file includes information about the instructions for each functional unit. For example, each functional unit includes an instruction instance (ins) and a src field. The instruction instance (ins) defines the instructions and contains a template for all instructions. The src field points to the specific source code file that implements the functional unit. The instruction configuration file can be configured based on the instruction instance (ins), such as which fields it consists of and the constraints between the fields.

[0035] Information for any instruction includes: the name of any instruction (Inst_name), the template of any instruction (Temp), the fields of any instruction (Field), and the general constraints of any instruction template (Const).

[0036] Table 2 shows a feasible example of an instruction configuration file.

[0037] Table 2

[0038] In addition, the information of any instruction may also include: the constraints of any instruction.

[0039] The constraints include one or more of the following: the name of the destination register not supported by any instruction (Notsupport dst), the name of the module not used by any instruction (Not support model), the constraint added when any instruction is used by a module (Add const), the constraint on the parameters of any instruction (Base const), the random order constraint (Liner_para), the constraint passed to the destination register by any instruction (Add dst const), the number of consecutive lock cycles of the destination register (Lock dst), the slot occupancy constraint (Reg_delay lock), the instruction addition constraint before any instruction (Front), the instruction addition constraint after any instruction (End), the instruction addition restriction constraint before any instruction (Notfront), the instruction addition restriction constraint after any instruction (Not end), the write operation time constraint of any instruction, and the binding constraint of any instruction.

[0040] in, Names of destination registers not supported by the instruction (Not support dst): This indicates which destination registers (dst) are not supported by this instruction.

[0041] The name of the module in which the instruction is not used (Not support model): indicates which module the instruction cannot be used in.

[0042] Constraints added when instructions are used by modules (Add const): This means that a certain constraint is added when a module is used. This constraint can only be applied to instructions and is applicable to different functional units of the same module.

[0043] Instruction parameter constraints (Base const): This mainly constrains the internal parameters of the instruction, which is combined with the random order constraint (Liner_para).

[0044] Random order constraint (Liner_para): Used to specify the random order of parameters.

[0045] For example, when parameter c1 is 1, parameter c2 cannot be 0. The instruction code is if (c1==1) c2!=0, then the random order constraint (Liner_para) specifies that c1 is random before c2.

[0046] The constraint passed from the instruction to the destination register (Add dst const): This defines some related constraints passed from the instruction to certain destination registers (dst).

[0047] Number of consecutive lock cycles for the destination register (Lock dst): This is used to lock the destination register (dst) for a specific number of cycles and is suitable for multi-cycle functions.

[0048] If an instruction needs to write to the same target domain in multiple consecutive cycles, the instruction needs to be constrained by the number of consecutive lock cycles (Lock dst) of the destination register to prevent other instructions from writing to the corresponding register in those cycles and causing conflicts.

[0049] Slot occupancy constraint (Reg_delay lock): Applicable to updates of some implicit parameters, such as a++, update5, etc., which will occupy the relevant slots.

[0050] For certain instructions, when a certain option appears, the source register may also be used as the destination register for a write operation a few clock cycles later. In this case, the slot occupancy constraint (Reg_delay lock) is used to constrain it.

[0051] The slot occupancy constraint (Reg_delay lock) can be implemented through two functions: one is the Lock_para function (applicable to accumulator instructions such as a++), and the other is the Lock function (applicable to instructions such as update5).

[0052] The Lock function has five parameters. The first parameter indicates which register to update, the second parameter indicates the name of the register to update, the third parameter indicates the clock cycle to update the corresponding register, the fourth parameter indicates the number of consecutive clock cycles to update, and the fifth parameter indicates whether to occupy the channel of the write destination register (dst).

[0053] The Lock_para function also includes 5 parameters. The first parameter indicates which variable's register is being updated in this instruction. The second parameter indicates the name of the updated register. The third parameter indicates on which clock cycle the corresponding register is being updated. The fourth parameter indicates how many consecutive clock cycles the update will take. The fifth parameter indicates whether to update the global register (share), which is mainly used for biu. If it is any other register, the fifth parameter is 0.

[0054] Adding instruction constraints (Front) before an instruction: indicates which instructions need to be added before this instruction.

[0055] For example, some instructions (such as parallel instructions) need to be followed by corresponding instructions to construct a set of instructions that meet the conditions. In this case, adding an instruction constraint (Front) before the instruction indicates the constraint.

[0056] For example, the added instruction constraints (Front) before the instruction include: Set_front and Link_front.

[0057] Set_front specifies the constraints that the preceding instruction should meet and defines the identifier of that instruction. The format of Set_front is {id, Ins_name, Const_0+const_1, Lock_para, Liner_pata, Num}.

[0058] id: Indicates the identifier of the previous instruction and constraint set.

[0059] Ins_name: Indicates the name of the previous instruction.

[0060] Const_0+const_1: This represents the constraint assigned to the previous instruction; multiple constraints can be added.

[0061] Lock_para: Indicates a constraint on the destination register (dst) of the previous instruction.

[0062] Liner_pata: Indicates whether it must be adjacent to the previous instruction.

[0063] Num: Indicates how many times the previous instruction can be randomized. Num can be a fixed value such as 2, or a range such as 0~3.

[0064] Link_front specifies the correct order of instructions, with two selection modes. One mode is Link_front{id_0, id_1}, which allows either id_0 or id_1 to precede the instruction. The other mode is Link_front{id_0+id_1, id_2}, which allows either two consecutive instructions (id_0, id_1, or id_2) to precede the instruction.

[0065] Adding instruction constraints (End) after an instruction: indicates which instruction should be added after this instruction.

[0066] For example, some instructions (such as parallel instructions) require a follow-up instruction to construct a set of instructions that meet certain conditions. In this case, adding an instruction constraint (End) after the instruction represents this constraint. Its implementation can be referenced from the implementation of adding an instruction constraint (Front) before the instruction.

[0067] Not front: This indicates which instruction cannot be added before this instruction.

[0068] For example, the constraint to prevent adding instructions before an instruction is (ins_name,cycle).

[0069] Here, ins_name is the name of the instruction that cannot be added before this instruction, and cycle is the number of consecutive lines before which an instruction named ins_name cannot appear.

[0070] Not end: This indicates that no instruction constraint can be added after this instruction.

[0071] For example, the constraint to prevent adding instructions after an instruction (Not end) is (ins_name,cycle).

[0072] Here, ins_name is the name of the instruction that cannot be added after this instruction, and cycle is the number of consecutive lines after which the instruction named ins_name cannot appear.

[0073] Instruction write operation time constraints: include the time to write to the target register and the time to write to each exit.

[0074] You can specify various randomization methods by adding instruction constraints before any instruction (Front), adding instruction constraints after any instruction (End), disallowing instruction constraints before any instruction (Not front), and disallowing instruction constraints after any instruction (Not end).

[0075] 3. Source operand configuration file The source operand configuration file includes information about the source operands. This includes the combination of fields of the functional units involved in the source operands, and the relationships between the fields and registers.

[0076] Information for any source operand includes: the register name (Reg_name) corresponding to any source operand, the offset address (Offset) of any source operand, the number of bits (Bit) of any source operand, the type (Type) of any source operand, the registers (Reg) involved in any source operand, the associated fields (Link) of any source operand, and the general constraints (Const) of any source operand.

[0077] Table 3 shows a feasible example of a source operand configuration file.

[0078] Table 3

[0079] In addition, configuration files may also include: module configuration files.

[0080] The module configuration file includes module information for all instantiated files.

[0081] The information for any module includes: the name of any module (Model_name), the name of the source operand involved in any module (Src_model), the number of bits of any source operand (Bit), the type of any source operand (Type), and the pattern identifier involved in any module (Model_id).

[0082] In addition, configuration files may include: Conflict linked configuration files.

[0083] The Conflict linker configuration file includes the mapping relationships referenced in the instruction set specification, mainly defining the dpath (data path), which indicates the overwrite situation when writing to a register.

[0084] The Conflict link configuration file is two-dimensional data, where one dimension (such as rows) represents the functional unit and the other dimension (such as columns) represents the name of the write register.

[0085] The instruction set specification is the official document that defines the processor instruction set architecture, specifying instruction formats, functions, register usage rules, etc., to ensure software and hardware compatibility.

[0086] In addition, configuration files may also include: external constraint configuration files.

[0087] Some source registers may have configuration limitations. If these registers are used as destination registers, their initial values ​​will be altered, rendering them unusable. Therefore, external constraint configuration files can be used to constrain source and destination registers, thereby obtaining instructions that meet the conditions. Alternatively, for certain testing needs (e.g., testing the processing of instructions performed by this unit when other units write to it, checking for conflicts in the top-level slot), a special register constraint can be applied to send all functional units to the same special register. This special register can then be constrained through an external constraint configuration file, allowing for random control of instructions.

[0088] In addition, configuration files may also include: functional unit configuration files.

[0089] For example, the following constraints can be imposed through the functional unit configuration file: The constraint of an execution unit on an instruction: that is, a certain functional unit does not support the instruction or a certain parameter of the instruction.

[0090] The execution unit imposes constraints on the destination register: that is, the execution unit does not support the instruction or a certain destination register in the instruction.

[0091] After configuring the above configuration file, the instructions are generated using the instruction data packet generation method provided in this embodiment. See also Figure 1 This embodiment provides a method for generating instruction data packets, the implementation process of which is as follows: 101, Obtain processing instructions.

[0092] For example, each instruction in the instruction instance is retrieved; the retrieved instruction is the processing instruction.

[0093] For example, the processing instructions are obtained based on the input command. That is, the instructions required for the input command are obtained from the command entered by the user in the Linux interface.

[0094] 102. Determine the source operands of the processing instruction based on the pre-configured instruction configuration file.

[0095] The instruction configuration file includes information about the instructions for each functional unit.

[0096] Information for any instruction includes: the name of any instruction (Inst_name), the template of any instruction (Temp), the fields of any instruction (Field), and the general constraints of any instruction template (Const).

[0097] In addition, the information for any instruction also includes: the constraints of any instruction.

[0098] The constraints include one or more of the following: the name of the destination register not supported by any instruction (Notsupport dst), the name of the module not used by any instruction (Not support model), the constraint added when any instruction is used by a module (Add const), the constraint on the parameters of any instruction (Base const), the random order constraint (Liner_para), the constraint passed to the destination register by any instruction (Add dst const), the number of consecutive lock cycles of the destination register (Lock dst), the slot occupancy constraint (Reg_delay lock), the instruction addition constraint before any instruction (Front), the instruction addition constraint after any instruction (End), the instruction addition restriction constraint before any instruction (Notfront), the instruction addition restriction constraint after any instruction (Not end), the write operation time constraint of any instruction, and the binding constraint of any instruction.

[0099] 103. Based on the pre-configured source operand configuration file, determine the definition of the source operand and the register corresponding to the source operand.

[0100] The source operand configuration file includes information about the source operands.

[0101] Information for any source operand includes: the register name (Reg_name) corresponding to any source operand, the offset address (Offset) of any source operand, the number of bits (Bit) of any source operand, the type (Type) of any source operand, the registers (Reg) involved in any source operand, the associated fields (Link) of any source operand, and the general constraints (Const) of any source operand.

[0102] 104. Determine the register definitions based on the pre-configured register configuration file.

[0103] The register configuration file includes information about all shared registers (Reg).

[0104] Information for any register includes: the name of any register (Reg_name), the write format of any register (Write_temp), the number of registers in the group to which any register belongs (Reg_map), and the general constraints of any register (Const).

[0105] 105. Based on the definitions of the source operand and the register, bind the processing instruction, source operand, and register to generate a data packet that calls the processing instruction.

[0106] Because many variables in VLIW have constraints, when generating a data packet for calling and processing instructions, it is necessary to consider some constraints of the instructions in order to generate a relatively healthy data packet. Therefore, the variables in the generated data packet satisfy the constraints.

[0107] The constraint relationships are determined through the following steps: A. Form a first sequence from all the variables in the data packet.

[0108] For example, all variables of data packet 1 of instruction 1 are formed into the first sequence q1.

[0109] B. Form a second sequence based on random order constraints.

[0110] For example, obtain the random order constraint (Liner_para) from the instruction configuration file of instruction 1, and form the second sequence q based on the random order constraint (Liner_para).

[0111] C. Obtain the random order of all variables based on the first and second sequences, and determine the random order as a constraint relationship.

[0112] For example, a) Pack all variables in the second sequence q, calculate the union of all variables, and place them in the third sequence q2. b) Sort the variables in the third sequence q2 according to the order in the second sequence q to obtain the fourth sequence q3 that conforms to the order. c) Divide the variables in the first sequence q1 into two groups: those in the fourth sequence q3 and those not in the fourth sequence q3. d) Form a random order of all variables from the two groups, and define the random order as a constraint relationship.

[0113] If a constraint includes a precondition (such as a variable c3 in a constraint must follow the other variables c4), then c3 also satisfies the precondition.

[0114] Furthermore, the random order constraint (Liner_para) can contain multiple sets of constraints, such as c5>c6, c6>c7, c8>c5>c9. Therefore: A. Form a first sequence from all the variables in the data packet.

[0115] For example, all variables of data packet 1 of instruction 1 are formed into the first sequence q1.

[0116] B. Form a second sequence based on random order constraints.

[0117] For example, obtain the random order constraint (Liner_para) from the instruction configuration file of instruction 1, form a queue for each group of constraints according to the random order constraint (Liner_para), and form a two-dimensional queue for all groups of queues. This two-dimensional queue is the second sequence q.

[0118] C. Obtain the random order of all variables based on the first and second sequences, and determine the random order as a constraint relationship.

[0119] For example, a) Pack all variables in the second sequence q, calculate the union of all variables, and place them in the third sequence q2. b) Sort the variables in the third sequence q2 according to the order in the second sequence q to obtain the fourth sequence q3 that conforms to the order. c) Divide the variables in the first sequence q1 into two groups: those in the fourth sequence q3 and those not in the fourth sequence q3. d) Form a random order of all variables from the two groups, and define the random order as a constraint relationship.

[0120] In addition, the generated data packet also satisfies the solver constraints between the instruction and the destination register.

[0121] For example, if a destination register (dst) contains many solutions and can be written to multiple functional units, the constraint passed to the destination register by the instruction in the instruction configuration file (Add dst const) will be recorded. Then, in step B, when forming the second sequence based on the random order constraint, the constraint passed to the destination register by the instruction in the instruction configuration file (Add dst const) will also be retrieved. This constraint will be considered when forming the second sequence, resulting in a second sequence q that satisfies both the random order constraint (Liner_para) and the constraint passed to the destination register by the instruction (Add dst const).

[0122] In addition, the generated data packets also satisfy external constraints.

[0123] For example, the instruction retrieves the external constraint profile, checks whether the source registers designed by the instruction are constrained by the external constraint profile, and if so, tags the data packet with the external constraint so that the external constraint can be satisfied based on the tag during subsequent instruction execution.

[0124] In addition, after executing step 105, the access data of the data packet can be statistically analyzed using the simulator to determine whether there is a problem with the data packet.

[0125] In practical implementation, steps 101 to 105 above can be executed via a script. For example, in step 101, the script extracts a processing instruction (such as ins_0) from the instruction instance (ins); in step 102, the source operand of ins_0 (such as src_0) is determined according to the instruction configuration file; in step 103, the definition of src_0 and the corresponding register (such as reg_0) of src_0 are determined according to the source operand configuration file; in step 104, the definition of reg_0 is determined according to the register configuration file; and in step 105, ins_0, src_0, and reg_0 are bound according to the definitions of src_0 and reg_0 to generate a data packet that calls ins_0.

[0126] The script repeats steps 101 to 105 until it generates a data packet containing all instructions in the instruction instance (ins). Then, the data packets containing all instructions can be used to generate an instruction library for subsequent instruction execution.

[0127] The instruction data packet generation method provided in this embodiment uses configuration files (such as register configuration files, instruction configuration files, and source operand configuration files) to pass parameters and then generate the data packet corresponding to the instruction.

[0128] In addition, after generating the data packet, the data packet can also be executed. The execution process is as follows: 201, determines the number of slots in the vector processor that can be executed in parallel.

[0129] The implementation process of step 201 is as follows: 201-1, retrieve the pre-configured parallel parameter values ​​and select the mode.

[0130] The selection mode can be either random or non-random.

[0131] 201-2, If the selected mode is random mode, then a random value is determined, and the number of slots to be executed in parallel is also determined to be a random value.

[0132] For example, if the parallel parameter value is d1, then a random value d2 is randomly determined from 1 to d1, and the number of slots executed in parallel is determined to be d2.

[0133] 201-3 If the selected mode is non-random mode, then determine the number of parallel operations supported by the vector processor, and determine the number of slots to be executed in parallel as the minimum value between the parallel parameter value and the number of parallel operations supported by the vector processor.

[0134] For example, if the parallel parameter value is d1, the number of parallel operations supported by the vector processor is d3, and the number of slots to execute in parallel is determined to be min{d1, d3}. Here, min{} is the function for finding the minimum value.

[0135] 202. Based on the number of slots that can be executed in parallel, data packets are processed by the functional units of the vector processor in each cycle.

[0136] For example, if the number of slots executed in parallel is d4, then in each cycle, d4 functional units of the vector processor are randomly selected to process the data packets obtained by the data packet generation method of the instructions in this embodiment.

[0137] When processing data packets through the functional units of the vector processor, the preconditions, constraints, and the order of solving for the remaining variables are determined based on the constraints. If the preconditions, constraints, and the order of solving for the remaining variables are satisfied, a solution is determined; otherwise, no solution exists. If no solution exists, the process reverts to the initial state; if a solution exists, the state is recorded.

[0138] Additionally, in VLIW, there may be instances where the same command or data must be sent within the same timeframe. This constraint is configured in the command binding constraints within the command information. Therefore: A. After the data packet is processed by the vector processor's functional unit, it will determine whether the pre-bound slot has been sent.

[0139] Among them, the pre-bound slots are determined according to any instruction binding constraint.

[0140] B. If the data packet has already been sent, then send the corresponding instruction. Subsequently, based on the constraints, determine the preconditions, constraints, and the order in which to solve the remaining variables. If the preconditions, constraints, and the order in which to solve the remaining variables are satisfied, then a solution exists; otherwise, no solution exists. If no solution exists, revert to the initial state; if a solution exists, record the state.

[0141] C. If not sent, then a) if there is no corresponding instruction in the pre-bound slot, pause the sending of the instruction corresponding to the data packet. b) if there is a corresponding instruction in the pre-bound slot, back up all states, send the instruction corresponding to the data packet, use the label of the instruction corresponding to the pre-bound slot as the label of the instruction corresponding to the data packet, and place the label of the pre-bound slot randomly after the instruction corresponding to the data packet.

[0142] For example, check if a bound command exists in the slot. If not, the command cannot be sent, i.e., pause the sending of the command corresponding to the data packet. If it exists, back up all states at this time (i.e., back up all states), send the command (i.e., send the command corresponding to the data packet), and in the command prompt, mark the command in another slot with the same label (i.e., label the command corresponding to the pre-bound slot as the command corresponding to the data packet), allowing only this command to be sent, and placing the random slot label after this command (i.e., placing the random slot label after the command corresponding to the data packet). In specific implementations, a tag can also be added in the command prompt, indicating that a set of bound commands needs to be sent.

[0143] D. If the instruction corresponding to the data packet and the instruction corresponding to the pre-bound slot are not randomly obtained according to the tag, then roll back to the specified position.

[0144] For example, check the tags of relevant commands in cmd crtl to see if both commands are randomly selected. If not, roll back to the specified position.

[0145] The rollback process can be implemented using copy functions (such as the Copy function) and rollback functions (such as the Back function). Specifically, the copy function (such as the Copy function) backs up the data to the new node and clears the original node, while the rollback function restores the data in the new node.

[0146] For example, back up all the data before any processing, and if it is determined that there is no solution, roll back all updated states to the recorded state. All data structures are packaged into a single class and placed in a queue. Two functions are added to implement copying and rollback, preventing data corruption.

[0147] The Copy function performs a deep copy of the corresponding queue function to a new node tag1, thereby backing up the data and clearing the previous node.

[0148] Back function: Due to an error in the previous step, the function in the previous step is rolled back, and the queue corresponding to tag1 is replaced with the existing queue.

[0149] Furthermore, there are no slot conflicts when the data packets are processed by the vector processor's functional units. Slot conflicts are determined based on slot occupancy constraints (Reg_delay lock). Instruction information can be obtained, parsed, and its constraints, including slot occupancy constraints (Reg_delay lock), can be used to determine the slot.

[0150] In addition, the registers involved in processing the executed data packets through the functional units of the vector processor satisfy external constraints. These external constraints can be configured in the external constraint configuration file.

[0151] Registers can also be updated using locking parameters. These locking parameters include: the variable corresponding to the register in the first instruction, the register name, the update phase flag, the number of consecutive update phases for the register, and whether to update the global register.

[0152] In addition, when processing certain data heaps, different read / write ports may access different storage areas, requiring the resolution of conflicts between different storage spaces. Therefore, when processing data packets through the functional units of the vector processor, there are no conflicts in the storage spaces involved.

[0153] For example, pre-configure constraints for reading and writing to different storage spaces. This could involve configuring two tables: one table constrains write operations to different storage spaces (e.g., `fail` indicates that writing to that storage space is not possible, and the same letter indicates that the same write port is used to write to the corresponding storage space); the other table constrains read operations from storage spaces (e.g., `fail` indicates that reading from that storage space is not possible, and the same letter indicates that the same read port is used to read from the corresponding storage space). By pre-configuring these constraints for reading and writing to different storage spaces, the problem of identical read / write channels can be solved, and different read / write ports can be instantiated.

[0154] Furthermore, during each iteration, when data packets are processed by the vector processor's functional units, instructions are issued out of order. The issuance of out-of-order instructions can be implemented based on the functional unit configuration file and instruction configuration file.

[0155] Because VLIW instructions have many constraints and take a long time to generate, after the data packet is obtained in step 105, it can be encapsulated using a script that performs a one-click regression.

[0156] Taking test scenarios (fully random, semi-random) as an example, each instruction has different input options, i.e., a case. All possible cases can be predefined according to actual needs such as testing requirements. Furthermore, when different seeds are input, the generated instruction patterns are also different, thus resulting in different cases. Using the method provided in this embodiment, a data packet of random instructions for all cases is generated according to the configuration file. After executing the data packet in steps 201 and 202, all cases are generated in parallel, and the problems in each case are counted in real time. Then, gem5 and rtl are run separately to compare whether any problems exist in these cases.

[0157] Since ISGs can be used in various scenarios, including fully random and semi-random scenarios, and can be single-slot or multi-slot scenarios, some sel options are incorporated into the development of ISGs to improve processing speed. Table 4 shows examples of the incorporated options, but the actual implementation is not limited to the options shown in Table 4.

[0158] Table 4

[0159] Additionally, when all commands are randomly selected, it can be checked whether the command can be tagged. If a tagged command is added, it will not be randomly selected, thus implementing this functionality. Based on the above behavior definition of the cases, when running all the cases, the cases are split and extracted, and then the following steps are performed: 1. Each instruction generates a corresponding ISG file, which is then converted into ELF and Hex files and stored in the case folder.

[0160] 2. Submit the ELF file to the simulator to generate the corresponding register data that can be processed and to collect statistics.

[0161] 3. Compare the data generated by the hex and simulator with the RTL to check for any data issues.

[0162] Each of the above steps must be completed before proceeding to the next step. During the process, cases that generate, run gem5, or encounter problems with rtl will be identified and processed in parallel by step 1. In addition, after a random instruction is issued, the corresponding log information is printed, and the usage of the registers, the testing of the slots, the usage of the functional units, and the usage of other constraints are recorded.

[0163] In addition, the registers involved in the instruction data packet generation method provided in this embodiment are located in the vector processor, and the vector processor also includes: a vector program control unit, multiple functional units, a private vector register of the vector interleaving unit, and a private vector register of the vector access unit.

[0164] The registers include: register file stack and scalar registers.

[0165] like Figure 2 The structure of a vector processor is shown. Figure 2 Only the vector program control unit, multiple functional units, and registers (including register file stack and scalar registers) are shown. Figure 2 The private vector registers of the vector interleaving unit and the vector access unit are not shown in the diagram.

[0166] 1. Vector Program Control Unit Vector program control unit, used for instruction fetching and instruction issuing.

[0167] That is, the vector program control unit is used to retrieve instructions, determine whether to execute them, and issue instructions to functional units based on the determination result.

[0168] The vector program control unit is also used to control instruction jumps.

[0169] The vector program control unit has scalar computation capabilities.

[0170] The vector program control unit interacts with the scalar register.

[0171] In practical implementation, the vector program control unit is an instruction fetch and instruction issue unit. It fetches instructions from the cache based on the PC value, and after determining whether to execute, issues instructions to each functional unit based on the wait value (configured by the wait instruction). It also controls instruction jumps and has some scalar computation capabilities.

[0172] In addition, the vector program control unit is also used to receive start commands from other processing processors and start the vector processor. It also returns an indication signal to other processing processors indicating whether the vector processor has finished.

[0173] Taking other processing processors as scalar processors as an example, the vector program control unit receives the start command issued by the synchronization unit of the scalar processor, starts the vector processor to execute, and also returns an indication signal to the synchronization unit whether the vector processor execution has ended.

[0174] 2. Functional Units Functional units are used to perform functional processing according to instructions.

[0175] For example, a functional unit receives instructions from a vector program control unit, processes the data accordingly, and outputs the processing results at the address specified in the instructions.

[0176] The functional units include: one or more vector operation units, one or more vector interleaving units, and one or more vector access units.

[0177] 1) Vector operation unit Any vector operation unit is used to perform vector operations according to instructions.

[0178] like Figure 3 As shown, any vector operation unit includes: a floating-point multiply-add subunit, a floating-point multiply-accumulate subunit, a floating-point arithmetic subunit, a tensor multiplication subunit, and an intermediate result register.

[0179] The floating-point multiply-accumulate subunit and the floating-point arithmetic subunit share one slot. Therefore, a maximum of 8 instructions from the vector operation unit can be issued per cycle.

[0180] The floating-point multiplication-accumulation subunit and the tensor multiplication subunit share the same slot.

[0181] The floating-point multiply-accumulate subunit is a functional unit that executes instructions related to floating-point multiply-accumulate operations. For example, instructions related to floating-point multiply-accumulate operations include integer and floating-point vector multiplication and accumulation, multiplication, addition, tensor calculation, etc.

[0182] Each vector operation unit has its own intermediate result register.

[0183] One floating-point multiply-accumulate subunit, one floating-point multiply-accumulate subunit, one tensor multiplication subunit, and one floating-point arithmetic subunit share an intermediate result register.

[0184] (1) Floating-point multiply-accumulate and floating-point multiply-accumulate subunits, which can perform integer and floating-point vector multiplication, multiply-accumulate and other operations. Supported types include, but are not limited to, int32, fp32, and fp64.

[0185] (2) The floating-point arithmetic subunit can perform integer and floating-point vector arithmetic operations, such as comparison, addition, subtraction, bitwise operations, etc. Supported types include, but are not limited to, int8, uint8, int16, uint16, int32, uint32, bool, fp16, bf16, fp32, tf32, fp64.

[0186] (3) The tensor multiplication subunit can perform tensor multiplication, multiply-accumulate and other operations. Supported types include, but are not limited to, int8, bf16, fp16 and tf32.

[0187] 2) Vector interleaving unit Any vector interleaving unit is used to perform data interleaving and logical processing according to instructions.

[0188] The vector interleaving unit is the control and data processing unit within the vector processor. It is responsible for interleaving data, supporting logical and some fixed-point and floating-point calculations. It also supports numerous customized instructions, including table lookup, horizontal calculation, sparse matrix calculation, precision conversion, and FIFO (First Input First Output) functions. It executes instructions such as data broadcasting, extraction, and internal interleaving.

[0189] Each vector interleaving unit has a set of private vector registers; therefore, the private vector registers of each vector interleaving unit correspond one-to-one with the vector interleaving units.

[0190] 3) Vector Access Unit Each vector access unit is used to perform multi-mode memory access, address calculation, and scalar calculation according to instructions.

[0191] The vector access unit is the memory access unit within the vector processor, primarily responsible for reading / writing instructions and various scalar calculations.

[0192] The read / write instructions support multiple memory access modes, such as row mode, column mode, discrete mode, extended mode, and accumulation mode.

[0193] It supports multiple parameter configurations, with a maximum read / write instruction data width of up to 1024 bits. It executes instructions such as address calculation, load / store, etc.

[0194] All vector access units share a set of private vector registers, so the private vector registers of a vector access unit are shared by multiple vector access units.

[0195] 3. Register file stack The register file is used to receive and return data after read / write requests. The data is rearranged and then returned. It interacts with functional units for read / write operations. The configuration registers of the vector program control unit are configured using data within the register file.

[0196] The register file stack is a general-purpose vector register stack, which is the main storage unit within the vector processor. It is responsible for receiving read and write requests and returning data. In some functions, it can rearrange the data before returning it to the requesting module.

[0197] The register file stack interacts with functional units within the vector processor (such as the floating-point multiply-accumulate subunit, floating-point arithmetic subunit, floating-point multiply-accumulate subunit, and tensor multiplication subunit), and also supports configuring the instruction fetch unit configuration register using data in the register file stack.

[0198] The register file is also used to write data to other processing units. It receives status messages from other processing units indicating whether the data has been written.

[0199] Taking other processing processors as examples, such as scalar processors, the synchronization unit of a scalar processor can write data to the register file, and the register file can also receive status information from the synchronization unit of the scalar processor to query whether the data has been written.

[0200] The depth of the register file heap is configurable.

[0201] Figure 4 A schematic diagram of a vector processor is shown, comprising four vector operation units, four vector interleaving units, and four vector access units.

[0202] The vector processor provided in this embodiment supports the VLIW (Very Long Instruction Word) instruction set. Each VLIW can consist of one or more instructions, and each instruction corresponds to a functional unit.

[0203] In addition, read FIFO units and write FIFO units are set up between the vector processor and other computing processors.

[0204] The vector program control unit and other arithmetic processors both perform read operations on the read FIFO unit and write operations on the write FIFO unit.

[0205] Other processing units perform read or write operations on scalar registers.

[0206] Taking other processing processors as examples, such as scalar processors, there are read FIFO and write FIFO units between the scalar processor and the vector processor for transmitting data. The scalar processor and the vector program control unit can perform read operations or write operations on the read and write FIFOs.

[0207] Meanwhile, the synchronization unit of the scalar processor can perform read or write operations on the scalar registers of the vector processor.

[0208] The instruction data packet generation method provided in this embodiment can solve the problem of long instruction generator development cycles, especially in the early stages of development when developers are unclear about the details related to instruction definitions, leading to long instruction generation cycles. When requirements change, the corresponding program can be quickly modified simply by changing the configuration file. For example, when adding an instruction or expanding the bit width of all instruction fields, the instruction data packet generation method provided in this embodiment can complete the instruction configuration change without modifying the script, shortening the cycle of each instruction configuration modification and avoiding development cycle delays.

[0209] Following the same inventive concept as the instruction-based data packet generation method, this embodiment provides an instruction-based data packet generation apparatus, see [link to previous document]. Figure 5 The device includes: The acquisition module 501 is used to acquire processing instructions.

[0210] The first determining module 502 is used to determine the source operands of the processing instruction according to the pre-configured instruction configuration file.

[0211] The second determining module 503 is used to determine the definition of the source operand and the register corresponding to the source operand according to the pre-configured source operand configuration file.

[0212] The third determining module 504 is used to determine the definition of the registers based on the pre-configured register configuration file.

[0213] The generation module 505 is used to bind the processing instruction, source operand, and register according to the definition of the source operand and the definition of the register, and generate a data packet for calling the processing instruction.

[0214] The registers are located within the vector processor, which also includes: a vector program control unit, multiple functional units, a private vector register for the vector interleaving unit, and a private vector register for the vector access unit.

[0215] The registers include: register file stack and scalar registers.

[0216] The vector program control unit is used for instruction fetching and instruction issuance. The vector program control unit interacts with scalar registers.

[0217] Functional units are used to perform functional processing according to instructions.

[0218] The register file is used to receive and return data after read / write requests. The data is rearranged and then returned. It interacts with functional units for read / write operations. The configuration registers of the vector program control unit are configured using data within the register file.

[0219] Among them, the private vector register of the vector interleaving unit corresponds one-to-one with the vector interleaving unit.

[0220] The private vector register of a vector access unit is shared by multiple vector access units.

[0221] The instruction configuration file includes information about the instructions for each functional unit.

[0222] The information for any instruction includes: the name of any instruction, the template of any instruction, the fields of any instruction, and the general constraints of any instruction template.

[0223] The source operand configuration file includes information about the source operands.

[0224] The information for any source operand includes: the register name corresponding to the source operand, the offset address of the source operand, the number of bits of the source operand, the type of the source operand, the registers involved in the source operand, the associated fields of the source operand, and the general constraints of the source operand.

[0225] The register configuration file includes information about all shared registers.

[0226] The information for any register includes: the name of any register, the format for writing to any register, the number of registers in the group to which any register belongs, and the general constraints of any register.

[0227] The information for any instruction also includes the constraints of any instruction.

[0228] The constraints include one or more of the following: the name of the destination register not supported by any instruction; the name of the module not used by any instruction; the constraints added when any instruction is used by a module; the constraints on the parameters of any instruction; random order constraints; the constraints passed by any instruction to the destination register; the number of consecutive lock cycles of the destination register; slot occupancy constraints; the constraint to add an instruction before any instruction; the constraint to add an instruction after any instruction; the constraint to prohibit adding an instruction before any instruction; the constraint to prohibit adding an instruction after any instruction; the write operation time constraint of any instruction; and the binding constraint of any instruction.

[0229] The variables in the data packet satisfy the constraint relationships.

[0230] The constraint relationships are determined through the following steps: All variables in the data packet are arranged into a first sequence.

[0231] A second sequence is formed based on random order constraints.

[0232] The random order of all variables is obtained based on the first and second sequences, and the random order is determined as a constraint relationship.

[0233] This process, after binding the processing instruction, source operand, and register according to the definitions of the source operand and register, and generating the data packet for invoking the processing instruction, also includes: The simulator is used to perform register access statistics on data packets.

[0234] Determine if there are any problems with the data packets based on the statistical access data.

[0235] The processing instructions include: Obtain processing instructions based on the input command.

[0236] The device provided in this embodiment can modify instructions each time they are modified, through the configured instruction configuration file, source operand configuration file, and register configuration file. This allows for changes to the instruction configuration without modifying the script, shortening the cycle of each instruction configuration modification and avoiding delays in the development cycle.

[0237] Based on the same inventive concept as the instruction-based data packet generation method, this embodiment provides an electronic device, which includes: a memory; High-performance processors; and Computer programs; The computer program is stored in memory and configured to be executed by a high-performance processor to implement a data packet generation method of instructions.

[0238] Specifically, Obtain processing instructions.

[0239] The source operands of a processing instruction are determined based on a pre-configured instruction configuration file.

[0240] Based on the pre-configured source operand configuration file, determine the definition of the source operand and the register corresponding to the source operand.

[0241] The register definitions are determined based on the pre-configured register configuration file.

[0242] Based on the definitions of the source operand and the register, the processing instruction, source operand, and register are bound together to generate a data packet that calls the processing instruction.

[0243] The registers are located within the vector processor, which also includes: a vector program control unit, multiple functional units, a private vector register for the vector interleaving unit, and a private vector register for the vector access unit.

[0244] The registers include: register file stack and scalar registers.

[0245] The vector program control unit is used for instruction fetching and instruction issuance. The vector program control unit interacts with scalar registers.

[0246] Functional units are used to perform functional processing according to instructions.

[0247] The register file is used to receive and return data after read / write requests. The data is rearranged and then returned. It interacts with functional units for read / write operations. The configuration registers of the vector program control unit are configured using data within the register file.

[0248] Among them, the private vector register of the vector interleaving unit corresponds one-to-one with the vector interleaving unit.

[0249] The private vector register of a vector access unit is shared by multiple vector access units.

[0250] The instruction configuration file includes information about the instructions for each functional unit.

[0251] The information for any instruction includes: the name of any instruction, the template of any instruction, the fields of any instruction, and the general constraints of any instruction template.

[0252] The source operand configuration file includes information about the source operands.

[0253] The information for any source operand includes: the register name corresponding to the source operand, the offset address of the source operand, the number of bits of the source operand, the type of the source operand, the registers involved in the source operand, the associated fields of the source operand, and the general constraints of the source operand.

[0254] The register configuration file includes information about all shared registers.

[0255] The information for any register includes: the name of any register, the format for writing to any register, the number of registers in the group to which any register belongs, and the general constraints of any register.

[0256] The information for any instruction also includes the constraints of any instruction.

[0257] The constraints include one or more of the following: the name of the destination register not supported by any instruction; the name of the module not used by any instruction; the constraints added when any instruction is used by a module; the constraints on the parameters of any instruction; random order constraints; the constraints passed by any instruction to the destination register; the number of consecutive lock cycles of the destination register; slot occupancy constraints; the constraint to add an instruction before any instruction; the constraint to add an instruction after any instruction; the constraint to prohibit adding an instruction before any instruction; the constraint to prohibit adding an instruction after any instruction; the write operation time constraint of any instruction; and the binding constraint of any instruction.

[0258] The variables in the data packet satisfy the constraint relationships.

[0259] The constraint relationships are determined through the following steps: All variables in the data packet are arranged into a first sequence.

[0260] A second sequence is formed based on random order constraints.

[0261] The random order of all variables is obtained based on the first and second sequences, and the random order is determined as a constraint relationship.

[0262] This process, after binding the processing instruction, source operand, and register according to the definitions of the source operand and register, and generating the data packet for invoking the processing instruction, also includes: The simulator is used to perform register access statistics on data packets.

[0263] Determine if there are any problems with the data packets based on the statistical access data.

[0264] The processing instructions include: Obtain processing instructions based on the input command.

[0265] In addition, high-performance processors include vector processors.

[0266] The vector processor includes: a vector program control unit, multiple functional units, a private vector register for the vector interleaving unit, a private vector register for the vector access unit, and registers.

[0267] The registers include: register file stack and scalar registers.

[0268] In practical implementations, high-performance processors also include scalar processors.

[0269] The connection between scalar processors and vector processors can be as follows: Figure 6 As shown.

[0270] In this architecture, scalar processors and vector processors share data storage. However, vector processors can only access the data storage and are executed solely by scalar processors.

[0271] A connection is established between scalar processors and vector processors. For example, scalar processors and vector processors can be connected via a dedicated instruction channel.

[0272] In addition, a high-performance processor may include two registers: one for the scalar processor and the other for the vector processor. The vector processor can read and write its corresponding register, while the scalar processor can read and write both its corresponding register and the register corresponding to the vector processor.

[0273] Scalar processors can read and write the registers of vector processors.

[0274] The scalar processor establishes a connection with global memory.

[0275] (a) Scalar Processor See Figure 7 The scalar processor includes: an instruction fetch unit, a register renaming unit, an arithmetic reserved stack unit, a memory reserved stack unit, a scalar arithmetic unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit.

[0276] In addition, a scalar processor may include one or more other units, such as one or more other functional modules, one or more instruction caches, one or more data stores, one or more special vector registers, one or more status flag registers, etc.

[0277] 1. Instruction Fetch Unit The instruction fetch unit is used to fetch and dispatch instructions.

[0278] Specifically, the instruction fetch unit generates an instruction fetch request address, outputs the fetch request address to the instruction cache for instruction fetching, receives instructions from the instruction cache, and stores them in the data storage. Each cycle, it sequentially reads qualified instructions from the data storage, decodes and performs relevant checks on the read instructions, and then dispatches the checked instructions sequentially.

[0279] For example, the instruction fetch unit generates an instruction fetch request address and outputs it to the instruction cache for instruction fetching. It also receives instructions from the instruction cache and stores them in the data storage. In each cycle, it sequentially searches for one or more instructions from the qualified instructions, performs decoding and related checks, and dispatches the qualified instructions in sequence. At most, it dispatches one program control unit instruction and one synchronization unit instruction at a time. In addition, it can dispatch one or more scalar arithmetic unit instructions and one or more memory access unit instructions at a time.

[0280] 2. Register renaming unit The register renaming unit is used to receive instructions dispatched by the instruction fetch unit and to rename registers.

[0281] Specifically, the register renaming unit receives and stores instructions dispatched by the instruction fetch unit, renames special vector registers, performs instruction conditional decoding, and generates pipeline congestion signals. It receives data from one or more of the following: the scalar arithmetic unit, memory access unit, program control unit, synchronization unit, special vector registers, condition registers, and flag registers, and writes it back. It sends instructions to the arithmetic reserved stack unit, and stores them in one or more of the following: the program control unit, and the synchronization unit.

[0282] For example, the register renaming unit in a scalar processor is used to receive instructions dispatched by the instruction fetch unit and rename registers and special vector registers, decode instruction conditions, generate pipeline congestion signals, and simultaneously receive data from execution units (such as scalar arithmetic units, memory access units, program control units, and synchronization units) to write back registers, special vector registers, condition registers, and status flag registers and write them back to the corresponding registers.

[0283] Scalar processors support out-of-order write-back, resulting in high execution efficiency. They also distribute instructions to the arithmetic stack, storage stack, program control unit, or synchronization unit.

[0284] The register renaming unit bandwidth can be 6 bits, during which multiple (e.g., 4) input instructions can be valid at the same time.

[0285] There can be multiple condition registers, which are located in the register renaming unit.

[0286] The instructions for the scalar arithmetic unit and memory access unit support reading and writing condition registers.

[0287] The instructions for the synchronization unit support reading the condition register.

[0288] The program control unit's jump and function call instructions support reading the condition register.

[0289] When an instruction enters the condition register, the pipeline will be blocked if there are unexecuted instructions in the condition register.

[0290] In other words, the condition register is not renamed; when a read / write request occurs, a dispatch blocking mechanism is triggered to wait. The conditions register read / write rules are as follows: Reading rules: (1) All instructions in the scalar arithmetic unit, memory access unit, and synchronization unit support conditional execution and require reading the value of the condition register.

[0291] (2) The scalar arithmetic unit also supports read condition register instruction operations.

[0292] (3) The jump and function call instructions of the program control unit support reading condition register operations.

[0293] Write the rules: (1) The scalar arithmetic unit supports write condition register instructions.

[0294] (2) Scalar arithmetic unit logic instructions and comparison instructions support the option to write to the condition register.

[0295] When a previously issued instruction to write to the condition register has not yet finished executing, and another instruction to read or write to the same condition register enters, the pipeline becomes congested, generating a condition execution block signal, and waits for the previous condition register to finish writing.

[0296] In addition, the register renaming unit includes one or more physical registers and one or more logical registers.

[0297] Each of the following physical registers can be one of the following: scalar physical register, vector physical register, condition register, or flag register.

[0298] Any logic register can be one of the following: scalar logic register or vector logic register.

[0299] For example, a register renaming unit contains one or more physical registers, such as multiple 512-bit special vector registers, multiple condition registers, and a status flag register.

[0300] Among them, the special vector register is renamed, while the condition register and status flag register are not renamed.

[0301] There are multiple logic registers, such as scalar logic registers and multiple vector logic registers.

[0302] In addition, the mapping relationship between logical registers and physical registers is maintained by a register mapping table. The mapping relationship between vector logical registers and vector physical registers is maintained by a special vector register mapping table.

[0303] 1) Register Map Table Initially, the mapped physical registers for all entries corresponding to logical register indices in the register map are all 0. When an instruction is executed, or when an interrupt occurs, the logical register allocated to the relevant physical register is determined, and the mapping of the entries corresponding to the allocated logical register indices in the register map is updated to the identifier of the relevant physical register.

[0304] For example, a register map table with a depth of 32 bits and a width of 6 bits stores the mapping relationship between all logical registers and all physical registers. Initially, the register map table is invalid, and all entries mapping physical registers are all 0. When a physical register is allocated to a logical register, the entry in the register map table corresponding to the logical register index is changed to the ID of that physical register.

[0305] It should be noted that the register map is only updated when an instruction is actually executed. If the conditional execution instruction is not executed, the register map will not be updated. In addition, the register map will not be updated when a jump occurs. However, when an interrupt occurs, the interrupt return address must update the register map to ensure that the interrupt can return normally.

[0306] 2) Special Vector Register Mapping Table Initially, the mapped vector physical registers for all entries corresponding to vector logical register indices in the special vector register map are all 0. When an instruction is executed, the vector logical register allocated to the relevant vector physical register is determined, and the mapping of the entries corresponding to the allocated vector logical register indices in the special vector register map is updated to the identifier of the relevant vector physical register.

[0307] For example, the special vector register map table, with a depth of 4 bits and a width of 3 bits, stores the mapping relationship between all vector logic registers and all vector physical registers. Initially, the special vector register map table is invalid, and all entries mapping to vector physical registers are 0. When a vector physical register is allocated to a vector logic register, the entry in the special vector register map table corresponding to the vector logic register index is changed to the ID of that vector physical register.

[0308] It should be noted that the special vector register mapping table is only updated when the instruction is actually executed. If the conditional execution instruction is not executed, the special vector register mapping table will not be updated. In addition, the special vector register mapping table will not be updated when a jump occurs.

[0309] 3. Operations retain stack units The operation-reserved stack unit is the issue queue of scalar operation units.

[0310] The arithmetic stack is used to receive instructions, dispatch and rename information from the register renaming unit and push them into the queue. Ready instructions are popped into the scalar arithmetic unit for execution.

[0311] The stack space is reserved for operations and is also used to decode input instructions and store instruction type information.

[0312] In other words, the arithmetic reserve stack is the dispatch queue of the scalar arithmetic unit. The arithmetic reserve stack receives instructions and related dispatch and renaming information from the register renaming unit and pushes them into the queue. It also pops ready instructions onto the scalar arithmetic unit for execution. The arithmetic reserve stack decodes the input instructions and stores the instruction type information.

[0313] In practice, the depth of the operation reserve stack can be flexibly adjusted, such as a depth of 8. Multiple scalar operation units share one operation reserve stack unit.

[0314] The rules for issuing and receiving instructions that reserve stack space are as follows: (1) The output of the register renaming unit enters the operation reserve stack unit.

[0315] (2) When there is any free scalar arithmetic unit, it will fetch instructions and operands from the arithmetic reserve stack and execute them.

[0316] (3) The principle of fetching instructions from the operation reserved stack is to fetch executable instructions that can be sent from the operation reserved stack in the order from front to back.

[0317] (4) Whether it is possible to send a value based on the values ​​of all source registers or special vector registers or condition registers and status flag registers is ready to be determined.

[0318] (5) If there are multiple instructions that can be sent, send the oldest instruction first according to the order of instructions.

[0319] (6) If any scalar arithmetic unit is blocked, it can no longer receive new instructions.

[0320] (7) If the instruction previously sent to any scalar arithmetic unit was a division instruction, a new division instruction can only be sent to it after the division result is calculated and the calculation completion En signal is returned.

[0321] 4. Store and retain stack units The storage-reserved stack unit is the issue queue for memory access units.

[0322] The storage reserve stack unit is used to receive instructions and register renaming information from the register renaming unit and push them into the queue.

[0323] The storage reserve stack unit is also used to send a read request to the register renaming unit when the instruction address register is ready, and to save the read address operand.

[0324] The register renaming unit is also used to calculate the address after the instruction has obtained the address, decode the address, and save the decoded information.

[0325] The register renaming unit is also used to detect when the existence source register of any instruction is ready and the address decoding is complete, and then issue it to the memory access unit for execution.

[0326] In practice, the depth of the memory reservation stack unit can be flexibly adjusted, such as 16. Multiple memory access units share one memory reservation stack unit. The memory reservation stack unit is the issue queue for memory access units. The memory reservation stack unit receives instructions and register renaming information from the register renaming unit and pushes them into the queue. When the instruction address register in the memory reservation stack unit is ready, a read request is sent to the register renaming unit, and the read address operand is saved to the queue. After the instruction in the memory reservation stack unit obtains the address, it can calculate the address and decode the address, saving the resulting decoding information to the queue. When the source register of an instruction (such as a write instruction) is ready in the memory reservation stack unit and the address decoding is complete, it can be issued to the memory access unit for execution. Before issuance, a series of checks are performed, such as address type checks, address comparison checks, and address forward checks.

[0327] The rules for storing and reserving stack cells for sending and receiving instructions are as follows: (1) The output of the register renaming unit enters the memory retention stack unit.

[0328] (2) Once the source operand for the calculation address is ready, calculate the memory access address and store it in the memory reservation stack.

[0329] (3) Address-independent instructions: can be out of order. The out-of-order rules are: read instructions after read instructions, write instructions after read instructions, and read instructions after write instructions can all be sent out of order. Write instructions after write instructions need to be ordered (cannot be sent to different memory access units at the same time). Even if the address-independent write instructions are written after write instructions, the order still needs to be maintained.

[0330] (4) Address-related instructions: The order of reading instructions followed by writing instructions, writing instructions followed by reading instructions, writing instructions followed by writing instructions, and reading instructions followed by reading instructions must be guaranteed.

[0331] (5) When addresses are unrelated but are located in the same memory space as all instructions that have not been successfully sent (i.e. instructions on the way that have not been sent to the destination, including those at the memory access unit level and the memory access unit output level), they can be sent out of order to the same memory access unit, but they cannot be sent to two or more memory access units.

[0332] (6) Only one memory access instruction located in the same memory space but with unrelated addresses can be sent at the same time. Two or more memory access instructions cannot be sent at the same time.

[0333] (7) Address correlation judgment principle: whether addresses are related is: if they are located in different storage spaces, they are not related; if they are located in the same storage space, the address correlation is judged based on the data granularity.

[0334] 5. Scalar Operation Unit In a practical implementation, there can be one or more scalar operation units.

[0335] For example, a scalar processor includes two scalar arithmetic units, namely scalar arithmetic unit 0 and scalar arithmetic unit 1.

[0336] The scalar arithmetic unit is used to receive instructions and data sent by the arithmetic storage stack unit, perform operations on the data based on the instructions, and write the operation result back to the register renaming unit.

[0337] The scalar arithmetic unit is the computational unit of the scalar processor. It can perform various types of fixed-point and floating-point operations, such as addition, subtraction, multiplication, division, logical operations, comparison operations, and shifting. It receives instructions and data sent from the arithmetic stack, performs the operations, and writes the results back to the register file of the register renaming unit or the special vector register file.

[0338] The following are some example instructions. In actual implementation, the instructions are not limited to these, nor is it limited to including all of them.

[0339] Instructions at execution level 1 include: fixed-point addition and subtraction, logical instructions, shift instructions, fixed-point and floating-point comparison instructions, read / write Flag instructions, fixed-point and floating-point max / min instructions, ABS instructions, bit reversal instructions, selection instructions, special vector register dispatch instructions, read special vector register instructions, Byte reversal instructions, Merge instructions, immediate assignment instructions, FirstOne instructions, CRC instructions, floating-point classification instructions, floating-point partial field extraction instructions, and Rounding instructions.

[0340] Instructions with an execution level of three include: fixed-point multiplication instructions, fixed-to-floating-point conversion instructions, bit filtering instructions, count instructions, and floating-point addition and subtraction instructions.

[0341] Instructions that support bypass include: selection instructions, fixed-point addition and subtraction instructions, shift instructions, immediate assignment instructions, ABS instructions, logical instructions, comparison instructions, and maximum and minimum instructions.

[0342] The execution cycle of a division instruction is indeterminate and depends on the data of the divisor and dividend. Upon completion, the instruction generates a DivEn instruction, indicating its completion and outputting the result to the register file. No new division instructions can be input during the execution of a division instruction, but other scalar computation unit instructions can be input. The output result of the division is multiplexed with the output port of the first-stage pipeline. When the output port of the first-stage pipeline is not used by other scalar computation unit instructions, the division outputs its result and simultaneously outputs the DivEn flag. This DivEn flag is output to the arithmetic reserve stack, indicating that Div instructions can continue to be output to the current scalar computation unit. 6. Memory access unit In a practical implementation, there can be one or more memory access units.

[0343] For example, a scalar processor includes two memory access units, namely memory access unit 0 and memory access unit 1.

[0344] The memory access unit is used to receive instructions, data, and register information sent by the memory-reserved stack unit, and to read and write the data based on the instructions and register information.

[0345] The memory access unit is a functional module that executes memory access-related instructions in a scalar processor. The memory access unit receives instructions and data, as well as register-related information, from the memory-reserved stack. It executes the instructions accordingly, interacts with other units for data reading and writing, and writes data back to the register renaming unit for read and write instructions. This includes register-level read and write instructions, including 8-bit, 16-bit, 32-bit, 64-bit, or other bit granularities, as well as vector-level read and write instructions. Vector granularities include 128-bit, 256-bit, 512-bit, or other bit granularities. Different instructions have different processing times.

[0346] In addition, the memory access unit is responsible for providing the number of instructions required by the FENCE, and the memory access unit interacts with the memory reservation stack unit to complete the data storage configuration.

[0347] 7. Program Control Unit In practice, there is only one program control unit.

[0348] The program control unit receives instructions and data from the register renaming unit, processes the data based on the instructions, and outputs the processing results.

[0349] The program control unit is a functional module that executes instructions related to the execution order of the scalar processor's control program. The program control unit receives instructions and data from the register renaming unit, processes the data accordingly, and outputs the processing results to other modules of the scalar processor. Different instructions have different processing time cycles.

[0350] The program control unit is responsible for controlling the direction of program execution (such as stopping, interrupting, jumping, and function calling), involving the execution of related instructions and the reading and writing control of configuration information; the program control unit is responsible for the configuration and prefetching operation of the instruction cache, as well as the FENCE operation; the program control unit is responsible for the reading, writing and control of the counter, as well as the reading and writing of some other control information, etc.

[0351] 8. Synchronization Unit In practice, there is only one synchronization unit.

[0352] The synchronization unit is used for synchronizing the scalar processor and the vector processor.

[0353] like Figure 8 As shown, the synchronization unit establishes communication connections with the pipeline control unit, register renaming unit, program control unit, and vector processor.

[0354] The instructions for the synchronization unit come from the register renaming unit, and the reading and writing of data in the synchronization unit are all done in interaction with the register renaming unit.

[0355] The synchronization unit is used to receive the pause signal sent by the pipeline control unit and send the execution-level pause signal generated during communication with the vector processor to the pipeline control unit in order to generate the execution pause signal of the scalar processor.

[0356] The synchronization unit is used to generate instructions and transmit them to the program control unit.

[0357] In other words, the synchronization unit is the unit that synchronizes the scalar processor and the vector processor. It receives instructions and data from the register renaming unit, reads data from the vector processor and writes it back to the register file, and reads data from the register file unit or special vector register file unit and sends it to the vector processor. It is responsible for the startup and status query of the vector processor, such as querying the read and write FIFO (First Input First Output) in the vector program control unit of the vector processor, the configuration of the register file, the read or write of scalar registers, the status query of the register file, reading the FIFO depth, reading the startup vector processor instruction counter, etc., and providing synchronization unit instruction information to the program control unit.

[0358] The synchronization unit interacts with the pipeline control unit, register renaming unit, and program control unit within the scalar processor, as well as with the external vector processor, scalar processor, and vector processor transfer queue module. Synchronization unit instructions originate from the register renaming unit, and data reads and writes require interaction with this unit. It receives blocking signals from the pipeline control unit, generates its own execution-level blocking signal when communicating with the vector processor, and sends it to the pipeline control unit to generate the ExeStall signal affecting the entire scalar processor. The synchronization unit generates the instructions to be executed in the next cycle and transmits them to the program control unit for use by the program control unit's counter instructions. The synchronization unit interacts with the vector processor, including but not limited to: configuring the register file using special vector registers or registers, reading and writing scalar registers, and querying the write status of the register file. The scalar processor interacts with the scalar processor and vector processor transfer queue module, including but not limited to: starting the vector processor, querying the vector processor status, reading and writing FIFO data in the vector processor's instruction fetch unit, reading the FIFO depth, and reading the start vector processor instruction counter.

[0359] Therefore, in a specific implementation, the synchronization unit can have the following functions (it should be noted that the following functions are only examples, and other functions may also be available. This embodiment and subsequent embodiments do not limit the specific functions of the synchronization unit): The Startup Vector Processor function is used to start the vector processor, including immediate start and register start, such as pipeline waiting until the start is successful, or writing the result of the start success or failure back to the destination register.

[0360] The query vector processor execution status function supports option B.

[0361] The read / write FIFO function is located in the instruction fetch unit of the vector processor. For example, the FIFO has a bit width of 32 bits. Reading / writing the FIFO will wait until success, or the result of reading / writing the FIFO will be written back to the register whether it is successful or not.

[0362] Write register file stack functionality, including special vector register write or register write.

[0363] The function allows reading and writing scalar registers, including reading and writing immediate indexes or register indexes.

[0364] The function queries the register file stack write-back status. If necessary, it waits until all writes to the register file stack are complete, or returns the result of whether the write to the register file stack is complete to the register.

[0365] When the relevant operation is not completed, a blocking signal is generated by the synchronization unit itself, and the unit blocks and waits. This signal is then sent to the pipeline control unit to generate a pipeline blocking signal.

[0366] A FIFO (such as a 32-bit deep FIFO) can be added between the scalar processor and the vector processor to store the vector processor start request. The read / write FIFO previously located in the vector processor is moved to the scalar processor and vector processor transfer queue module. The scalar processor and vector processor transfer queue module unit implements the functions of starting the vector processor, querying the vector processor execution status, reading and writing the FIFO, reading the FIFO depth, and reading the start vector processor instruction counter. The conditions for successfully starting the vector processor are that the start vector processor FIFO is not full, and the query of the vector processor execution status is successful. The conditions for the vector processor status to stop are that the vector processor has finished executing and the start vector processor FIFO is empty.

[0367] 9. Production line control unit The pipeline control unit is used to generate a pause signal for the pipeline and / or to generate start and stop signals for the scalar processor.

[0368] The pipeline control unit is the pipeline control unit of the scalar processor. It is connected to various units inside the scalar processor and is responsible for generating pipeline blocking signals, such as blocking in normal operation mode and blocking in debug mode.

[0369] The pipeline control unit also communicates with the communication and synchronization unit to generate signals for starting and stopping the scalar processor.

[0370] In addition, scalar processors can also perform conditional execution decoding in practical applications. For example, when performing conditional execution decoding, a scalar processor checks the preset bits of the instruction to determine the execution condition. If the condition is met, a valid instruction is output; otherwise, a null instruction is output. Here, a null instruction represents an empty instruction or an invalid instruction.

[0371] If a read / write operation is active in the condition register, pipeline blocking is triggered, waiting for the condition register write operation to complete before the read operation can proceed. There is no bypass for condition register reads and writes.

[0372] Taking two condition registers, namely condition register 0 and condition register 1, with the preset bits [29:28] as an example, when the scalar processor performs conditional execution decoding, it judges the execution conditions of the input instruction based on the [29:28] bits of the instruction set encoding. If the conditions are met, a valid instruction is output; otherwise, a null instruction is output.

[0373] In this instruction, bits [29:28] being 00 indicates that condition register 0 is 1 and the instruction is executed; bits [29:28] being 01 indicates that condition register 1 is 1 and the instruction is executed; bits [29:28] being 10 indicates that condition register 0 is 0 and the instruction is executed without conditions; and bits [29:28] being 11 indicates that the instruction is executed without conditions. If the conditions are not met, the instruction is invalid and an empty instruction is output.

[0374] If there is a read / write dependency in the condition register, pipeline blocking is triggered, and the read operation is performed only after the condition register has been written. There is no bypass for condition register read / write operations.

[0375] (ii) Vector Processor This vector processor can be used for Figure 2 or Figure 4 The vector processor shown.

[0376] Specifically, the vector processor includes: a vector program control unit, multiple functional units, a private vector register of the vector interleaving unit, a private vector register of the vector access unit, and registers.

[0377] The registers include: register file stack and scalar registers.

[0378] The vector program control unit is used for instruction fetching and instruction issuance. The vector program control unit interacts with scalar registers.

[0379] Functional units are used to perform functional processing according to instructions.

[0380] The register file is used to receive and return data after read / write requests. The data is rearranged and then returned. It interacts with functional units for read / write operations. The configuration registers of the vector program control unit are configured using data within the register file.

[0381] The vector program control unit is used to retrieve the instruction, determine whether to execute it, and send the instruction to the functional unit based on the determination result.

[0382] The vector program control unit is also used to control instruction jumps.

[0383] The vector program control unit has scalar computation capabilities.

[0384] The functional units include: one or more vector operation units, one or more vector interleaving units, and one or more vector access units.

[0385] Any vector operation unit is used to perform vector operations according to instructions.

[0386] Any vector interleaving unit is used to perform data interleaving and logical processing according to instructions.

[0387] Each vector access unit is used to perform multi-mode memory access, address calculation, and scalar calculation according to instructions.

[0388] Each vector operation unit includes: a floating-point multiply-add subunit, a floating-point multiply-accumulate subunit, a floating-point arithmetic subunit, a tensor multiplication subunit, and an intermediate result register.

[0389] The floating-point multiply-add subunit, floating-point multiply-accumulate subunit, floating-point arithmetic subunit, and tensor multiplication subunit share an intermediate result register.

[0390] The floating-point multiply-add subunit and the floating-point arithmetic subunit share the same slot.

[0391] The floating-point multiplication-accumulation subunit and the tensor multiplication subunit share the same slot.

[0392] The vector processor also includes: a private vector register for the vector interleaving unit and a private vector register for the vector access unit.

[0393] Among them, the private vector register of the vector interleaving unit corresponds one-to-one with the vector interleaving unit.

[0394] The private vector register of a vector access unit is shared by multiple vector access units.

[0395] The register file is also used to write data to other processing units. It receives status information from other processing units, such as whether the data has been written.

[0396] The vector program control unit is also used to receive start commands from other processing processors, start the vector processor, and return an indication signal to other processing processors indicating whether the vector processor has finished.

[0397] The vector processor is connected to other processing processors by a read-first-in-first-out (FIFO) unit and a write-first-out (FIFO) unit.

[0398] The vector program control unit and other arithmetic processors both perform read operations on the read FIFO unit and write operations on the write FIFO unit.

[0399] Other processing units perform read or write operations on the vector register.

[0400] In other words, in the high-performance processor provided in this embodiment, The register file is used to write data to the scalar processor. It receives status information from the scalar processor indicating whether the data has been written.

[0401] The vector program control unit receives the start command from the scalar processor and starts the vector processor. It also returns an indication signal to the scalar processor indicating whether the vector processor has finished.

[0402] A read-first-in-first-out (FIFO) unit and a write-first-out (FIFO) unit are provided between the vector processor and the scalar processor.

[0403] Both the vector program control unit and the scalar processor perform read operations on the read FIFO unit and write operations on the write FIFO unit.

[0404] Scalar processors perform read or write operations on scalar registers.

[0405] The electronic device provided in this embodiment has a computer program executed by a processor so that the instructions can be modified each time they are modified, through the configured instruction configuration file, source operand configuration file, and register configuration file. This allows the instruction configuration to be changed without changing the script, shortening the cycle of each instruction configuration modification and avoiding development cycle delays.

[0406] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0407] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0408] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0409] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0410] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0411] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0412] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0413] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0414] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for generating instruction data packets, characterized in that, The method includes: Obtain processing instructions; The source operands of the processing instructions are determined based on the pre-configured instruction configuration file. Based on the pre-configured source operand configuration file, determine the definition of the source operand and the register corresponding to the source operand; The register definitions are determined based on the pre-configured register configuration file; Based on the definitions of the source operand and the register, the processing instruction, source operand, and register are bound together to generate a data packet that calls the processing instruction; The register is located within the vector processor, and the vector processor further includes: a vector program control unit, multiple functional units, a private vector register of the vector interleaving unit, and a private vector register of the vector access unit. The registers include: register file stack and scalar registers; The vector program control unit is used for instruction fetching and instruction issuing; the vector program control unit interacts with the scalar register. The functional unit is used to perform functional processing according to instructions; The register file stack is used to receive read / write requests and return data; rearrange the data and return it; perform read / write interactions with the functional units; and configure the configuration registers of the vector program control unit using the data in the register file stack. Among them, the private vector register of the vector interleaving unit corresponds one-to-one with the vector interleaving unit; The private vector register of a vector access unit is shared by multiple vector access units.

2. The method according to claim 1, characterized in that, The instruction configuration file includes information about the instructions for each functional unit; The information for any instruction includes: the name of any instruction, the template of any instruction, the fields of any instruction, and the general constraints of any instruction template.

3. The method according to claim 1, characterized in that, The source operand configuration file includes information about the source operands; The information for any source operand includes: the register name corresponding to the source operand, the offset address of the source operand, the number of bits of the source operand, the type of the source operand, the registers involved in the source operand, the associated fields of the source operand, and the general constraints of the source operand.

4. The method according to claim 1, characterized in that, The register configuration file includes information about all shared registers (reg). The information for any register includes: the name of any register, the format for writing to any register, the number of registers in the group to which any register belongs, and the general constraints of any register.

5. The method according to claim 2, characterized in that, The information of any instruction also includes: the constraints of any instruction; The constraints include one or more of the following: the name of the destination register not supported by any instruction; the name of the module not used by any instruction; constraints added when any instruction is used by a module; constraints on the parameters of any instruction; random order constraints; constraints passed by any instruction to the destination register; the number of consecutive lock cycles of the destination register; slot occupancy constraints; add instruction constraints before any instruction; add instruction constraints after any instruction; prohibit add instruction constraints before any instruction; prohibit add instruction constraints after any instruction; write operation time constraints for any instruction; and binding constraints for any instruction.

6. The method according to claim 5, characterized in that, The variables in the data packet satisfy the constraint relationship; The constraint relationship is determined through the following steps: Form a first sequence from all variables in the data packet; A second sequence is formed based on random order constraints; The random order of all variables is obtained based on the first and second sequences, and the random order is determined as a constraint relationship.

7. The method according to claim 1, characterized in that, After generating the data packet for invoking the processing instruction by binding the processing instruction, source operand, and register according to the definitions of the source operand and register, the process further includes: The access data of the data packets to the registers is statistically analyzed using a simulator; The presence of problems with the data packets is determined based on the statistical access data.

8. The method according to claim 1, characterized in that, The acquisition and processing instructions include: Obtain processing instructions based on the input command.

9. A data packet generation apparatus for instructions, characterized in that, The device includes: The acquisition module is used to acquire processing instructions; The first determining module is used to determine the source operands of the processing instruction based on the pre-configured instruction configuration file. The second determining module is used to determine the definition of the source operand and the register corresponding to the source operand based on the pre-configured source operand configuration file. The third determining module is used to determine the definition of the registers based on the pre-configured register configuration file; The generation module is used to bind the processing instruction, source operand, and register according to the definitions of the source operand and register, and generate a data packet that calls the processing instruction; The register is located within the vector processor, and the vector processor further includes: a vector program control unit, multiple functional units, a private vector register of the vector interleaving unit, and a private vector register of the vector access unit. The registers include: register file stack and scalar registers; The vector program control unit is used for instruction fetching and instruction issuing; the vector program control unit interacts with the scalar register. The functional unit is used to perform functional processing according to instructions; The register file stack is used to receive read / write requests and return data; rearrange the data and return it; perform read / write interactions with the functional units; and configure the configuration registers of the vector program control unit using the data in the register file stack. Among them, the private vector register of the vector interleaving unit corresponds one-to-one with the vector interleaving unit; The private vector register of a vector access unit is shared by multiple vector access units.

10. An electronic device, characterized in that, include: Memory; High-performance processor; as well as Computer programs; The high-performance processor includes: a vector processor; The vector processor includes: a vector program control unit, multiple functional units, a private vector register of the vector interleaving unit, a private vector register of the vector access unit, and registers; The registers include: register file stack and scalar registers; The computer program is stored in the memory and configured to be executed by the high-performance processor to implement the method as described in any one of claims 1-8.

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