Chip control method and device, electronic equipment and vehicle

Abstract

The invention relates to the technical field of vehicle control, in particular to a chip control method and device, electronic equipment and a vehicle. The method is applied to a system chip, the system chip is arranged in a controller of a vehicle after being connected with a control chip, and the method specifically comprises the steps that it is determined that an operation mode is entered, and whether the operation duration is larger than or equal to a duration threshold value or not is judged; and in response to the fact that the operation duration is larger than or equal to the duration threshold value, and after the sleep condition is met, a restart request is generated and sent to the control chip, so that the control chip controls the system chip to execute a restart process to clear cache data based on the restart request. In this way, after the running duration is larger than or equal to the duration threshold value, the restart request can be generated and sent to the control chip only after the dormancy condition is met, other functions of the system chip cannot be affected, then the control chip restarts the system chip to achieve clearing of the cached data, and therefore the system chip can be cleared conveniently. And the running speed and the computing power of a system chip are effectively improved.

Description

Technical Field

[0001] This application relates to the field of vehicle control technology, and in particular to a chip control method, device, electronic device, and vehicle. Background Technology

[0002] Currently, system-on-a-chip (SoC) is mainly used to provide computing power support for operation.

[0003] However, during the operation of the system chip, the operating speed may slow down after a period of time. Summary of the Invention

[0004] In view of this, the purpose of this application is to propose a chip control method, device, electronic device and vehicle to solve the technical problem that the operating speed of current system chips slows down after running for a period of time.

[0005] To achieve the above objectives, this application provides a chip control method applied to a system chip, wherein the system chip is connected to a control chip, and both the system chip and the control chip are disposed in the vehicle's controller; The method includes: Once the system is in operation mode, it checks whether the runtime is greater than or equal to the runtime threshold. In response to the runtime being greater than or equal to the duration threshold, it is determined whether the sleep condition is met, and the determination result is obtained; In response to the judgment result that the hibernation condition is met, a restart request is generated and sent to the control chip, so that the control chip can control the system chip to perform a restart process based on the restart request and clear the cached data in the system chip.

[0006] In some embodiments, determining to enter the operating mode includes: After confirming startup, determine whether the reset cause is a cold start; In response to the reset cause being a cold start, the control memory reset flag is set to invalid, and the system enters the running mode; or, If the reset reason is not a cold start, enter the running mode.

[0007] In some embodiments, the response to the reset cause being a cold start, deactivating the control memory reset flag and entering the running mode, includes: In response to the reset reason being a cold start, determine whether the memory reset flag is valid; In response to the storage area reset flag being valid, the power restart flag is set to invalid, and based on the invalid power restart flag, the valid storage area reset flag is set to invalid, entering the running mode; or, In response to the invalidation of the storage area reset flag, the power restart flag is set to valid, while the invalid storage area reset flag remains unchanged, and the system enters the running mode.

[0008] In some embodiments, the step of determining whether a sleep condition is met in response to the runtime being greater than or equal to a duration threshold, and obtaining a determination result, includes: In response to the runtime being greater than or equal to the duration threshold, the storage area reset flag is set to valid; Determine whether the initial hibernation conditions are met; In response to the fulfillment of the initial sleep conditions, determine whether a wake-up source exists; In response to the absence of the wake-up source, the determination result is that the sleep condition is met; or, In response to the presence of the wake-up source, the determination result indicates that the sleep condition is not met.

[0009] In some embodiments, determining whether a wake-up source exists in response to satisfying the initial sleep condition includes: In response to the initial sleep condition being met, it is determined whether the memory area reset flag is valid and whether communication with the control chip is enabled. In response to the storage area reset flag being valid and the communication being open with the control chip, a restart pending request is generated and sent to the control chip; Turn off the power domain control function and check if there is a wake-up source.

[0010] In some embodiments, after determining whether the memory area reset flag is valid and whether communication with the control chip is enabled, the method further includes: In response to the memory area reset flag being invalid, or the communication with the control chip being disconnected, the power domain control function is turned off, and it is determined whether there is a wake-up source.

[0011] In some embodiments, after determining whether the runtime is greater than a duration threshold, the method further includes: In response to the runtime being less than the runtime threshold, the storage area reset flag is set to invalid. Determine whether the initial hibernation conditions are met; In response to the initial sleep conditions being met, the power domain control function is turned off, and it is determined whether there is a wake-up source; In response to the presence of a wake-up source, enter the running mode; or, In response to the absence of the wake-up source, the control system chip enters a sleep state.

[0012] Based on the same inventive concept, this application also provides a chip control device, which is disposed in a system chip, and the system chip is connected to a control chip. Both the system chip and the control chip are disposed in the vehicle's controller. The device includes: The runtime determination module is configured to determine whether to enter the running mode and whether the runtime is greater than or equal to the runtime threshold. The hibernation condition determination module is configured to determine whether the hibernation condition is met in response to the runtime being greater than or equal to a duration threshold, and obtain a determination result. The restart request module is configured to generate a restart request in response to the judgment result that the hibernation condition is met, and send the restart request to the control chip, so that the control chip can control the system chip to perform a restart process based on the restart request and clear the cached data in the system chip.

[0013] Based on the same inventive concept, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the method described above when executing the computer program.

[0014] Based on the same inventive concept, this application also provides a vehicle, including the chip control device as described above, or the electronic device as described above.

[0015] As can be seen from the above, the chip control method, device, electronic device, and vehicle provided in this application have interconnected system chips and control chips in the vehicle controller. Therefore, when the system chip executes, after determining that it has entered the running mode, it will count the running time. If the running time is greater than or equal to the time threshold, it proves that the system chip has been running for a long time and there may be a lot of internal cached data that needs to be cleared. However, if the cached data is cleared directly by restarting during the system chip's operation, it may cause the system chip to malfunction and affect the control of the vehicle. Therefore, the system chip will determine whether the sleep condition is met. Only when the sleep condition is met will a restart request be generated and sent to the control chip, which will then restart the system chip. In this way, the system chip can clear the cached data by restarting. Moreover, the restart process is performed during the sleep period and will not affect other functions of the system chip, thus achieving a seamless restart of the system chip. After the system chip restarts, the cached data is cleared, which effectively improves its running speed and computing power. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a diagram illustrating a specific application scenario of the chip control method according to an embodiment of this application. Figure 2 This is a flowchart of a chip control method according to an embodiment of this application; Figure 3 This is a schematic diagram of the system chip and control chip in an embodiment of this application; Figure 4 This is a flowchart of a chip control method according to another embodiment of this application; Figure 5 This is a structural block diagram of the chip control device according to an embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0019] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0020] ZCU: Zone Control Unit, vehicle body domain controller.

[0021] VCU: Vehicle Control Unit.

[0022] SOC: System on Chip, also known as a system-on-a-chip, provides computing power support.

[0023] MCU: Motor Control Unit, a control chip responsible for I / O (Input, Output, input and output pins) expansion.

[0024] PMIC: Power Management IC.

[0025] SPI: Serial Peripheral Interface.

[0026] QUC: Quiescent Voltage Control.

[0027] PWRON: Indicates functions related to power on or power status.

[0028] In related technologies, with the development of intelligent driving, the computing power requirements of vehicle controllers are getting higher and higher. Therefore, vehicle controllers (e.g., body domain controller ZCU) are generally equipped with at least two main chips, including: a system chip (e.g., SOC) that provides computing power support and a control chip (e.g., MCU) that provides IO expansion.

[0029] If a system chip runs for a long time, it will generate a large number of cache files, which will affect the workload of the system chip and may reduce the overall operating speed or even cause lag. However, for the vehicle controller, if the operating speed is reduced or lag occurs, it may affect driving safety.

[0030] Therefore, how to clean up the large number of cache files generated without affecting the normal function of the vehicle's controller has become an urgent technical problem to be solved.

[0031] refer to Figure 1 This is a schematic diagram illustrating an application scenario of the chip control method provided in this application embodiment. The application scenario includes a system chip 101 and a control chip 102 disposed in the vehicle's controller 100. The system chip 101 includes a System-on-a-Chip (SOC) chip, and the control chip 102 includes a Microcontroller Unit (MCU) chip.

[0032] After the system chip 101 determines that it has entered the running mode, it will time the runtime and check if the runtime is greater than or equal to a duration threshold. If it is greater than or equal to the duration threshold, it indicates that there is a large amount of cached data inside the system chip 101, which needs to be cleared by restarting. However, to ensure the normal operation of the system chip 101, a restart will not be performed. First, it will check if the system chip 101 meets the sleep conditions. If the sleep conditions are met, and the system chip 101 is confirmed to be in sleep mode, a restart request will be generated and sent to the control chip 102. The control chip 102 will then control the system chip 101 to perform the restart process. In this way, the system chip 101 can clear the internal cached data after restarting. This prevents excessive cached data in the system chip 101 from affecting its operation.

[0033] Based on the above, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0034] The chip control method proposed in the embodiments of this application is applied to a system chip (e.g., a SOC), which is connected to a control chip (e.g., an MCU) (e.g., the system chip and the control chip are connected via SPI), and both the system chip and the control chip are located in the vehicle's controller.

[0035] The vehicle controller also includes a first power control unit (e.g., PMIC) for power management of the system chip. The first power control unit is connected to the power supply terminal and also to the control chip. In this way, the first power control unit manages the power supply, power-off, or restart of the system chip. In addition, the control chip can also control the first power control unit to power supply, power-off, or restart the system chip.

[0036] The vehicle controller also includes a second power control unit (e.g., PMIC), which is connected to the power supply terminal and is used to manage the power supply of the control chip. For example, the second power control unit manages the power supply of the control chip through QUC instructions.

[0037] like Figure 2 As shown, the method includes: Step 201: Determine whether to enter the running mode and check whether the running time is greater than or equal to the duration threshold.

[0038] In practice, the operating mode is the mode in which the system chip normally provides computing power support, such as during driving, parking and waiting, or parking and entertainment.

[0039] When the system chip is in running mode, it will keep track of the runtime. If the system chip is in sleep or other non-running mode during the runtime time, the runtime will stop. And unless the runtime is reset to zero, the runtime will continue to accumulate.

[0040] When the system chip is in operation mode, it will periodically check the runtime to determine whether it is greater than or equal to a duration threshold. "Periodically" can refer to a set period or a set time point.

[0041] Step 202: In response to the runtime being greater than or equal to the duration threshold, determine whether the sleep condition is met and obtain the determination result.

[0042] In practice, if the runtime is greater than or equal to the runtime threshold, it indicates that the system chip has been running for a long time and may have a large amount of internal cached data, requiring the cached data to be cleared. Since the system chip has a function to clear cached data via reboot (e.g., cold start), this function can be fully utilized to complete the cache clearing process. However, clearing cached data via reboot cannot be used during runtime. Therefore, it is necessary to determine whether the current state data of the system chip meets the hibernation conditions to decide whether to execute the reboot to clear cached data.

[0043] Step 203: In response to the judgment result that the hibernation condition is met, a restart request is generated and sent to the control chip, so that the control chip can control the system chip to perform a restart process based on the restart request and clear the cached data in the system chip.

[0044] In practice, a restart request is only generated and sent to the control chip after the judgment result meets the hibernation conditions and the system chip is determined to enter hibernation mode. Upon receiving the restart request, the control chip controls the system chip's first power control unit (e.g., PMIC) to stop supplying power to the system chip, causing it to power down. During this shutdown, the system chip clears its cached data. After a predetermined delay (e.g., 1s, 1.1s, or 1.2s, preferably 1s, which can be set according to actual needs), the first power control unit resumes powering the system chip, restarting it and allowing it to re-enter hibernation mode. Subsequently, upon detecting a wake-up source, the system chip can re-enter the running state and repeat steps 201 to 203.

[0045] For example, if the power-off control signal corresponding to the first power control unit is low, the control chip will send a low-level signal and maintain it for a predetermined delay to allow the system chip to be completely shut down after power failure. Then, it will send a high-level signal to the first power control unit to allow the first power control unit to resume its power supply function to the system chip, thereby allowing the system chip to complete the restart process.

[0046] Furthermore, after the system chip restarts, it will determine the working state corresponding to the last shutdown. If it is in hibernation state, it will directly enter hibernation state after restarting and wait for the wake-up source to appear before entering the running mode.

[0047] The restart request is a hard restart request, which involves restarting the system chip by powering off and then powering on again, so that the system chip can complete the cold start process and clear the internal cache data through the cold start.

[0048] Because a cold start requires powering off the system chip, the system chip cannot control this process on its own. Therefore, the hard reboot request needs to be sent to the control chip so that the control chip can control the first power control unit to achieve the cold start process of the system chip by powering off and then powering on the system chip.

[0049] The above scheme works by tracking the runtime of the system chip after it enters the operating mode. If the runtime is greater than or equal to a threshold, it indicates that the system chip has been running for a long time and may have a lot of internal cached data that needs to be cleared. However, if the cached data is cleared directly by restarting the system chip during operation, it may cause the system chip to malfunction and affect vehicle control. Therefore, the system chip will determine whether the sleep conditions are met. Only if the sleep conditions are met will a restart request be generated and sent to the control chip, which will then restart the system chip. In this way, the system chip can clear the cached data through restarting. Moreover, the restart process is performed during the sleep period and will not affect other functions of the system chip, achieving a seamless restart of the system chip. Because the cached data is cleared after the system chip restarts, its operating speed and computing power are effectively improved.

[0050] In some embodiments, determining to enter the operating mode in step 201 includes: Step 2011: After confirming the startup, determine whether the reset reason is a cold start.

[0051] In practice, the cold start is a restart performed by cutting off the power supply, which clears the cached data in the system chip.

[0052] After the system chip receives the startup signal, it executes the startup process. After startup is completed, it is necessary to determine the reason for the startup reset and whether it is a cold start.

[0053] Step 2012: In response to the reset reason being a cold start, the control storage area reset flag is set to invalid, and the system enters the running mode.

[0054] In practice, the storage area reset flag (e.g., NVM_ResetFlag) indicates whether the cached data in the storage area needs to be reset and cleared. A valid storage area reset flag indicates that the cached data in the storage area needs to be cleared; an invalid storage area reset flag indicates that the cached data in the storage area does not need to be cleared.

[0055] Therefore, after determining that the reset was caused by a cold start, which could be due to a power outage and subsequent restart of the vehicle, or it could be due to a large amount of cached data in the system chip causing a re-cold start. If the re-cold start was due to a large amount of cached data in the system chip, the corresponding memory reset flag might still be valid. To prevent another re-cold start from being triggered and the cached data from being cleared again, the memory reset flag will be set to invalid.

[0056] Then, after determining that the memory reset flag is invalid, the system chip enters the normal operating mode.

[0057] Alternatively, in step 2013, in response to the reset reason not being a cold start, the system enters the running mode.

[0058] In practice, if the reset reason is not a cold start, then the reset reason may be a warm start. A warm start is the process of controlling the system chip to restart under the premise that the system chip is normally powered on, and the power supply will not be cut off during the entire warm start process.

[0059] If the reset reason is not a cold start, it proves that this startup is not a cold start caused by a large amount of cached data in the system chip. At this time, the corresponding memory reset flag should be in an invalid state and no processing is required. The system chip can directly enter the running mode.

[0060] By analyzing the reset cause of this startup, the system promptly identifies the restart process caused by a cold start and sets the corresponding storage area reset flag to invalid. This prevents the storage area reset flag from being valid after entering the running mode, which could affect the normal operation of the running mode and ensure its smooth execution.

[0061] In some embodiments, step 2012 includes: Step 20121: In response to the reset reason being a cold start, determine whether the storage area reset flag is valid.

[0062] In practice, if the reset reason after startup is a cold start, it will determine whether the memory reset flag is valid. If it is, it proves that the cold start is caused by the system chip clearing the internal cache data by resetting the flag based on the valid memory area after the running time reaches the duration threshold. Otherwise, it may be a normal cold start performed by powering off and then powering on the system chip.

[0063] Step 20122: In response to the storage area reset flag being valid, the power restart flag is set to invalid. Based on the invalid power restart flag, the valid storage area reset flag is set to invalid, and the system enters the running mode.

[0064] In practice, the power-on reset flag (e.g., PowOnResetFlag) is a status flag stored within the system chip, used to indicate the specific reason for the most recent system chip reset or restart. This power-on reset flag can be used to reset the memory reset flag.

[0065] If the storage area flag is valid, it needs to be reset. First, invalidate the power reset flag (e.g., PowOnResetFlag=0). This invalid power reset flag will invalidate the storage area reset flag. This achieves the purpose of resetting the valid storage area reset flag, avoiding unnecessary impact on subsequent operating modes.

[0066] Alternatively, in step 20123, in response to the invalidation of the storage area reset flag, the power restart flag is set to valid, while the invalid storage area reset flag remains unchanged, and the system enters the running mode.

[0067] In practice, if the storage area reset flag is invalid, the power restart flag will remain valid and the storage area reset flag will remain invalid, and then the system can directly enter the running mode.

[0068] Furthermore, after entering the running mode, the running time will be accumulated based on the running time before the restart, and subsequent steps 202 and 203 will be executed so that the system chip can be restarted in a timely manner through the control chip to clear the cached data in the system chip.

[0069] The above scheme enables the timely invalidation of valid memory reset flags based on the power restart flag after determining that the reset cause is a cold start. Memory reset flags that are already invalid will not be processed, ensuring that the cold start will not be affected by the valid memory reset flags and that the running mode can be executed smoothly.

[0070] In some embodiments, step 202 includes: Step 2021: In response to the runtime being greater than or equal to the duration threshold, the storage area reset flag is set to valid.

[0071] In practice, if the accumulated runtime is greater than or equal to the runtime threshold, it indicates that the cached data in the system chip needs to be cleared. At this time, the memory reset flag will be set to valid. This valid memory reset flag indicates that the system chip is currently in a pending state where cached data can be cleared by restarting.

[0072] However, in order to ensure the normal operation of the functions being executed in the system chip's operating mode, a direct restart cannot be performed; a subsequent process of determining whether the hibernation conditions are met is required.

[0073] Step 2022: Determine whether the initial hibernation conditions are met.

[0074] In practice, the initial sleep condition is that, apart from some basic functions that need to be executed even in sleep mode, all other operating functions that require computing power support in the system chip are in a stopped state.

[0075] If the initial hibernation conditions are met, it means the system chip can enter hibernation mode; if the initial hibernation conditions are not met, it means the system chip cannot enter hibernation mode and will continue to operate in the operating mode.

[0076] Step 2023: In response to the initial sleep condition being met, determine whether there is a wake-up source.

[0077] In practice, the wake-up source is a function and / or request that wakes the system chip from sleep mode and into running mode. The wake-up source includes at least one of the following: a wake-up signal from hard-wired feedback, a wake-up signal from network feedback, and a wake-up signal from the end of a timer interval.

[0078] The wake-up signal provided by the hard wire feedback includes at least one of the following: a wake-up signal for starting the engine after the key is inserted, a signal for the passive keyless entry and start system, a trunk / tailgate opening switch signal, and an engine hood opening switch signal, etc.

[0079] The wake-up signal from the network feedback includes at least one of the following: local network management wake-up signal, message wake-up signal, and Power over Ethernet wake-up signal.

[0080] Step 2024: In response to the absence of the wake-up source, determine that the judgment result satisfies the sleep condition.

[0081] Alternatively, in step 2025, in response to the presence of the wake-up source, the determination result is that the sleep condition is not met.

[0082] In practice, if there is no wake-up source, it means that the system chip meets the sleep conditions and can directly enter the sleep state; if there is a wake-up source, it means that the system chip needs to be woken up, so it will end the initial sleep and enter the running mode, and execute the function corresponding to the wake-up source.

[0083] The above scheme enables the memory reset flag to be active when the runtime is greater than or equal to the runtime threshold. This allows the system chip to know that a restart and cache data clearing operation is required. Under the premise that the initial sleep conditions are met and there is no wake-up source, the system chip can be determined to meet the sleep conditions and enter a sleep state. Then, the control chip can be used to control the system chip to perform the restart and cache data clearing process in a timely manner, thereby ensuring the operating speed of the system chip.

[0084] As a preferred embodiment, when the system chip meets the sleep conditions and enters the final sleep state, it is also necessary to determine the duration of the sleep state to avoid accidentally entering the sleep state. After determining the duration of the sleep state, a restart request is sent to the control chip.

[0085] In some embodiments, step 2023 includes: Step 20231: In response to meeting the initial hibernation conditions, determine whether the memory area reset flag is valid and whether it is in the communication open state with the control chip.

[0086] In practice, this "communication open" state indicates that the communication path between the system chip and the control chip is open, enabling normal data communication.

[0087] If the initial hibernation conditions are met, it means that the system chip can enter hibernation mode. However, it cannot fully enter hibernation mode at this time. It is necessary to reset the memory area flag and determine the communication status with the control chip.

[0088] The system checks whether the memory reset flag is valid and whether the system chip and control chip are in an open communication state. This validity of the memory reset flag and the open communication state between the system chip and control chip are essential prerequisites for sending a restart request.

[0089] Step 20232: In response to the storage area reset flag being valid and the communication being open with the control chip, a restart pending request is generated and sent to the control chip.

[0090] In practice, if the conditions for sending a restart request are met, it proves that a restart is required and that the restart request sending condition has been met, indicating that the restart request stage has begun. Even if both conditions are met, the restart request cannot be sent directly; a restart pending request must first be generated and sent to the control chip. Upon receiving the restart pending request, the control chip will enter a restart control waiting state. This restart control waiting state is characterized by the control chip generating the corresponding restart control signal and waiting to send it.

[0091] Step 20233: Turn off the power domain control function and determine if there is a wake-up source.

[0092] In practice, because the system needs to enter a sleep state and the power domain control function consumes a significant amount of computing resources, the power domain control function will be disabled. However, to further ensure that the sleep state is not interfered with by other wake-up sources, a process to determine whether a wake-up source exists is also required.

[0093] If no wake-up source exists, it proves that the system chip meets the hibernation conditions and can directly enter hibernation mode. Then, a restart request is generated and sent to the control chip. After receiving the restart request, the control chip will control the first power control unit (e.g., PMIC) of the system chip to stop supplying power to the system chip, causing the system chip to power down. When the system chip powers down, it will clear the cached data. After a predetermined delay, the first power control unit will then supply power to the system chip, causing the system chip to restart.

[0094] If a wake-up source exists, it means that the system chip needs to be woken up. It will then end its initial sleep mode, enter the running mode, and execute the function corresponding to the wake-up source.

[0095] The above scheme ensures that the system meets the hibernation conditions only when the three conditions are met: the memory reset flag is valid, communication with the control chip is open, and there is no wake-up source. This allows the system chip to restart, further ensuring that the system chip restart process will not affect the normal operation of the system chip.

[0096] In some embodiments, after step 20231, the method further includes: Step 20234: In response to the memory area reset flag being invalid, or the communication with the control chip being disconnected, the power domain control function is turned off, and it is determined whether there is a wake-up source.

[0097] In practice, if the memory reset flag is invalid, or communication with the control chip is disconnected, it means the conditions for the system chip to request a restart are not met, but the conditions for the system chip to enter hibernation mode are met. Therefore, the power domain control function will be turned off, and before entering hibernation mode, it will again check if there is a wake-up source. If there is no wake-up source, it means that hibernation mode can be entered directly; if there is a wake-up source, the system chip will be woken up and enter the running mode.

[0098] By using the above method, when it is determined that the memory reset flag is invalid or that the communication with the control chip is disconnected, and the conditions for the system chip to request a restart are not met, the power domain control function is turned off. After a second check to see if there is a wake-up source, and after ensuring that there is no wake-up source, the system enters a normal sleep state, thereby ensuring the accuracy of entering the sleep state and avoiding other situations that may interfere with the entry into the sleep state.

[0099] In some embodiments, after step 201, the method further includes: Step A1: In response to the runtime being less than the runtime threshold, the storage area reset flag is set to invalid.

[0100] In practice, if the runtime is less than the runtime threshold, it means that the conditions for clearing cached data are not met. If the storage area reset flag is valid at this time, the storage area reset flag will be set to invalid; otherwise, it will remain unchanged. This ensures the accuracy of the storage area reset flag.

[0101] Step A2: Determine whether the initial hibernation conditions are met.

[0102] In practice, if the memory reset flag is invalid, the system chip will also be checked to determine whether it meets the initial hibernation conditions and whether it needs to enter hibernation mode.

[0103] The initial sleep condition is that, apart from some basic functions that need to be executed even during sleep, all other functions that require computing power to run in the system chip are in a stopped state.

[0104] Step A3: In response to the initial sleep condition being met, the power domain control function is turned off, and it is determined whether there is a wake-up source.

[0105] In practice, if the initial hibernation conditions are met, the power domain control function will be turned off in order to ensure that the system can enter hibernation smoothly and quickly in the future, and the system will also determine whether there is a wake-up source.

[0106] The wake-up source is the function and / or request that wakes up the system chip from sleep mode and puts it into running mode.

[0107] Step A4: In response to the presence of a wake-up source, enter the running mode.

[0108] Alternatively, in step A5, in response to the absence of the wake-up source, the system chip enters a sleep state.

[0109] In practice, if a wake-up source exists, it means the system chip cannot enter sleep mode and will re-enter operating mode. If no wake-up source exists, it means the system chip can enter sleep mode, and will shut down some operating functions other than basic functions, thus officially entering sleep mode.

[0110] In addition, once the system officially enters hibernation mode, the runtime will stop counting down.

[0111] The above solution ensures that the system chip can accurately and smoothly enter sleep mode when the runtime is less than the time threshold, thereby reducing the system chip's power consumption.

[0112] The chip control method of this application, which is applied to a system chip, is described below with a specific embodiment.

[0113] like Figure 3 As shown, the controller (e.g., the power domain controller ZCU) includes a system chip (e.g., a SOC, which may be an S32G) and a control chip (e.g., an MCU, which may be a TC377). The system chip and the control chip are connected (e.g., the system chip and the control chip are connected via SPI). Both the system chip and the control chip are located in the vehicle's controller.

[0114] The vehicle controller also includes a first power control unit (e.g., PMIC) for power management of the system chip (e.g., providing 12V power). The first power control unit is connected to the power supply terminal and also to the control chip. In this way, the first power control unit manages the power supply, power-off, or restart of the system chip. In addition, the control chip can also control the first power control unit to power supply, power-off, or restart the system chip.

[0115] The vehicle controller also includes a second power control unit (e.g., PMIC), which is connected to the power supply terminal and is used to manage the power supply of the control chip (e.g., to provide 12V power). For example, the second power control unit manages the power supply of the control chip through QUC instructions.

[0116] The control chip can control the power supply of the first power control unit through the PWRON instruction, thereby controlling the power supply of the system chip (i.e., disconnecting, shutting down, or restarting (e.g., cold start)).

[0117] like Figure 4 The flowchart shown illustrates how the system chip executes chip control methods. The specific process is as follows: S1, Startup, specifically initiated by a startup signal or a power supply signal. This triggers the startup process, which then reads the reset reason.

[0118] S2, determine whether the reset reason is a cold start. If yes, proceed to step S3; otherwise, proceed to step S6.

[0119] If the reset reason is not a cold start, it proves that this startup is not a cold start caused by a large amount of cached data in the system chip. At this time, the corresponding memory reset flag should be in an invalid state and no processing is required. The system chip can directly enter the S6 running mode.

[0120] S3. Determine whether the storage area reset flag bit (e.g., NVM_RestFlag) is valid (e.g., determine whether NVM_RestFlag=1). If yes, proceed to step S4; otherwise, proceed to step S5.

[0121] Among them, the storage area is a non-volatile storage area. If the reset flag of this storage area is valid, it means that the cached data in the storage area needs to be cleared. If the reset flag of this storage area is invalid, it means that the cached data in the storage area does not need to be cleared.

[0122] S4. Invalidate the power-on reset flag (e.g., PowOnResetFlag) (e.g., PowOnResetFlag=0) to invalidate the memory reset flag (e.g., NVM_RestFlag=0), thus preventing the valid memory reset flag from affecting the normal execution of subsequent operating modes. An invalid power-on reset flag will invalidate the memory reset flag. This achieves the purpose of resetting the valid memory reset flag, preventing it from unnecessarily affecting subsequent operating modes.

[0123] The power reset flag (e.g., PowOnResetFlag) is a status flag stored within the system chip, used to indicate the specific reason for the most recent system chip reset or restart. This power reset flag can be used to reset the memory reset flag.

[0124] S5, set the power reset flag (e.g., PowOnResetFlag) to active (e.g., PowOnResetFlag=1) so that the storage reset flag (e.g., NVM_RestFlag) remains inactive.

[0125] S6, enter running mode.

[0126] S7. Determine if the runtime is greater than or equal to the runtime threshold. If yes, proceed to step S8; otherwise, proceed to step S9. The system chip periodically checks the runtime when in running mode.

[0127] S8, reset the storage area reset flag position to valid (e.g., NVM_RestFlag=1) and then proceed to step S10.

[0128] S9, set the storage area reset flag position to invalid (e.g., NVM_RestFlag=0), and then proceed to step S10.

[0129] S10: Determine whether the initial sleep conditions are met. If yes, proceed to S11; otherwise, return to step S6.

[0130] If the initial hibernation conditions are met, it means that the system chip can enter hibernation mode. However, it cannot fully enter hibernation mode at this time. It is necessary to reset the memory area flag and determine the communication status with the control chip.

[0131] S11. Determine whether the memory reset flag bit is valid (e.g., NVM_RestFlag=1) and whether the communication with the control chip is open (e.g., BD4SlpSts = FULLCOM). If yes, proceed to step S12; otherwise, proceed to step S16.

[0132] S12 generates a restart pending request and sends it to the control chip.

[0133] After receiving a restart pending request, the control chip will enter a state of generating the corresponding restart control signal and waiting to send it.

[0134] S13, disable the power domain control function (e.g., turn off PNC PRCANFD). The power domain control function consumes a lot of computing resources, so it will be disabled.

[0135] S14. Determine if a wake-up source exists. If yes, return to step S6; otherwise, proceed to step S15.

[0136] S15 generates a restart request and sends it to the control chip, allowing the control chip to perform a hard restart process through the first power control unit. This involves shutting down the control chip by cutting off the power supply and then performing a cold start by connecting the power supply.

[0137] If there is no wake-up source, it proves that the system chip meets the hibernation conditions and can directly enter the hibernation state. Then, a restart request is generated and sent to the control chip.

[0138] Then, after receiving the restart request, the control chip will control the system chip to perform a hard restart. That is, the control chip sends a low-level signal to the first power control unit (e.g., PMIC) and holds it for a predetermined time (e.g., 1 second), controlling the first power control unit (e.g., PMIC) to stop supplying power to the system chip, causing the system chip to power down. When the system chip powers down, it will clear the cached data. After a predetermined delay (e.g., 1 second, 1.1 second, or 1.2 seconds, preferably 1 second, which can be set according to actual needs), it sends a high-level signal to the first power control unit again, causing the first power control unit to supply power to the system chip, allowing the system chip to restart and re-enter the sleep state.

[0139] S16, disable the power domain control function (e.g., turn off PNC PRCANFD).

[0140] S17. Determine if a wake-up source exists. If yes, return to step S6; otherwise, proceed to step S18.

[0141] S18, enters hibernation mode.

[0142] The above steps S16 to S18 are normal hibernation processes to ensure that the system chip can perform a hard reboot while also performing a normal hibernation process.

[0143] It should be noted that the method in this embodiment can be executed by a single device, such as a computer or server. The method can also be applied in a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method in this embodiment, and the multiple devices will interact with each other to complete the method described.

[0144] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0145] Based on the same inventive concept, corresponding to any of the above embodiments, this application also provides a chip control device, which is disposed in a system chip, the system chip is connected to a control chip, and both the system chip and the control chip are disposed in the vehicle controller.

[0146] refer to Figure 5 The device includes: The runtime judgment module 301 is configured to determine whether to enter the running mode and whether the runtime is greater than or equal to the runtime threshold. The hibernation condition judgment module 302 is configured to determine whether the hibernation condition is met in response to the runtime being greater than or equal to the runtime threshold, and obtain a judgment result. The restart request module 303 is configured to generate a restart request in response to the judgment result that the sleep condition is met, and send the restart request to the control chip so that the control chip can control the system chip to perform a restart process based on the restart request and clear the cached data in the system chip.

[0147] In some embodiments, the runtime determination module 301 is specifically configured as follows: After confirming startup, determine whether the reset cause is a cold start; In response to the reset cause being a cold start, the control memory reset flag is set to invalid, and the system enters the running mode; or, If the reset reason is not a cold start, enter the running mode.

[0148] In some embodiments, the runtime determination module 301 is specifically configured as follows: In response to the reset reason being a cold start, determine whether the memory reset flag is valid; In response to the storage area reset flag being valid, the power restart flag is set to invalid, and based on the invalid power restart flag, the valid storage area reset flag is set to invalid, entering the running mode; or, In response to the invalidation of the storage area reset flag, the power restart flag is set to valid, while the invalid storage area reset flag remains unchanged, and the system enters the running mode.

[0149] In some embodiments, the hibernation condition determination module 302 is specifically configured as follows: In response to the runtime being greater than or equal to the duration threshold, the storage area reset flag is set to valid; Determine whether the initial hibernation conditions are met; In response to the fulfillment of the initial sleep conditions, determine whether a wake-up source exists; In response to the absence of the wake-up source, the determination result is that the sleep condition is met; or, In response to the presence of the wake-up source, the determination result indicates that the sleep condition is not met.

[0150] In some embodiments, the hibernation condition determination module 302 is further configured to: In response to the initial sleep condition being met, it is determined whether the memory area reset flag is valid and whether communication with the control chip is enabled. In response to the storage area reset flag being valid and the communication being open with the control chip, a restart pending request is generated and sent to the control chip; Turn off the power domain control function and check if there is a wake-up source.

[0151] In some embodiments, the device further includes a sleep module configured to: After determining whether the storage area reset flag is valid and whether communication with the control chip is open, in response to the storage area reset flag being invalid or communication with the control chip being disconnected, the power domain control function is turned off, and it is determined whether there is a wake-up source.

[0152] In some embodiments, the hibernation module is specifically configured as follows: After determining whether the runtime is greater than the runtime threshold, in response to the runtime being less than the runtime threshold, the storage area reset flag is set to invalid. Determine whether the initial hibernation conditions are met; In response to the initial sleep conditions being met, the power domain control function is turned off, and it is determined whether there is a wake-up source; In response to the presence of a wake-up source, enter the running mode; or, In response to the absence of the wake-up source, the control system chip enters a sleep state.

[0153] For ease of description, the above devices are described in terms of function, divided into various modules. Of course, in implementing this application, the functions of each module can be implemented in one or more software and / or hardware.

[0154] The apparatus of the above embodiments is used to implement the corresponding method in any of the foregoing embodiments and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0155] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the methods described in any of the above embodiments.

[0156] Figure 6 This embodiment illustrates a more specific hardware structure of an electronic device. The device may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0157] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0158] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0159] The input / output interface 1030 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.

[0160] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0161] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0162] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0163] The electronic devices described above are used to implement the corresponding methods in any of the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0164] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a non-transitory computer-readable storage medium that stores computer instructions for causing the computer to perform the methods described in any of the above embodiments.

[0165] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random-access memory (SRAM), dynamic random-access memory (DRAM), other types of random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital video disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0166] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to perform the methods described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0167] Based on the same concept, corresponding to any of the above embodiments, this application also provides a computer program product, including computer program instructions, which, when run on a computer, cause the computer to perform the method described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0168] Based on the same inventive concept, this application also provides a vehicle including the device or electronic device described in the above embodiments. The beneficial effects of embodiments having corresponding devices or electronic devices will not be elaborated further here.

[0169] It is understood that before using the technical solutions of the various embodiments in this application, users will be informed of the type, scope of use, and usage scenarios of the personal information involved in an appropriate manner, and user authorization will be obtained.

[0170] For example, upon receiving a user's active request, a prompt message is sent to the user to explicitly inform them that the requested operation will require the acquisition and use of the user's personal information. This allows the user to independently choose, based on the prompt message, whether to provide personal information to the software or hardware such as electronic devices, applications, servers, or storage media performing the operations described in this application.

[0171] As an optional but not limited implementation, in response to a user's active request, sending a prompt message to the user can be done via a pop-up window, where the prompt message can be presented in text format. Furthermore, the pop-up window can also include a selection control allowing the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0172] It is understood that the above notification and user authorization process is merely illustrative and does not limit the implementation of this application. Other methods that comply with relevant laws and regulations may also be applied to the implementation of this application.

[0173] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0174] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0175] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0176] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A chip control method, characterized in that, It is applied to a system chip, which is connected to a control chip, and both the system chip and the control chip are located in the vehicle's controller; The method includes: Once the system is in operation mode, it checks whether the runtime is greater than or equal to the runtime threshold. In response to the runtime being greater than or equal to the duration threshold, it is determined whether the sleep condition is met, and the determination result is obtained; In response to the judgment result that the hibernation condition is met, a restart request is generated and sent to the control chip, so that the control chip can control the system chip to perform a restart process based on the restart request and clear the cached data in the system chip.

2. The method according to claim 1, characterized in that, The process of determining to enter the operating mode includes: After confirming startup, determine whether the reset cause is a cold start; In response to the reset cause being a cold start, the control memory reset flag is set to invalid, and the system enters the running mode; or, If the reset reason is not a cold start, enter the running mode.

3. The method according to claim 2, characterized in that, The response to the reset reason being a cold start, setting the control storage reset flag to invalid, and entering the running mode includes: In response to the reset reason being a cold start, determine whether the memory reset flag is valid; In response to the storage area reset flag being valid, the power restart flag is set to invalid, and based on the invalid power restart flag, the valid storage area reset flag is set to invalid, entering the running mode; or, In response to the invalidation of the storage area reset flag, the power restart flag is set to valid, while the invalid storage area reset flag remains unchanged, and the system enters the running mode.

4. The method according to claim 1, characterized in that, The response to the runtime being greater than or equal to a duration threshold determines whether the sleep condition is met, and obtains a determination result, including: In response to the runtime being greater than or equal to the duration threshold, the storage area reset flag is set to valid; Determine whether the initial hibernation conditions are met; In response to the fulfillment of the initial sleep conditions, determine whether a wake-up source exists; In response to the absence of the wake-up source, the determination result is that the sleep condition is met; or, In response to the presence of the wake-up source, the determination result indicates that the sleep condition is not met.

5. The method according to claim 4, characterized in that, The step of determining whether a wake-up source exists in response to the initial sleep condition being met includes: In response to the initial sleep condition being met, it is determined whether the memory area reset flag is valid and whether communication with the control chip is enabled. In response to the storage area reset flag being valid and the communication being open with the control chip, a restart pending request is generated and sent to the control chip; Turn off the power domain control function and check if there is a wake-up source.

6. The method according to claim 5, characterized in that, After determining whether the memory area reset flag is valid and whether communication with the control chip is enabled, the method further includes: In response to the memory area reset flag being invalid, or the communication with the control chip being disconnected, the power domain control function is turned off, and it is determined whether there is a wake-up source.

7. The method according to claim 1, characterized in that, After determining whether the runtime exceeds the runtime threshold, the process further includes: In response to the runtime being less than the runtime threshold, the storage area reset flag is set to invalid. Determine whether the initial hibernation conditions are met; In response to the initial sleep conditions being met, the power domain control function is turned off, and it is determined whether there is a wake-up source; In response to the presence of a wake-up source, enter the running mode; or, In response to the absence of the wake-up source, the control system chip enters a sleep state.

8. A chip control device, characterized in that, The device is installed in the system chip, which is connected to the control chip. Both the system chip and the control chip are installed in the vehicle's controller. The device includes: The runtime determination module is configured to determine whether to enter the running mode and whether the runtime is greater than or equal to the runtime threshold. The hibernation condition determination module is configured to determine whether the hibernation condition is met in response to the runtime being greater than or equal to a duration threshold, and obtain a determination result. The restart request module is configured to generate a restart request in response to the judgment result that the hibernation condition is met, and send the restart request to the control chip, so that the control chip can control the system chip to perform a restart process based on the restart request and clear the cached data in the system chip.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1 to 7.

10. A vehicle, characterized in that, This includes the chip control device as described in claim 8, or the electronic device as described in claim 9.

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