Built-in self-test circuit supporting error information output

Abstract

The invention discloses a built-in self-test circuit supporting error information output, which comprises a BIST state machine, the output end of the BIST state machine is connected with an MEM control signal generation logic module and an ADDR signal generation logic module, the ADDR signal generation logic module is connected with a WDATA signal generation logic module, the WDATA signal generation logic module is connected with a result comparison module, and the result comparison module is connected with an error information output module. The result comparison module is connected with the BIST state and is connected with the error printing mechanism module, and the MEM control signal generation logic module, the ADDR signal generation logic module, the WDATA signal generation logic module and the result comparison module are all connected with the memory. According to the method, the error flag bit and the serial port output mechanism are cooperatively optimized, so that the efficient real-time output of the error information and the address is realized while low hardware resource consumption is maintained, and the observability and the debugging efficiency of the BIST test are remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and relates to integrated circuit testing, in particular to a built-in self-test circuit supporting error information output. BACKGROUND

[0002] In the prior art, BIST (Built-In Self-Test) circuit, as an important DFT (Design for Testability) scheme, is widely used to improve the reliability and manufacturing yield of chips. With the continuous miniaturization of semiconductor process nodes, the complexity of integrated circuits grows exponentially. The traditional external testing method has been difficult to meet the testing needs of modern chips due to limited test coverage, long test period, and high cost of test equipment. In contrast, BIST technology can realize efficient and automated testing of storage units (such as SRAM, register files), logic modules, and analog circuits by integrating dedicated test circuits inside the chip, thereby greatly reducing the dependence on external test equipment.

[0003] Currently, mainstream BIST technology can be divided into two categories: logic BIST (LBIST) and memory BIST (MBIST). Among them, LBIST is usually based on a pseudo-random test vector generator and a multi-input signature register, combined with a scan chain structure to complete the testing of combinational logic; while MBIST is designed for embedded memory, and performs read / write operations and fault detection on storage units through predefined test algorithms.

[0004] However, during the operation of the BIST circuit, how to efficiently and accurately output self-test error information to ensure the observability and diagnosability of the test results is still a technical problem to be solved in the field.

[0005] In the BIST circuit, the error information output mechanism is a key part to ensure the observability and diagnosability of the test results. Usually, BIST circuit outputs error information during self-test through the following ways: 1. Error flag signal Global error indication: BIST circuit usually outputs a global error signal, which is set to active (such as high or low) when any fault is detected; module-level error indication: in a multi-module BIST architecture, each sub-module can output an independent error signal to facilitate fault source localization.

[0006] 2. Error storage register The BIST circuit can integrate a dedicated error state register to record fault type, address or test vector information, such as storing fault address and error type. The error register can be read by an external test device or an on-chip processor through an interface for subsequent analysis.

[0007] In the prior art, the BIST circuit usually realizes self-check error output by setting a flag signal or storing error information to a specific register. However, the former can only provide fault indication and cannot present specific error information, and the latter needs to rely on a serial port to read internal register data, resulting in reduced test efficiency and increased system complexity. Both of the two traditional methods have obvious technical defects and need to be improved. SUMMARY

[0008] In view of the technical defects existing in the prior art, the application discloses a built-in self-test circuit supporting error information output.

[0009] The built-in self-test circuit supporting error information output comprises a BIST state machine, and the output end of the BIST state machine is connected with a MEM control signal generation logic module and an ADDR signal generation logic module, characterized in that the ADDR signal generation logic module is connected with a WDATA signal generation logic module, the WDATA signal generation logic module is connected with a result comparison module, the result comparison module is connected with the BIST state and an error printer mechanism module, and the MEM control signal generation logic module, the ADDR signal generation logic module, the WDATA signal generation logic module and the result comparison module are all connected with a memory. The function of the error printer mechanism module is to determine whether to perform error printing according to the comparison result of the result comparison module, and the error printing comprises outputting error information and address.

[0010] Preferably, the ADDR signal generation logic module generates a series of address signals for accessing different storage units of the memory in a certain order and outputs the address signals to the memory address through ADDR signals.

[0011] Preferably, the function of the result comparison module is to compare the data RDATA read from the memory MEM with expected data in a read test state, wherein the expected data is the data generated by the WDATA signal generation logic module and input into the result comparison module during a write operation. If the read data is inconsistent with the expected data, an error signal is generated.

[0012] Preferably, the error data output by the error printer mechanism module comprises a reference width and error information located after the reference width.

[0013] Preferably, the error printing mechanism module comprises a first selector connected with the input end, the first input end of the first selector is connected with the input end, the zeroth input end is connected with the output end of the register, the output end of the first register is connected with the input end of the register, and the output end of the register is further connected with a bit number selector, the bit number input end of the bit number selector is connected with the output end of the counter, and the output end of the bit number selector is connected with the output circuit. The error signal input end is connected with the control end of the first selector and a counter enable end generating circuit, the counter enable end generating circuit comprises a second selector and a D flip-flop, the first input end of the second selector is connected with the error signal input end, the zeroth input end is connected with the Q end of the D flip-flop, the output end of the second selector is connected with the D end of the D flip-flop, the Q end of the D flip-flop is connected with the output end of the counter, and the control end of the second selector is connected with an enable judgment circuit.

[0014] Preferably, the control end of the second selector is connected with the enable judgment circuit, the enable judgment circuit comprises a digital comparator and an or gate, the two input ends of the or gate are respectively connected with the error signal input end and the output end of the digital comparator, the output end of the or gate is connected with the control end of the second selector, and the two input ends of the digital comparator are respectively connected with the output end of the counter and the input end of the error printing mechanism module.

[0015] The present application realizes efficient and real-time output of error information and address while maintaining low hardware resource consumption by optimizing the error flag bit and the serial output mechanism, and significantly improves the observability and debugging efficiency of BIST test. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A specific embodiment schematic diagram of the built-in self-test circuit according to the present application; Figure 2 A specific embodiment schematic diagram of the error printing mechanism module according to the present application; Figure 3 A specific embodiment waveform schematic diagram of the result signal output by the error printing mechanism module according to the present application; In the figure, the figure mark names are as follows: MUX1-first selector, MUX2-second selector, MUX3-third selector, LD-length analysis circuit, CP-digital comparator. DETAILED DESCRIPTION

[0017] In order to more directly and clearly describe the technical scheme specific details of the present application, the following will be described in detail in combination with specific embodiments and example drawings.

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0019] like Figure 1 As shown, the built-in self-test circuit supporting error information output of the present invention includes a BIST state machine. The output terminal of the BIST state machine is connected to a MEM control signal generation logic module and an ADDR signal generation logic module. The ADDR signal generation logic module is connected to a WDATA signal generation logic module. The WDATA signal generation logic module is connected to a result comparison module. The result comparison module is connected to the BIST state machine and to an error printing mechanism module. The MEM control signal generation logic module, ADDR signal generation logic module, WDATA signal generation logic module, and result comparison module are all connected to a memory. The function of the error printing mechanism module is to determine whether to print an error based on the comparison result of the result comparison module. The error printing includes outputting error information and address.

[0020] BIST circuits are a technique used to test the internal modules of integrated circuits. BIST circuits can automatically test memory, detect potential faults, and improve the reliability and maintainability of integrated circuits. The following is based on... Figure 1 The diagram illustrates the operation of the BIST circuit: The BIST state machine is responsible for the state management of the entire BIST process. It coordinates the work of each module based on different test phases, such as the MEM (memory) write phase or read test phase, or different state signals, such as the BIST enable signal and the ERR error signal, ensuring the orderly progress of the test process. When the test is completed or an error occurs, the state machine control circuit stops working.

[0021] The MEM control signal generation logic module is used to control the control signals for memory operations, such as read / write enable and chip select signals, and outputs them to the memory MEM through the MEM control signal mem_ctrl.

[0022] The ADDR signal generation logic module generates a series of address signals for accessing different memory cells and outputs them to the memory MEM via the ADDR signal mem_addr. These address signals are generated in a specific order to cover all memory cells.

[0023] The WDATA signal generation logic module generates data WDATA to be written into the memory and outputs to the memory MEM. These data are usually pre-designed test vectors for detecting the correctness of the memory in write and read operations.

[0024] The result comparison module compares the data RDATA read from the memory MEM with the expected data in the read test state, where the expected data is the data generated by the WDATA signal generation logic module and input into the result comparison module when the write operation is performed. If the read data is inconsistent with the expected data, it means that the memory may have a fault, and an error signal ERR is generated at this time.

[0025] When the result comparison module generates an error signal, the error printing mechanism is triggered. It records and outputs information about the error, such as the address where the error occurred, the current state, and the actual read data, to facilitate debugging and analysis.

[0026] The test results of the BIST circuit can be output through the result signal bist_result. When bist_result is valid, it means that the error printing mechanism module detects the ERR signal, an error occurs during the self-checking process, and the bist_result signal will contain error information for external devices to further process and analyze the test results. When the BIST circuit is working, it needs to input external BIST clock and reset signal BIST-RSTN for system reset.

[0027] As shown in Figure 2 a specific embodiment of the error printing mechanism module is given, which includes a first selector connected with the input end IN, the first input end of the first selector is connected with the input end, the zeroth input end is connected with the output end of the register, the output end of the first register is connected with the input end of the register, and the output end of the register is also connected with the bit number selector, the bit number input end of the bit number selector is connected with the output end of the counter, and the output end of the bit number selector is connected with the output circuit; The error signal input end is connected with the control end of the first selector and the counter enable end generation circuit, the counter enable end generation circuit includes a second selector and a D flip-flop, the first input end of the second selector is connected with the error signal input end, the zeroth input end is connected with the Q end of the D flip-flop, the output end of the second selector is connected with the D end of the D flip-flop, and the Q end of the D flip-flop is connected with the output end of the counter.

[0028] The control end of the second selector is connected with the enable judgment circuit, which can be directly connected with the error signal, Figure 2In the specific embodiment shown, the enable judging circuit includes a digital comparator and an OR gate, two input terminals of the OR gate are connected to an error signal input terminal and an output terminal of the digital comparator respectively, an output terminal of the OR gate is connected to a control terminal of the second selector, two input terminals of the digital comparator are connected to an output terminal of the counter and an input terminal of the error printer mechanism module respectively.

[0029] The data length signal LENGTH is extracted from the input terminal and input to the digital comparator, when the output value of the counter is not equal to the data length signal LENGTH, the digital comparator continuously outputs zero, so that the OR gate is equivalent to a transmission gate, directly outputs the error signal in the form of a pulse signal, and continuously enables the counter, when the output value of the counter is equal to the data length signal LENGTH, it is indicated that all the error data has been received, the digital comparator outputs 1, so that the output of the OR gate is continuously 1, the D terminal cannot receive the error signal in the form of a pulse, and the counter is no longer enabled.

[0030] The error signal ERR is a pulse signal with a clock cycle width, when it is effective, the first selector MUX1 selects the first input terminal, and combines the signals input by the data input terminal IN connected to the first input terminal of the first selector, such as the state signal state, the ADDR signal, and the RDATA data, into the error information fail_info and temporarily stores them in the register array.

[0031] At the same time, the second selector MUX2 selects the first input terminal, and the error signal ERR makes the enable terminal C_EN of the counter high under the action of the error signal ERR, during the effective period of C_EN, the counter starts to work and outputs the count signal to the bit number selector, the function of the bit number selector is to input the error information fail_info stored in the register according to the bit number of the counter, from low to high according to the register address bit, into the output circuit in bit, to form the result signal bist_result.

[0032] Figure 2 In the specific embodiment shown, the output circuit includes a third selector and a D flip-flop connected to the output terminal of the third selector, when the enable signal EN is high, the first input terminal of the third selector is selected, so that the output of the bit number selector is input to the D terminal of the D flip-flop through the third selector, and is output in bit under the action of the clock signal.

[0033] When the counter reaches the set value, that is, the error information fail_info is sent to the last bit, the enable terminal C_EN is closed, and then the result signal bist_result resumes to continuously output high level, completing the error information output and error indication functions.

[0034] When the error printer mechanism module works, the clock signals required by the various flip-flops, registers and circuit modules can be input from the outside.

[0035] A specific waveform of the result signal bist_result output by the error printing mechanism module output end is shown as follows Figure 3 As shown in the figure, during the test process, when error information is detected, the module packs the current state, error address and read error data, and outputs them through the output end, and keeps high after outputting.

[0036] Before the serial data starts, a reference width is contained, which is used to calibrate the length of the subsequent data LENGTH, and then the error information is output in turn, including state, addr, rdata, etc., wherein state represents the state when the error occurs, and the expected write value can also be inferred from it; addr represents the error address; rdata represents the error value. The reference width value is input from the input end of the error printing mechanism module together with other data, and is a fixed width high level.

[0037] The present application realizes efficient and real-time output of error information and address while maintaining low hardware resource consumption by optimizing the error flag bit and serial output mechanism in cooperation, and significantly improves the observability and debugging efficiency of BIST test.

[0038] The foregoing is the various preferred embodiments of the present application, and the preferred embodiments in the various preferred embodiments can be arbitrarily combined and used if not obviously contradictory or with a certain preferred embodiment as a prerequisite. The embodiments and specific parameters in the embodiments are only for clearly describing the inventor's verification process, and are not used to limit the patent protection range of the present application, and the patent protection range of the present application is still subject to its claims, and any equivalent structural changes made by using the content of the present application should also be included in the protection range of the present application.

Claims

1. A built-in self-test circuit supporting error message output, comprising a BIST state machine, wherein the output terminal of the BIST state machine is connected to a MEM control signal generation logic module and an ADDR signal generation logic module, characterized in that, The ADDR signal generation logic module is connected to the WDATA signal generation logic module, the WDATA signal generation logic module is connected to the result comparison module, the result comparison module is connected to the BIST state, and is also connected to the error printing mechanism module. The MEM control signal generation logic module, the ADDR signal generation logic module, the WDATA signal generation logic module, and the result comparison module are all connected to the memory. The function of the error printing mechanism module is to determine whether to print an error based on the comparison result of the result comparison module. The error printing includes outputting error information and address.

2. The built-in self-test circuit supporting error information output as described in claim 1, characterized in that, The ADDR signal generation logic module generates a series of address signals for accessing different memory cells in a certain order, and outputs them to the memory address through the ADDR signal.

3. The built-in self-test circuit supporting error information output as described in claim 2, characterized in that, The result comparison module functions as follows: In read test mode, it compares the data RDATA read from memory MEM with the expected data, where the expected data is generated by the WDATA signal generation logic module and input into the result comparison module during write operation. An error signal is generated if the data read is inconsistent with the expected data.

4. The built-in self-test circuit supporting error information output as described in claim 1, characterized in that, The error printing mechanism module outputs error data including a baseline width and error information following the baseline width.

5. The built-in self-test circuit supporting error information output as described in claim 1, characterized in that, The error printing mechanism module includes a first selector connected to the input terminal. The first input terminal of the first selector is connected to the input terminal, the zero input terminal is connected to the register output terminal, the output terminal of the first register is connected to the register input terminal, the register output terminal is also connected to a bit selector, the bit input terminal of the bit selector is connected to the counter output terminal, and the output terminal of the bit selector is connected to the output circuit. The error signal input terminal is connected to the control terminal of the first selector and to the counter enable terminal generation circuit. The counter enable terminal generation circuit includes a second selector and a D flip-flop. The first input terminal of the second selector is connected to the error signal input terminal, the zero input terminal is connected to the Q terminal of the D flip-flop, the output terminal of the second selector is connected to the D terminal of the D flip-flop, the Q terminal of the D flip-flop is connected to the output terminal of the counter, and the control terminal of the second selector is connected to an enable judgment circuit.

6. The built-in self-test circuit supporting error information output as described in claim 5, characterized in that, The control terminal of the second selector is connected to an enable judgment circuit, which includes a digital comparator and an OR gate. The two input terminals of the OR gate are respectively connected to the error signal input terminal and the output terminal of the digital comparator. The output terminal of the OR gate is connected to the control terminal of the second selector. The two input terminals of the digital comparator are respectively connected to the counter output terminal and the input terminal of the error printing mechanism module.

Images