Display panel and display device

Abstract

The invention relates to a display panel and a display device, the display panel comprises a gate drive circuit and N rows of pixel circuits, each pixel circuit comprises a drive transistor, a threshold compensation module, a storage module and a data write-in module, and the gate drive circuit comprises M cascaded first scanning drive units and N cascaded second scanning drive units, the first scanning driving unit is used for providing a first scanning signal for the threshold compensation module, and the second scanning driving unit is used for providing a second scanning signal for the data writing module; the driving period of the pixel circuit comprises a threshold compensation stage and a data writing stage, and in the threshold compensation stage, a threshold compensation module is switched on in response to a first scanning signal; in the data writing stage, the data writing module is switched on in response to the second scanning signal. The display panel provided by the invention has a relatively good display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Display technology, as an important component of the information industry, has played a vital role in the development of information technology. With the advancement of display technology, display panels of various types, such as organic light-emitting diode (OLED) displays, have been widely adopted.

[0003] However, the display effect of the display panel in the related technology is poor. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel and a display device, which aim to improve the display effect of the display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, including a gate driving circuit and N rows of pixel circuits; the pixel circuits include:

[0006] A driving transistor is used to generate driving current.

[0007] A threshold compensation module, wherein the first terminal of the threshold compensation module is connected to the second terminal of the driving transistor, the second terminal of the threshold compensation module is connected to the gate of the driving transistor, and the control terminal of the threshold compensation module is used to receive a first scan signal;

[0008] A storage module, wherein a first terminal of the storage module is connected to the gate of the driving transistor; the storage module is used to store a threshold voltage.

[0009] A data writing module, wherein a first end of the data writing module is used to receive a data writing signal, a second end of the data writing module is connected to a second end of the storage module, and a control end of the data writing module is used to receive a second scan signal;

[0010] The gate driving circuit includes:

[0011] M cascaded first scan driving units, the m-th first scan driving unit being connected to multiple rows of pixel circuits respectively, for outputting the first scan signal to the pixel circuits;

[0012] N cascaded second scan driving units, the nth level of the second scan driving unit is connected to the pixel circuit in the nth row, and is used to output the second scan signal to the pixel circuit; wherein, 1≤n≤N, 1≤m≤M, N<M;

[0013] The driving cycle of the pixel circuit includes a threshold compensation stage and a data writing stage; wherein, in the threshold compensation stage, the threshold compensation module is turned on in response to the first scan signal; and in the data writing stage, the data writing module is turned on in response to the second scan signal.

[0014] Secondly, embodiments of this application also provide a display device, which includes the display panel provided in the first aspect.

[0015] The display panel provided in this application includes a gate driving circuit and N rows of pixel circuits. Each pixel circuit includes a driving transistor, a threshold compensation module, a storage module, and a data writing module. The gate driving circuit includes M cascaded first scan driving units and N cascaded second scan driving units. The first scan driving units provide a first scan signal to the threshold compensation module, and the second scan driving units provide a second scan signal to the data writing module. The driving cycle of the pixel circuit includes a threshold compensation phase and a data writing phase. In the threshold compensation phase, the threshold compensation module is turned on in response to the first scan signal; in the data writing phase, the data writing module is turned on in response to the second scan signal. In this application, the threshold compensation phase and the data writing phase are independent of each other, and one first scan driving unit provides a first scan signal to multiple rows of pixel circuits. Multiple rows of pixels undergo threshold compensation simultaneously, which increases the time for threshold compensation of the driving transistors, improves the threshold compensation effect, and thus enhances the display performance of the display panel. Attached Figure Description

[0016] Figure 1 This is a circuit structure diagram of a pixel circuit in related technologies;

[0017] Figure 2 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of this application;

[0018] Figure 3 A circuit structure diagram of a pixel circuit provided in an embodiment of this application;

[0019] Figure 4 A circuit structure diagram of another pixel circuit provided in an embodiment of this application;

[0020] Figure 5 A circuit structure diagram of another pixel circuit provided in an embodiment of this application;

[0021] Figure 6 A circuit structure diagram of another pixel circuit provided in an embodiment of this application;

[0022] Figure 7 A schematic diagram of another display panel structure provided in an embodiment of this application;

[0023] Figure 8 A schematic diagram of another display panel structure provided in an embodiment of this application;

[0024] Figure 9 A schematic diagram of the planar structure of another display panel provided in an embodiment of this application;

[0025] Figure 10 A circuit structure diagram of another pixel circuit provided in an embodiment of this application;

[0026] Figure 11 A schematic diagram of the planar structure of another display panel provided in an embodiment of this application;

[0027] Figure 12 A timing diagram of the driving of the pixel circuit provided in the embodiments of this application;

[0028] Figure 13 This is a schematic diagram of the structure of the display device provided in the embodiments of this application.

[0029] Explanation of reference numerals in the attached drawings: 10-Gate driving circuit, 11-First scan driving unit, 12-Second scan driving unit, 13-Third scan driving unit, 14-First light-emitting driving unit, 15-Second light-emitting driving unit, 200-Pixel circuit row, 20-Pixel circuit, 21-Threshold compensation module, 22-Storage module, 23-Data writing module, 24-Voltage regulator module, 25-First reset module, 26-Second reset module, 27-First light-emitting control module, 28-Second light-emitting control module, 1000-Display panel, 2000-Display device. Detailed Implementation

[0030] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0033] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0034] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0035] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0036] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0037] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0038] Please see Figure 1 , Figure 1 This is a circuit structure diagram of a pixel circuit in related technologies. From... Figure 1As can be seen, the first terminal of the second transistor M2 is used to receive the data signal Vdata, and the second terminal of the second transistor M2 is connected to the first terminal of the driving transistor M3. The gate of the second transistor M2 is used to receive the scan signal SC_P. The first terminal of the fourth transistor M4 is connected to the second terminal of the driving transistor M3, and the second terminal of the fourth transistor M4 is connected to the gate of the driving transistor M3. The gate of the fourth transistor M4 is used to receive the scan signal SC_P. Since the second transistor T2 and the fourth transistor T4 receive the same scan signal, the data writing stage and the threshold compensation stage are performed simultaneously in the driving cycle of the pixel circuit in the related technology. With the development of high-frequency technology, the charging time of each row of pixel circuits is getting shorter and shorter. Taking a resolution of 2800*1260 as an example, when the resolution is 120Hz, the time 1H of each row of pixel circuits is about 2.89us, while when the resolution is 240Hz, 1H is about 1.45us. It can be seen that the charging and writing time of the data signal line is greatly reduced, which in turn leads to a significant reduction in the threshold compensation time. This makes it impossible to effectively compensate for the threshold voltage of the driving transistor in the pixel circuit, resulting in a serious problem of image quality uniformity in the display panel at high frequencies.

[0039] Based on the aforementioned technical problems, the inventors discovered that by independently controlling the data writing stage and the threshold compensation stage of the pixel circuit, the threshold voltage compensation can be made no longer limited by the data writing cycle time, thereby improving the display effect of the display panel. Based on this, the inventors further developed the technical solution of the embodiments of this application. Specifically, the display panel provided in the embodiments of this application includes a gate driving circuit and N rows of pixel circuits; the pixel circuit includes: a driving transistor for generating a driving current; a threshold compensation module, the first terminal of which is connected to the second terminal of the driving transistor, the second terminal of which is connected to the gate of the driving transistor, and a control terminal of which is used to receive a first scan signal; a storage module, the first terminal of which is connected to the gate of the driving transistor; the storage module is used to store the threshold voltage; a data writing module, the first terminal of which is used to receive a data writing signal, the second terminal of which is connected to the second terminal of the storage module, and a control terminal of which is used to receive a first scan signal; a storage module, the first terminal of which is connected to the gate of the driving transistor; the storage module is used to store the threshold voltage; and a data writing module, the first terminal of which is used to receive a data writing signal, the second terminal of which is connected to the second terminal of the storage module, and a control terminal of which is used to receive a first scan signal. The gate driving circuit is used to receive the second scan signal. It includes: M cascaded first scan driving units, with the m-th level first scan driving unit connected to multiple rows of pixel circuits, for outputting the first scan signal to the pixel circuits; and N cascaded second scan driving units, with the n-th level second scan driving unit connected to the n-th row of pixel circuits, for outputting the second scan signal to the pixel circuits; wherein 1≤i≤N, 1≤m≤M, and N<M; the driving cycle of the pixel circuit includes a threshold compensation stage and a data writing stage; wherein, in the threshold compensation stage, the threshold compensation module is turned on in response to the first scan signal; and in the data writing stage, the data writing module is turned on in response to the second scan signal. By separating the data writing stage and the threshold compensation stage of the pixel circuit, the threshold voltage compensation is no longer limited by the data writing cycle time. Simultaneously, since each first scan driving unit is connected to multiple rows of pixel circuits, the time when the first scan signal is at an effective level can be extended, thereby extending the duration of the threshold compensation stage. This effectively compensates for the threshold voltage of the driving transistors in the pixel circuit, improving the display effect of the display panel.

[0040] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0041] In some exemplary embodiments, please refer to the following: Figure 2 and Figure 3 This application provides a display panel, including a gate driving circuit 10 and an N-row pixel circuit 20; the pixel circuit 20 includes:

[0042] The driving transistor T0 is used to generate the driving current;

[0043] The threshold compensation module 21 has a first terminal connected to the second terminal of the driving transistor T0, a second terminal connected to the gate of the driving transistor T0, and a control terminal for receiving the first scan signal S1.

[0044] Storage module 22, the first terminal of storage module 22 is connected to the gate of driving transistor T0; storage module 22 is used to store threshold voltage;

[0045] The data writing module 23 has a first end for receiving a data writing signal Vdata, a second end for being connected to the second end of the storage module 22, and a control end for receiving a second scan signal S2.

[0046] The gate drive circuit 10 includes:

[0047] M cascaded first scan driving units 11, the m-th first scan driving unit 11 is connected to the multi-row pixel circuit 20 respectively, and is used to output the first scan signal to the pixel circuit 20;

[0048] N cascaded second scan driving units 12, the nth level second scan driving unit 12 is connected to the nth row pixel circuit 20, and is used to output the second scan signal to the pixel circuit 20; where 1≤i≤N, 1≤m≤M, N<M.

[0049] The driving cycle of the pixel circuit includes a threshold compensation stage and a data writing stage; wherein, in the threshold compensation stage, the threshold compensation module 21 is turned on in response to the first scan signal S1; in the data writing stage, the data writing module 23 is turned on in response to the second scan signal S2.

[0050] In one embodiment, such as Figure 2 As shown, the display panel has a display area AA and a non-display area FA that at least partially surrounds the display area AA. The display area AA of the display panel includes N pixel circuit rows 200, and each pixel circuit row 200 includes multiple pixel circuits 20. The non-display area FA of the display panel includes a gate driving circuit 10, which includes M cascaded first scan driving units 11 and N cascaded second scan driving units 12.

[0051] like Figure 3As shown, the pixel circuit 20 includes a driving transistor T0, a threshold compensation module 21, a storage module 22, and a data writing module 23. The threshold compensation module 21 includes a threshold compensation transistor T1. The first terminal of the threshold compensation transistor T1 is connected to the second terminal of the driving transistor T0, and the second terminal of the threshold compensation transistor T1 is connected to the gate of the driving transistor T0. The gate of the threshold compensation transistor T1 is used to receive a first scan signal S1 output by the corresponding first scan driving unit 11. The storage module 22 includes a first capacitor C1. The first terminal of the first capacitor C1 is connected to the gate of the driving transistor T0, and the second terminal of the first capacitor C1 is connected to the second terminal of the data writing transistor T2. The data writing module 23 includes a data writing transistor T2. The first terminal of the data writing transistor T2 is used to receive a data writing signal Vdata, and the second terminal of the data writing transistor T2 is connected to the second terminal of the first capacitor C1. The gate of the data writing transistor T2 is used to receive a second scan signal S2 output by the corresponding second scan driving unit.

[0052] In this embodiment, the number of second scan driving units 12 in the display panel is the same as the number of pixel circuit rows 200, and one second scan driving unit 12 provides a second scan signal S2 for one row of pixel circuits 20; the number of first scan driving units 11 is less than the number of pixel circuit rows 200, and one first scan driving unit 11 simultaneously provides a first scan signal S1 for multiple rows of pixel circuits 20. In one example, please refer to [further details]. Figure 2 ,from Figure 2 As can be seen from the diagram, a second scan driving unit 12 provides a second scan signal S2 to a row of pixel circuits 20, and a first scan driving unit 11 provides a first scan signal S1 to two rows of pixel circuits 20.

[0053] In this example, the driving cycle of the pixel circuit includes a threshold compensation stage and a data writing stage. In the threshold compensation stage, the threshold compensation transistor T1 turns on in response to the first scan signal S1, and the data writing transistor T2 turns off in response to the second scan signal S2. In the data writing stage, the data writing transistor T2 turns on in response to the second scan signal S2, and the threshold compensation transistor T1 turns off in response to the first scan signal S1. It can be seen that the threshold compensation stage and the data writing stage are completely independent. Since one first scan driving unit 11 provides the first scan signal S1 to two rows of pixel circuits 20, the duration of the threshold compensation stage can be 2H (1H is the scan time of one row).

[0054] It should be noted that this example is only used to illustrate the threshold compensation phase duration of 2 hours. In practical applications, the duration of the threshold compensation phase can be set to be greater than 2 hours, and this application does not impose any restrictions on this.

[0055] In the application, the threshold compensation transistor T1 can be a single-gate transistor or a dual-gate transistor, and the data writing transistor T2 can be a single-gate transistor or a dual-gate transistor.

[0056] The display panel provided in this application includes a gate driving circuit and N rows of pixel circuits. Each pixel circuit includes a driving transistor, a threshold compensation module, a storage module, and a data writing module. The gate driving circuit includes M cascaded first scan driving units and N cascaded second scan driving units. The first scan driving units provide a first scan signal to the threshold compensation module, and the second scan driving units provide a second scan signal to the data writing module. The driving cycle of the pixel circuit includes a threshold compensation phase and a data writing phase. In the threshold compensation phase, the threshold compensation module is turned on in response to the first scan signal; in the data writing phase, the data writing module is turned on in response to the second scan signal. In this application, the threshold compensation phase and the data writing phase are independent of each other, and one first scan driving unit provides a first scan signal to multiple rows of pixel circuits. Multiple rows of pixels undergo threshold compensation simultaneously, which increases the time for threshold compensation of the driving transistors, improves the threshold compensation effect, and thus enhances the display performance of the display panel.

[0057] In some exemplary embodiments, please refer to Figure 4 The pixel circuit 20 also includes:

[0058] The voltage regulator module 24 has its first terminal connected to the second terminal of the data writing module 23. The second terminal of the voltage regulator module 24 is used to receive the first power signal PVDD and to stabilize the potential of the second terminal of the data writing module 23.

[0059] In the application, the voltage regulator module 24 may include a second capacitor C2. The first terminal of the second capacitor C2 is connected to the second terminal of the data writing transistor T2, and the second terminal of the second capacitor C2 is used to receive the first power supply signal PVDD.

[0060] The voltage regulator module 24, by connecting to a stable first power signal PVDD, can suppress potential drift and noise at the second end of the data writing module 23 caused by signal crosstalk, leakage, and timing switching, ensuring that the data voltage is accurately and stably written to the storage module, improving the accuracy of data writing in the pixel circuit, and thus ensuring the grayscale display accuracy and brightness uniformity of the display panel.

[0061] Furthermore, during the threshold compensation stage, the data writing module 23 is turned off, and the voltage regulation module 24 can maintain the potential stability of the data writing node (i.e., the second end of the data writing module 23), avoiding abnormal fluctuations and drifts of the node potential from interfering with the threshold voltage storage of the driving transistor gate, ensuring a pure and sufficient threshold compensation process, and further solving the problem of incomplete threshold compensation of the driving transistor.

[0062] In some exemplary embodiments, please refer to Figure 5 The pixel circuit 20 also includes:

[0063] The first reset module 25 has a first terminal for receiving a first reset signal Vref1, a second terminal for being connected to the second terminal of the data writing module 23, and a control terminal for receiving a third scan signal S3.

[0064] The driving cycle of the pixel circuit 20 also includes a first reset phase. In the first reset phase, the data writing module 23 is turned off in response to the second scan signal S2, and the first reset module is turned on in response to the third scan signal S3.

[0065] The first reset module 25 may include a first reset transistor T3. The first terminal of the first reset transistor T3 is used to receive a first reset signal Vref1, the second terminal of the first reset transistor T3 is connected to the second terminal of the data writing transistor T2, and the gate of the first reset transistor T3 is used to receive a third scan signal S3. The first reset transistor T3 may be a single-gate transistor or a dual-gate transistor.

[0066] In this embodiment, the first reset stage can be performed before the data writing stage. By resetting the second end of the data writing module 23 in advance during the first reset stage, the residual charge / voltage after the previous frame is worked can be cleared, so as to avoid the residual potential from interfering with the data writing and threshold compensation process of the current frame and reduce display defects such as ghosting, crosstalk, and grayscale shift.

[0067] In some exemplary embodiments, the display panel further includes:

[0068] There are N first scan signal lines, the nth first scan signal line is connected to the nth row pixel circuit, and the mth level first scan driving unit is connected to multiple first scan signal lines respectively. Different first scan driving units are connected to different first scan signal lines.

[0069] The control terminal of the first reset module 25 and the control terminal of the threshold compensation module are respectively connected to the first scan signal line.

[0070] In applications, the third scan signal S3 can reuse the first scan signal S1. For an example, please refer to [link / reference needed]. Figure 2 The first scan driving unit 11 can lead out two first scan signal lines. One first scan signal line is connected to a pixel circuit row 200, and the gate of the threshold compensation transistor T1 and the gate of the first reset transistor T3 in the pixel circuit 20 both receive the first scan signal S1 through the first scan signal line.

[0071] This application uses the first scan signal line to share the control terminals of the threshold compensation module 21 and the first reset module 25, eliminating the need for separate control traces for each module. This reduces the wiring density of the array substrate, saves panel wiring space, and facilitates the design of display panels with narrow bezels and high pixel density. Simultaneously, the first scan drive unit 11 is used for both threshold compensation control and first reset control, eliminating the need for an additional dedicated first reset drive unit. Furthermore, in conjunction with the architecture of a single-level first scan drive unit supporting multiple rows of pixels, it fully utilizes a drive unit layout where M > N while still satisfying the N-row pixel driving requirement, reducing the number of drive circuit components, power consumption, and process complexity.

[0072] In some exemplary embodiments, please refer to Figure 6 The pixel circuit 20 also includes:

[0073] The second reset module 26 has a first terminal for receiving the second reset signal Vref2, a second terminal for being connected to the second terminal of the driving transistor T0, and a control terminal for receiving the fourth scan signal S4.

[0074] The driving cycle of the pixel circuit 20 also includes a second reset phase. In the second reset phase, the threshold compensation module 21 is turned on in response to the first scan signal, and the second reset module 26 is turned on in response to the fourth scan signal.

[0075] The second reset module 26 may include a second reset transistor T4. The first terminal of the second reset transistor T4 is used to receive the second reset signal Vref2, the second terminal of the second reset transistor T4 is connected to the second terminal of the driving transistor T0, and the gate of the second reset transistor T4 is used to receive the fourth scan signal S4. The second reset transistor T4 may be a single-gate transistor or a dual-gate transistor.

[0076] During the second reset phase, the threshold compensation module 21 and the second reset module 26 are turned on, and the second reset signal Vref2 resets the gate of the driving transistor, which can completely clear the residual charge and residual voltage of the previous frame, avoid the potential of the previous frame from interfering with the current frame threshold voltage sampling and storage, and improve the threshold compensation accuracy.

[0077] In some exemplary embodiments, please refer to Figure 7 The gate drive circuit 10 also includes:

[0078] M cascaded third scan drive units 13, with the m-th third scan drive unit connected to a multi-row pixel circuit, are used to output a fourth scan signal to the pixel circuit.

[0079] In the application, the pixel circuit row connected to the m-th level third scan driving unit 13 is the same as the pixel circuit row connected to the m-th level first scan driving unit 11. For example, please refer to... Figure 7 A first scanning drive unit 11 is connected to two rows of pixel circuits 20, and a third scanning drive unit 13 is connected to two rows of pixel circuits 20. The first-level first scanning drive unit 11 and the first-level third scanning drive unit 13 are both connected to the first row of pixel circuits and the second row of pixel circuits. The second-level first scanning drive unit 11 and the second-level third scanning drive unit 13 are both connected to the third row of pixel circuits and the fourth row of pixel circuits.

[0080] In some exemplary embodiments, the m-th level first scan driving unit 11 is used to output a first scan signal S1 to the (m-1)*p+1-th row pixel circuit 20 to the m*p-th row pixel circuit 20;

[0081] The first scanning drive unit 11 of the i-th stage is also used to output the fourth scanning signal S4 to the pixel circuits 20 of the (i+k)*p+1th row to the (i+k+1)*pth row;

[0082] The first scanning drive unit 11 of the M-k+q level is also used to output the fourth scanning signal S4 to the pixel circuits 20 of the q*p+1th row to the (q+1)*pth row; where p*M=N, p>1, 0≤q≤k, 1≤i<Mk.

[0083] In application, instead of setting up a third scan drive unit 13, the fourth scan signal S4 can be output by the first scan drive unit 11.

[0084] In one example, assuming p=2 and k=0, the number of pixel circuit rows 200 in the display panel is twice the number of first scan driving units 11. Each first scan driving unit 11 is used to provide a first scan signal S1 to two rows of pixel circuits 20. The first-level first scan driving unit 11 outputs the first scan signal to the first row of pixel circuits and the second row of pixel circuits, and outputs the fourth scan signal to the third row of pixel circuits and the fourth row of pixel circuits; the second-level first scan driving unit 11 outputs the first scan signal to the third row of pixel circuits and the fourth row of pixel circuits, and outputs the fourth scan signal to the fifth row of pixel circuits and the sixth row of pixel circuits; ...; the Mth-level first scan driving unit 11 outputs the first scan signal to the (N-1)th row of pixel circuits and the Nth row of pixel circuits, and outputs the fourth scan signal to the first row of pixel circuits and the second row of pixel circuits.

[0085] exist Figure 8In the example shown, the first scan driving unit 11-1 provides the first scan signal S1 to pixel circuit rows 200-1 and 200-2 respectively; the first scan driving unit 11-2 provides the first scan signal S1 to pixel circuit rows 200-3 and 200-4 respectively; and the first scan driving unit 11-3 provides the first scan signal S1 to pixel circuit rows 200-5 and 200-6 respectively. Please continue reading. Figure 8 The first scan driving unit 11-1 also provides a fourth scan signal S4 to pixel circuit row 200-3 and pixel circuit row 200-4 respectively, and the first scan driving unit 11-2 also provides a fourth scan signal S4 to pixel circuit row 200-5 and pixel circuit row 200-6 respectively.

[0086] In another example, assuming p=2 and k=1, the first-level first scan driving unit 11 outputs a first scan signal to the first and second row pixel circuits, and a fourth scan signal to the fifth and sixth row pixel circuits; the second-level first scan driving unit 11 outputs a first scan signal to the third and fourth row pixel circuits, and a fourth scan signal to the seventh and eighth row pixel circuits; ...; the (M-1)th level first scan driving unit 11 outputs a first scan signal to the (N-3)th and (N-2)th row pixel circuits, and a fourth scan signal to the first and second row pixel circuits; the Mth level first scan driving unit 11 outputs a first scan signal to the (N-1)th and Nth row pixel circuits, and a fourth scan signal to the third and fourth row pixel circuits.

[0087] exist Figure 9 In the example shown, the first scan driving unit 11-1 provides the first scan signal S1 to pixel circuit rows 200-1 and 200-2 respectively; the first scan driving unit 11-2 provides the first scan signal S1 to pixel circuit rows 200-3 and 200-4 respectively; the first scan driving unit 11-3 provides the first scan signal S1 to pixel circuit rows 200-5 and 200-6 respectively; and the first scan driving unit 11-4 provides the first scan signal S1 to pixel circuit rows 200-7 and 200-8 respectively. Please continue reading. Figure 8 The first scan driving unit 11-1 also provides a fourth scan signal S4 to pixel circuit row 200-5 and pixel circuit row 200-6 respectively, and the first scan driving unit 11-2 also provides a fourth scan signal S4 to pixel circuit row 200-7 and pixel circuit row 200-8 respectively.

[0088] In this embodiment, there is no need to set up a separate third scan driving unit for the fourth scan signal. The existing M first scan driving units can be reused to complete the threshold compensation control and the second reset control. This reduces the number of driving units, the number of devices and the layout area, and significantly reduces the complexity and cost of the gate driving circuit.

[0089] In some exemplary embodiments, please refer to Figure 10 The pixel circuit 20 also includes:

[0090] The first light-emitting control module 27 has a first terminal for receiving a first power signal PVDD, a second terminal for connecting to the first electrode of the driving transistor T0, and a control terminal for receiving a first light-emitting control signal EM1.

[0091] The second light-emitting control module 28 has a first terminal connected to the second terminal of the driving transistor T0, a second terminal connected to the anode of the light-emitting element D, and a control terminal for receiving the second light-emitting control signal EM2.

[0092] During the threshold compensation phase, the first light emission control module 27 is turned on in response to the first light emission control signal EM1.

[0093] The driving cycle of the pixel circuit also includes a light-emitting stage. During the light-emitting stage, the first light-emitting control module 27 is turned on in response to the first light-emitting control signal EM1, and the second light-emitting control module 28 is turned on in response to the second light-emitting control signal EM2.

[0094] The driving cycle of the pixel circuit also includes a third reset phase. In the third reset phase, the second reset module is turned on in response to the fourth scan signal, the second light emission control module is turned on in response to the second light emission control signal, and the first light emission control module is turned off in response to the first light emission control signal.

[0095] The first light-emitting control module 27 may include a first light-emitting control transistor T5. The first terminal of the first light-emitting control transistor T5 is used to receive a first power supply signal PVDD, the second terminal of the first light-emitting control transistor T5 is connected to the first terminal of the driving transistor T0, and the gate of the first light-emitting control transistor T5 is used to receive a first light-emitting control signal EM1. The first light-emitting control transistor T5 may be a single-gate transistor or a dual-gate transistor.

[0096] The second light-emitting control module 28 may include a second light-emitting control transistor T6. The first terminal of the second light-emitting control transistor T6 is connected to the second terminal of the driving transistor T0. The second terminal of the second light-emitting control transistor T6 is connected to the anode of the light-emitting element D. The gate of the second light-emitting control transistor T6 is used to receive the second light-emitting control signal EM2. The second light-emitting control transistor T6 may be a single-gate transistor or a dual-gate transistor.

[0097] During the threshold compensation stage, the first light-emitting control transistor T5 turns on in response to the first light-emitting control signal EM1, and the threshold compensation transistor T1 turns on in response to the first scan signal S1. Thus, the first power supply signal PVDD can perform threshold compensation on the gate of the driving transistor T0 through the first light-emitting control transistor T5, the driving transistor T0, and the threshold compensation transistor T1.

[0098] In the third reset phase, the second reset transistor T4 turns on in response to the fourth scan signal S4, the second light-emitting control transistor T6 turns on in response to the second light-emitting control signal EM2, and the first light-emitting control transistor T5 turns off in response to the first light-emitting control signal EM1. Thus, the second reset signal Vref2 can reset the anode of the light-emitting element D.

[0099] During the light-emitting stage, the first light-emitting control transistor T5 turns on in response to the first light-emitting control signal EM1, and the second light-emitting control transistor T6 turns on in response to the second light-emitting control signal EM2. This drives the transistor T0 to provide a driving current to the light-emitting element D, so that the light-emitting element D emits light.

[0100] In some exemplary embodiments, please refer to Figure 11 The gate drive circuit 10 also includes:

[0101] M cascaded first light-emitting driving units 14, the m-th first light-emitting driving unit 14 is connected to the multi-row pixel circuit, and is used to output the first light-emitting control signal EM1 to the pixel circuit 20.

[0102] M cascaded second light-emitting driving units 15, the m-th second light-emitting driving unit 15 is connected to the multi-row pixel circuit, and is used to output the second light-emitting control signal EM2 to the pixel circuit.

[0103] By setting up independent first light-emitting driving unit 14 and second light-emitting driving unit 15, different control signals can be provided to the first light-emitting control module 27 and the second light-emitting control module 28, thereby independently controlling the on / off state of the first light-emitting control module 27 and the second light-emitting control module 28, which is beneficial for isolating the threshold compensation stage, the third reset stage and the light-emitting stage.

[0104] In a detailed embodiment, please refer to [reference needed]. Figure 10 , Figure 11 and Figure 12 The pixel circuit 20 includes a driving transistor T0, a threshold compensation transistor T1, a data writing transistor T2, a first reset transistor T3, a second reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first capacitor C1, and a second capacitor C2.

[0105] The gate driving circuit 10 includes M cascaded first scan driving units 11, N cascaded second scan driving units 12, M cascaded third scan driving units 13, M cascaded first light-emitting driving units 14, and M cascaded second light-emitting driving units 15. Each second scan driving unit 12 may include a second A scan driving unit 121 and a second B scan driving unit 122. The second A scan driving unit 121 and its corresponding second B scan driving unit 122 are connected to the same row of pixel circuits, jointly providing a second scan signal to the connected pixel circuits, thereby achieving bilateral driving of the pixel circuits.

[0106] In the third reset phase t1, the second light emission control signal EM2 and the fourth control signal S4 are at active levels, while the first light emission control signal EM1, the first scan signal S1, and the second scan signal S2 are at inactive levels. Consequently, the second reset signal Vref2 resets the second electrode of the driving transistor T0 and the anode of the light-emitting element.

[0107] During the first reset phase / second reset phase t2, the second light emission control signal EM2, the fourth control signal S4, and the first scan signal S1 are at active levels, while the first light emission control signal EM1 and the second scan signal S2 are at inactive levels. Consequently, the second reset signal Vref2 resets the second electrode of the driving transistor, the anode of the light-emitting element, and the gate of the driving transistor, while the first reset signal Vref1 resets the second electrode of the data writing transistor T2.

[0108] During the threshold compensation stage t3, the first light emission control signal EM1 and the first scan signal S1 are at active levels, while the second light emission control signal EM2, the fourth control signal S4, and the second scan signal S2 are at inactive levels. The first power supply signal PVDD performs threshold compensation on the driving transistor T0, and at the same time, the first reset signal Vref1 resets the second electrode of the data writing transistor T2.

[0109] During the data writing stage t4, the first light emission control signal EM1 and the second scan signal S2 are at active levels, while the second light emission control signal EM2, the fourth control signal S4, and the first scan signal S1 are at inactive levels. The data signal Vdata is written to the second terminal of the data writing transistor T2 and coupled to the gate of the driving transistor T0 through the first capacitor C1.

[0110] During the light-emitting stage t5, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at active levels, while the fourth control signal S4, the first scan signal S1, and the second scan signal S2 are at inactive levels, and the light-emitting element D emits light.

[0111] Based on the same concept, this application also provides a display device. Figure 13 This is a schematic diagram of the structure of the display device 2000 provided in the embodiments of this application, as shown below. Figure 13 As shown, the display device 2000 includes the display panel 1000 in any of the above embodiments. Exemplarily, as... Figure 13 As shown, the display device 2000 includes a display panel 1000. Therefore, the display device 2000 also has the beneficial effects of the display panel 1000 in the above embodiments. The similarities can be understood with reference to the explanation of the display panel 1000 above, and will not be repeated below.

[0112] The display device 2000 provided in this application embodiment can be... Figure 13 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0113] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, Includes gate drive circuitry and N-row pixel circuitry; The pixel circuit includes: A driving transistor is used to generate driving current. A threshold compensation module, wherein the first terminal of the threshold compensation module is connected to the second terminal of the driving transistor, the second terminal of the threshold compensation module is connected to the gate of the driving transistor, and the control terminal of the threshold compensation module is used to receive a first scan signal; A storage module, wherein a first terminal of the storage module is connected to the gate of the driving transistor; the storage module is used to store a threshold voltage. A data writing module, wherein a first end of the data writing module is used to receive a data writing signal, a second end of the data writing module is connected to a second end of the storage module, and a control end of the data writing module is used to receive a second scan signal; The gate driving circuit includes: M cascaded first scan driving units, the m-th first scan driving unit being connected to multiple rows of pixel circuits respectively, for outputting the first scan signal to the pixel circuits; N cascaded second scan driving units, the nth level of the second scan driving unit is connected to the pixel circuit in the nth row, and is used to output the second scan signal to the pixel circuit; where 1≤i≤N, 1≤m≤M, N<M; The driving cycle of the pixel circuit includes a threshold compensation phase and a data writing phase; wherein, in the threshold compensation phase, the threshold compensation module is turned on in response to the first scan signal; and in the data writing phase, the data writing module is turned on in response to the second scan signal.

2. The display panel according to claim 1, characterized in that, The pixel circuit also includes: A voltage regulator module, wherein a first terminal of the voltage regulator module is connected to a second terminal of the data writing module, the second terminal of the voltage regulator module is used to receive a first power signal; the voltage regulator module is used to stabilize the potential of the second terminal of the data writing module.

3. The display panel according to claim 1, characterized in that, The pixel circuit also includes: A first reset module, wherein a first terminal of the first reset module is used to receive a first reset signal, a second terminal of the first reset module is connected to the second terminal of the data writing module, and a control terminal of the first reset module is used to receive a third scan signal; The driving cycle of the pixel circuit also includes a first reset phase, in which the data writing module is turned off in response to the second scan signal, and the first reset module is turned on in response to the third scan signal.

4. The display panel according to claim 3, characterized in that, The display panel also includes: There are N first scan signal lines, the nth first scan signal line is connected to the pixel circuit in the nth row, and the mth first scan driving unit is connected to multiple first scan signal lines respectively. Different first scan driving units are connected to different first scan signal lines. The control terminal of the first reset module and the control terminal of the threshold compensation module are respectively connected to the first scan signal line.

5. The display panel according to claim 1, characterized in that, The pixel circuit also includes: The second reset module has a first terminal for receiving a second reset signal, a second terminal for being connected to the second electrode of the driving transistor, and a control terminal for receiving a fourth scan signal. The driving cycle of the pixel circuit further includes a second reset phase, in which the threshold compensation module is turned on in response to the first scan signal, and the second reset module is turned on in response to the fourth scan signal.

6. The display panel according to claim 5, characterized in that, The gate driving circuit further includes: M cascaded third scan drive units, with the m-th third scan drive unit connected to multiple rows of pixel circuits respectively, for outputting the fourth scan signal to the pixel circuits.

7. The display panel according to claim 5, characterized in that, The first scanning drive unit at level m is used to output the first scanning signal to the pixel circuits from row (m-1)*p+1 to row m*p. The first scanning drive unit of the i-th stage is also used to output the fourth scanning signal to the pixel circuits of the (i+k)*p+1th row to the (i+k+1)*pth row; The first scanning drive unit of the M-k+q level is also used to output the fourth scanning signal to the pixel circuits of the q*p+1th row to the (q+1)*pth row; where p*M=N, p>1, 0≤q≤k, 1≤i<Mk.

8. The display panel according to claim 5, characterized in that, The pixel circuit also includes: A first light-emitting control module, wherein a first terminal of the first light-emitting control module is used to receive a first power signal, a second terminal of the first light-emitting control module is connected to the first electrode of the driving transistor, and a control terminal of the first light-emitting control module is used to receive a first light-emitting control signal; During the threshold compensation phase, the first light emission control module is turned on in response to the first light emission control signal.

9. The display panel according to claim 8, characterized in that, The gate driving circuit further includes: M cascaded first light-emitting driving units, the m-th first light-emitting driving unit being connected to multiple rows of pixel circuits respectively, for outputting the first light-emitting control signal to the pixel circuits.

10. The display panel according to claim 8, characterized in that, The pixel circuit also includes: The second light-emitting control module has a first terminal connected to the second electrode of the driving transistor, a second terminal connected to the anode of the light-emitting element, and a control terminal for receiving a second light-emitting control signal. The driving cycle of the pixel circuit also includes a light-emitting phase, in which the first light-emitting control module is turned on in response to the first light-emitting control signal, and the second light-emitting control module is turned on in response to the second light-emitting control signal.

11. The display panel according to claim 10, characterized in that, The driving cycle of the pixel circuit further includes a third reset phase, in which the second reset module is turned on in response to the fourth scan signal, the second light emission control module is turned on in response to the second light emission control signal, and the first light emission control module is turned off in response to the first light emission control signal.

12. The display panel according to claim 10, characterized in that, The gate driving circuit further includes: M cascaded second light-emitting driving units, with the m-th stage of the second light-emitting driving unit connected to multiple rows of pixel circuits respectively, for outputting the second light-emitting control signal to the pixel circuits.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 12.

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