Voltage-time logic power distribution network adaptive feeder coordination control method and system

Abstract

This invention relates to the field of power distribution system feeder automation technology, and discloses a voltage-time logic power distribution network adaptive feeder coordinated control method and system. The method includes: capturing the discrete sequence of voltage loss attenuation during line undervoltage process, fitting and calculating the equivalent attenuation time constant to generate the load impedance inertia index; calculating the time slot bubble occupancy width on the reference recovery time axis and generating an adaptive delay increment, and obtaining the target access time threshold after superimposing the discretized jitter factor; using a timing integrator to monitor the incoming bus voltage dip event in real time and synthesizing a congestion warning signal, performing freeze and unfreeze operations on the integrator according to the degree of congestion, and issuing an access drive pulse only when the accumulated effective time integral value reaches the target access time threshold; this invention realizes the self-organized peak-shifting access of multiple feeder terminals according to load weight and grid steady state, effectively suppressing the risk of upstream power supply overcurrent tripping caused by cold start inrush current superposition.

Description

Technical Field

[0001] This invention relates to the field of power distribution system feeder automation technology, and more specifically, to a voltage-time logic power distribution network adaptive feeder coordination control method and system. Background Technology

[0002] With the rapid development of smart distribution network technology, power supply reliability has become a core indicator for measuring the service quality of power systems. In distribution automation implementation schemes, voltage-time (VT) feeder automation is widely used in fault isolation and power restoration scenarios in medium-voltage distribution networks due to its independence from real-time communication networks, low construction costs, and strong logical independence. This mode monitors line voltage status through feeder terminals (FTUs) and, based on preset voltage judgment logic and time settings, automatically switches and coordinates the timing of sectionalizing switches to achieve the redistribution and supply of electrical energy.

[0003] To ensure the accuracy of the logical actions of such feeder terminals, various testing and verification schemes have been proposed in the prior art. For example, Chinese Patent No. CN110261724B discloses an automated testing method for voltage-time type feeders. This method uses a voltage-time type logic tester to control the AC voltage output interface, simulate voltage changes in the line, and collect switch position feedback to determine whether the action logic of the feeder terminal is correct under a specific voltage sequence. In addition, Chinese Patent Application No. CN112540262A discloses an automated testing system and testing method for voltage-time type feeders. By cooperating with a control backend and multiple testers, control signals are sent to the feeder terminals distributed on various switches of the line under test, and test cases are extracted. This achieves batch and serialized automated testing of multiple devices, improving testing efficiency and coverage.

[0004] However, although existing technologies have effectively solved the verification and testing problems of feeder terminal equipment functions, there is still a risk of systemic power supply failure at the level of actual power restoration control strategies in distribution networks due to the mismatch between "fixed timing logic" and "dynamic load inertia". Specifically, traditional voltage-time logic usually executes the connection operation of sectionalizing switches based on pre-fixed fixed time steps, such as X time limit and Y time limit. This rigid timing setting method treats the feeder terminal as a simple time counter, ignoring the differences in the physical characteristics of the actual loads in the power outage area, such as the proportion of inductive loads and cold start power requirements. During a power outage caused by voltage loss, motor loads such as air conditioners, compressors, and water pumps on the line will enter a "cold state" due to shutdown, and their equivalent impedance will be significantly reduced. When the upstream power supply resumes operation, if multiple feeder sections are mechanically connected sequentially at fixed time intervals without considering the "cold start inertia" of each section's load, a "disorderly stacking" phenomenon can easily occur. This means that before the inrush current caused by the connection of the preceding heavily loaded section has decayed and the bus voltage is in a vulnerable recovery period, the subsequent section switch is forcibly connected under a fixed delay. This lack of awareness of the timing overlap leads to a destructive vector superposition of multiple cold start inrush currents in the power supply circuit, causing the total current to instantaneously exceed the carrying capacity of the upstream power supply or substation outgoing switch. This causes the upstream power supply to be overloaded and interrupt power supply again, ultimately resulting in the failure of the entire feeder's self-healing recovery and restricting the stability and continuity of the distribution network's power supply capacity. Summary of the Invention

[0005] To overcome the aforementioned shortcomings of existing technologies, this invention provides a voltage-time logic distribution network adaptive feeder coordinated control method and system. By mining the natural voltage decay characteristics during line undervoltage processes to quantify local load inertia, the connection timing of each feeder terminal is dynamically adjusted accordingly, and an integral control mechanism based on voltage dip feedback is introduced. This method enables feeder terminals to autonomously achieve peak-shifting connection based on load intensity without communication interaction, effectively mitigating cold-start inrush current impacts, eliminating the risk of upstream power supply overcurrent tripping due to load superposition, and improving the self-healing success rate and power supply reliability of the distribution network.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] Voltage-time logic distribution network adaptive feeder coordination control method, including:

[0008] Capture the discrete sequence of voltage drop decay during the line undervoltage process, fit the discrete sequence of voltage drop decay and calculate the equivalent decay time constant, and generate the load impedance inertia index based on the equivalent decay time constant;

[0009] Define a reference recovery time axis, calculate the slot bubble occupancy width on the reference recovery time axis based on the load impedance inertia index, generate an adaptive delay increment based on the slot bubble occupancy width, and superimpose a discretized jitter factor on the adaptive delay increment to generate the target access time threshold.

[0010] The timing integrator is started. During the operation of the timing integrator, the voltage dip event of the incoming bus is monitored in real time and a congestion warning signal is synthesized. The timing integrator is frozen and unfrozen according to the congestion warning signal. When the accumulated time integration value of the timing integrator reaches the target access time threshold, an access drive pulse is issued.

[0011] The term "line voltage loss" refers to a line voltage that is lower than the rated voltage threshold.

[0012] The method for obtaining the discrete sequence of voltage undervoltage decay includes: when the feeder terminal detects line undervoltage, collecting multiple discrete data points of voltage amplitude within a transient window and arranging them in chronological order to form a discrete sequence of voltage undervoltage decay.

[0013] The method for calculating the equivalent decay time constant includes:

[0014] Curve fitting is performed on the discrete sequence of voltage drop decay to construct a voltage decay trajectory curve; an effective analysis segment is selected from the voltage decay trajectory curve, and the average decay rate of the voltage amplitude within the effective analysis segment is calculated; the equivalent decay time constant is calculated based on the average decay rate.

[0015] The load impedance inertia index is obtained by dividing the preset no-load line reference attenuation constant by the equivalent attenuation time constant.

[0016] The method for defining the baseline recovery time axis includes:

[0017] When the feeder terminal detects a single-sided voltage recovery, the reference recovery time axis is defined with the moment of detection of the single-sided voltage recovery as the zero point;

[0018] The larger the load impedance inertia index, the wider the time slot bubble occupancy width.

[0019] The method for generating the discretized jitter factor is as follows: extract the unique physical code of the feeder terminal, and perform a hash operation on the unique physical code of the feeder terminal to generate the discretized jitter factor;

[0020] The target access time threshold is obtained by adding the preset base delay, adaptive delay increment, and discretized jitter factor.

[0021] The activation condition for the timing integrator is:

[0022] When the feeder terminal detects a single-sided voltage recovery event, it monitors the voltage waveform of the incoming bus in real time to confirm whether the incoming bus voltage is within the stable threshold range and maintains the preset start-up stability confirmation time. If the condition is met, the timing integrator is started and the time integral value is initialized to zero.

[0023] The method for synthesizing the congestion warning signal includes:

[0024] During the operation of the timing integrator, voltage sag events are captured and the voltage sag depth and voltage sag duration are extracted. The voltage sag depth and voltage sag duration are weighted and synthesized into a congestion warning signal.

[0025] The method for performing time integration freeze and unfreeze operations on the time integrator based on the congestion warning signal includes:

[0026] When the congestion warning signal exceeds the preset safety warning threshold, the time integration freeze operation is performed on the time integrator, pausing the time integrator and keeping the current time integration value unchanged.

[0027] The congestion warning signal is continuously calculated under the time integral freeze state. When the congestion warning signal is lower than the preset congestion mitigation and return threshold and the incoming bus voltage remains within the stable threshold range for a preset unfreezing and stabilization confirmation time, the time integral unfreezing operation is performed on the time integrator. The time integrator continues to accumulate from the time integral value before the time integral freeze. The congestion mitigation and return threshold is less than the safety warning threshold.

[0028] A voltage-time logic distribution network adaptive feeder coordination control system, used to implement the aforementioned voltage-time logic distribution network adaptive feeder coordination control method, the system comprising:

[0029] Load inertia calculation module: used to capture the discrete sequence of voltage attenuation during line undervoltage process, fit the discrete sequence of voltage attenuation and calculate the equivalent attenuation time constant, and generate the load impedance inertia index based on the equivalent attenuation time constant;

[0030] Access threshold generation module: used to define the reference recovery time axis, calculate the slot bubble occupancy width on the reference recovery time axis according to the load impedance inertia index, generate an adaptive delay increment according to the slot bubble occupancy width, and superimpose a discretized jitter factor on the adaptive delay increment to generate the target access time threshold;

[0031] Integration access control module: Used to start the timing integrator, monitor voltage dip events on the incoming bus in real time during the operation of the timing integrator and synthesize congestion warning signals, and perform time integration freeze and unfreeze operations on the timing integrator according to the congestion warning signals. When the accumulated time integration value of the timing integrator reaches the target access time threshold, an access drive pulse is issued.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0033] This invention constructs a closed-loop adaptive control mechanism that couples local load characteristics with the real-time state of the power grid. By analyzing the discrete sequence of voltage undervoltage decay to generate a load impedance inertia index, it achieves on-site quantitative perception of the potential cold start impact intensity of feeder segments in a communication-free environment, providing a physical basis for differentiated timing allocation. This index is mapped to the time slot bubble occupancy width and an adaptive delay increment is generated, which automatically shifts the access time of heavy-load segments backward and relatively forwards the access time of light-load segments. Combined with the discretization effect of the discretized jitter factor, a macroscopically ordered access sequence based on load weight is established. Feedback control of a timing integrator and congestion warning signal is introduced to transform the traditional rigid delay logic of "absolute time" into a flexible integral logic of "effective stable time". By freezing the integral when a voltage dip caused by the access of other feeders is detected, microscopic timing isolation between the access impacts of adjacent feeders is forcibly achieved. This ensures that each access action is only executed after the voltage of the incoming bus recovers to a steady state, thereby avoiding the concentrated superposition of cold start inrush currents from multiple feeders and improving the self-healing success rate and operational stability of the distribution network in heavy-load power restoration scenarios. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A flowchart of the voltage-time logic distribution network adaptive feeder coordinated control method provided in this embodiment of the invention;

[0036] Figure 2 This is a schematic diagram of the discrete sequence acquisition of voltage undervoltage decay within a transient window provided in an embodiment of the present invention;

[0037] Figure 3 A schematic diagram of time-slot bubble distribution based on load impedance inertia index provided for an embodiment of the present invention;

[0038] Figure 4 The integral access control flowchart provided in this embodiment of the invention;

[0039] Figure 5 This is a schematic diagram of voltage dip event feature parameter extraction provided in an embodiment of the present invention;

[0040] Figure 6A functional block diagram of the voltage-time logic distribution network adaptive feeder coordinated control system provided in an embodiment of the present invention. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] Example 1:

[0043] Please see Figure 1 As shown, this embodiment provides a voltage-time logic distribution network adaptive feeder coordinated control method, including:

[0044] Step S10: Capture the discrete sequence of voltage attenuation during the line voltage loss process, fit the discrete sequence of voltage attenuation and calculate the equivalent attenuation time constant, and generate the load impedance inertia index based on the equivalent attenuation time constant;

[0045] Step S10 addresses the practical constraint in distribution network fault recovery scenarios where feeder terminals cannot obtain the actual load scale and characteristics within their assigned line segments. In traditional centralized distribution automation architectures, load information relies on communication networks to be uploaded from various measurement points to the master station for aggregation and analysis. However, when a fault causes communication interruption or network congestion, the feeder terminal becomes an information island, unable to obtain external load data support. Step S10, by exploring the physical laws of natural voltage decay during line undervoltage, encodes load characteristic information into the voltage decay trajectory, enabling the feeder terminal to infer load severity solely based on local voltage sampling, providing quantitative input for subsequent adaptive access timing allocation.

[0046] Further, step S10 includes:

[0047] Step S11: When the feeder terminal detects that the line voltage has dropped below the rated voltage threshold, it starts the high-frequency sampling mode, collects multiple discrete data points of voltage amplitude within the transient window, and arranges them in time order to form a discrete sequence of voltage loss attenuation.

[0048] The acquisition of the discrete voltage attenuation sequence is triggered by the feeder terminal detecting that the line voltage begins to drop below the rated voltage threshold. The rated voltage threshold is the limit value for determining whether the line has entered an undervoltage state; in distribution networks, it is typically set to 95% of the rated voltage. This threshold value avoids false triggering of sampling due to slight voltage fluctuations during normal operation while ensuring timely capture of the initial attenuation process when a real undervoltage event occurs. When the voltage drops below this threshold, the feeder terminal's digital signal processor immediately switches from the conventional sampling mode to the high-frequency sampling mode. The sampling rate of the high-frequency sampling mode is significantly higher than the power frequency sampling rate during normal operation. Its purpose is to acquire sufficiently dense voltage data points within the extremely short time window of the undervoltage transient process to accurately characterize the dynamic trajectory of voltage attenuation. For example, the conventional power frequency sampling rate is 12 points per cycle, while the high-frequency sampling mode can increase it to 96 points per cycle or higher, enabling the acquisition of hundreds of discrete data points within a transient window lasting from tens to hundreds of milliseconds.

[0049] The transient window refers to the time interval from when the voltage drops to the rated voltage threshold until the voltage drops to a preset zero-voltage setpoint. See also Figure 2 This is a schematic diagram of the discrete sequence acquisition of voltage undervoltage decay within the transient window provided in the embodiments of this application. Figure 2 The diagram visually illustrates the monotonically decreasing trend of voltage over time, with the horizontal axis representing time and the vertical axis representing voltage amplitude. Figure 2 The transient window is clearly defined, corresponding on the horizontal axis to the time interval between the rated voltage threshold and the zero-voltage setting on the vertical axis. The zero-voltage setting is the voltage threshold at which the feeder terminal determines a complete loss of line voltage, typically set at 30% or lower in distribution networks. The starting point of the transient window is chosen to be the rated voltage threshold rather than the rated voltage itself because the initial stage of the voltage drop from the rated value to the rated voltage threshold may contain high-frequency transient components at the moment the power supply side fault is cleared. These components do not reflect load characteristics but are related to the fault point impedance and system transient response; excluding them avoids interference with subsequent load analysis. The ending point of the transient window is chosen to be the zero-voltage setting rather than the voltage returning to zero because when the voltage drops to an extremely low level, the measurement accuracy of the instrument transformer decreases, the noise ratio increases, and continued sampling will introduce errors. Multiple voltage amplitude data points collected by the feeder terminal within the transient window are obtained through an electromagnetic voltage transformer. This transformer converts the primary high voltage into a secondary low voltage signal that the feeder terminal can process, and its output is converted from analog to digital to form a digital voltage amplitude. Figure 2As shown, within a defined transient window, the feeder terminal initiates high-frequency sampling, acquiring multiple discrete black solid dots, which are the high-frequency sampling data points. The feeder terminal arranges the acquired discrete data points in chronological order, forming a discrete voltage attenuation sequence that monotonically decreases over time. This sequence contains complete dynamic information about the voltage loss process. After sampling, the feeder terminal writes the voltage attenuation discrete sequence into its internal non-volatile storage unit. Non-volatile storage units are storage media that do not lose data after power failure, ensuring that even if the power supply is completely lost later, the acquired attenuation sequence can still be retained and used for subsequent steps after the voltage is restored.

[0050] The activation of high-frequency sampling mode enables feeder terminals to capture minute changes in voltage attenuation within an extremely short transient window. Traditional power frequency sampling can only acquire a small number of data points, making it difficult to distinguish differences in attenuation rates under different load conditions. Figure 2 The densely distributed high-frequency sampling data points support detailed analysis of the attenuation curve shape, thereby improving the resolution of load characteristic identification. Precise definition of the transient window separates valid from invalid data; the starting threshold filters out interference from fault clearing transient components, and the ending threshold eliminates measurement noise in the low-voltage region, ensuring the quality of data used in subsequent analysis. The discrete voltage attenuation sequence, serving as the original data source for load characteristic analysis, is stored in a non-volatile memory unit, enabling the feeder terminal to retain critical data across power cycles. Even if the feeder terminal's power supply is interrupted during a voltage loss, the attenuation sequence can still be read after power restoration. This characteristic makes load analysis unaffected by power fluctuations, enhancing the applicability of the entire method under harsh power conditions.

[0051] Step S12: Perform curve fitting on the discrete sequence of voltage loss decay to construct a voltage decay trajectory curve; select an effective analysis segment from the voltage decay trajectory curve and calculate the average decay rate of the voltage amplitude within the effective analysis segment; calculate the equivalent decay time constant based on the average decay rate.

[0052] The voltage attenuation trajectory curve is the result of continuous smoothing of discrete data points. The purpose of curve fitting is to eliminate random measurement errors at individual sampling points and transform the discrete sequence into a continuous function that can be mathematically analyzed. The logic processor of the feeder terminal uses the least squares method or a similar standard fitting algorithm to process the discrete voltage attenuation sequence, generating a smooth curve with minimal deviation from the original data points. This fitting process is completed internally within the feeder terminal, requiring no external computing resources, which meets the requirements of on-site autonomous decision-making in the absence of communication.

[0053] The effective analysis section is selected from the voltage decay trajectory curve, specifically the interval where the voltage amplitude drops from 80% to 40% of the rated voltage. 80% of the rated voltage is chosen as the starting point because when the voltage first begins to drop, the charge stored in the line-to-ground distributed capacitance has not yet been released on a large scale. The voltage decay rate is dominated by the energy stored in the capacitor, rather than by the load impedance. The decay characteristics at this stage cannot effectively reflect the load weight. 40% of the rated voltage is chosen as the ending point because after the voltage drops to an extremely low level, the load equipment may have already disconnected due to undervoltage, causing a sudden change in load impedance. The decay characteristics at this stage no longer reflect the normal load condition. The 80% to 40% range of the effective analysis section covers the intermediate stage where load impedance has the most significant impact on voltage decay. Within this stage, the line-to-ground distributed capacitance discharges stably through the load circuit. The heavier the load, the lower the equivalent load impedance, the faster the energy stored in the capacitor is consumed, and the higher the voltage decay rate. Conversely, the lighter the load, the higher the equivalent load impedance, and the lower the voltage decay rate.

[0054] The average attenuation rate is calculated as follows: extract the total change in voltage amplitude from 80% to 40% of the rated voltage within the effective analysis section, divide it by the time taken for this change, and obtain the ratio of voltage change to time. This ratio, expressed as voltage change per second, quantifies the rate of voltage decrease within the effective analysis section. The average attenuation rate is a linear approximation of the slope of the voltage attenuation trajectory curve within the effective analysis section. Although the actual attenuation curve may be exponential, using the average attenuation rate for linear approximation significantly reduces computational complexity, enabling the limited computing power of the feeder terminal to complete the calculation in a very short time, meeting the real-time requirements of fault recovery scenarios.

[0055] The calculation of the equivalent decay time constant is based on the physical principle of a resistive-capacitive discharge circuit. When a line loses power, the charge stored in the line's distributed capacitance to ground discharges through the load circuit. This process can be equivalent to a resistive-capacitive discharge circuit, where the distributed capacitance is equivalent to a capacitor and the load impedance is equivalent to a resistor. The voltage decay of the resistive-capacitive discharge circuit follows an exponential law, and its characteristic parameter is the time constant, which is equal to the product of the resistance and capacitance values. Assuming the distributed capacitance remains essentially constant, the time constant is proportional to the load impedance: a heavier load means a lower equivalent load impedance, a smaller time constant, and faster voltage decay; a lighter load means a higher equivalent load impedance, a larger time constant, and slower voltage decay. The feeder terminal uses the correspondence between the average decay rate and the exponential decay model to deduce the equivalent decay time constant that matches the average decay rate. The specific method is as follows: In the resistive-capacitive discharge model, the time required for the voltage to drop from its initial value to a specific proportion has a definite mathematical relationship with the time constant. The feeder terminal uses the calculated average attenuation rate, combined with the properties of the exponential attenuation function, to deduce the equivalent attenuation time constant that matches the average attenuation rate. Since the change in voltage from 80% to 40% of the rated voltage within the effective analysis section is fixed, and the average attenuation rate is inversely proportional to the measured time experienced during this change, the equivalent attenuation time constant is directly proportional to the measured time. Curve fitting transforms discrete data points into continuous trajectory curves, eliminating the influence of single-point measurement errors on subsequent analysis, thus making the calculation of the equivalent attenuation time constant more stable and repeatable. Precise definition of the effective analysis section extracts the interval where load impedance has the most significant impact on voltage attenuation, eliminating interference data from the capacitor-dominated stage and the load shedding stage, ensuring that the average attenuation rate truly reflects the load intensity under normal operating conditions. The equivalent decay time constant, as a characteristic parameter of the resistive-capacitive discharge model, compresses the complex voltage decay dynamic process into a single value. This not only preserves the core information of the load characteristics but also greatly simplifies the amount of data to be processed in the subsequent stages, enabling the feeder terminal to complete load analysis with extremely low storage and computing resources.

[0056] Step S13: Divide the preset no-load line reference attenuation constant by the equivalent attenuation time constant to obtain the load impedance inertia index.

[0057] The unloaded line reference attenuation constant refers to the attenuation time constant corresponding to the discharge circuit formed by the line-to-ground distributed capacitance and the line's own insulation leakage resistance when the feeder segment is unloaded and relies solely on this circuit. This reference value is obtained through offline testing or engineering estimation before the feeder terminal is put into operation and is stored in the feeder terminal's memory unit as a preset parameter. Under unloaded conditions, the discharge circuit has only extremely high insulation leakage resistance, and the energy stored in the capacitor is consumed very slowly. Therefore, the value of the unloaded line reference attenuation constant is usually much larger than the equivalent attenuation time constant under actual load. The load impedance inertia index is calculated by dividing the unloaded line reference attenuation constant by the measured equivalent attenuation time constant. Since the equivalent attenuation time constant is negatively correlated with the load weight (smaller equivalent attenuation time constant for heavy loads and larger equivalent attenuation time constant for light loads), the result of the above division operation is positively correlated with the load weight: the load impedance inertia index value for heavy loads is greater than that for light loads. For example, if the unloaded line reference attenuation constant is 500 milliseconds and the equivalent attenuation time constant of a heavily loaded section is 50 milliseconds, then the load impedance inertia index of that section is 10; if the equivalent attenuation time constant of a lightly loaded section is 250 milliseconds, then the load impedance inertia index of that section is 2. The load impedance inertia index is a dimensionless relative ratio, and its value does not depend on the absolute voltage level or sampling accuracy. It only reflects the relative difference between the current load state and the unloaded reference, which makes feeder sections of different voltage levels or different line lengths comparable.

[0058] The load impedance inertia index characterizes the magnitude of the starting inertia that may occur when power is restored to a particular line segment. When power is restored, cold loads such as air conditioners, motors, and charging piles connected to that segment will start simultaneously, generating surge currents much larger than the steady-state operating current. A larger load impedance inertia index indicates a heavier load on that segment before the power outage, resulting in a larger cold-start surge current and a stronger impact on the upstream power supply. Conversely, a smaller load impedance inertia index indicates a lighter load on that segment, leading to a relatively mild impact during power restoration. The feeder terminal writes the calculated load impedance inertia index into a non-volatile storage unit for subsequent steps in S20 when generating the adaptive access timing. The unloaded line reference attenuation constant serves as a normalization benchmark, providing a unified reference coordinate for the load impedance inertia indexes of different feeder segments, facilitating cross-segment timing coordination in subsequent steps. The load impedance inertia exponent is obtained by division to obtain a dimensionless ratio, avoiding the dimensional dependence problem caused by absolute values. This allows the exponent to be directly used in subsequent delay increment calculations without additional unit conversions. The positive correlation between the load impedance inertia exponent and the load weight allows subsequent steps to intuitively determine the load impact level based on the exponent's magnitude: a larger exponent requires a longer time slot bubble to avoid the period of weak grid capacity during the initial recovery phase, while a smaller exponent allows for a shorter time slot bubble to accelerate the power restoration process.

[0059] Step S10, through in-depth analysis of the natural voltage decay pattern during line loss, enables local autonomous sensing of load characteristics under conditions of complete communication interruption. Traditional distribution automation relies on communication networks to obtain load data. When a fault causes communication interruption, the feeder terminal becomes an information island, unable to adjust the access strategy according to the load situation, and can only mechanically execute preset fixed delays. Using the same timing parameters in heavily loaded and lightly loaded sections leads to the possibility of premature access in heavily loaded sections before the grid's carrying capacity has recovered, causing inrush current superposition, while lightly loaded sections may experience delays in power restoration due to excessive waiting time. Step S10 enables the feeder terminal to infer the load severity solely from local voltage sampling. This capability liberates load information from dependence on external communication, allowing adaptive timing allocation to still be executed under extreme conditions of complete communication interruption. The load impedance inertia index, as a fingerprint marker of load characteristics, compresses the continuously changing voltage decay process into a single characteristic value. This value retains the core information of load severity while significantly reducing the data dimensionality of subsequent processing. Step S10 employs a high-frequency sampling mode to capture transient details during the data acquisition phase, curve fitting to eliminate random errors during the data processing phase, effective analysis segment selection to exclude interfering data during the feature extraction phase, and benchmark division to eliminate dimensional dependence during the normalization phase. This multi-layered data processing flow ensures that the final output load impedance inertia index has high anti-interference capability and cross-segment comparability. The load impedance inertia index output in step S10 provides a direct and usable quantitative basis for the subsequent calculation of the time slot bubble occupancy width in step S20. This allows feeder terminals to autonomously find suitable access positions on the time axis based on the load characteristics of their respective segments. Lightly loaded segments automatically move forward to accelerate power restoration, while heavily loaded segments automatically move backward to avoid weak grid periods. Multiple feeder terminals can achieve self-organized peak-shifting access without communication coordination. This adaptive characteristic breaks through the rigid constraints of traditional fixed step-delay, enabling the access timing to dynamically adapt to actual load conditions rather than rigidly executing preset parameters.

[0060] Step S20: Define a reference recovery time axis, calculate the time slot bubble occupancy width on the reference recovery time axis based on the load impedance inertia index, generate an adaptive delay increment based on the time slot bubble occupancy width, and superimpose a discretized jitter factor on the adaptive delay increment to generate a target access time threshold.

[0061] Step S20 addresses the practical constraint that traditional fixed-step power-on delay settings lead to multiple sectionalizing switches connecting at similar times, resulting in inrush currents exceeding the capacity of the upstream power supply. In traditional voltage-time type feeder automation logic, the power-on delay of each sectionalizing switch is typically executed according to a pre-set fixed time step. For example, the first sectionalizing switch connects after a 7-second delay, the second after a 14-second delay, and the third after a 21-second delay. This rigid timing setting method does not consider the differences in actual load on each section of the line. When the heavily loaded section and the lightly loaded section use the same fixed delay interval, the heavily loaded section may connect prematurely before the grid's capacity has fully recovered. Its cold-start inrush current overlaps with the inrush current generated by the previous connection, causing the upstream power supply overcurrent protection to trip again, resulting in reclosing failure. Step S20 uses the load impedance inertia index generated in step S10 as a quantization input to dynamically allocate differentiated access positions to each feeder terminal on the time axis, so that the heavy load section is automatically moved backward to avoid the weak period of the power grid, and the light load section is automatically moved forward to accelerate the power restoration process, thereby realizing the self-organized peak-shaving access between multiple feeder terminals under the condition of no communication.

[0062] Further, step S20 includes:

[0063] Step S21: When the feeder terminal detects a single-sided voltage recovery, a reference recovery time axis is defined with the moment when the single-sided voltage recovery is detected as the zero point, and an elastic time delay interval is set on the reference recovery time axis according to the load impedance inertia index.

[0064] Specifically, single-sided voltage recovery refers to the situation where the feeder terminal detects that the incoming bus voltage of the switch it controls has recovered from an undervoltage state to a voltage-enabled state, while the outgoing bus voltage remains undervoltage or has not recovered. The feeder terminal continuously monitors the amplitude of the incoming bus voltage using an electromagnetic voltage transformer. When the amplitude of the incoming bus voltage rises from below the undervoltage setpoint and stabilizes above the rated voltage threshold, the feeder terminal determines that a single-sided voltage recovery event has occurred. The moment the feeder terminal captures the single-sided voltage recovery event is used as the starting reference point for subsequent timing calculations, and this moment is defined as the zero point of the reference recovery time axis. See also... Figure 3 As shown, the reference recovery time axis starts from the moment of single-sided voltage recovery and extends in the positive time direction. Figure 3The diagram illustrates the timing distribution of different load segments on this time axis. The reference recovery time axis is a virtual coordinate axis extending in the positive direction of time with the single-sided voltage recovery moment as its origin. Feeder terminals mark their own connection time position on this coordinate axis. The single-sided voltage recovery moment is chosen as the zero point of the reference recovery time axis because this moment has almost the same physical meaning for all feeder terminals on the same feeder. When the upstream power supply resumes power supply or the upstream sectionalizing switch is connected, the voltage wave propagates downstream along the feeder. Each feeder terminal detects the single-sided voltage recovery event almost simultaneously. Therefore, using this event as the timing starting point allows all feeder terminals in the network to establish a unified time reference without relying on external clock synchronization or communication networks for time alignment.

[0065] Upon detecting a single-sided voltage recovery event, the feeder terminal immediately reads the load impedance inertia index generated and stored in step S13 from the non-volatile storage unit. The load impedance inertia index is a quantitative representation of the load severity inferred from the voltage decay characteristics of the feeder segment during the power outage process; a larger value indicates a heavier load and a larger cold-start inrush current during power restoration. Based on the read load impedance inertia index, the feeder terminal's logic processor sets a floating elastic delay interval on the reference recovery time axis. The elastic delay interval refers to the time range within which the feeder terminal may perform a connection action. The lower limit of this interval is the base delay after the zero point of the reference recovery time axis. The base delay is a pre-tuned fixed delay amount used to provide a common time reference for all feeder terminals. The upper limit of this interval is positively correlated with the load impedance inertia index. The physical logic for setting the flexible time delay interval is as follows: A larger load impedance inertia index indicates a heavier load in that section, resulting in a stronger impact on the upstream power supply upon power restoration. Therefore, a larger time margin is needed to avoid the initial period of grid restoration when the load capacity is weak, and the upper limit of the flexible time delay interval is set accordingly higher. Conversely, a smaller load impedance inertia index indicates a lighter load in that section, resulting in a relatively mild cold-start inrush current. This allows for earlier grid connection during the initial restoration phase without causing inrush current superposition, and the upper limit of the flexible time delay interval is set accordingly lower. The mapping relationship between the upper limit of the flexible time delay interval and the load impedance inertia index can be implemented using linear mapping or piecewise linear mapping. For example, when the load impedance inertia index is a preset minimum value, the upper limit of the flexible time delay interval is set to the preset minimum delay upper limit value; when the load impedance inertia index is a preset maximum value, the upper limit of the flexible time delay interval is set to the preset maximum delay upper limit value; when the load impedance inertia index is between the minimum and maximum values, the upper limit of the flexible time delay interval is determined by linear interpolation.

[0066] Step S21 sets the zero point of the reference recovery time axis to the single-sided voltage recovery time, enabling all feeder terminals in the network to establish a common time reference without communication. This design completely eliminates the need for time synchronization in traditional centralized distribution automation, which relies on the master station to issue a unified clock or on the communication network. This allows feeder terminals to independently perform timing calculations even under communication interruption or network congestion conditions. The setting of the flexible delay interval transforms the fixed stepped delay setting method into a dynamic floating delay range. Different load impedance inertia indices correspond to different upper limits of the flexible delay interval, naturally separating the heavy load section and the light load section on the time axis. The heavy load section is assigned to a more distant time position, and the light load section is assigned to a more recent time position. This differentiated allocation fundamentally avoids the situation where heavy load sections and light load sections are connected at close intervals. Step S21 and step S10 form a close data transmission relationship. The load impedance inertia index output by step S10 serves as the sole quantization input for setting the elastic delay interval in step S21. The elastic delay interval provides a time range constraint for the subsequent step S22 to calculate the specific adaptive delay increment within this interval. If the load characteristic information provided by step S10 is missing, step S21 will be unable to set the elastic delay interval according to the differences in load weight and will only degenerate into the traditional fixed delay tuning method, losing the ability to adaptively allocate timing.

[0067] Step S22: Within the elastic time delay interval, calculate the time slot bubble occupancy width based on the load impedance inertia index. The larger the load impedance inertia index, the wider the time slot bubble occupancy width. Generate an adaptive delay increment based on the time slot bubble occupancy width.

[0068] The time slot bubble occupancy width is a concrete concept, likening the connection waiting process of a feeder terminal to a bubble occupying a certain width on the reference recovery time axis. The width of the bubble represents the length of exclusive time that the feeder terminal needs to reserve on the time axis. The physical meaning of the time slot bubble occupancy width is as follows: When a feeder terminal connects, the inrush current generated by the start-up of its downstream cold load will cause a brief voltage dip on the upstream bus. This voltage dip takes a certain amount of time to recover from. During this period, the upstream power supply is bearing the impact load from this feeder segment. If other feeder terminals also perform connection actions during this period, the newly added cold start inrush current will superimpose with the preceding inrush current that has not yet subsided, causing overcurrent in the upstream power supply. Therefore, each feeder terminal needs to reserve an exclusive time window for itself on the time axis, i.e., the time slot bubble occupancy width, within which it will not have timing collisions with other feeder terminals.

[0069] The feeder terminal calculates the time slot bubble occupancy width based on the load impedance inertia index read from the non-volatile memory unit. The calculation logic is as follows: the larger the load impedance inertia index, the heavier the load in that section, the larger the cold start inrush current generated after connection, the longer the inrush current duration, and the longer the time required for the upstream power supply to recover from the impact. Therefore, a wider time slot bubble occupancy width needs to be reserved for this feeder terminal. Conversely, the smaller the load impedance inertia index, the lighter the load in that section, the smaller the inrush current amplitude and the shorter the duration. The upstream power supply can recover from the impact quickly, so a narrower time slot bubble occupancy width needs to be reserved for this feeder terminal. The relationship between the time slot bubble width and the load impedance inertia index can be calculated using a linear proportional relationship. For example, the time slot bubble width is equal to the load impedance inertia index multiplied by a preset unit load time slot coefficient. The unit load time slot coefficient is a conversion constant that converts the dimensionless load impedance inertia index into the time slot bubble width with a time dimension. This constant is determined based on the actual operating experience of the distribution network or simulation analysis. For example, the unit load time slot coefficient can be set to a value between 100 milliseconds and 500 milliseconds. A larger value is taken when there are many feeder segments in the distribution network and a larger time interval is required, and a smaller value is taken when there are few feeder segments and fast power restoration is required. Taking a unit load time slot coefficient of 200 milliseconds as an example, if the load impedance inertia index of a certain feeder segment is 5, then the time slot bubble width of that segment is 5 × 200 milliseconds = 1000 milliseconds.

[0070] Based on the slot bubble occupancy width, the feeder terminal generates an adaptive delay increment. This adaptive delay increment is an additional delay superimposed on the preset base delay, used to dynamically adjust the feeder terminal's connection position on the reference recovery time axis according to the load intensity. There is a positive correlation between the adaptive delay increment and the slot bubble occupancy width: a wider slot bubble occupancy width indicates a heavier load on the feeder segment and a longer reserved exclusive time; the adaptive delay increment is assigned a larger positive value, automatically shifting the feeder terminal's position on the reference recovery time axis backward, delaying its connection time to avoid the period of weak grid capacity during the initial recovery phase. Conversely, a narrower slot bubble occupancy width indicates a lighter load on the feeder segment and a shorter reserved exclusive time; the adaptive delay increment is zero or a small positive value, allowing the feeder terminal to connect earlier to accelerate the power restoration process. The adaptive delay increment is calculated by directly using the slot bubble occupancy width of the feeder terminal section as the adaptive delay increment. Since the width of the time slot bubble is proportional to the load impedance inertia index, combined with... Figure 3 As shown, the magnitude of the load impedance inertia index directly determines the morphological characteristics of the time slot bubble: for lightly loaded sections with a smaller load impedance inertia index, the corresponding time slot bubble is narrower, i.e. Figure 3The text indicates a pattern of "small exponent, narrow bubble"; however, for heavily loaded sections with a large load impedance inertia exponent, the corresponding time slot bubble widens significantly. Figure 3 The "larger exponent, wider bubble" designation indicates a direct proportional relationship. This means the adaptive delay increment of heavily loaded sections is naturally greater than that of lightly loaded sections, causing the connection position of heavily loaded sections to automatically shift backward on the time axis, while the connection position of lightly loaded sections shifts relatively forward. From a global perspective, multiple feeder segments on the same feeder line have different adaptive delay increments due to their varying load impedance inertia exponents. This is equivalent to each feeder segment automatically and implicitly sorting itself according to its load weight. Figure 3 As shown in the distribution on the mid-base recovery time axis, the light load segment is allocated to an earlier time closer to zero due to its narrow bubble and small delay, followed by the medium load segment, and the heavy load segment is allocated to a later time farther from zero due to its wide bubble and large delay. Figure 3 This intuitively demonstrates the timing logic of prioritizing access to lightly loaded sections and delaying access to heavily loaded sections, thereby achieving the orderly release of inrush impacts rather than their concentrated accumulation. Since the range of the load impedance inertia index is bounded, the value of the time slot bubble occupancy width also falls within a limited range. This range corresponds to the elastic delay interval set in step S21, ensuring that the adaptive delay increment does not exceed the boundary of the elastic delay interval.

[0071] Step S22 establishes a positive correlation between the time slot bubble occupancy width and the load impedance inertia index, ensuring that heavier load sections require a longer exclusive time on the time axis. This design directly transforms load characteristic information into the basis for timing resource allocation, achieving dynamic adaptation between access timing and actual load conditions. The generation of adaptive delay increments allows each feeder terminal to autonomously adjust its access position based on its own load weight, with lightly loaded sections moving forward and heavily loaded sections moving backward. This adaptive feature eliminates the need for manual pre-tuning of fixed delay parameters and reliance on the communication network to obtain global load information; the feeder terminal can determine its relative position on the time axis solely based on its locally calculated load impedance inertia index. Step S22 and Step S21 form a progressive relationship. The flexible delay interval set in Step S21 defines the possible access time range boundary for the feeder terminal. Step S22 independently calculates the time slot bubble occupancy width and generates adaptive delay increments based on the load impedance inertia index of its own section. The two steps work together to achieve a progressive refinement from coarse-grained time range division to fine-grained time position determination. If step S22 is missing, the flexible delay interval set in step S21 can only provide a time range constraint and cannot determine the specific access time. The feeder terminal will not be able to obtain accurate delay parameters to perform the access action.

[0072] Step S23: Extract the unique physical code of the feeder terminal, perform a hash operation on the unique physical code of the feeder terminal to generate a discretized jitter factor, and add the preset base delay, adaptive delay increment and discretized jitter factor to generate the target access time threshold.

[0073] The discretization jitter factor is introduced to prevent timing collisions between two or more feeder segments with similar load characteristics due to the calculation of identical or extremely similar adaptive delay increments. In actual distribution networks, multiple feeder segments with similar load characteristics may exist on the same feeder. The load impedance inertia exponents of these segments are close, and the adaptive delay increments calculated in step S22 are also extremely close. If this delay increment is directly used as the connection time parameter, these feeder terminals may perform connection actions at almost the same time, causing inrush current superposition. The discretization jitter factor is a tiny time quantity on the order of microseconds or milliseconds, superimposed on the adaptive delay increment, forcibly separating feeder terminals with similar load characteristics in micro-timing. The generation of the discretization jitter factor depends on the unique physical code of the feeder terminal. The feeder terminal reads its factory-installed unique physical code from its underlying hardware registers or non-volatile memory. This unique physical code is the feeder terminal's Media Access Control (MAC) address or hardware serial number, and it is absolutely unique across the entire network, remaining unchanged regardless of the feeder terminal's operating status, load, or software version updates. The MAC address is the physical layer identifier of the feeder terminal's network interface, programmed into the network interface chip by the manufacturer during production. It follows globally unified address allocation rules, ensuring that no two feeder terminals have the same MAC address. The hardware serial number is a unique identifier assigned to the feeder terminal at the factory, numbered sequentially by the manufacturer or generated using a random algorithm, also ensuring network-wide uniqueness.

[0074] The feeder terminal uses a preset hash mapping algorithm to perform numerical calculations on the read unique physical code of the device, generating a discretized jitter factor. A hash mapping algorithm is a deterministic algorithm that converts input data of arbitrary length into a fixed-length output value; the same input will inevitably produce the same output, and different inputs will very likely result in different outputs. The specific implementation of the hash mapping algorithm used in the feeder terminal is as follows: the unique physical code of the device is converted into a decimal value; this decimal value is divided by the preset maximum jitter time window in milliseconds, and the remainder is taken. The result is the remainder after dividing the dividend by the divisor, and the remainder ranges from 0 to the divisor minus 1. The maximum jitter time window is a preset time parameter that represents the maximum possible value of the discretized jitter factor; for example, the maximum jitter time window can be set to 100 milliseconds. Through modulo operation, the unique physical code of the device is mapped to a value between zero and the maximum jitter time window; this value is the discretized jitter factor. Since the unique physical codes of different feeder terminals are necessarily different, the remainders obtained after modulo operation will also fall at different positions within the maximum jitter time window. This ensures that even if the load impedance inertia indexes of two feeder terminals are exactly the same and the adaptive delay increments are exactly equal, their discretized jitter factors are still different, and the final target access time thresholds are also different, thus achieving forced peak shifting at the micro-time level.

[0075] The feeder terminal adds the preset base delay, the adaptive delay increment calculated in step S22, and the discretized jitter factor generated in step S23 to finally generate the target access time threshold. The base delay is a pre-tuned fixed delay amount, the value of which is determined based on the number of feeder segments in the distribution network and the capacity characteristics of the upstream power supply. A typical value ranges from 3 to 10 seconds, serving as a common benchmark for the access delay of all feeder terminals. This ensures that even feeder terminals with the minimum load impedance inertia index will not immediately connect after single-sided voltage recovery, but will wait for a certain base delay to confirm the stability of voltage recovery. The adaptive delay increment is a differentiated delay amount dynamically calculated based on the load impedance inertia index, allowing feeder terminals with different load characteristics to be naturally separated on the time axis. The discretized jitter factor is a small time offset generated based on the unique physical code of the device, used to break the timing overlap between feeder terminals with similar load characteristics. The target access time threshold obtained by adding the three together is a dynamic value accurate to the millisecond level. The target access time thresholds of each feeder terminal in the entire network are different, providing a comparison benchmark for the integral access control in the subsequent step S30.

[0076] Step S23, which generates a discrete jitter factor using a unique physical code and hash mapping algorithm, leverages the inherent uniqueness of the feeder terminal hardware to introduce a randomized separation mechanism for timing allocation, eliminating the possibility of timing collisions between feeder terminals with similar load characteristics. The factory-fixed nature of the unique physical code ensures that the discrete jitter factor remains unchanged throughout the feeder terminal's entire lifecycle. The discrete jitter factor generated by the same feeder terminal remains the same under different fault recovery scenarios. This determinism guarantees the predictability and repeatability of access timing, facilitating fault analysis and system debugging by maintenance personnel. The modulo operation of the hash mapping algorithm evenly distributes the unique physical code within the maximum jitter time window, avoiding the aggregation of discrete jitter factors at certain specific values, resulting in a uniform distribution of the target access time threshold across all feeder terminals in the network on the time axis. The target access time threshold is designed with three parts: basic delay, adaptive delay increment, and discretized jitter factor. This design achieves multi-level timing allocation from coarse-grained to fine-grained: basic delay provides a common time reference, adaptive delay increment is macroscopically separated according to load weight, and discretized jitter factor eliminates residual timing collision risks at the micro level. The three work together to ensure that the access times of all feeder terminals in the entire network are completely staggered on the time axis.

[0077] Step S20 achieves self-organized timing allocation among multiple feeder terminals under no-communication conditions by unifying the reference recovery time axis, setting load-related parameters for the elastic delay interval, calculating the time slot bubble occupancy width and adaptive delay increment differently, and implementing a forced peak-shaving mechanism for the discretized jitter factor. Traditional voltage-time type feeder automation uses a fixed stepped delay setting method. The access delay parameters of all feeder terminals in the network are pre-set and fixed before commissioning, and cannot be dynamically adjusted according to the actual load conditions. When the distribution network operation mode changes or the load distribution shifts, the pre-set fixed delay parameters may no longer be suitable for the actual operating conditions, resulting in unreasonable access timing arrangements and increased risk of inrush current superposition. Step S20 enables feeder terminals to autonomously calculate access delay parameters based on the load characteristic information captured before the voltage loss. The access timing changes dynamically with the load weight rather than executing the preset value immutably. When the load distribution changes, the load impedance inertia index changes accordingly, which in turn causes the adaptive delay increment and the target access time threshold to be adjusted accordingly, realizing automatic tracking and adaptation of the access timing to load changes. The self-organizing timing allocation mechanism prioritizes the connection of lightly loaded sections and postpones the connection of heavily loaded sections. Inrush surges are released in an orderly manner from small to large rather than concentrated at similar times. The upstream power supply can obtain sufficient recovery time after each inrush surge to cope with the next surge. This orderly release mechanism fundamentally reduces the risk of upstream power supply overcurrent tripping caused by inrush surge superposition, making the distribution network fault recovery process more stable and controllable. The target access time threshold provides a precise endpoint for the voltage dip feedback integral control in the subsequent step S30. When the upstream power source is detected to be under impact load, step S30 pauses the time integral accumulation and resumes accumulation after the grid returns to stability until the target access time threshold is reached. This design makes the macro-sequence arrangement determined in step S20 complementary to the micro-real-time adjustment implemented in step S30. The macro-sequence arrangement ensures the overall peak-shaving distribution of each feeder terminal on the time axis, while the micro-real-time adjustment ensures that each feeder terminal only performs the access action when the grid is truly stable. The synergy of the two makes the distribution network fault recovery process both globally coordinated and locally adaptable, effectively smoothing the peak impact current of the entire network.

[0078] Step S30: Start the timing integrator. During the operation of the timing integrator, monitor the voltage dip event of the incoming bus in real time and synthesize the congestion warning signal. Perform time integration freeze and unfreeze operations on the timing integrator according to the congestion warning signal. When the accumulated time integration value of the timing integrator reaches the target access time threshold, an access drive pulse is issued.

[0079] Step S30 addresses the risk of voltage fluctuations caused by insufficient upstream power supply capacity or the start-up of large loads on nearby lines during the connection process. In traditional voltage-time type feeder automation logic, the feeder terminal uses a countdown timer to perform delayed connection upon power restoration. Once the timer starts, it counts down at a fixed rate, and the connection action is performed after the preset delay regardless of changes in the grid state. This rigid timing mechanism has a fundamental flaw: when multiple sectionalizing switches on the same feeder sequentially restore power, the inrush current generated by the downstream cold load of the preceding switch will cause a brief voltage dip on the upstream bus. At this time, the upstream power supply is under impact load. If the timer of the subsequent switch happens to reach its full count and triggers connection, the newly added cold-start inrush current will overlap with the inrush current of the preceding switch, causing the upstream power supply overcurrent protection to trip again. Step S30 upgrades the traditional timing logic to integral logic, introducing voltage stability as an adjustment signal for time accumulation. The timer integrator only accumulates time when the grid is stable and pauses accumulation when the grid is under impact load, ensuring that the feeder terminal only performs the connection action when the grid is truly capable of carrying the load.

[0080] Further, see Figure 4 Step S30 includes:

[0081] Step S31: When the feeder terminal detects a single-sided voltage recovery event, it monitors the voltage waveform of the incoming bus in real time to further confirm whether the voltage of the incoming bus is within the stable threshold range and continues to maintain the preset start-up stability confirmation time. If the condition is met, the timing integrator is started and the time integration value is initialized to zero. Otherwise, the voltage waveform of the incoming bus is monitored until the voltage stabilizes before starting.

[0082] Specifically, the timing integrator is a software module implemented within the feeder terminal logic processor, and its operating mechanism differs fundamentally from that of a traditional countdown timer. A traditional countdown timer counts down at fixed intervals after startup, continuing to count until zero regardless of changes in external conditions. Its behavior is entirely determined by preset delay parameters and is unaffected by real-time grid conditions. The timing integrator, however, uses an accumulation counting method, gradually accumulating the time integral value from zero. Its accumulation is controlled by real-time monitoring enable conditions. The enable condition is that the incoming bus voltage remains within a preset startup stability confirmation time within a stable threshold range. Accumulation only occurs when the enable condition is met. This design allows the timing integrator's accumulation process to be interrupted and resumed by external events, thus providing responsiveness to real-time grid conditions. The time integral value is the accumulated amount maintained internally by the timing integrator, using standard time elapsed units as the basic accumulation unit. For example, after each control cycle, the timing integrator adds the duration of that control cycle to the time integral value. The control cycle is typically set to several milliseconds to tens of milliseconds. When the timing integrator is started, the time integral value is initialized to zero, and then gradually accumulates as long as the enable conditions are met, until the target access time threshold is reached.

[0083] After detecting a single-sided voltage recovery event, the feeder terminal does not immediately activate the timing integrator but instead enters the voltage stability confirmation stage. The method for determining a single-sided voltage recovery event is the same as in step S21, i.e., the feeder terminal detects that the incoming bus voltage of the switch it controls has recovered from an undervoltage state to a voltage-enabled state. A single-sided voltage recovery event only indicates that the voltage has changed from an undervoltage state to a voltage-enabled state, but the initial stage of voltage recovery may involve transient overvoltage, undervoltage, or oscillation fluctuations. Such transient processes should not be used as the activation timing for the timing integrator. The input bus voltage continuously maintaining a preset activation stability confirmation time within the stability threshold range serves as the enable condition for the timing integrator to accumulate the integral value. The stability threshold range is a preset voltage range used to determine whether the input bus voltage is in a normal stable state. The lower limit of the stability threshold range is set as a specific percentage of the rated voltage, for example, 90% of the rated voltage, representing the lowest acceptable level of voltage amplitude; the upper limit of the stability threshold range is set as a specific percentage of the rated voltage, for example, 110% of the rated voltage, representing the highest acceptable level of voltage amplitude. The feeder terminal determines that the voltage has stabilized only when the amplitude of the incoming bus voltage is between the lower and upper limits of the stable threshold range and remains within the preset start-up stabilization confirmation time. Only then does the timing integrator meet the voltage enable condition and can accumulate the time integral value at the normal rate. The start-up stabilization confirmation time is the waiting time calculated from the moment the voltage first enters the stable threshold range. It is used to exclude situations where the voltage briefly enters the normal range during the initial recovery phase and then deviates due to transient fluctuations. An exemplary setting is 100 milliseconds to 500 milliseconds, with a typical value of 200 milliseconds. If the voltage deviates from the stable threshold range during the start-up stabilization confirmation time, the timing restarts until the voltage remains stable.

[0084] Once voltage stability is confirmed, the feeder terminal activates the timing integrator and initializes the time integral value to zero. This design ensures that the timing integrator only starts timing after the grid has truly stabilized, avoiding the accumulation of the time integral value during the transient fluctuation phase at the beginning of voltage recovery. Transient phenomena that may occur at the beginning of voltage recovery include: brief overvoltage caused by inrush current generated when the upstream switch is connected, voltage oscillations during the charging process of the line distributed capacitor, and voltage dips caused by sudden load connection. These transient processes typically last from tens to hundreds of milliseconds. Setting the stability confirmation time effectively excludes them from the timing integrator's activation timing. Simultaneously with activating the timing integrator, the feeder terminal initializes the time integral value to zero, ensuring that the timing integrator starts operating from a uniform initial state during each fault recovery process, eliminating interference from historical accumulation on the current connection timing.

[0085] Step S31 replaces the traditional countdown timer with a timing integrator, transforming the access delay from a fixed duration to a variable effective accumulated time. The traditional countdown timer's delay is an absolute time, flowing at a fixed rate regardless of the grid's state. The timing integrator's delay is an effective time, only counting periods when the grid is stable, excluding periods of instability. This transformation allows the access delay to automatically adapt to the actual grid recovery process: when grid recovery is smooth and each feeder segment is connected sequentially and stably, the timing integrator continuously accumulates, and the access delay approaches the target access time threshold; when significant voltage fluctuations occur during grid recovery, the timing integrator pauses accumulation, and the access delay automatically extends, waiting for the grid to stabilize before resuming timing. The design uses whether the incoming bus voltage is within a stable threshold range as an enabling condition, allowing the feeder terminal to sense the current load status of the upstream power source. When the upstream power source is experiencing impact loads, causing the bus voltage to be low or fluctuate significantly, the feeder terminal automatically postpones connection to avoid adding new impact loads. The real-time voltage monitoring initiated in step S31 provides a continuous data source for the subsequent step S32 to detect voltage sag events, enabling the detection of voltage sag events to be performed in real time throughout the entire operation of the timing integrator.

[0086] Step S32: During the operation of the timing integrator, capture voltage sag events and extract voltage sag depth and voltage sag duration, and weight the voltage sag depth and voltage sag duration to synthesize a congestion warning signal.

[0087] When the timing integrator is operating normally and no voltage sag event is detected, the congestion warning signal remains at zero, and the timing integrator continues to accumulate the time integral value according to the enable condition defined in step S31. The feeder terminal analyzes the voltage waveform in each control cycle to determine if a voltage sag event exists. If the voltage waveform remains stable within the stability threshold range, it is determined that no voltage sag event exists, and the timing integrator continues to accumulate normally. If a voltage sag event is detected, the voltage sag depth and duration are extracted and synthesized into a congestion warning signal. A voltage sag event refers to a transient process in which the incoming bus voltage drops from a normal level to a lower level within a short period and then recovers to a normal level. In distribution network fault recovery scenarios, voltage sag events are usually caused by inrush currents generated by cold loads connected to other sectionalizing switches on the same feeder. The inrush current generates a momentary voltage drop on the upstream bus, causing a brief drop in bus voltage. After the inrush current decays, the bus voltage recovers to a normal level. See also... Figure 5 This is a schematic diagram of voltage dip event feature parameter extraction provided in the embodiments of this application. Figure 5The coordinate system uses the horizontal axis as the time axis and the vertical axis as the voltage amplitude axis, visually displaying the waveform trajectory of the incoming bus voltage over time. The figure clearly marks the normal voltage line and the lower limit of the stable threshold range, illustrating the physical process of voltage drops due to impact loads. The feeder terminal continuously acquires the incoming bus voltage waveform through an electromagnetic voltage transformer, digitizes the voltage waveform using its analog acquisition unit, and then performs real-time analysis of the digitized voltage waveform by the feeder terminal's logic processor to detect any voltage dips.

[0088] Voltage sag events are detected using an amplitude comparison method to determine event boundaries. The voltage sag depth and duration are continuously calculated as dynamically updated parameters during the event. The feeder terminal calculates the instantaneous amplitude of the incoming bus voltage in real time, combined with... Figure 5 As shown, when the instantaneous amplitude drops from above the lower limit of the stable threshold range to below the lower limit of the stable threshold range, the feeder terminal determines that a voltage sag event has begun, records the start time of the event as the sag start time, records the voltage amplitude at the sag start time as the reference voltage amplitude, and starts timing. Simultaneously, it continuously tracks voltage amplitude changes and records the lowest voltage amplitude currently detected. When the instantaneous amplitude recovers from below the lower limit of the stable threshold range to above the lower limit of the stable threshold range and maintains a preset recovery confirmation time, the feeder terminal determines that the voltage sag event has ended, stops timing, and resets the congestion warning signal to zero. The recovery confirmation time is used to avoid misjudgment when the voltage briefly recovers and then drops again; for example, it can be set to 20 milliseconds. The voltage sag depth is the difference between the reference voltage amplitude and the lowest voltage amplitude currently detected, such as... Figure 5 The "voltage sag depth" indicated in the figure is the vertical distance from the baseline where the normal voltage is located to the lowest point of the voltage waveform. This parameter changes in real time as the lowest voltage amplitude is updated during the voltage sag event. This parameter quantifies the severity of the voltage sag; a larger sag depth indicates a heavier impact load on the upstream power supply. The voltage sag duration is the length of time from the start of the sag to the current time, as shown in the figure. Figure 5 As indicated by the “Voltage Sag Duration”, it is the time span during which the voltage waveform remains below the lower limit of the stable threshold range (dashed line). This parameter continuously increases over time during the voltage sag event. This parameter quantifies the time span of the voltage sag; a longer duration indicates that the upstream power supply requires a longer time to recover from the impact and that the current carrying capacity is weaker.

[0089] The feeder terminal synthesizes a congestion warning signal by weighting the voltage sag depth and voltage sag duration. The congestion warning signal is a comprehensive quantitative indicator, its magnitude representing the instantaneous load surge pressure experienced by the upstream power source. The congestion warning signal is synthesized using a weighted summation method. To eliminate dimensional differences, the voltage sag depth and voltage sag duration must first be normalized. The specific synthesis method is as follows: divide the voltage sag depth by the rated voltage to obtain the per-unit value of the voltage sag depth; if the result is greater than 1, it is set to 1. Divide the voltage sag duration by a preset baseline sag duration to obtain the per-unit value of the voltage sag duration; if the result is greater than 1, it is set to 1. Then, multiply the per-unit value of the voltage sag depth by a preset depth weighting coefficient, and multiply the per-unit value of the voltage sag duration by a preset time weighting coefficient. The products of these two values ​​are then added to obtain the congestion warning signal. The baseline sag duration is determined based on the typical duration of inrush current during cold-state load startup in the distribution network; for example, it can be set to 200 milliseconds. The congestion warning signal is a dimensionless value, ranging from 0 to the sum of the depth weighting coefficient and the time weighting coefficient. The depth and time weighting coefficients are set based on actual operating experience of the distribution network. The relative magnitudes of these two coefficients reflect the relative importance of voltage sag depth and voltage sag duration in assessing the degree of grid congestion. For example, when the upstream power supply capacity margin of the distribution network is small, the voltage sag depth has a more significant impact on the degree of congestion, and the depth weighting coefficient can be appropriately increased; when the inrush current duration of cold load startup in the distribution network is long, the voltage sag duration has a more significant impact on the degree of congestion, and the time weighting coefficient can be appropriately increased. In a typical configuration, the depth weighting coefficient can be set to 0.6, and the time weighting coefficient can be set to 0.4, with a sum of 1. When it is necessary to emphasize the impact of voltage sag depth, the depth weighting coefficient can be increased to 0.8, and the time weighting coefficient can be correspondingly decreased to 0.2. The congestion warning signal, as a dynamically calculated quantity, changes in real time as voltage sag events occur and subside. During the duration of a voltage sag event, the feeder terminal updates the congestion warning signal in real time within each control cycle according to the weighted synthesis method described above, based on the real-time updated duration and depth of the voltage sag. Therefore, when a voltage sag event continues, the congestion warning signal gradually increases with the increase in the duration and depth of the voltage sag. When the voltage sag event ends and the voltage returns to normal, the feeder terminal resets the congestion warning signal to zero. At this time, the congestion warning signal naturally meets the condition of being below the congestion relief and return threshold, providing a basis for the subsequent step S33 to determine whether to unfreeze the timing integrator.

[0090] Step S32, through the design of monitoring voltage dip events and synthesizing congestion warning signals, enables feeder terminals to sense inrush current impacts caused by the connection of other sectionalizing switches on the same feeder. In traditional voltage-time-based feeder automation logic, each feeder terminal only focuses on whether its own delay has been completed, without caring about the connection status of other feeder terminals or the load status of the upstream power supply, lacking the ability to perceive the overall grid status. Step S32 enables feeder terminals to indirectly obtain the load information of the upstream power supply through the common signal of bus voltage fluctuations: when the bus voltage dips, it indicates that other loads have just been connected to the grid and the upstream power supply is experiencing impact loads; when the bus voltage remains stable, it indicates that the upstream power supply currently has sufficient load capacity. This design achieves the effect of mutual perception between multiple feeder terminals without communication. Each feeder terminal can infer the current status of the upstream power supply simply by monitoring the common bus voltage fluctuations, thereby autonomously adjusting its own connection timing to avoid timing collisions with other feeder terminals. The weighted synthesis design of the congestion warning signal compresses information from two dimensions—voltage sag depth and voltage sag duration—into a single comprehensive index. This retains the core information needed to assess grid congestion while simplifying the complexity of subsequent decision-making logic, enabling feeder terminals to complete congestion status assessment with minimal computational resources. Steps S32 and S31 work closely together: Step S31 initiates voltage monitoring and manages the routine accumulation of the timing integrator, while Step S32 identifies abnormal voltage sag events in the voltage monitoring data and synthesizes the congestion warning signal. Both provide input for the integration freeze and unfreeze determination in Step S33. When no voltage sag event is detected, the congestion warning signal is zero, and the timing integrator continues to accumulate. Once a voltage sag event is detected, the congestion warning signal rises as the event progresses, providing a basis for triggering the integration freeze operation in Step S33.

[0091] Step S33: The congestion warning signal is compared with the preset safety warning threshold and congestion relief return threshold by hysteresis, and the time integration freeze operation and time integration unfreeze operation are performed on the time integrator respectively.

[0092] Specifically, this includes: when the congestion warning signal exceeds the safety warning threshold, performing a time integration freeze operation on the time integrator, pausing the time integrator and keeping the current time integration value unchanged; continuously calculating the congestion warning signal while in the time integration freeze state; and after the congestion warning signal is lower than the congestion mitigation and return threshold and the incoming bus voltage remains within the stable threshold range for a preset unfreezing and stabilization confirmation time, performing a time integration unfreezing operation on the time integrator, and the time integrator continues to accumulate from the time integration value before the time integration freeze; the congestion mitigation and return threshold is less than the safety warning threshold.

[0093] The safety warning threshold is a pre-set upper limit for congestion warning signals, representing the impact load pressure boundary that the upstream power supply can withstand. When the congestion warning signal exceeds the safety warning threshold, it indicates that the current pressure carried by the upstream power supply has exceeded the safe range, and it is not advisable to add new impacts. When the congestion warning signal does not exceed the safety warning threshold, the time integrator continues to accumulate the time integral value. The setting of the safety warning threshold is determined based on the capacity characteristics and overcurrent protection settings of the upstream power supply in the distribution network. It is necessary to ensure that when the congestion warning signal reaches the safety warning threshold, the upstream power supply still has sufficient margin to cope with possible unexpected impacts without triggering overcurrent protection. The quantitative determination method for the safety warning threshold is as follows: According to the normalization synthesis rule of the congestion warning signal, the theoretical maximum value of the congestion warning signal is equal to the sum of the depth weighting coefficient and the time weighting coefficient. The safety warning threshold is set as a specific percentage of this theoretical maximum value. For example, when the depth weighting coefficient is 0.6, the time weighting coefficient is 0.4, and the sum of the two is 1, the safety warning threshold can be set to a value between 0.5 and 0.7, with a typical value of 0.6, indicating that when the congestion warning signal reaches 60% of its theoretical maximum value, the integral freeze operation is triggered. The congestion mitigation and return threshold is a pre-set lower limit of the congestion warning signal, representing the judgment boundary for the upstream power supply to recover from the impact to a safe state. When the congestion warning signal falls below the congestion mitigation and return threshold, it indicates that the upstream power supply has recovered from the previous impact and has the ability to bear the new load. The congestion mitigation return threshold is less than the safety warning threshold. The difference between the two thresholds forms a hysteresis interval. The hysteresis interval is set to prevent the timing integrator from repeatedly starting and stopping due to small fluctuations in the congestion warning signal near the threshold. For example, the congestion mitigation return threshold can be set to 85% of the safety warning threshold.

[0094] During the normal accumulation of time integral values ​​by the time integrator, the feeder terminal compares the congestion warning signal synthesized in step S32 with the safety warning threshold in real time. Once the value of the congestion warning signal exceeds the safety warning threshold, the feeder terminal determines that the upstream power grid is in a state of instantaneous congestion and immediately executes a time integral freeze operation. The specific execution process of the time integral freeze operation is as follows: the logic processor of the feeder terminal sends a freeze command to the time integrator. After receiving the freeze command, the time integrator pauses the accumulation operation, keeps the current time integral value unchanged, and the feeder terminal enters a logic hover state. The logic hover state refers to the working mode in which the feeder terminal suspends the accumulation of time integrals, only continuously monitors the voltage waveform of the incoming bus, and waits for the unfreezing conditions to be met. In the logic hover state, the feeder terminal does not issue any access commands to the switch operating mechanism to avoid superimposing new access impacts when the upstream power supply is under excessive pressure. The triggering of the time integration freeze operation is instantaneous. The delay between the congestion warning signal exceeding the safety warning threshold and the time integrator pausing accumulation is controlled within a single control cycle, ensuring that the feeder terminal can respond in a very short time after a voltage dip event occurs.

[0095] During the time-integrated freeze state, the feeder terminal continuously monitors the incoming bus voltage waveform and calculates the congestion warning signal in real time. Since the congestion warning signal is a dynamic variable calculated in real time based on the voltage sag depth and duration, the voltage sag event ends and the congestion warning signal is reset to zero once the incoming bus voltage gradually recovers from the sag to a normal level and maintains a recovery confirmation time. The feeder terminal compares the real-time calculated congestion warning signal with the congestion mitigation and return threshold to determine whether the upstream power grid has recovered from the congestion state. Because the congestion mitigation and return threshold is lower than the safety warning threshold, the congestion warning signal must drop below the congestion mitigation and return threshold to meet part of the unfreezing conditions. This hysteresis design avoids frequent freezing and unfreezing of the timer integrator when the congestion warning signal fluctuates slightly near the safety warning threshold. In addition to the congestion warning signal falling below the congestion mitigation and return threshold, the unfreezing conditions also require the incoming bus voltage to maintain a preset unfreezing stability confirmation time within a stable threshold range. The thawing stabilization confirmation time is an additional waiting time calculated from the point when the congestion warning signal drops below the congestion mitigation return threshold and the incoming bus voltage enters the stable threshold range. It is used to confirm the stability of voltage recovery rather than a transient rise. The thawing stabilization confirmation time is set based on the typical decay time of inrush current starting from a cold load in the distribution network. For example, it can be set to 500 milliseconds to 2 seconds, with a typical value of 1 second, ensuring that the inrush current has sufficiently decayed and that the voltage recovery is indeed stable rather than a transient fluctuation.

[0096] Only when the congestion warning signal drops below the congestion mitigation and return threshold and the incoming bus voltage remains within the stable threshold range for a certain period of time before the freeze is lifted, does the feeder terminal determine that the congestion has been completely relieved and execute a time-integral unfreezing operation. The specific execution process of the time-integral unfreezing operation is as follows: the feeder terminal's logic processor sends a unfreezing command to the timing integrator. Upon receiving the unfreezing command, the timing integrator continues to accumulate from the time integral value before the pause, and the feeder terminal exits the logic hover state and resumes the normal integral control process. The key characteristic of the time-integral unfreezing operation lies in the preservation and continuation of the time integral value: the time integral value remains unchanged during the freeze period, and after unfreezing, it continues to accumulate from the value before the freeze rather than resetting to zero. This design ensures that the effective time accumulated during the freeze period is not lost, and the feeder terminal does not need to start timing again from the beginning, thus avoiding the problem of indefinitely extended access delay due to multiple freezes.

[0097] Step S33 introduces a hysteresis mechanism into the control logic through a hysteresis comparison design between the safety warning threshold and the congestion mitigation return threshold. The hysteresis mechanism works as follows: when the congestion warning signal rises from below the safety warning threshold to above the safety warning threshold, freezing is immediately triggered. However, unfreezing does not occur immediately when the congestion warning signal drops below the safety warning threshold; instead, it requires the signal to further drop below the congestion mitigation return threshold before unfreezing. This design avoids the jitter phenomenon caused by the timing integrator frequently switching between frozen and unfrozen states when the congestion warning signal oscillates slightly near the safety warning threshold. This jitter increases the uncertainty of the access timing, which is detrimental to the smooth and controllable fault recovery process. The introduction of a unfreezing stabilization confirmation time further enhances the reliability of the unfreezing determination, ensuring that the feeder terminal resumes integration only after confirming that the voltage has stabilized, avoiding false freezing caused by a brief voltage rebound followed by another dip. The time integration freeze and unfreeze mechanism enables the accumulation process of the time integrator to be dynamically adjusted by the real-time status of the power grid. It allows for normal accumulation when the power grid is stable and to pause accumulation when the power grid is congested, thereby automatically adapting the access delay to the actual recovery process of the power grid without the need for manual intervention or master station coordination.

[0098] Step S34: The current accumulated time integral value of the time integrator is compared with the target access time threshold in real time. When the time integral value reaches the target access time threshold, an access drive pulse is sent to the switch operation mechanism.

[0099] The logic processor of the feeder terminal reads the current time integral value of the timing integrator in each control cycle and compares it with the target access time threshold calculated in step S23. The target access time threshold is a dynamic value accurate to the millisecond level, calculated in step S20 based on parameters such as load impedance inertia index and unique physical code of the equipment. The target access time threshold is different for each feeder terminal in the entire network. The comparison judgment condition is that the time integral value is greater than or equal to the target access time threshold. Only when this condition is met will the feeder terminal determine that the adaptive power-on delay logic condition is met. If the time integral value is less than the target access time threshold, the feeder terminal determines that the adaptive power-on delay logic condition is not met, does not issue an access drive pulse, but maintains the current operating state, returns to the main logic loop, and reads the latest time integral value of the timing integrator again for comparison in the next control cycle. The access drive pulse is an electrical signal issued by the feeder terminal to the switch operating mechanism it controls, used to trigger the closing action of the circuit breaker. The switch operating mechanism is an electric or electromagnetic drive device installed inside the pole-mounted switch body. After receiving the access drive pulse output from the feeder terminal, it performs a mechanical action to close the main contacts of the circuit breaker. The control signal output port of the feeder terminal is connected to the access coil of the switch operating mechanism via a control signal connector. When the feeder terminal determines that the access conditions are met, it applies a drive pulse to the control signal output port. The drive pulse is transmitted to the access coil via the connector, energizing the coil and generating electromagnetic force to drive the operating mechanism to close the main contacts of the circuit breaker. The duration and amplitude of the access drive pulse are determined based on the technical parameters of the switch operating mechanism, ensuring that the access coil receives sufficient energizing energy to reliably complete the access action. After the access drive pulse is issued, the feeder terminal confirms whether the access action has been successfully executed by monitoring the switch position feedback signal. The switch position feedback signal is provided by the auxiliary contacts of the switch body and input to the feeder terminal via the control signal connector.

[0100] Step S34 converts the time integral value of the timing integrator into the actual access action. Reaching the target access time threshold is the sole condition for triggering the access drive pulse. This condition ensures that the timing of the access action is jointly determined by the target access time threshold calculated in step S20 and the integral control implemented in step S30. The target access time threshold embodies macroscopic adaptive timing allocation, staggering the distribution of feeder terminals with different load characteristics on the time axis based on the load impedance inertia index. Integral control embodies microscopic real-time adjustment, dynamically adjusting the accumulation process of the effective accumulated time according to the real-time state of the power grid. Through their combined action, the feeder terminal executes the access action near the target time and when the power grid is in a stable state, satisfying both the macroscopic timing requirements of peak-shaving access and ensuring that each access occurs at a microscopic moment when the power grid truly has the capacity to carry the load. The integral control implemented in step S30 provides micro-level dynamic adjustment for the macro-sequence arrangement determined in step S20. Without the integral control in step S30 and relying solely on the target access time threshold in step S20 to execute a fixed delay, feeder terminals might still perform access actions when the grid is congested, resulting in the inrush current superposition risk not being avoided at the micro-level. The synergy between steps S20 and S30 enables the distribution network fault recovery process to have both global coordination and local adaptability: step S20 ensures the overall peak-shaving distribution of each feeder terminal on the time axis, while step S30 ensures that each feeder terminal only performs access actions when the grid is truly stable. Together, they effectively mitigate the peak inrush current of the entire network. Step S10 generates a load impedance inertia index by analyzing the voltage drop attenuation characteristics. This index is converted into the target access time threshold in step S20 and then used in step S30. The larger the load impedance inertia index, the longer the target access time threshold calculated in step S20. Therefore, the timing integrator in step S30 needs to accumulate a longer effective time to trigger the access action, thus automatically shifting the access time of the heavily loaded section later. Conversely, the smaller the load impedance inertia index, the shorter the target access time threshold, and the faster the timing integrator reaches the trigger condition, thus relatively shifting the access time of the lightly loaded section earlier. The load characteristic information obtained in step S10 is converted into timing parameters in step S20, and finally reflected as the actual occurrence time of the access action in step S30. These three steps form a complete control chain from load characteristic perception to timing parameter calculation to access action execution.

[0101] Step S30 employs a series of technical means—replacing the traditional countdown timer with a timing integrator, introducing voltage stability enable conditions, real-time monitoring of voltage dip events to synthesize congestion warning signals, and performing integral freeze and unfreeze operations based on hysteresis comparison—to upgrade the traditional rigid timing logic to flexible integral logic. The delay time of traditional rigid timing logic is absolute time, unaffected by the real-time state of the power grid. Each feeder terminal independently times according to its own preset fixed delay, lacking a coordination mechanism. The delay time of flexible integral logic is effective time, only counting the time periods when the power grid is in a stable state. Each feeder terminal indirectly obtains the load information of the upstream power source by monitoring the voltage fluctuations of the common bus. When grid congestion is detected, it autonomously pauses timing to avoid the inrush current impact caused by the preceding connection. This transformation allows multiple feeder terminals to avoid each other without communication. They can self-organize and adjust their connection timing solely based on the perception of common bus voltage fluctuations, thus achieving a peak-shaving effect similar to communication coordination without communication. The freeze and unfreeze mechanism of the timing integrator allows the access delay to automatically adapt to the actual recovery process of the power grid. When the power grid recovers smoothly, the access delay approaches the target access time threshold. When significant fluctuations occur during the power grid recovery process, the access delay is automatically extended to wait for the power grid to stabilize. This adaptive characteristic makes the fault recovery process smoother and more controllable, reducing the risk of reclosing failure caused by overcurrent tripping of the upstream power supply due to inrush current superposition. The hysteresis comparison design of the congestion warning signal and the introduction of the unfreeze stabilization confirmation time ensure the reliability of the integral freeze and unfreeze determination, avoid control jitter caused by voltage fluctuations, and make the access timing deterministic and predictable, facilitating fault analysis and system debugging by operation and maintenance personnel. By transforming the access delay from absolute time to effective time, the actual access time of each feeder terminal is no longer a predetermined fixed value, but a variable dynamically adjusted according to the real-time state of the power grid. When a feeder terminal experiences an inrush current surge, other feeder terminals detect the surge by monitoring bus voltage dip events and pause their respective timing integrators. Timing resumes after the surge subsides. This mechanism is equivalent to dynamically reserving recovery time for each access surge on the time axis. Without needing to know the load characteristics or access sequence of each feeder terminal in advance, the system can automatically achieve temporal isolation between surges. This self-organizing avoidance mechanism complements the load-related timing allocation achieved in step S20: step S20 prioritizes access for lightly loaded sections and delays access for heavily loaded sections, achieving macro-level load prioritization; step S30 allows the next access to occur only after each access surge has subsided, achieving micro-level surge isolation. With the combined effect of the two, the fault recovery process of the distribution network presents an orderly situation in which the inrush impacts are released in order from small to large, and there is a sufficient recovery interval between each impact. This fundamentally eliminates the risk of overcurrent tripping of the upstream power supply caused by the superimposed inrush current generated by the simultaneous connection of multiple switches, and improves the success rate of power restoration of the distribution network.

[0102] Example 2:

[0103] This embodiment, based on Embodiment 1, provides a voltage-time logic distribution network adaptive feeder coordination control system, such as... Figure 6 As shown, it includes:

[0104] Load inertia calculation module: used to capture the discrete sequence of voltage attenuation during line undervoltage process, fit the discrete sequence of voltage attenuation and calculate the equivalent attenuation time constant, and generate the load impedance inertia index based on the equivalent attenuation time constant;

[0105] Access threshold generation module: used to define the reference recovery time axis, calculate the slot bubble occupancy width on the reference recovery time axis according to the load impedance inertia index, generate an adaptive delay increment according to the slot bubble occupancy width, and superimpose a discretized jitter factor on the adaptive delay increment to generate the target access time threshold;

[0106] Integration access control module: Used to start the timing integrator, monitor voltage dip events on the incoming bus in real time during the operation of the timing integrator and synthesize congestion warning signals, and perform time integration freeze and unfreeze operations on the timing integrator according to the congestion warning signals. When the accumulated time integration value of the timing integrator reaches the target access time threshold, an access drive pulse is issued.

[0107] Furthermore, in the load inertia calculation module, the method for obtaining the discrete sequence of voltage undervoltage decay includes: when the feeder terminal detects line undervoltage, collecting multiple discrete data points of voltage amplitude within a transient window and arranging them in chronological order to form a discrete sequence of voltage undervoltage decay.

[0108] The method for calculating the equivalent decay time constant includes:

[0109] Curve fitting is performed on the discrete sequence of voltage drop decay to construct a voltage decay trajectory curve; an effective analysis segment is selected from the voltage decay trajectory curve, and the average decay rate of the voltage amplitude within the effective analysis segment is calculated; the equivalent decay time constant is calculated based on the average decay rate.

[0110] The load impedance inertia index is obtained by dividing the preset no-load line reference attenuation constant by the equivalent attenuation time constant.

[0111] Furthermore, in the access threshold generation module, the method for defining the benchmark recovery time axis includes:

[0112] When the feeder terminal detects a single-sided voltage recovery, the reference recovery time axis is defined with the moment of detection of the single-sided voltage recovery as the zero point;

[0113] The larger the load impedance inertia index, the wider the time slot bubble occupancy width.

[0114] The method for generating the discretized jitter factor is as follows: extract the unique physical code of the feeder terminal, and perform a hash operation on the unique physical code of the feeder terminal to generate the discretized jitter factor;

[0115] The target access time threshold is obtained by adding the preset base delay, adaptive delay increment, and discretized jitter factor.

[0116] Furthermore, in the integral access control module, the method for performing time integral freeze and unfreeze operations on the timing integrator according to the congestion warning signal includes:

[0117] When the congestion warning signal exceeds the preset safety warning threshold, the time integration freeze operation is performed on the time integrator, pausing the time integrator and keeping the current time integration value unchanged.

[0118] The congestion warning signal is continuously calculated under the time integral freeze state. When the congestion warning signal is lower than the preset congestion mitigation and return threshold and the incoming bus voltage remains within the stable threshold range for a preset unfreezing and stabilization confirmation time, the time integral unfreezing operation is performed on the time integrator. The time integrator continues to accumulate from the time integral value before the time integral freeze. The congestion mitigation and return threshold is less than the safety warning threshold.

[0119] The methods and systems of this application may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the method is for illustrative purposes only, and the steps of the method of this application are not limited to the order specifically described above, unless otherwise specifically stated.

[0120] In addition, the parts of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of the corresponding technical solutions in the prior art have not been described in detail, so as to avoid excessive elaboration.

[0121] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A voltage-time logic distribution network adaptive feeder coordinated control method, characterized in that, The method includes: Capture the discrete sequence of voltage drop decay during the line undervoltage process, fit the discrete sequence of voltage drop decay and calculate the equivalent decay time constant, and generate the load impedance inertia index based on the equivalent decay time constant; Define a reference recovery time axis, calculate the slot bubble occupancy width on the reference recovery time axis based on the load impedance inertia index. The larger the load impedance inertia index, the wider the slot bubble occupancy width. Generate an adaptive delay increment based on the slot bubble occupancy width, and superimpose a discretized jitter factor on the adaptive delay increment to generate the target access time threshold. Start the timing integrator, monitor the voltage sag event of the incoming bus in real time during the operation of the timing integrator, extract the voltage sag depth and voltage sag duration, and weight the voltage sag depth and voltage sag duration to synthesize a congestion warning signal. Perform time integration freeze and unfreeze operations on the timing integrator according to the congestion warning signal. When the accumulated time integration value of the timing integrator reaches the target access time threshold, an access drive pulse is issued. The activation condition of the timing integrator is as follows: when the feeder terminal detects a single-sided voltage recovery event, it monitors the voltage waveform of the incoming bus in real time, confirms whether the incoming bus voltage is within the stable threshold range and maintains the preset activation stability confirmation time. If the conditions are met, the timing integrator is activated and the time integration value is initialized to zero.

2. The voltage-time logic distribution network adaptive feeder coordination control method according to claim 1, characterized in that, The line voltage loss refers to the line voltage being lower than the rated voltage threshold. The method for obtaining the discrete sequence of voltage undervoltage decay includes: when the feeder terminal detects line undervoltage, collecting multiple discrete data points of voltage amplitude within a transient window and arranging them in chronological order to form a discrete sequence of voltage undervoltage decay.

3. The voltage-time logic distribution network adaptive feeder coordination control method according to claim 2, characterized in that, The method for calculating the equivalent decay time constant includes: Curve fitting is performed on the discrete sequence of voltage drop decay to construct a voltage decay trajectory curve; an effective analysis segment is selected from the voltage decay trajectory curve, and the average decay rate of the voltage amplitude within the effective analysis segment is calculated; the equivalent decay time constant is calculated based on the average decay rate.

4. The voltage-time logic distribution network adaptive feeder coordination control method according to claim 3, characterized in that, The load impedance inertia index is obtained by dividing the preset no-load line reference attenuation constant by the equivalent attenuation time constant.

5. The voltage-time logic distribution network adaptive feeder coordination control method according to claim 4, characterized in that, The method for defining the baseline recovery time axis includes: When the feeder terminal detects a single-sided voltage recovery, the reference recovery time axis is defined with the moment of detection of the single-sided voltage recovery as the zero point.

6. The voltage-time logic distribution network adaptive feeder coordination control method according to claim 5, characterized in that, The method for generating the discretized jitter factor is as follows: extract the unique physical code of the feeder terminal, and perform a hash operation on the unique physical code of the feeder terminal to generate the discretized jitter factor; The target access time threshold is obtained by adding the preset base delay, adaptive delay increment, and discretized jitter factor.

7. The voltage-time logic distribution network adaptive feeder coordinated control method according to claim 6, characterized in that, The method for performing time integration freeze and unfreeze operations on the time integrator based on the congestion warning signal includes: When the congestion warning signal exceeds the preset safety warning threshold, the time integration freeze operation is performed on the time integrator, pausing the time integrator and keeping the current time integration value unchanged. The congestion warning signal is continuously calculated under the time integral freeze state. When the congestion warning signal is lower than the preset congestion mitigation and return threshold and the incoming bus voltage remains within the stable threshold range for a preset unfreezing and stabilization confirmation time, the time integral unfreezing operation is performed on the time integrator. The time integrator continues to accumulate from the time integral value before the time integral freeze. The congestion mitigation and return threshold is less than the safety warning threshold.

8. A voltage-time logic distribution network adaptive feeder coordination control system, used to implement the voltage-time logic distribution network adaptive feeder coordination control method according to any one of claims 1-7, characterized in that, The system includes: Load inertia calculation module: used to capture the discrete sequence of voltage attenuation during line undervoltage process, fit the discrete sequence of voltage attenuation and calculate the equivalent attenuation time constant, and generate the load impedance inertia index based on the equivalent attenuation time constant; Access threshold generation module: used to define the reference recovery time axis, calculate the slot bubble occupancy width on the reference recovery time axis according to the load impedance inertia index, generate an adaptive delay increment according to the slot bubble occupancy width, and superimpose a discretized jitter factor on the adaptive delay increment to generate the target access time threshold; Integration access control module: Used to start the timing integrator, monitor voltage dip events on the incoming bus in real time during the operation of the timing integrator and synthesize congestion warning signals, and perform time integration freeze and unfreeze operations on the timing integrator according to the congestion warning signals. When the accumulated time integration value of the timing integrator reaches the target access time threshold, an access drive pulse is issued.

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