Low-delay Q-switching drive circuit

Abstract

The invention discloses a low-delay Q-switching drive circuit which comprises a booster circuit, a signal modulation circuit and a voltage-multiplying drive circuit. The booster circuit comprises a PWM generator U1, an MOS tube U2, a transformer T1 and a first voltage doubling circuit, a PWM signal output by the PWM generator U1 is output to the MOS tube U2 to control a primary circuit of the transformer T1 connected with an external input power supply after capacitor filtering, and a secondary side of the transformer T1 is connected with the first voltage doubling circuit; the signal modulation circuit comprises a triode Q1 and a wire L, a C pole of the triode Q1 is connected with the first voltage doubling circuit output power supply, a B pole is connected with an input signal Q +, an E pole is connected with an input signal Q-and is grounded, one end of the wire L is grounded, and the other end is connected with the C pole of the triode Q1 through a capacitor; the voltage-multiplying driving circuit comprises a second voltage-multiplying circuit and a magnetic ring wound on a lead L, capacitors in the second voltage-multiplying circuit are respectively provided with parallel MOS (Metal Oxide Semiconductor) tubes, and two ends of the magnetic ring are respectively connected with G poles and S poles of the parallel MOS tubes to control the on-off of the parallel MOS tubes.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor lasers, and particularly relates to a low-delay Q-switching driving circuit. BACKGROUND

[0002] Semiconductor lasers have the advantages of small volume, light weight, high conversion efficiency, long service life and the like, and have been widely applied in the fields of industry, military, medical treatment and the like. As one of the core technologies, Q-switching is used to realize the mutation of the Q value of a laser resonant cavity through the electro-optic effect caused by the voltage applied to both ends of an electro-optic crystal. The phase delay of linearly polarized light passing through the crystal is changed, so that the continuous laser energy is compressed to generate a laser pulse with high peak power and narrow pulse width.

[0003] Therefore, Q-switching is a core factor for determining the timing of laser pulse generation, and with the development of technology, the requirements for laser pulse timing, amplitude and trigger accuracy are becoming higher and higher (such as precise laser micro-processing equipment). In the traditional semiconductor laser, the Q-switching circuit often uses an optical coupler and the like to isolate signals, and uses a MOS tube in series with a voltage divider, so that the response speed of the Q-switching circuit to the trigger signal is slow, the delay is large, and the requirements of new equipment cannot be met.

[0004] The existing traditional Q-switching driving circuit has the following disadvantages: 1. Slow response speed to the trigger signal and high delay; 2. Long high-voltage rise time of the driving circuit. SUMMARY

[0005] In view of the deficiencies of the prior art, the application provides a low-delay Q-switching driving circuit, which has low delay from the Q-switching trigger signal to high-voltage output and short high-voltage rise time.

[0006] The application is implemented by the following technical scheme: A low-delay Q-switching driving circuit, comprising a voltage boosting circuit, a signal modulation circuit and a voltage doubling driving circuit; The voltage boosting circuit comprises a PWM generator U1, a MOS tube U2, a transformer T1 and a first voltage doubling circuit. The PWM signal output by the PWM generator U1 is output to the MOS tube U2 to control the transformer T1 primary circuit connected to the capacitor filtered external input power supply. The secondary side of the transformer T1 is connected to the first voltage doubling circuit. The signal modulation circuit comprises a triode Q1 and a wire L. The C pole of the triode Q1 is connected to the output power supply of the first voltage doubling circuit. The B pole of the triode Q1 is connected to the input signal Q+. The E pole of the triode Q1 is connected to the input signal Q- and grounded. One end of the wire L is grounded, and the other end of the wire L is connected to the C pole of the triode Q1 through a capacitor. The voltage doubling driving circuit comprises a second voltage doubling circuit and a magnetic ring arranged on the lead L, the first voltage doubling circuit outputs a power supply as an input power supply of the second voltage doubling circuit, the second voltage doubling circuit adopts a direct current voltage doubling and capacitor series connection mode, each capacitor in the second voltage doubling circuit is arranged with a parallel MOS tube, and the magnetic ring is connected with the G pole and the S pole of the parallel MOS tube at two ends to control the switch of each parallel MOS tube.

[0007] Further, the potentiometer RW1 and the resistor R2 form a series circuit connected to the voltage feedback signal input end of the PWM generator U1, wherein the fixed end of the potentiometer RW1 is connected to the ground, and the adjustable end of the potentiometer RW1 is connected in series with the resistor R2.

[0008] Further, a parallel circuit of a resistor and a capacitor is arranged at the Comp input end of the PWM generator U1 to control the frequency of the output driving signal.

[0009] Further, a current limiting resistor is arranged in the circuit.

[0010] Further, a diode D3 is arranged on the input signal Q+ and Q- input line, the positive pole of the diode D3 is connected to the input signal Q+ input line, and the negative pole of the diode D3 is connected to the input signal Q- input line.

[0011] Further, a triode and a MOS tube with small input capacitance and fast conduction speed are selected in the circuit.

[0012] Further, a series voltage balancing resistor is arranged for the MOS tube connected in parallel with each capacitor in the second voltage doubling circuit.

[0013] Compared with the prior art, the application has the beneficial effects that: The application designs a low-delay Q-switching driving circuit for a semiconductor pulse laser, which can solve the problems of long signal response time, slow high-voltage rising edge, low signal trigger precision and the like in the electro-optic Q-switching circuit of a traditional semiconductor laser. The application sets a voltage boosting circuit, a signal modulation circuit and a voltage doubling driving circuit to ensure that the delay of the Q-switching signal to the high-voltage output is about 10 ns; the whole driving circuit uses the turn-on or turn-off of a power device MOS tube to change the working state of the voltage doubling driving circuit, thereby shortening the establishment time of the high voltage; the electromagnetic induction signal of the magnetic ring is used to control the turn-on or turn-off of the MOS tube, thereby improving the response speed of the driving circuit to the Q-switching trigger signal. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 FIG. 1 is a schematic diagram of the Q-switching driving circuit of the application; Figure 2 FIG. 2 is a circuit diagram of the voltage boosting circuit of the application; Figure 3 FIG. 3 is a circuit diagram of the signal modulation circuit of the application; Figure 4The circuit diagram of the voltage doubling driving circuit of the present application; Figure 5 The schematic diagram of the wire structure of the magnetic ring of the present application. DETAILED DESCRIPTION

[0015] Exemplary embodiments of the present application will be described in detail with reference to the drawings. Although exemplary embodiments of the present application are shown in the drawings, it is understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present application can be more thoroughly understood, and the scope of the present application can be accurately conveyed to those skilled in the art. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0016] As Figures 1 to 5 shown, the present application provides a high-voltage and high-power semiconductor laser low-delay Q-switching driving circuit, which comprises a voltage boosting circuit, a signal modulation circuit and a voltage doubling driving circuit.

[0017] The voltage boosting circuit structure is shown in Figure 2 , and specifically, VCC is an input power supply, generally 15-24V, the VCC power supply is filtered by capacitors C4, C5 and C6 and then input to the primary of the transformer T1, at the same time, filtered by capacitor C11 to supply power to the PWM generator U1. In this embodiment, the type of PWM generator U1 is UC2845. The MOS tube U2 is connected to the ground, the primary of the transformer T1 and the signal output end of the PWM generator U1, respectively. The 6-pin output pulse driving signal of the PWM generator U1 controls the working state of the MOS tube U2, and at the same time, cooperates with the transformer T1 to form a stable voltage boosting circuit. The capacitor C1, the capacitor C3, the diode D1 and the diode D2 form a double voltage circuit connected to one end of the secondary of the transformer T1 to play a role of secondary voltage boosting. In this embodiment, the double voltage circuit is taken as an example, and the voltage boosting multiple can be changed according to the specific use conditions to enhance the applicability of the circuit. The filter capacitor C2 is arranged between the output end of the double voltage circuit and the ground, and the double voltage circuit finally outputs the voltage V+. The output voltage of the double voltage circuit is input to the 2-pin voltage feedback end of the PWM generator U1 through the resistor R1. The potentiometer RW1 and the resistor R2 form a series circuit, the fixed end of the potentiometer RW1 is grounded, and the adjustable end is connected in series with the resistor R2. Adjusting the resistance value of the potentiometer RW1 changes the voltage at the 2-pin of the PWM generator U1, so that the output amplitude of the voltage boosting circuit has an adjustable function. The 1-pin of the PWM generator U1 is connected to the parallel circuit of the resistor R5 and the capacitor C7, which is used to control the frequency of the 6-pin output driving signal of the PWM generator U1. The resistor R7 is a current sampling resistor, which plays a role of current limiting and power limiting to prevent the circuit from burning out.

[0018] The signal modulation circuit is shown inFigure 3 As shown in the figure, specifically: the output voltage V+ of the voltage doubler circuit is connected to the signal modulation circuit through the resistor R17 to provide power supply, and is connected to the 3-pin C pole of the transistor Q1 through the resistor R17. The input signals Q+ and Q- are the trigger signals of the circuit, usually using 5-15V TTL signals, the input signal Q+ is connected to the 1-pin B pole of the transistor Q1 through the direct current isolation capacitor C13 and the resistor R9. The input signal Q- is connected to the 2-pin E pole of the transistor Q1, and the 2-pin E pole of the transistor Q1 is grounded. One end of the wire L is grounded, and the other end of the wire L is connected to the 3-pin of the transistor Q1 through the capacitor C12. The resistor R8 and the diode D3 are connected to the input lines of the input signals Q+ and Q- respectively, the resistor R8 and the resistor R9 are current limiting resistors, and the diode D3 prevents reverse connection to prevent the input signals Q+ and Q- from being connected incorrectly, wherein the positive pole of the diode D3 is connected to the input line of the input signal Q+, and the negative pole is connected to the input line of the input signal Q-. When the trigger signal flows into the transistor Q1, the transistor Q1 will continuously change between conduction and shutdown according to the signal, and the 2-pin of the transistor Q1 and one end of the capacitor C12 are connected by the wire L, so that a pulse current is generated on the wire L.

[0019] The voltage doubler drive circuit is as shown in the figure Figure 4 As shown in the figure, specifically: the output voltage V+ of the voltage doubler circuit is connected to the signal modulation circuit through the resistor R17 to provide power supply, and is connected to the 3-pin C pole of the transistor Q1 through the resistor R17. The input signals Q+ and Q- are the trigger signals of the circuit, usually using 5-15V TTL signals, the input signal Q+ is connected to the 1-pin B pole of the transistor Q1 through the direct current isolation capacitor C13 and the resistor R9. The input signal Q- is connected to the 2-pin E pole of the transistor Q1, and the 2-pin E pole of the transistor Q1 is grounded. One end of the wire L is grounded, and the other end of the wire L is connected to the 3-pin of the transistor Q1 through the capacitor C12. The resistor R8 and the diode D3 are connected to the input lines of the input signals Q+ and Q- respectively, the resistor R8 and the resistor R9 are current limiting resistors, and the diode D3 prevents reverse connection to prevent the input signals Q+ and Q- from being connected incorrectly, wherein the positive pole of the diode D3 is connected to the input line of the input signal Q+, and the negative pole is connected to the input line of the input signal Q-. When the trigger signal flows into the transistor Q1, the transistor Q1 will continuously change between conduction and shutdown according to the signal, and the 2-pin of the transistor Q1 and one end of the capacitor C12 are connected by the wire L, so that a pulse current is generated on the wire L. Figure 5 As shown in the figure, specifically: the output voltage V+ of the voltage doubler circuit is connected to the signal modulation circuit through the resistor R17 to provide power supply, and is connected to the 3-pin C pole of the transistor Q1 through the resistor R17. The input signals Q+ and Q- are the trigger signals of the circuit, usually using 5-15V TTL signals, the input signal Q+ is connected to the 1-pin B pole of the transistor Q1 through the direct current isolation capacitor C13 and the resistor R9. The input signal Q- is connected to the 2-pin E pole of the transistor Q1, and the 2-pin E pole of the transistor Q1 is grounded. One end of the wire L is grounded, and the other end of the wire L is connected to the 3-pin of the transistor Q1 through the capacitor C12. The resistor R8 and the diode D3 are connected to the input lines of the input signals Q+ and Q- respectively, the resistor R8 and the resistor R9 are current limiting resistors, and the diode D3 prevents reverse connection to prevent the input signals Q+ and Q- from being connected incorrectly, wherein the positive pole of the diode D3 is connected to the input line of the input signal Q+, and the negative pole is connected to the input line of the input signal Q-. When the trigger signal flows into the transistor Q1, the transistor Q1 will continuously change between conduction and shutdown according to the signal, and the 2-pin of the transistor Q1 and one end of the capacitor C12 are connected by the wire L, so that a pulse current is generated on the wire L.

[0020] In order to realize short high-voltage rise time, the circuit adopts DC voltage multiplication and capacitor series connection mode, utilizes the characteristics of capacitor charge conservation, and realizes voltage promotion through series connection of multiple capacitors. When MOS tubes Q2-Q6 are off, high voltage V+ charges capacitors C14-C16, and the voltage between the two ends of each capacitor is equal to V+. When MOS tubes Q2-Q6 are on, capacitors C14-C16 are in series, and Vout=5xV+. That is, when the MOS tube is off, the voltage between the high end and the low end of each capacitor is V+. Because the voltage between the two ends of the capacitor has the characteristic of not changing suddenly, when the MOS tube is off, the voltage difference between the 3-pin of MOS tube Q6 and GND is V+, the voltage difference between the 3-pin of MOS tube Q5 and the 2-pin of MOS tube Q6 is still V+, according to the superposition principle of voltage, the voltage difference between the 3-pin of MOS tube Q5 and GND is 2xV+ at this time. By analogy, the 3-pin of MOS tube Q2 is Vout=5xV+.

[0021] Because the voltage between the two ends of the 5 capacitors C14-C16 is in a pre-charged full state, the energy storage is completed before Vout is output. Therefore, the high-voltage rise time of the circuit is approximately equal to the conduction time of the MOS tube, and the circuit can realize the requirement of short high-voltage rise time by selecting a MOS tube with low input capacitance.

[0022] In order to realize low delay from the Q-switch trigger signal to high-voltage output, the application adopts the principle of magnetic ring electromagnetic induction, and drives MOS tubes Q2-Q6 through the current on the wire L. When Q+, Q- signals drive the triode Q1 to be on, the capacitor C12 discharges to GND through the wire L to generate a current, thereby generating a pulse driving signal between MOS tubes Q2-Q6 through magnetic ring induction, and generating high voltage. Therefore, the delay from the Q-switch trigger signal to high-voltage output is approximately the conduction time of the triode Q1 and the MOS tubes Q2-Q6 in the rear stage, and the low delay time from the Q-switch trigger signal to high-voltage output can be realized by selecting a triode and a MOS tube with small input capacitance and fast conduction speed. In the verification experiment of the application, the delay is about 10ns.

[0023] The application has been described in detail through the above embodiments, but the content described is only exemplary embodiments of the application and cannot be considered as limiting the implementation scope of the application. The protection scope of the application is defined by the claims. Any technical solution utilizing the technical solutions described in the application, or any similar technical solution designed by the person skilled in the art under the inspiration of the technical solutions of the application within the essence and protection scope of the application, and achieving the above technical effects, or any equivalent changes and improvements to the application scope, shall still belong to the patent protection scope of the application. It should be noted that, in order to clearly express, the description of the application omits the description of some components and processes which are not directly and obviously related to the protection scope of the application but are known to the person skilled in the art.

Claims

1. A low-delay Q-switching drive circuit, characterized in that, Includes a boost circuit, a signal modulation circuit, and a voltage multiplier drive circuit; The boost circuit includes a PWM generator U1, a MOSFET U2, a transformer T1, and a first voltage doubler circuit. The PWM signal output by the PWM generator U1 is output to the MOSFET U2 to control the primary circuit of the transformer T1, which is connected to the external input power supply after being filtered by the capacitor. The secondary circuit of the transformer T1 is connected to the first voltage doubler circuit. The signal modulation circuit includes a transistor Q1 and a wire L. The collector of transistor Q1 is connected to the output power of the first voltage multiplier circuit, the base of transistor Q1 is connected to the input signal Q+, the emitter of transistor Q1 is connected to the input signal Q- and grounded, one end of wire L is grounded, and the other end of wire L is connected to the collector of transistor Q1 through a capacitor. The voltage multiplier drive circuit includes a second voltage multiplier circuit and a magnetic ring mounted on the conductor L. The output power of the first voltage multiplier circuit serves as the input power of the second voltage multiplier circuit. The second voltage multiplier circuit adopts a DC voltage multiplication and capacitor series connection method. Each capacitor in the second voltage multiplier circuit is connected to a parallel MOSFET. The two ends of the magnetic ring are connected to the gate and source terminals of the parallel MOSFETs to control the switching of each parallel MOSFET.

2. The low-delay Q-switching drive circuit according to claim 1, characterized in that, Potentiometer RW1 and resistor R2 form a series circuit connected to the voltage feedback signal input terminal of PWM generator U1, wherein the fixed terminal of potentiometer RW1 is grounded, and the adjustable terminal of potentiometer RW1 is connected in series with resistor R2.

3. The low-delay Q-switching drive circuit according to claim 1, characterized in that, A parallel circuit of resistors and capacitors is set at the Comp input terminal of PWM generator U1 to control the frequency of the output drive signal.

4. The low-delay Q-switching drive circuit according to claim 1, characterized in that, Set a current-limiting resistor in the circuit.

5. The low-delay Q-switching drive circuit according to claim 1, characterized in that, Diode D3 is placed on the input signal Q+ and Q- input lines. The positive terminal of diode D3 is connected to the input signal Q+ input line, and the negative terminal is connected to the input signal Q- input line.

6. The low-delay Q-switching drive circuit according to claim 1, characterized in that, The circuit uses transistors and MOSFETs with small input capacitance and fast conduction speed.

7. The low-delay Q-switching drive circuit according to claim 1, characterized in that, In the second voltage multiplier circuit, the MOS transistors connected in parallel with each capacitor are equipped with series voltage equalization resistors.

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