Power conversion apparatus and control method therefor

Abstract

The invention provides power conversion equipment and a control method thereof, the power conversion equipment comprises a sampling circuit, a controller and at least one bridge arm, the sampling circuit is connected with a bridge arm midpoint of the bridge arm, and the bridge arm comprises a first switch tube and a second switch tube which are connected in series; the sampling circuit is used for sampling the voltage of the midpoint of the bridge arm and sending the voltage to the controller; the controller is used for controlling the first switching tube to be switched on in a first switching period and a second switching period of the first switching tube when the second switching tube is switched off and the voltage difference between the two ends of the first switching tube is smaller than or equal to a voltage difference threshold value; the first switching period and the second switching period are two adjacent switching periods of the first switching tube, and the absolute value of the difference between the period duration of the first switching period and the period duration of the second switching period is greater than or equal to the first duration. According to the invention, when the working condition of the power conversion equipment dynamically changes, the switching tube can realize ZVS, and the applicability is high.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, specifically to a power conversion device and its control method. Background Technology

[0002] Each arm of a power conversion device includes two switching transistors connected in series. By controlling the alternating conduction of these two transistors, the power conversion device can convert the DC power supplied by the DC source and provide it to the load. During the alternating conduction of the two transistors, there is a certain delay between the initial turn-off and complete turn-off. To avoid the simultaneous conduction of both transistors due to the turn-off delay, which could cause a short circuit, the power conversion device incorporates a dead time between the switching actions of the two transistors. Furthermore, during the dead time, the resonant current in the power conversion device can cause the voltage across the transistor about to be turned on to drop to 0, thereby achieving zero-voltage switching (ZVS) and reducing switching losses.

[0003] Typically, power conversion devices can maintain stable output voltage and optimize efficiency by adjusting the switching frequency under different operating conditions (such as changes in load voltage or DC source voltage). However, adjusting the switching frequency causes changes in the resonant current, which in turn affects the dead time (the length of the dead period) required for the switching transistor to achieve Zero-Switching-Voltage (ZVS). Therefore, to control the switching transistor to achieve ZVS, the power conversion device needs to adjust the dead time of the switching transistor according to changes in operating conditions. However, due to numerous limitations of conventional adjustment methods, there is a significant delay in adjusting the dead time under dynamic operating conditions, preventing the switching transistor from achieving ZVS and resulting in substantial switching losses. Therefore, ensuring that the switching transistor can achieve ZVS under changing operating conditions is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a power conversion device and its control method. The power conversion device can ensure that the switching transistor can achieve ZVS when the operating conditions of the power conversion device change dynamically, and has strong applicability.

[0005] In a first aspect, this application provides a power conversion device, which includes a sampling circuit, a controller, and at least one bridge arm. The sampling circuit is connected to the midpoint of the bridge arm, and the bridge arm includes a first switch and a second switch connected in series. During the operation of the power conversion device, the first switch and the second switch are alternately turned on. The sampling circuit is used to sample the voltage at the midpoint of the bridge arm and send it to the controller. The controller is used to control the first switch to turn on when the second switch is turned off and the voltage difference across the first switch is less than or equal to a voltage difference threshold during a first switching cycle and a second switching cycle of the first switch. The magnitude of the voltage difference across the first switch is positively or negatively correlated with the magnitude of the voltage at the midpoint of the bridge arm. The first switching cycle and the second switching cycle are two adjacent switching cycles of the first switch, and the absolute value of the difference between the duration of the first switching cycle and the duration of the second switching cycle is greater than or equal to the first duration.

[0006] In this embodiment, since the period duration of the first switch is equal to the reciprocal of its switching frequency, when the first and second switching periods are two adjacent switching periods of the first switch, if the absolute value of the difference between the period duration of the first and second switching periods is greater than or equal to the first period duration, it indicates that the switching frequency of the first switch changes within the first and second switching periods. This change in switching frequency causes a change in the dead time required for the first switch to achieve ZVS, meaning the dead time required for ZVS is different in the first and second switching periods. To ensure that the first switch can achieve ZVS in both the first and second switching periods, in this embodiment, the power conversion device can detect the voltage difference across the first switch via a sampling circuit before controlling its conduction. This voltage difference is equal to the difference between the voltage at the midpoint of the bridge arm and the voltage at the other end of the first switch. Therefore, the power conversion device can obtain the voltage difference across the first switch by sampling the voltage at the midpoint of the bridge arm. Furthermore, when the power conversion device detects through the controller that the voltage difference across the first switching transistor is less than or equal to a voltage difference threshold, it indicates that the voltage difference across the first switching transistor is sufficiently small, meaning that the first switching transistor can achieve ZVS. Therefore, the power conversion device can control the first switching transistor to turn on at this time to achieve ZVS. Since the power conversion device provided in this embodiment only controls the first switching transistor to turn on when it detects that the first switching transistor can achieve ZVS, regardless of how the duration of the first and second switching cycles changes, the power conversion device can control the first switching transistor to achieve ZVS within the first and second switching cycles. Thus, this embodiment can ensure that the first switching transistor can still achieve ZVS within switching cycles with varying durations (such as the first or second switching cycle), solving the problem of dead-time adjustment delay causing the first switching transistor to fail to achieve ZVS within switching cycles with varying durations. It can also reduce switching losses, ensuring the high efficiency, reliability, and strong applicability of the power conversion device.

[0007] In one possible implementation, the controller is further configured to: during the first switching cycle and the second switching cycle, when the second switch is turned off, and the duration experienced after the second switch is turned off is greater than or equal to the second duration, and the absolute value of the voltage difference across the first switch is less than or equal to the voltage difference threshold, control the first switch to turn on.

[0008] In this embodiment, the time elapsed from the turn-off of the second switch to the turn-on of the first switch is the dead time. To avoid the dead time being too short, causing the first and second switches to conduct simultaneously due to the turn-off delay, in this embodiment, the controller also checks whether the time elapsed after the second switch is turned off is greater than or equal to a second time before controlling the first switch to conduct. This second time refers to the minimum value of the aforementioned dead time that ensures the first and second switches will not conduct simultaneously. Therefore, when the controller detects that the second switch is turned off, and the time elapsed after the second switch is turned off is greater than or equal to the second time, and the absolute value of the voltage difference across the first switch is less than or equal to the voltage difference threshold, the controller controls the first switch to conduct and achieves ZVS (Zero-Voltage Switching), while ensuring that the first and second switches will not conduct simultaneously, resulting in high reliability.

[0009] In one possible implementation, if the duration of the second switching cycle is greater than or equal to the duration of the first switching cycle, the duration from the second switch being turned off to the first switch being turned on within the first switching cycle is equal to a third duration, and the duration from the second switch being turned off to the first switch being turned on within the second switching cycle is equal to a fourth duration, and the fourth duration is less than or equal to the third duration.

[0010] In this embodiment, since the cycle duration of the first switching transistor is equal to the reciprocal of its switching frequency, when the cycle duration of the second switching cycle is greater than or equal to the cycle duration of the first switching cycle, the switching frequency of the first switching cycle is greater than or equal to the switching frequency of the second switching cycle. Furthermore, when the switching frequency decreases, the dead time required for the first switching transistor to achieve ZVS decreases. Therefore, when the power conversion device controls the first switching transistor to conduct and achieve ZVS within the first and second switching cycles, the dead time within the first and second switching cycles will adaptively adjust according to the change in switching frequency, thereby making the dead time of the second switching cycle (i.e., the fourth duration) less than or equal to the dead time of the first switching cycle (i.e., the third duration). Thus, this embodiment can promptly and adaptively adjust the dead time when the switching frequency of the first switching transistor changes, avoiding adjustment delays and demonstrating high reliability.

[0011] In one possible implementation, if the duration of the second switching cycle is less than the duration of the first switching cycle, the duration from the second switch being turned off to the first switch being turned on in the first switching cycle is equal to the fifth duration, and the duration from the second switch being turned off to the first switch being turned on in the second switching cycle is equal to the sixth duration, and the sixth duration is greater than the fifth duration.

[0012] In this embodiment, since the cycle duration of the first switching transistor is equal to the reciprocal of its switching frequency, when the cycle duration of the second switching cycle is shorter than that of the first switching cycle, the switching frequency of the first switching cycle is shorter than that of the second switching cycle. Furthermore, as the switching frequency increases, the dead time required for the first switching transistor to achieve ZVS increases. Therefore, when the power conversion device controls the first switching transistor to conduct and achieve ZVS within the first and second switching cycles, the dead time within the first and second switching cycles is adaptively adjusted according to the change in switching frequency, thereby making the dead time of the second switching cycle (i.e., the sixth duration) greater than the dead time of the first switching cycle (i.e., the fifth duration). Thus, this embodiment can promptly and adaptively adjust the dead time when the switching frequency of the first switching transistor changes, avoiding adjustment delays and demonstrating high reliability.

[0013] In one possible implementation, the sampling circuit is also connected to the other end of the first switching transistor connected to the midpoint of the bridge arm; the sampling circuit is also used to sample the voltage at the other end of the first switching transistor connected to the midpoint of the bridge arm, and output the voltage difference between the two ends of the first switching transistor to the controller based on the difference between the voltage at the other end of the first switching transistor connected to the midpoint of the bridge arm and the voltage at the midpoint of the bridge arm.

[0014] In this embodiment, the voltage difference across the first switch is equal to the difference between the voltage at the midpoint of the bridge arm and the voltage at the other end of the first switch. Since the voltage at the other end of the first switch may not remain stable, in order to ensure sampling accuracy, the sampling circuit can simultaneously sample the voltage at the midpoint of the bridge arm and the voltage at the other end of the first switch to ensure that the voltage difference across the first switch output to the controller is correct.

[0015] In one possible implementation, when the second switch is turned off and the voltage difference across the first switch is less than or equal to a voltage difference threshold, the controller controls the first switch to turn on. Specifically, this includes: obtaining a pulse width modulation (PWM) reference signal for the second switch based on the switching frequency and duty cycle of the bridge arm; within the reference off-range of the second switch, the PWM reference signal for the second switch is equal to a first level; obtaining a soft-on signal for the first switch based on the voltage difference across the first switch; wherein, when the voltage difference across the first switch is less than or equal to the voltage difference threshold, the soft-on signal for the first switch is equal to a second level; and when the PWM signal for the second switch is equal to the first level and the soft-on signal for the first switch is equal to the second level, the controller controls the first switch to turn on.

[0016] In this embodiment, the controller controls the first switch to turn on based on the pulse width modulation reference signal of the second switch and the soft-turn signal of the first switch, thus ensuring that the first switch can achieve ZVS when it is turned on. The implementation principle is simple.

[0017] In one possible implementation, when the second switch is turned off, and the duration of time elapsed after the second switch is turned off is greater than or equal to a second duration, and the absolute value of the voltage difference across the first switch is less than or equal to a voltage difference threshold, the controller controls the first switch to turn on. Specifically, this includes: obtaining the pulse width modulation (PWM) reference signal of the first switch and the PWM reference signal of the second switch based on the switching frequency and duty cycle of the bridge arm; wherein the time interval between the falling edge of the PWM reference signal of the second switch and the rising edge of the adjacent PWM reference signal of the first switch is equal to the second duration; in the second switch... Within the reference off-range, the pulse width modulation signal of the second switch is equal to the first level; within the reference on-range of the first switch, the pulse width modulation signal of the first switch is equal to the third level; the soft-on signal of the first switch is obtained based on the voltage difference across the first switch; wherein, when the voltage difference across the first switch is less than or equal to the voltage difference threshold, the soft-on signal of the first switch is equal to the second level; when the pulse width modulation signal of the first switch is equal to the third level, and the soft-on signal of the first switch is equal to the second level, and the pulse width modulation signal of the second switch is equal to the first level, the first switch is controlled to be turned on.

[0018] In this embodiment, the controller adjusts the time interval between the falling edge of the pulse width modulation reference signal of the second switch and the rising edge of the pulse width modulation reference signal of the adjacent first switch to be equal to the second time interval. Then, it controls the first switch to be turned on according to the pulse width modulation reference signal of the second switch, the pulse width modulation reference signal of the first switch, and the soft-on signal of the first switch. This ensures that the first switch can achieve ZVS when it is turned on, and at the same time makes the dead time of the first switch and the second switch greater than or equal to the second time interval, thereby avoiding the simultaneous turn-on of the first switch and the second switch. This method has high reliability and a simple implementation principle.

[0019] In one possible implementation, the controller includes a comparison module, a logic module, a protection module, a wave generation module, and a drive module; the input terminal of the comparison module is connected to the sampling circuit, the comparison module, the logic module, the protection module, and the drive module are connected in sequence, the output terminal of the drive module is connected to the control electrode of the first switching transistor, and the wave generation module is connected to the protection module;

[0020] The comparison module is used to output a second level to the logic module when the voltage difference across the first switch is less than or equal to a voltage difference threshold.

[0021] The logic module is used to output a fourth level to the protection module upon receiving the second level.

[0022] The waveform generation module is used to output a first level to the protection module within the reference turn-off interval of the second switch.

[0023] The protection module is used to output a fifth level to the drive module when it receives the fourth level and the first level.

[0024] The driver module is used to control the first switch to turn on when the fifth level is received.

[0025] In this embodiment, the controller performs simple logic operations through a comparison module, a logic module, a protection module, a wave generation module, and a drive module, which can control the first switch to conduct and ensure ZVS is achieved, making the implementation principle simple.

[0026] In one possible implementation, the controller includes a comparison module, a logic module, a protection module, a wave generation module, and a drive module; the input terminal of the comparison module is connected to the sampling circuit, the comparison module, the logic module, the protection module, and the drive module are connected in sequence, the output terminal of the drive module is connected to the control electrodes of the first and second switching transistors, and the wave generation module is connected to the protection module and the logic module respectively.

[0027] The comparison module is used to output a second level to the logic module when the voltage difference across the first switch is less than or equal to a voltage difference threshold.

[0028] The waveform generation module is used to output a first level to the protection module during the reference off-range of the second switch transistor; and to output a third level to the logic module during the reference on-range of the first switch transistor; wherein the interval between the waveform generation module outputting the first level and the outputting the third level is equal to the second duration;

[0029] The logic module is used to output a fourth level to the protection module upon receiving the second and third level levels;

[0030] The protection module is used to output a fifth level to the drive module when it receives the fourth level and the first level.

[0031] The driver module is used to control the first switch to turn on when the fifth level is received.

[0032] In this embodiment, the controller performs simple logic operations through a comparison module, a logic module, a protection module, a wave generation module, and a drive module. This allows it to control the first switch to conduct and ensure ZVS is achieved. At the same time, it controls the dead time of the first and second switches to be greater than or equal to the second time, thereby preventing the first and second switches from conducting simultaneously. This results in high reliability and a simple implementation principle.

[0033] In one possible implementation, at least one bridge arm includes a bridge arm, a first switch and a second switch connected in series between the positive and negative terminals of the DC input; the power conversion device further includes a first inductor, a first capacitor, a first transformer and a first rectifier circuit; the first inductor is connected to the midpoint of the bridge arm, the first capacitor is connected to the negative terminal of the DC input, the primary coil of the transformer is connected between the first inductor and the first capacitor; the rectifier circuit is connected to the secondary coil of the transformer, and the rectifier circuit is also used to connect the load.

[0034] In this embodiment, the power conversion device can be implemented using a half-bridge LLC resonant converter, which has strong applicability.

[0035] In one possible implementation, at least one bridge arm includes two bridge arms, with a first switch and a second switch in each bridge arm connected in series between the positive and negative terminals of the DC input. The power conversion device further includes a second inductor, a second capacitor, a second transformer, and a second rectifier circuit. The second inductor is connected to the midpoint of one bridge arm, the second capacitor is connected to the midpoint of the other bridge arm, and the primary coil of the second transformer is connected between the second inductor and the second capacitor. The second rectifier circuit is connected to the secondary coil of the second transformer and is also used to connect a load.

[0036] In this embodiment, the power conversion device can be implemented using a full-bridge LLC resonant converter, which has strong applicability.

[0037] In one possible implementation, at least one bridge arm includes three bridge arms, with a first and a second switch in each bridge arm connected in series between the positive and negative terminals of the DC input. The power conversion device also includes three resonant circuits, three third transformers, and a third rectifier circuit. Each resonant circuit includes a third capacitor, a third inductor, and a fourth inductor. The third capacitor is connected to the midpoint of a corresponding bridge arm, the third inductor is connected between the third capacitor and the fourth inductor, and the fourth inductor is also connected in parallel with the primary coil of a corresponding third transformer. The third rectifier circuit is connected to the secondary coil of each third transformer and is also used to connect a load.

[0038] In this embodiment, the power conversion device can be implemented using a three-phase LLC resonant converter, which has strong applicability.

[0039] In one possible implementation, at least one bridge arm includes a bridge arm, a first switch and a second switch connected in series between the positive and negative terminals of the DC input terminal; the power conversion device also includes a fifth inductor and a fourth capacitor; the fifth inductor is connected to the midpoint of the bridge arm, the four ends of the fourth capacitor are connected to the fifth inductor, the other end of the fourth capacitor is connected to the negative terminal of the DC input terminal, and the two ends of the fourth capacitor are also used to connect the load.

[0040] In this embodiment, the power conversion device can be implemented using a Buck converter, which has strong applicability.

[0041] In one possible implementation, at least one bridge arm includes a bridge arm, and the power conversion device further includes a sixth inductor and a fifth capacitor; one end of the sixth inductor is connected to the midpoint of the bridge arm, and the other end of the sixth inductor is used to connect to the positive terminal of the DC input terminal; the fifth capacitor is connected in parallel with the bridge arm, and both ends of the fifth capacitor are also used to connect to the load, and the end of the fifth capacitor connected to the negative terminal of the load is also used to connect to the negative terminal of the DC input terminal.

[0042] In this embodiment, the power conversion device can be implemented using a Boost converter, which has strong applicability.

[0043] Secondly, this application also provides a control method for a power conversion device. The control method is applied to a power conversion device including a sampling circuit and at least one bridge arm. The sampling circuit is connected to the midpoint of the bridge arm. The bridge arm includes a first switch and a second switch connected in series. During operation of the power conversion device, the first switch and the second switch are alternately turned on. The method includes: sampling the voltage at the midpoint of the bridge arm through the sampling circuit; during a first switching cycle and a second switching cycle of the first switch, when the second switch is turned off and the voltage difference across the first switch is less than or equal to a voltage difference threshold, controlling the first switch to turn on; the magnitude of the voltage difference across the first switch is positively or negatively correlated with the voltage at the midpoint of the bridge arm; wherein the first switching cycle and the second switching cycle are two adjacent switching cycles of the first switch, and the absolute value of the difference between the duration of the first switching cycle and the duration of the second switching cycle is greater than or equal to the first duration.

[0044] In one possible implementation, the method further includes: during a first switching cycle and a second switching cycle, when the second switch is turned off, and the duration experienced after the second switch is turned off is greater than or equal to the second duration, and the absolute value of the voltage difference across the first switch is less than or equal to a voltage difference threshold, controlling the first switch to turn on.

[0045] In one possible implementation, if the duration of the second switching cycle is greater than or equal to the duration of the first switching cycle, the duration from the second switch being turned off to the first switch being turned on within the first switching cycle is equal to a third duration, and the duration from the second switch being turned off to the first switch being turned on within the second switching cycle is equal to a fourth duration, and the fourth duration is less than or equal to the third duration.

[0046] In one possible implementation, if the duration of the second switching cycle is less than the duration of the first switching cycle, the duration from the second switch being turned off to the first switch being turned on in the first switching cycle is equal to the fifth duration, and the duration from the second switch being turned off to the first switch being turned on in the second switching cycle is equal to the sixth duration, and the sixth duration is greater than the fifth duration.

[0047] In one possible implementation, the sampling circuit is also connected to the other end of the first switching transistor connected to the midpoint of the bridge arm; the method further includes: sampling the voltage of the other end of the first switching transistor connected to the midpoint of the bridge arm through the sampling circuit, and obtaining the voltage difference across the first switching transistor based on the difference between the voltage of the other end of the first switching transistor connected to the midpoint of the bridge arm and the voltage at the midpoint of the bridge arm.

[0048] In one possible implementation, when the second switch is turned off and the voltage difference across the first switch is less than or equal to a voltage difference threshold, the first switch is controlled to turn on. Specifically, this includes: obtaining a pulse width modulation (PWM) reference signal for the second switch based on the switching frequency and duty cycle of the bridge arm; within the reference off-range of the second switch, the PWM reference signal for the second switch is equal to a first level; obtaining a soft-on signal for the first switch based on the voltage difference across the first switch; wherein, when the voltage difference across the first switch is less than or equal to the voltage difference threshold, the soft-on signal for the first switch is equal to a second level; and when the PWM signal for the second switch is equal to the first level and the soft-on signal for the first switch is equal to the second level, the first switch is controlled to turn on.

[0049] In one possible implementation, when the second switch is turned off, and the duration of time elapsed after the second switch is turned off is greater than or equal to a second duration, and the absolute value of the voltage difference across the first switch is less than or equal to a voltage difference threshold, the first switch is controlled to turn on. Specifically, this includes: obtaining the pulse width modulation (PWM) reference signal of the first switch and the PWM reference signal of the second switch based on the switching frequency and duty cycle of the bridge arm; wherein the interval between the falling edge of the PWM reference signal of the second switch and the rising edge of the adjacent PWM reference signal of the first switch is equal to the second duration; in the second switch… Within the reference off interval, the pulse width modulation signal of the second switch is equal to the first level; within the reference on interval of the first switch, the pulse width modulation signal of the first switch is equal to the third level; the soft-on signal of the first switch is obtained based on the voltage difference across the first switch; wherein, when the voltage difference across the first switch is less than or equal to the voltage difference threshold, the soft-on signal of the first switch is equal to the second level; when the pulse width modulation signal of the first switch is equal to the third level, and the soft-on signal of the first switch is equal to the second level, and the pulse width modulation signal of the second switch is equal to the first level, the first switch is controlled to turn on.

[0050] It should be understood that the implementations and beneficial effects of the above-mentioned aspects of this application can be referenced from each other. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of an application scenario for the communication base station power supply system provided in the embodiments of this application;

[0052] Figure 2 A schematic diagram of a half-bridge LLC resonant converter provided in an embodiment of this application;

[0053] Figure 3 A schematic diagram of a full-bridge LLC resonant converter provided in an embodiment of this application;

[0054] Figure 4 A schematic diagram of a three-phase LLC resonant converter provided in an embodiment of this application;

[0055] Figure 5 A schematic diagram of the Buck converter provided in the embodiments of this application;

[0056] Figure 6 This is a schematic diagram of the Boost converter provided in an embodiment of this application;

[0057] Figure 7 This is a schematic diagram of the power conversion device provided in an embodiment of this application;

[0058] Figure 8a A schematic diagram of a pulse width modulation signal for a switching transistor provided in an embodiment of this application;

[0059] Figure 8b This is a schematic diagram of another pulse width modulation signal for the switching transistor provided in an embodiment of this application;

[0060] Figure 9 This is a schematic diagram of an electrical signal change provided in an embodiment of this application;

[0061] Figure 10 This is another structural schematic diagram of the power conversion device provided in the embodiments of this application;

[0062] Figure 11 This is another schematic diagram of electrical signal changes provided in an embodiment of this application;

[0063] Figure 12a This is yet another schematic diagram of electrical signal changes provided in an embodiment of this application;

[0064] Figure 12b This is yet another schematic diagram of electrical signal changes provided in an embodiment of this application;

[0065] Figure 13a This is yet another schematic diagram of electrical signal changes provided in an embodiment of this application;

[0066] Figure 13b This is yet another schematic diagram of electrical signal changes provided in an embodiment of this application;

[0067] Figure 14 This is a schematic flowchart of a control method for a power conversion device provided in an embodiment of this application. Detailed Implementation

[0068] The power conversion device provided in this application is suitable for various application scenarios, such as communication base station power supply scenarios, data center power supply scenarios, new energy power supply scenarios, energy storage power supply scenarios, or uninterruptible power supply scenarios. Specifically, it can be applied to devices with DC-DC voltage conversion functions, such as blade power supplies, vehicle chargers, and switching power supplies. For ease of understanding, the following description uses the application of the power conversion device in a communication base station power supply system as an example.

[0069] Please see Figure 1 , Figure 1 This is a schematic diagram of an application scenario for the power supply system for a communication base station provided in an embodiment of this application. Figure 1 The communication base station power supply system 100 shown includes a filter 110, a rectifier 120, and a power conversion device 130 connected in sequence. The input terminal of the filter 110 is connected to the power grid, and the output terminal of the power conversion device 130 is connected to the DC bus of the communication base station power supply system 100. The filter 110 filters the AC power input from the power grid to eliminate high-frequency noise and harmonic interference, ensuring the communication quality of the communication base station. The rectifier 120 converts the AC power output from the filter 110 into DC power and outputs it to the power conversion device 130. The power conversion device 130 converts and regulates the voltage of the DC power output from the rectifier 120, for example, converting approximately 400 volts of DC power into 48 volts of regulated DC power, and outputting it to the DC bus. The DC bus transmits and distributes DC power to various loads of the communication base station, such as the antenna system, radio frequency unit, baseband unit, and corresponding supporting systems. In addition, to ensure power supply to the communication base station during power grid outages, the communication base station power supply system 100 also includes at least one battery module, such as battery module 140 and battery module 1n0, where n is a positive integer greater than or equal to 5. When the power grid is operating stably, the battery modules draw DC power from the DC bus for charging. During power grid outages, the battery modules discharge power to the DC bus, allowing the DC bus to continuously supply power to the load, thereby preventing communication network interruptions due to power loss.

[0070] Therefore, power conversion devices are used in communication base station power supply systems to convert DC power voltage and achieve regulated output. Specifically, the power conversion device internally has at least one bridge arm, and each bridge arm includes two switching transistors connected in series. By controlling the two switching transistors of each bridge arm to alternately conduct, the power conversion device can convert the input DC power voltage. Furthermore, as described in the background art above, to avoid a short circuit caused by the simultaneous conduction of the two switching transistors, the power conversion device can set a dead time between the switching actions of the two switching transistors. Moreover, by adjusting the duration of the dead time, the power conversion device can also control the switching transistors to achieve ZVS, thereby reducing switching losses. However, since the dead time required for the power conversion device to control the switching transistors to achieve ZVS varies under different operating conditions, and conventional dead time adjustment methods have many limitations, the power conversion device experiences a significant delay in adjusting the dead time under dynamic operating conditions. In other words, conventional power conversion devices may not be able to control the switching transistors to achieve ZVS under dynamic operating conditions, resulting in significant switching losses. Therefore, how to ensure that the switching transistors can achieve ZVS when the operating conditions of power conversion equipment change dynamically is a technical problem that urgently needs to be solved by those skilled in the art.

[0071] Based on this, the present application provides a power conversion device and its control method. The power conversion device can ensure that the switching transistor can achieve ZVS when the operating conditions of the power conversion device change dynamically, and has strong applicability.

[0072] The above are merely examples of application scenarios for the power conversion device provided in this application, and are not exhaustive. This application does not limit the application scenarios.

[0073] The following content combines Figures 2 to 13b The specific implementation principle of the power conversion device provided in the embodiments of this application will be introduced.

[0074] For ease of understanding, the following is a brief introduction to the circuit topology of the power conversion device provided in the embodiments of this application.

[0075] In some feasible implementations, the power conversion device provided in this application embodiment can be specifically implemented using a half-bridge LLC resonant converter. For the specific structure of this half-bridge LLC resonant converter, please refer to... Figure 2 As shown, Figure 2 This is a schematic diagram of a half-bridge LLC resonant converter provided in an embodiment of this application. Figure 2The shown half-bridge LLC resonant converter 200 has its DC input terminals (positive i+ and negative i-) for receiving externally input DC power, and its DC output terminals (positive o+ and negative o-) for outputting regulated DC power. For example, when the half-bridge LLC resonant converter 200 is applied in… Figure 1 In the application scenario shown, the DC input terminal can be understood as one end of the power conversion device 130 used to connect to the rectifier 120, and the DC output terminal can be understood as one end of the power conversion device 130 used to connect to the DC bus.

[0076] The half-bridge LLC resonant converter 200 internally includes a first capacitor C1, a first inductor L1, a first transformer 210, a first rectifier circuit 220, a first switch Q1, and a second switch Q2. The first switch Q1 and the second switch Q2 are connected in series between the positive terminal i+ and the negative terminal i- of the DC input, forming one arm of the half-bridge LLC resonant converter 200. The midpoint M1 of this arm is connected to the first inductor L1, and the first inductor L1, the primary coil of the first transformer 210, and the first capacitor C1 are connected sequentially. The first capacitor C1 is also connected to the negative terminal i- of the DC input. The primary coil and the secondary coil of the first transformer 210 are coupled together. The first rectifier circuit 220 is connected to the secondary coil of the first transformer 210, and the first rectifier circuit 220 is also connected to the positive terminal o+ and the negative terminal o- of the DC output. The positions of the first switch Q1 and the second switch Q2 can be interchanged. Figure 2 The example shown is for illustrative purposes only.

[0077] In some feasible implementations, the power conversion device provided in this application embodiment can also be implemented using a full-bridge LLC resonant converter. For the specific structure of this full-bridge LLC resonant converter, please refer to... Figure 3 As shown, Figure 3 This is a schematic diagram of a full-bridge LLC resonant converter provided in an embodiment of this application. Figure 3 In the above, the implementation methods of the DC input and DC output terminals of the full-bridge LLC resonant converter 300 are the same as those described above. Figure 2 The DC input and DC output terminals of the half-bridge LLC resonant converter 200 shown are implemented in a similar manner, and will not be described in detail here.

[0078] The full-bridge LLC resonant converter 300 internally includes a second capacitor C2, a second inductor L2, a second transformer 310, a second rectifier circuit 320, first switching transistors Q11 and Q12, second switching transistors Q21 and Q22. The first switching transistors Q11 and Q21 are connected in series between the positive and negative terminals i+ and i- of the DC input, forming one arm of the full-bridge LLC resonant converter 300, with the midpoint M1 of this arm connected to the second inductor L2. The first switching transistors Q12 and Q22 are connected in series between the positive and negative terminals i+ and i- of the DC input, forming the other arm of the full-bridge LLC resonant converter 300, with the midpoint M2 of this arm connected to the second capacitor C2. The primary coil of the second transformer 310 is positioned between the second inductor L2 and the second capacitor C2. The primary and secondary coils of the second transformer 310 are coupled together. The second rectifier circuit 320 is connected to the secondary coil of the second transformer 310. The second rectifier circuit 320 is also connected to the positive (o+) and negative (o-) terminals of the DC output. The positions of the first and second switching transistors in each bridge arm can be interchanged. Figure 3 The example shown is for illustrative purposes only.

[0079] In some feasible implementations, the power conversion device provided in this application embodiment can also be implemented using a three-phase LLC resonant converter. For the specific structure of this three-phase LLC resonant converter, please refer to... Figure 4 As shown, Figure 4 This is a schematic diagram of a three-phase LLC resonant converter provided in an embodiment of this application. Figure 4 In the above, the implementation methods of the DC input and DC output terminals of the three-phase LLC resonant converter 400 are the same as those described above. Figure 2 The DC input and DC output terminals of the half-bridge LLC resonant converter 200 shown are implemented in a similar manner, and will not be described in detail here.

[0080] Figure 4The three-phase LLC resonant converter 400 shown internally includes three resonant circuits, three third transformers, a third rectifier circuit 430, first switching transistors Q11, Q12, and Q13, second switching transistors Q21, Q22, and Q23. The first switching transistors Q11 and Q21 are connected in series between the positive and negative terminals i+ and i- of the DC input, forming one arm of the three-phase LLC resonant converter 400. The midpoint M1 of this arm is connected to the resonant circuit 411. The resonant circuit 411 includes a third capacitor C31, a third inductor L31, and a fourth inductor L41 connected in sequence. The fourth inductor L41 is connected in parallel with the primary coil of the third transformer 421. The primary and secondary coils of the third transformer 421 are coupled together. The third rectifier circuit 430 is connected to the secondary coil of the third transformer 421 and is also connected to the positive and negative terminals o+ and o- of the DC output. Similarly, the first switch Q12 and the second switch Q22 are connected in series between the positive terminal i+ and the negative terminal i- of the DC input, forming another bridge arm of the three-phase LLC resonant converter 400, and the midpoint M2 of this bridge arm is connected to the resonant circuit 412. The resonant circuit 412 includes a third capacitor C32, a third inductor L32, and a fourth inductor L42 connected in sequence, with the fourth inductor L42 connected in parallel with the primary coil of the third transformer 422. The primary coil and secondary coil of the third transformer 422 are coupled together. The third rectifier circuit 430 is connected to the secondary coil of the third transformer 422. Similarly, the first switch Q13 and the second switch Q23 are connected in series between the positive terminal i+ and the negative terminal i- of the DC input, forming yet another bridge arm of the three-phase LLC resonant converter 400, and the midpoint M3 of this bridge arm is connected to the resonant circuit 413. The resonant circuit 413 includes a third capacitor C33, a third inductor L33, and a fourth inductor L43 connected in sequence, with the fourth inductor L43 connected in parallel with the primary coil of the third transformer 423. The primary and secondary coils of the third transformer 423 are coupled together. The third rectifier circuit 430 is connected to the secondary coil of the third transformer 423. The positions of the first and second switching transistors in each of the above bridge arms can be interchanged. Figure 4 The example shown is for illustrative purposes only.

[0081] It should be noted that during operation, the half-bridge LLC resonant converter 200, full-bridge LLC resonant converter 300, and three-phase LLC resonant converter 400 can control the alternating conduction of the first and second switching transistors in each bridge arm to convert the DC input voltage to the DC output voltage. The specific working principles of the voltage conversion achieved by the half-bridge LLC resonant converter 200, full-bridge LLC resonant converter 300, and three-phase LLC resonant converter 400 can be found in existing technical descriptions and will not be elaborated upon here.

[0082] In some feasible implementations, the power conversion device provided in this application embodiment can also be implemented using a Buck converter. For the specific structure of the Buck converter, please refer to... Figure 5 As shown, Figure 5 This is a schematic diagram of the Buck converter provided in an embodiment of this application. Figure 5 In this context, the implementation of the DC input and DC output terminals of the Buck converter 500 is similar to that described above. Figure 2 The DC input and DC output terminals of the half-bridge LLC resonant converter 200 shown are implemented in a similar manner, and will not be described in detail here.

[0083] Figure 5 The Buck converter 500 shown internally includes a fourth capacitor C4, a fifth inductor L5, a first switch Q1, and a second switch Q2. The first switch Q1 and the second switch Q2 are connected in series between the positive terminal i+ and the negative terminal i- of the DC input, forming one arm of the Buck converter 500. The midpoint M1 of this arm is connected to one end of the fifth inductor L5, and the other end of the fifth inductor L5 is connected to one end of the fourth capacitor C4. One end of the fourth capacitor C4 is also connected to the positive terminal o+ of the DC output, and the other end of the fourth capacitor C4 is connected to both the negative terminal i+ of the DC input and the negative terminal o- of the DC output. Furthermore, the positions of the first switch Q1 and the second switch Q2 can be interchanged. Figure 5 The example shown is for illustrative purposes only.

[0084] During operation, the Buck converter 500 can alternately turn on the first switch Q1 and the second switch Q2 to step down the DC input voltage and output it to the DC output voltage. The specific working principle of the Buck converter 500 in achieving voltage conversion can be found in existing technical descriptions, and will not be elaborated here.

[0085] In some feasible implementations, the power conversion device provided in this application embodiment can also be implemented using a Boost converter. For the specific structure of the Boost converter, please refer to... Figure 6 As shown, Figure 6 This is a schematic diagram of the Boost converter provided in an embodiment of this application. Figure 6 In the above, the implementation of the DC input and DC output terminals of the Boost converter 600 is the same as described above. Figure 2 The DC input and DC output terminals of the half-bridge LLC resonant converter shown are implemented in a similar manner, and will not be described in detail here.

[0086] Figure 6The Boost converter 600 shown internally includes a fifth capacitor C5, a sixth inductor L6, a first switch Q1, and a second switch Q2. The first switch Q1 and the second switch Q2 form one arm of the Boost converter 600, and the sixth inductor L6 is positioned between the midpoint M1 of this arm and the positive terminal i+ of the DC input. The fifth capacitor C5 is connected in parallel with this arm between the positive terminal o+ and the negative terminal o- of the DC output, and is also connected to the negative terminal i- of the DC input. Furthermore, the positions of the first switch Q1 and the second switch Q2 can be interchanged. Figure 6 The example shown is for illustrative purposes only.

[0087] It should be noted that during operation, the Boost converter 600 can alternately turn on the first switch Q1 and the second switch Q2 to boost the DC input voltage and output it to the DC output voltage. The specific working principle of the Boost converter 600 in achieving voltage conversion can be found in existing technical descriptions, and will not be elaborated here.

[0088] In this embodiment of the application, the power conversion device can also be implemented using other types of circuit topologies, as described above. Figures 2 to 6 The illustration is merely an example. Furthermore, when the operating conditions of the power conversion device change dynamically, the implementation methods for adaptively adjusting the dead time of the switching transistors (such as the first and second switching transistors mentioned above) in each bridge arm are similar for different types of power conversion devices. For ease of explanation, the following description uses the adaptive adjustment of the dead time of a switching transistor in one bridge arm as an example. Simultaneously, since the implementation methods for adaptively adjusting the dead time of a switching transistor in one bridge arm to achieve ZVS for the first or second switching transistor are similar, the following description uses the example of the power conversion device controlling the first switching transistor in one bridge arm to achieve ZVS. The implementation methods for the power conversion device controlling the second switching transistor or other bridge arm switching transistors to achieve ZVS can be referred to the following specific embodiments, which will not be elaborated upon in this application.

[0089] For details, please refer to Figure 7 , Figure 7 This is a schematic diagram of the power conversion device provided in an embodiment of this application. Figure 7The power conversion device 700 shown includes a controller 710 and a first switch Q1 and a second switch Q2 connected in series. The controller 710 is connected to the control electrodes of both the first switch Q1 and the second switch Q2. During operation of the power conversion device 700, the controller 710 controls the first switch Q1 and the second switch Q2 to perform corresponding switching actions by transmitting corresponding pulse width modulation (PWM) signals to the control electrodes of the first switch Q1 and the second switch Q2. For an example, please refer to [link to example]. Figure 8a and Figure 8b , Figure 8a This is a schematic diagram of a pulse width modulation signal for a switching transistor provided in an embodiment of this application. Figure 8b This is a schematic diagram of another pulse width modulation signal for the switching transistor provided in an embodiment of this application. Figure 8a and Figure 8b In this diagram, PWM1 represents the PWM signal of the first switch Q1, and PWM2 represents the PWM signal of the second switch Q2. When the level of PWM1 equals Va1, the controller 710 controls the first switch Q1 to turn on; when the level of PWM1 equals Va2, the controller 710 controls the first switch Q1 to turn off. When the level of PWM2 equals Vb1, the controller 710 controls the second switch Q2 to turn on; when the level of PWM2 equals Vb2, the controller 710 controls the second switch Q2 to turn off. Therefore, the controller 710 can control the first switch Q1 and the second switch Q2 to alternately turn on by adjusting the alternating levels of PWM1 and PWM2.

[0090] It is understandable that during the alternating conduction of the first switch Q1 and the second switch Q2, after the second switch Q2 switches from on to off, when both the first and second switches Q1 remain off, the first and second switches Q1 enter a dead time, which ends when the first switch Q1 turns on. Therefore, the length of this dead time (i.e., dead duration) is the time elapsed from the second switch Q2 turning off to the first switch Q1 turning on. When the dead duration is appropriate, when the controller 710 controls the first switch Q1 to turn on, the resonant current generated within the power conversion device 700 can precisely reduce the voltage across the first switch Q1 to 0, thereby controlling the first switch Q1 to achieve ZVS. However, if the dead duration is too short or too long, the first switch Q1 may not be able to achieve ZVS.

[0091] For example, please refer to again Figure 2During the alternating conduction of the first switch Q1 and the second switch Q2, when the first switch Q1 is off and the second switch Q2 is on, the resonant current generated by the resonant cavity formed by the first inductor, the first capacitor, and the first transformer flows through the second switch Q2. Furthermore, when the second switch Q2 switches from on to off, and the first switch Q1 remains off, both switches enter a dead time. At this time, since the direction of the resonant current cannot change abruptly, the resonant current flows through the parasitic capacitance of the first switch Q1 and the parasitic capacitance of the second switch Q2, respectively, causing the parasitic capacitance of the first switch Q1 to discharge and the parasitic capacitance of the second switch Q2 to charge. After the parasitic capacitance of the second switch Q2 is fully charged and the parasitic capacitance of the first switch Q1 is fully discharged, the remaining resonant current flows through the parasitic diode of the first switch Q1, making the voltage difference across the first switch Q1 close to zero. If the dead time ends just then, and the controller 710 switches the first switch Q1 from off to on, then the first switch Q1 can achieve ZVS (Zero Voltage Switching). Therefore, whether the first switch Q1 achieves ZVS depends on the resonant current during the dead time precisely discharging the parasitic capacitance of the first switch Q1 to zero and maintaining this voltage until the first switch Q1 is turned on. In some applications, when the dead time is too long, the resonant current may cross zero before the dead time ends and flow in reverse through the parasitic capacitance of the first switch Q1. This causes the parasitic capacitance of the first switch Q1 to recharge after discharging, increasing the voltage difference across the first switch Q1 to a non-zero value. Therefore, when the controller 710 turns the first switch Q1 on, the first switch Q1 cannot achieve ZVS. Alternatively, in other applications, when the dead time is too short, the resonant current provides insufficient discharge time for the parasitic capacitance of the first switch Q1, preventing it from fully discharging to zero voltage. Therefore, when the first switch Q1 is turned on, the first switch Q1 also cannot achieve ZVS.

[0092] Therefore, both excessively short and excessively long dead times will prevent the first switch Q1 from achieving ZVS, thereby increasing switching losses and heat generation. Thus, to ensure that the first switch Q1 can achieve ZVS, the controller needs to appropriately adjust the dead time. Furthermore, when the operating conditions of the power conversion equipment change, the controller will adjust the switching frequencies of the first switch Q1 and the second switch Q2 (hereinafter referred to as switching frequencies) to ensure output voltage stability. Adjusting the switching frequencies will cause changes in the dead time required for the first switch Q1 to achieve ZVS.

[0093] For example, please refer to again Figure 2During the operation of the half-bridge LLC resonant converter 200, when the input voltage at the DC input terminal increases or the load connected to the DC output terminal decreases, the controller increases the switching frequency to reduce the gain of the half-bridge LLC resonant converter 200 and ensure output voltage stability. However, the increased switching frequency leads to a decrease in the resonant current, which in turn makes the time required for the parasitic capacitance of the first switch Q1 to discharge to zero longer, meaning the dead time required for the first switch Q1 to achieve ZVS (Zero-Voltage-Free Switching) is longer. Conversely, when the input voltage at the DC input terminal decreases or the load connected to the DC output terminal increases, the controller decreases the switching frequency of the first switch Q1 and the second switch Q2, significantly increasing the resonant current to improve the gain of the half-bridge LLC resonant converter 200 and ensure output voltage stability. Understandably, due to the increased resonant current, the time required for the parasitic capacitance of the first switch Q1 to discharge to zero is shorter, thus the dead time required for the first switch Q1 to achieve ZVS is also shorter. Therefore, under the dynamic changes of the operating conditions of the half-bridge LLC resonant converter 200, the controller needs to reasonably adjust the dead time according to the change of the switching frequency to ensure that the first switching transistor Q1 can achieve ZVS at different switching frequencies.

[0094] In this embodiment, to ensure that the first switch Q1 can achieve ZVS at different switching frequencies, the controller 710 determines whether the first switch Q1 can achieve ZVS before each time it is turned on, and only turns on the first switch Q1 when it is determined that ZVS can be achieved. It can be understood that, regardless of the switching frequency, as long as the controller 710 only turns on the first switch Q1 when ZVS can be achieved, it can guarantee that the first switch Q1 can achieve ZVS every time it is turned on, that is, the first switch Q1 can achieve ZVS at different switching frequencies.

[0095] Specifically, to determine whether the first switch Q1 can achieve ZVS before each turn-on, the controller 710 can detect whether the voltage difference across the first switch Q1 is close to zero during each switching cycle of the first switch Q1. Here, the switching cycle of the first switch Q1 refers to the time interval from when the first switch Q1 is turned off to when it is turned off again. For example, as... Figure 8a and Figure 8bT1, T2, and T3 shown represent the three switching cycles of the first switch Q1. Alternatively, the switching cycle of the first switch Q1 can also be the time interval from when the first switch Q1 is turned on to when it is turned on again; this embodiment of the application does not impose such a limitation. For ease of explanation, the switching cycle of the first switch Q1 described below refers to the time interval from when the first switch Q1 is turned off to when it is turned off again. Furthermore, when the voltage difference across the first switch Q1 is close to zero, the first switch Q1 does not generate switching losses when it is turned on, that is, the first switch Q1 can achieve ZVS. Therefore, the controller 710 can determine that the first switch Q1 can achieve ZVS when it detects that the voltage difference across the first switch Q1 is close to zero.

[0096] Specifically, in this embodiment, when the voltage difference across the first switch Q1 is less than or equal to a voltage difference threshold, the voltage difference across the first switch Q1 is close to zero. Therefore, in each switching cycle of the first switch Q1, when both the first switch Q1 and the second switch Q2 remain off (i.e., within the dead time), if the controller 710 detects that the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold, indicating that the first switch Q1 can achieve ZVS, the controller 710 can control the first switch Q1 to turn on and achieve ZVS, thereby ensuring that the first switch Q1 can achieve ZVS in each switching cycle. The aforementioned voltage difference threshold is typically close to zero, and its specific value depends on the requirements of the actual application scenario; therefore, it is not limited here.

[0097] For example, such as Figure 8a and Figure 8b As shown, the first switch Q1 will be turned on once in each switching cycle. For example, Figure 8a The time intervals t2 and t4 in the text Figure 8b The times t6 and t8 in the diagram represent the times when the first switch Q1 is turned on within its corresponding switching cycle. Within each switching cycle, regardless of the switching frequency, as long as the voltage difference across the first switch Q1 is close to zero, it means that the first switch Q1 can achieve ZVS (Zero-Voltage Switching). Therefore, in this embodiment, the controller 710 only needs to control the first switch Q1 to turn on when it detects that the voltage difference across the first switch Q1 is close to zero within each switching cycle of the first switch Q1, while the second switch Q2 is off, thus ensuring that the first switch Q1 achieves ZVS at different switching frequencies.

[0098] In some application scenarios, conventional power conversion devices have many limitations in adjusting dead time, resulting in significant delays in dead time adjustment under dynamic operating conditions. This prevents the first switch Q1 from achieving Zero-Switching-Time (ZVS) in every switching cycle. In contrast, in the power conversion device provided in this embodiment, the controller 710 can control the first switch Q1 to achieve ZVS in every switching cycle when the operating conditions of the power conversion device 700 change dynamically, resulting in high adjustment efficiency and strong reliability. To facilitate understanding of the differences between the power conversion device provided in this embodiment and conventional power conversion devices, the following describes how the controller controls the first switch Q1 to achieve ZVS under dynamic operating conditions of the power conversion device.

[0099] Specifically, as described above, when the operating conditions of the power conversion device 700 change, the controller 710 dynamically adjusts the switching frequencies of the first switch Q1 and the second switch Q2. The switching frequency of the first switch Q1 is equal to the reciprocal of its cycle duration (i.e., the duration of one switching cycle). Therefore, when the switching frequencies of the first and second switches Q1 change dynamically, the cycle duration of the first switch Q1's switching cycle also changes accordingly, resulting in different cycle durations for adjacent switching cycles. Thus, when the first and second switching cycles are adjacent to the first switch Q1, when the operating conditions of the power conversion device 700 change, the cycle durations of adjacent first and second switching cycles will be different. Specifically, in this embodiment, when the switching frequency of the first switch Q1 changes, the absolute value of the difference between the cycle duration of the first and second switching cycles will be greater than or equal to the first duration. The specific value of this first duration depends on the requirements of the actual application scenario and is not limited here.

[0100] In this embodiment, when the switching frequency of the first switch Q1 changes, causing the absolute value of the difference between the duration of the first switching cycle and the duration of the second switching cycle to be greater than or equal to the first duration, the controller 710 controls the first switch Q1 to turn on when the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold and the second switch Q2 is turned off during the first switching cycle and the second switching cycle. This enables the first switch Q1 to achieve ZVS in both the first and second switching cycles, that is, to control the first switch Q1 to achieve ZVS when the switching frequency changes.

[0101] For example, please refer to Figure 8a As shown. In Figure 8aIn the diagram, T1 is the first switching cycle, and T2 is the second switching cycle. The absolute value of the difference between the cycle length of T2 and the cycle length of T1 is greater than or equal to the first cycle length. Within T1, the controller 710 controls the second switch Q2 to turn off at time t1 and detects at time t2 that the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold. Therefore, the controller 710 can control the first switch Q1 to turn on at time t2 and achieve ZVS. The time length from time t1 to time t2 is the dead time s1 of T1. Similarly, within T2, the controller 710 controls the second switch Q2 to turn off at time t3 and detects at time t4 that the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold. Therefore, the controller 710 can control the first switch Q1 to turn on at time t4 and achieve ZVS. The time length from time t3 to time t4 is the dead time s2 of T2. Clearly, s2 is less than or equal to s1.

[0102] Therefore, when the switching frequency changes, causing variations in the duration of the first and second switching cycles, the controller provided in this embodiment can control the first switch Q1 to achieve ZVS within both the first and second switching cycles, while simultaneously enabling adaptive adjustment of the dead time within both cycles according to the switching frequency. In contrast, in conventional power conversion equipment, when the operating conditions change dynamically, the first switch Q1 typically requires a delay of several switching cycles to achieve ZVS due to the significant delay in dead time adjustment. Therefore, the first switch Q1 in conventional power conversion equipment may not be able to achieve ZVS in both adjacent first and second switching cycles.

[0103] In summary, conventional power conversion equipment cannot guarantee that the first switching transistor Q1 will achieve ZVS in every switching cycle under dynamic operating conditions. However, in the embodiments of this application, even when the operating conditions of the power conversion equipment change dynamically, the controller can control the first switching transistor Q1 to achieve ZVS in every switching cycle regardless of the switching frequency, thus solving the problem of adjustment delay and improving reliability.

[0104] In some feasible implementations, as can be seen from the above, when the controller 710 adjusts the switching frequency of the first switch Q1 to decrease, the dead time required for the first switch Q1 to achieve ZVS will be shorter. Therefore, if the period of the second switching cycle is greater than or equal to the period of the first switching cycle, when the controller 710 controls the first switch Q1 to achieve ZVS within the first and second switching cycles, the dead time of the second switching cycle will be less than or equal to the dead time of the first switching cycle. Specifically, in the embodiments of this application, when the dead time of the first switching cycle is equal to the third duration and the dead time of the second switching cycle is equal to the fourth duration, the fourth duration is less than or equal to the third duration. The third duration is the time elapsed from the second switch Q2 being turned off to the first switch Q1 being turned on within the first switching cycle, and the fourth duration is the time elapsed from the second switch Q2 being turned off to the first switch Q1 being turned on within the second switching cycle.

[0105] For example, please refer to Figure 8a As shown. In Figure 8a In the diagram, T1 is the first switching cycle, and T2 is the second switching cycle, with the duration of T2 being significantly greater than or equal to the duration of T1. Within T1, the controller 710 controls the second switch Q2 to turn off at time t1, and detects at time t2 that the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold. Therefore, the controller 710 can control the first switch Q1 to turn on at time t2, achieving zero-voltage switching (ZVS). The time length from time t1 to time t2 is the dead time s1 of T1. Similarly, within T2, the controller 710 controls the second switch Q2 to turn off at time t3, and detects at time t4 that the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold. Therefore, the controller 710 can control the first switch Q1 to turn on at time t4, achieving ZVS. The time length from time t3 to time t4 is the dead time s2 of T2. Clearly, s2 is less than or equal to s1.

[0106] In some feasible implementations, as can be seen from the above, when the controller 710 increases the switching frequency of the first switch Q1, the dead time required for the first switch Q1 to achieve ZVS will be longer. Therefore, if the period of the second switching cycle is shorter than the period of the first switching cycle, when the controller 710 controls the first switch Q1 to achieve ZVS within the first and second switching cycles, the dead time of the second switching cycle will be longer than the dead time of the first switching cycle. Specifically, in the embodiments of this application, when the dead time of the first switching cycle is equal to the fifth duration and the dead time of the second switching cycle is equal to the sixth duration, the sixth duration is longer than the fifth duration. Here, the fifth duration is the time elapsed from the second switch Q2 being turned off to the first switch Q1 being turned on within the first switching cycle, and the sixth duration is the time elapsed from the second switch Q2 being turned off to the first switch Q1 being turned on within the second switching cycle.

[0107] For example, please refer to Figure 8b As shown. In Figure 8b In the diagram, T3 is the first switching cycle, and T4 is the second switching cycle, with the cycle length of T4 being significantly shorter than that of T3. At time t5 within T3, controller 710 controls the second switch Q2 to turn off, and at time t6, detects that the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold. Therefore, controller 710 can control the first switch Q1 to turn on at time t6, achieving ZVS (Zero-Voltage Switching). The time length from time t5 to time t6 is the dead time s3 of T3. Similarly, at time t7 within T4, controller 710 controls the second switch Q2 to turn off, and at time t8, detects that the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold. Therefore, controller 710 can control the first switch Q1 to turn on at time t8, achieving ZVS. The time length from time t7 to time t8 is the dead time s4 of T4. Clearly, s4 is greater than s3.

[0108] To facilitate understanding of the specific implementation principle of the controller in the embodiments of this application, the following content is combined with Figures 7 to 1 3. The specific implementation principle of the controller will be introduced.

[0109] Understandably, to determine whether the first switch Q1 can achieve ZVS, the controller 710 needs to detect whether the voltage difference across the first switch Q1 is less than or equal to a voltage difference threshold. This voltage difference is equal to the difference between the voltage at the other end of the bridge arm connected to the first switch Q1 (hereinafter referred to as the other end of the first switch Q1) and the voltage at the bridge arm midpoint M1. Therefore, to detect whether the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold, the controller 710 can pre-set the relationship between the voltage at the bridge arm midpoint M1 and the voltage difference across the first switch Q1, and obtain the voltage at the bridge arm midpoint M1. Based on the voltage at the bridge arm midpoint M1, the controller 710 can determine whether the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold.

[0110] It should be noted that when the other end of the first switching transistor Q1 is connected to the positive terminal of the DC input, the voltage difference across the first switching transistor Q1 is equal to the voltage at the other end of the first switching transistor Q1 minus the voltage at the midpoint M1 of the bridge arm. Therefore, the magnitude of the voltage difference across the first switching transistor Q1 is negatively correlated with the magnitude of the voltage at the midpoint M1 of the bridge arm. Conversely, when the other end of the first switching transistor Q1 is connected to the negative terminal of the DC input, the voltage difference across the first switching transistor Q1 is equal to the voltage at the midpoint M1 of the bridge arm minus the voltage at the other end of the first switching transistor Q1. Therefore, the magnitude of the voltage difference across the first switching transistor Q1 is positively correlated with the magnitude of the voltage at the midpoint M1 of the bridge arm.

[0111] Specifically, in order to obtain the voltage magnitude at the midpoint M1 of the bridge arm, Figure 7 The power conversion device 700 shown also includes a sampling circuit 720. The input of the sampling circuit 720 is connected to the midpoint M1 of the bridge arm, and it acquires and processes the voltage magnitude at the midpoint M1. Simultaneously, the output of the sampling circuit 720 is connected to a controller 710, and it can send the processed voltage at the midpoint M1 to the controller 710. For an example, please refer to [reference needed]. Figure 9 , Figure 9 This is a schematic diagram of an electrical signal change provided in an embodiment of this application. Figure 9 In the diagram, Vmid represents the voltage signal transmitted to the controller 710 after the sampling circuit 720 collects and processes the voltage at the midpoint M1 of the bridge arm. Vin+ represents the voltage at the other end of the first switch Q1, and Vin- represents the voltage at the other end of the second switch Q2. It can be understood that since the voltage at the midpoint M1 of the bridge arm is related to the voltage difference across the first switch Q1, Vmid can be used to represent the voltage difference across the first switch Q1. Furthermore, as the first switch Q1 and the second switch Q2 alternately conduct, Vmid will vary between Vin+ and Vin-.

[0112] In some feasible implementations, the voltage at the other end of the first switching transistor Q1 may not remain stable. Therefore, to ensure sampling accuracy, the sampling circuit described above can also sample the voltage at the other end of the first switching transistor Q1. For details, please refer to... Figure 10 , Figure 10 Another structural schematic diagram of the power conversion device provided in an embodiment of this application is shown. Figure 10 As shown, the power conversion device 1000 includes a controller 1100 and a sampling circuit 1120. The input terminal of the sampling circuit 1120 is connected not only to the midpoint M1 of the bridge arm but also to the other end of the first switching transistor Q1. The sampling circuit 1120 can collect and process the voltage magnitudes at the midpoint M1 of the bridge arm and the other end of the first switching transistor Q1, and then send the processed voltage signal Vmid to the controller 1100.

[0113] In some feasible implementations, in order to determine whether the voltage difference across the first switching transistor Q1 is less than or equal to a voltage difference threshold based on the voltage signal Vmid sent by the sampling circuit 1120, the controller 1100 internally includes a comparison module 1110. This comparison module 1110 can compare the voltage magnitude of the voltage signal Vmid sent by the sampling circuit 1120 and determine whether the voltage difference across the first switching transistor Q1 is less than or equal to the voltage difference threshold based on the comparison result.

[0114] For example, please refer to again Figure 9 .exist Figure 9 In this context, Vref1 equals Vin + minus the voltage difference threshold. Therefore, when Vmid is greater than or equal to Vref1, the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold. CMP-OUT1 is the soft-on signal for the first switch Q1 output by the comparator module 1110. Figure 9 During the periods t11, t12, and t13 shown, when Vmid is greater than or equal to Vref1, the level of the CMP-OUT1 output by the comparison module 1110 is equal to the second level V2, indicating that the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold. Conversely, when the level of the CMP-OUT1 output by the comparison module 1110 is not equal to V2, it indicates that the voltage difference across the first switch Q1 is greater than the voltage difference threshold. Similarly, the controller 1100 can determine whether the voltage difference across the second switch Q2 is less than or equal to the voltage difference threshold based on the same implementation principle. For example, as... Figure 9As shown, Vin- represents the voltage at the negative terminal of the DC input connected to the second switch Q2, meaning Vin- equals the voltage at the other end of the second switch Q2. Vref2 equals Vin- plus the voltage difference threshold. Therefore, when Vmid is less than or equal to Vref2, the voltage difference across the second switch Q2 is less than or equal to the voltage difference threshold. At this time, the soft-on signal CMP-OUT2 output by the comparator module 1110 for the second switch Q2 is equal to the second level V2, indicating that the voltage difference across the second switch Q2 is less than or equal to the voltage difference threshold.

[0115] Furthermore, such as Figure 10 As shown, the controller 1100 also includes a logic module 1120, which receives the CMP-OUT1 output by the comparison module 1110 and outputs a logic signal TZa. Specifically, when the level of CMP-OUT1 received by the logic module 1120 is equal to the second level, the level of the logic signal TZa output by the logic module 1120 is equal to the fourth level. Therefore, the fact that the logic signal TZa output by the logic module 1120 is equal to the fourth level indicates that the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold.

[0116] As described above, in order to control the first switch Q1 to achieve ZVS, the controller 1100 needs to detect whether the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold, and also needs to determine whether the second switch Q2 is turned off. For this purpose, the controller 1100 also includes a waveform generation module 1140. This waveform generation module 1140 is used to output the pulse width modulation reference signal Q2-RAW for the second switch Q2, and when the level of Q2-RAW output by the waveform generation module 1140 is equal to a first level, it indicates that the second switch Q2 is turned off. Specifically, Q2-RAW is obtained by the waveform generation module 1140 based on the switching frequency and duty cycle of the bridge arm. The switching frequency of the bridge arm is equal to the switching frequencies of the second switch Q2 and the first switch Q1, and the duty cycle of the bridge arm is equal to the duty cycles of the second switch Q2 and the first switch Q1. It should be noted that within the reference turn-off interval of the second switch Q2, the level of the aforementioned Q2-RAW is equal to the first level. Therefore, when the level of Q2-RAW is equal to the first level, the second switch Q2 is turned off.

[0117] Furthermore, such as Figure 10As shown, the controller 1100 also includes a protection module 1130 and a drive module 1150. The protection module 1130 receives the logic signal TZa output from the logic module 1120 and the Q2-RAW output from the waveform generation module 1140, respectively, and outputs a drive signal Q1-DRV for the first switch Q1 to the drive module 1150. The drive module 1150 sends PWM1 (i.e., the PWM signal of the first switch Q1) to the first switch Q1 to control its on / off state. It can be understood that when the level of the logic signal TZa received by the protection module 1130 is equal to the fourth level, and the level of the received Q2-RAW is equal to the first level, it means that the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold, and the second switch Q2 is turned off. At this time, the protection module 1130 outputs a Q1-DRV signal equal to the fifth level. When the level of Q1-DRV received by the drive module 1150 is equal to the fifth level, the drive module 1150 adjusts PWM1 to control the first switching transistor Q1 to turn on and realize ZVS.

[0118] In some feasible implementations, the logic module 1120 may not be included inside the controller 1100. In this case, the Q2-RAW output by the comparison module 1110 can be directly transmitted to the protection module 1130. When the level of CMP-OUT1 received by the protection module 1130 is equal to the second level, and the level of the received Q2-RAW is equal to the first level, it means that the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold, and the second switch Q2 is turned off. Then, the controller 1100 can control the first switch Q1 to turn on based on the above and achieve ZVS.

[0119] It should be noted that, in the embodiments of this application, the controller and the aforementioned comparison module, logic module, protection module, wave generation module and drive module can be independent devices, and the aforementioned comparison module, logic module, protection module, wave generation module and drive module can be located inside or outside the controller. Figure 10 The examples shown are for illustrative purposes only and do not constitute a limitation.

[0120] In some feasible implementations, the signal changes transmitted by the above modules can be referred to Figure 11 As shown, Figure 11 This is another schematic diagram of electrical signal changes provided for an embodiment of this application. Figure 11In this diagram, T1 represents the first switching cycle of the first switch Q1, T2 represents the second switching cycle of the first switch Q1, Q1-RAW represents the pulse width modulation reference signal of the first switch Q2, and Q2-RAW represents the pulse width modulation reference signal of the second switch Q2. When Q1-RAW equals the sixth level V6, the first switch is turned off; when Q2-RAW equals the first level V1, the second switch is turned off. CMP-OUT1 represents the soft-on signal of the first switch Q1. When CMP-OUT1 equals the second level V2, the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold. Q1-DRV represents the drive signal of the first switch Q1. When Q1-DRV equals the fifth level V5, the controller 1100 controls the first switch Q1 to turn on. Figure 11 It can be seen that Q1-DRV equals V5 at times t1 and t2, meaning that the first switch Q1 is turned on at times t1 and t2. Furthermore, since Q2-RAW equals V1 and CMP-OUT1 equals V2 at times t1 and t2, the turning on of the first switch Q1 at times t1 and t2 achieves ZVS. In addition, time t1 is the turn-on time of the first switch Q1 within T1, and time t2 is the turn-on time of the first switch Q1 within T2. ​​The period length of T1 is significantly less than or equal to the period length of T2, meaning that the switching frequency of the first switch Q1 changes between T1 and T2. This is understandable. Figure 11 The examples shown are merely illustrative and do not constitute a limitation on the embodiments of this application.

[0121] In some feasible implementations, as can be seen from the above, when the dead time of the first switch Q1 and the second switch Q2 is too short, the turn-off delay may cause the first switch Q1 and the second switch Q2 to conduct simultaneously, resulting in a bridge arm short circuit. Therefore, in this embodiment, the controller 1100 can also detect whether the time elapsed after the second switch Q2 is turned off is greater than or equal to a second time before controlling the first switch Q1 to conduct. The second time refers to the minimum dead time of the first switch Q1 and the second switch Q2 without simultaneously turning on. The specific value of this second time depends on the requirements of the actual application scenario and is not limited here. It can be understood that when the controller 1100 detects that the time elapsed after the second switch Q2 is turned off is greater than or equal to the second time, it indicates that the dead time of the first switch Q1 and the second switch Q2 is greater than or equal to the second time. At this time, the controller 1100 controls the first switch Q1 to conduct, which will not cause the first switch Q1 and the second switch Q2 to conduct at the same time.

[0122] Therefore, in each switching cycle of the first switch Q1, when the controller 1100 detects that the second switch Q2 is turned off, and whether the duration after the second switch Q2 is turned off is greater than or equal to the second duration, and the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold, the controller controls the first switch Q1 to turn on. This can control the first switch Q1 to achieve ZVS in each switching cycle, while avoiding a short circuit caused by the simultaneous conduction of the first switch Q1 and the second switch Q2.

[0123] In this embodiment of the application, the controller 1100 can execute the corresponding control logic through the internal module to ensure that when the first switch Q1 is turned on, the duration experienced after the second switch Q2 is turned off is greater than or equal to the second duration.

[0124] In some feasible implementations, the controller 1100 can determine whether the duration of the second switch Q2 after being turned off is greater than or equal to a second duration based on the aforementioned Q2-RAW and the pulse width modulation reference signal Q1-RAW of the first switch Q1. Specifically, Q2-RAW and Q1-RAW are obtained by the waveform generation module 1140 based on the switching frequency and duty cycle of the bridge arm. Within the reference conduction interval of the first switch Q1, this Q1-RAW is equal to a third level. Furthermore, the interval between the output level of Q2-RAW by the waveform generation module 1140 being equal to a first level and the output level of Q1-RAW by the waveform generation module 1140 being equal to a third level is equal to the second duration. Therefore, when the output level of Q2-RAW by the waveform generation module 1140 is equal to the first level and the output level of Q1-RAW is equal to the third level, it indicates that the second switch Q2 is turned off, and the duration of the second switch Q2 after being turned off is greater than or equal to the second duration.

[0125] For example, please refer to Figure 12a and Figure 12b , Figure 12a This is another schematic diagram of electrical signal changes provided in an embodiment of this application. Figure 12b This is another schematic diagram of electrical signal changes provided in an embodiment of this application. Figure 12a and Figure 12b In this diagram, Q1-RAW represents the pulse width modulation reference signal of the first switch Q1, and Q2-RAW represents the pulse width modulation reference signal of the second switch Q2. During the reference turn-on interval of the first switch Q1, Q1-RAW is equal to the third level V3, and during the reference turn-off interval of the second switch Q2, Q2-RAW is equal to the first level V1. Furthermore, the interval between the falling edge of Q2-RAW and the rising edge of the adjacent Q1-RAW is equal to the second duration st2. Therefore, when Q2-RAW equals V1 and Q1-RAW equals V3, the duration experienced after the second switch Q2 is turned off is greater than or equal to the second duration st2.

[0126] Understandably, when the level of Q2-RAW received by the protection module 1130 is equal to the first level, the level of Q1-RAW is equal to the third level, and the logic module 1120 outputs a logic signal TZa with a level equal to the fourth level to the protection module 1130, this indicates that the second switch Q2 is currently off, the duration experienced after the second switch Q2 is off is greater than or equal to the second duration, and the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold value, meaning the duration experienced after the second switch Q2 is off is greater than or equal to the second duration. Therefore, the controller 1100 can control the first switch Q1 to turn on and achieve ZVS based on the above information, while preventing the first switch Q1 and the second switch Q2 from turning on simultaneously.

[0127] For example, please refer to again Figure 12b , Figure 12b CMP-OUT1 represents the soft-on signal of the first switch Q1. When CMP-OUT1 equals the second level V2, the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold. Q1-DRV represents the drive signal of the first switch Q1. When Q1-DRV equals the fifth level V5, the controller 1100 controls the first switch Q1 to turn on. Figure 12b It can be seen that when CMP-OUT1 equals V2, Q1-RAW equals V3, and Q2-RAW equals V1, it indicates that the second switch Q2 is turned off, and the duration experienced after the second switch Q2 is turned off is greater than or equal to the second duration st2, and the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold. This allows the first switch Q1 to achieve ZVS within T1 and T2, and avoids the simultaneous conduction of the first switch Q1 and the second switch Q2. Furthermore, the period length of T1 is significantly shorter than the period length of T2, meaning that the switching frequency of the first switch Q1 changes within T1 and T2. This is understandable. Figure 12a and Figure 12b The examples shown are merely illustrative and do not constitute a limitation on the embodiments of this application.

[0128] In some feasible implementations, the controller 1100 can also determine whether the duration of the second switch after it is turned off is greater than or equal to the second duration based on the minimum dead-time protection signal TZ-EN of the first switch Q1. Specifically, the waveform generation module 1140 can output the minimum dead-time protection signal TZ-EN of the first switch Q1 to the logic module 1120 based on the duration of the second switch Q2 after it is turned off, and when the duration of the second switch Q2 after it is turned off is greater than or equal to the second duration, the level of TZ-EN is equal to the seventh level. Furthermore, within the reference turn-off interval of the first switch Q1, the level of TZ-EN is equal to the sixth level. Therefore, when the level of Q2-RAW is equal to the first level, when the level of TZ-EN is equal to the sixth level, it indicates that the second switch Q2 is turned off, and the duration of the second switch Q2 after it is turned off is greater than or equal to the second duration.

[0129] For example, please refer to Figure 13a and Figure 13b , Figure 13a This is another schematic diagram of electrical signal changes provided in an embodiment of this application. Figure 13b This is another schematic diagram of electrical signal changes provided in an embodiment of this application. Figure 13a and Figure 13b In this diagram, Q1-RAW represents the pulse width modulation reference signal of the first switch Q1, and Q2-RAW represents the pulse width modulation reference signal of the second switch Q2. Within the reference turn-off interval of the first switch Q1, Q1-RAW is equal to the sixth level V6, and within the reference turn-off interval of the second switch Q2, Q2-RAW is equal to the first level V1. TZ-EN represents the minimum dead-time protection signal TZ-EN of the first switch Q1. When the duration experienced after the falling edge of Q2-RAW arrives is greater than or equal to the second duration, TZ-EN is equal to the seventh level V7. Therefore, when TZ-EN equals V7, it indicates that the second switch Q2 is turned off, and the duration experienced after the second switch Q2 is turned off is greater than or equal to the second duration st2.

[0130] As can be understood from the above, when the level of CMP-OUT1 received by logic module 1120 is equal to the second level, it indicates that the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold. Simultaneously, if the level of TZ-EN received by logic module 1120 is equal to the seventh level, it indicates that the second switch Q2 is turned off, and the duration experienced after the second switch Q2 is turned off is greater than or equal to the second duration. At this time, logic module 1120 can output a logic signal TZa with a level equal to the fourth level to drive module 1150, so that controller 1100 controls the first switch Q1 to turn on according to the above. This ensures that the first switch Q1 turns on when the second switch Q2 is turned off, the duration experienced after the second switch Q2 is turned off is greater than or equal to the second duration, and the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold, thereby controlling the first switch Q1 to achieve ZVS and preventing the first switch Q1 and the second switch Q2 from turning on simultaneously.

[0131] For example, please refer to again Figure 13b .exist Figure 13b In this diagram, T1 represents the first switching cycle of the first switching transistor Q1, T2 represents the second switching cycle of the first switching transistor Q1, CMP-OUT1 represents the soft-on signal of the first switching transistor Q1, and when CMP-OUT1 equals the second level V2, the voltage difference across the first switching transistor Q1 is less than or equal to the voltage difference threshold. Q1-DRV represents the drive signal of the first switching transistor Q1, and when Q1-DRV equals the fifth level V5, the controller 1100 controls the first switching transistor Q1 to turn on. Figure 13b It can be seen that when CMP-OUT1 equals V2 and TZ-EN equals V7, the second switch Q2 is turned off, and the duration after the second switch Q2 is turned off is equal to the second duration st2. Furthermore, the voltage difference across the first switch Q1 is less than or equal to the voltage difference threshold. This allows the first switch Q1 to achieve ZVS within T1 and T2, and prevents the first switch Q1 and the second switch Q2 from conducting simultaneously. In addition, the period length of T1 is significantly shorter than the period length of T2, meaning that the switching frequency of the first switch Q1 changes within T1 and T2. This is understandable. Figure 13a and Figure 13b The examples shown are merely illustrative and do not constitute a limitation on the embodiments of this application.

[0132] Please see Figure 14 , Figure 14 This is a flowchart illustrating a control method for a power conversion device provided in an embodiment of this application. The control method for a power conversion device provided in this embodiment is applicable to... Figures 1 to 1 3. The controller in the corresponding specific implementation. Specifically, the control method of the power conversion device may include the following steps:

[0133] S101. The voltage at the midpoint of the bridge arm is sampled through the sampling circuit.

[0134] Understandably, the power conversion device can detect the voltage difference across the first switching transistor using a sampling circuit before controlling its conduction. This voltage difference is equal to the difference between the voltage at the midpoint of the bridge arm and the voltage at the other end of the first switching transistor. Therefore, the power conversion device can obtain the voltage difference across the first switching transistor by sampling the voltage at the midpoint of the bridge arm.

[0135] For a detailed implementation of S101, please refer to the above. Figures 1 to 1 The implementation methods of the power conversion devices in the three categories will not be described again in the embodiments of this application.

[0136] S102. During the first and second switching cycles of the first switching transistor, when the second switching transistor is turned off and the voltage difference across the first switching transistor is less than or equal to a voltage difference threshold, the first switching transistor is controlled to turn on; the magnitude of the voltage difference across the first switching transistor is positively or negatively correlated with the voltage at the midpoint of the bridge arm; wherein, the first and second switching cycles are two adjacent switching cycles of the first switching transistor, and the absolute value of the difference between the cycle duration of the first switching cycle and the cycle duration of the second switching cycle is greater than or equal to the first duration.

[0137] Understandably, when the absolute value of the difference between the duration of the first switching cycle and the duration of the second switching transistor is greater than or equal to the first duration, the switching frequency of the first switching transistor changes within the first and second switching cycles. Therefore, the dead time required for the first switching transistor to achieve ZVS is different in the first and second switching cycles. To ensure that the first switching transistor can achieve ZVS in both the first and second switching cycles, the power conversion device, within both the first and second switching cycles, controls the first switching transistor to turn on and achieve ZVS when it detects that the second switching transistor is off and the voltage difference across the first switching transistor is less than or equal to a voltage difference threshold (i.e., when the first switching transistor can achieve ZVS). Since the power conversion device only controls the first switching transistor to turn on when it detects that the first switching transistor can achieve ZVS, the power conversion device can control the first switching transistor to achieve ZVS within the first and second switching cycles regardless of how the cycle lengths of the first and second switching cycles change. This solves the problem that dead time adjustment delays cause the first switching transistor to fail to achieve ZVS within the switching cycle when the cycle length changes. It can also reduce switching losses, ensure the high efficiency, reliability, and strong applicability of the power conversion device.

[0138] For a detailed implementation of S102, please refer to the above. Figures 1 to 1 The implementation methods of the power conversion devices in the three categories will not be described again in the embodiments of this application.

[0139] In an optional implementation, the method further includes: during a first switching cycle and a second switching cycle, when the second switch is turned off, and the duration experienced after the second switch is turned off is greater than or equal to the second duration, and the absolute value of the voltage difference across the first switch is less than or equal to a voltage difference threshold, controlling the first switch to turn on.

[0140] It is understood that the time elapsed from the turn-off of the second switch to the turn-on of the first switch is the dead time. To avoid this dead time being too short, causing the first and second switches to turn on simultaneously due to the turn-off delay, in this embodiment, the power conversion device also checks whether the time elapsed after the second switch turns off is greater than or equal to a second time before controlling the first switch to turn on. This second time refers to the minimum value of the aforementioned dead time that ensures the first and second switches will not turn on simultaneously. Therefore, when the power conversion device detects that the second switch is turned off, and the time elapsed after the second switch turns off is greater than or equal to the second time, and the absolute value of the voltage difference across the first switch is less than or equal to the voltage difference threshold, the power conversion device controls the first switch to turn on and achieves ZVS (Zero-Voltage Switching), while ensuring that the first and second switches will not turn on simultaneously, resulting in high reliability.

[0141] In an optional embodiment, if the duration of the second switching cycle is greater than or equal to the duration of the first switching cycle, the duration from the second switch being turned off to the first switch being turned on within the first switching cycle is equal to the third duration, and the duration from the second switch being turned off to the first switch being turned on within the second switching cycle is equal to the fourth duration, and the fourth duration is less than or equal to the third duration.

[0142] It is understandable that, since the cycle length of the first switching transistor is equal to the reciprocal of its switching frequency, when the cycle length of the second switching cycle is greater than or equal to the cycle length of the first switching cycle, the switching frequency of the first switching cycle is greater than or equal to the switching frequency of the second switching cycle. Furthermore, when the switching frequency decreases, the dead time required for the first switching transistor to achieve ZVS decreases. Therefore, when the power conversion device controls the first switching transistor to conduct and achieve ZVS within the first and second switching cycles, the dead time within the first and second switching cycles will adaptively adjust according to the change in switching frequency, thereby making the dead time of the second switching cycle (i.e., the fourth duration) less than or equal to the dead time of the first switching cycle (i.e., the third duration). Thus, this embodiment can promptly and adaptively adjust the dead time when the switching frequency of the first switching transistor changes, avoiding adjustment delays in the dead time and demonstrating high reliability.

[0143] In an optional implementation, if the duration of the second switching cycle is less than the duration of the first switching cycle, the duration from the second switch being turned off to the first switch being turned on within the first switching cycle is equal to the fifth duration, and the duration from the second switch being turned off to the first switch being turned on within the second switching cycle is equal to the sixth duration, and the sixth duration is greater than the fifth duration.

[0144] It is understandable that, since the cycle duration of the first switching transistor is equal to the reciprocal of its switching frequency, when the cycle duration of the second switching cycle is shorter than that of the first switching cycle, the switching frequency of the first switching cycle is also shorter than that of the second switching cycle. Furthermore, as the switching frequency increases, the dead time required for the first switching transistor to achieve ZVS increases. Therefore, when the power conversion device controls the first switching transistor to conduct and achieve ZVS within the first and second switching cycles, the dead time within both cycles will adaptively adjust according to the change in switching frequency, thereby making the dead time of the second switching cycle (i.e., the sixth duration) greater than the dead time of the first switching cycle (i.e., the fifth duration). Thus, this embodiment can promptly and adaptively adjust the dead time when the switching frequency of the first switching transistor changes, avoiding adjustment delays and demonstrating high reliability.

[0145] In an optional implementation, the sampling circuit is also connected to the other end of the first switching transistor connected to the midpoint of the bridge arm; the method further includes: sampling the voltage of the other end of the first switching transistor connected to the midpoint of the bridge arm through the sampling circuit, and obtaining the voltage difference across the first switching transistor based on the difference between the voltage of the other end of the first switching transistor connected to the midpoint of the bridge arm and the voltage at the midpoint of the bridge arm.

[0146] It is understandable that the voltage difference across the first switch is equal to the difference between the voltage at the midpoint of the bridge arm and the voltage at the other end of the first switch. Since the voltage at the other end of the first switch may not remain stable, in order to ensure sampling accuracy, the sampling circuit can simultaneously sample the voltage at the midpoint of the bridge arm and the other end of the first switch to ensure that the voltage difference across the first switch obtained by the power conversion device is correct.

[0147] In an optional implementation, when the second switch is turned off and the voltage difference across the first switch is less than or equal to a voltage difference threshold, the first switch is turned on. This specifically includes: obtaining a pulse width modulation reference signal for the second switch based on the switching frequency and duty cycle of the bridge arm; within the reference off interval of the second switch, the pulse width modulation reference signal for the second switch is equal to a first level; obtaining a soft-on signal for the first switch based on the voltage difference across the first switch; wherein, when the voltage difference across the first switch is less than or equal to the voltage difference threshold, the soft-on signal for the first switch is equal to a second level; when the pulse width modulation signal for the second switch is equal to the first level and the soft-on signal for the first switch is equal to the second level, the first switch is turned on.

[0148] It is understandable that the power conversion device controls the first switching transistor to turn on based on the pulse width modulation reference signal of the second switching transistor and the soft-turn signal of the first switching transistor, thus ensuring that the first switching transistor can achieve ZVS when it is turned on. The implementation principle is simple.

[0149] In an optional implementation, when the second switch is turned off, and the duration of time elapsed after the second switch is turned off is greater than or equal to a second duration, and the absolute value of the voltage difference across the first switch is less than or equal to a voltage difference threshold, the first switch is controlled to turn on. Specifically, this includes: obtaining the pulse width modulation (PWM) reference signal of the first switch and the PWM reference signal of the second switch based on the switching frequency and duty cycle of the bridge arm; wherein the interval between the falling edge of the PWM reference signal of the second switch and the rising edge of the adjacent PWM reference signal of the first switch is equal to the second duration; and in the second switch... Within the reference turn-off interval, the pulse width modulation signal of the second switch is equal to the first level; within the reference turn-on interval of the first switch, the pulse width modulation signal of the first switch is equal to the third level; the soft-on signal of the first switch is obtained based on the voltage difference across the first switch; wherein, when the voltage difference across the first switch is less than or equal to the voltage difference threshold, the soft-on signal of the first switch is equal to the second level; when the pulse width modulation signal of the first switch is equal to the third level, and the soft-on signal of the first switch is equal to the second level, and the pulse width modulation signal of the second switch is equal to the first level, the first switch is controlled to turn on.

[0150] Understandably, the power conversion device adjusts the time interval between the falling edge of the pulse width modulation reference signal of the second switch and the rising edge of the pulse width modulation reference signal of the adjacent first switch to be equal to the second time interval. Then, it controls the first switch to turn on based on the pulse width modulation reference signal of the second switch, the pulse width modulation reference signal of the first switch, and the soft-turn signal of the first switch. This ensures that the first switch can achieve ZVS when it is turned on, and at the same time, makes the dead time of the first switch and the second switch greater than or equal to the second time interval, thereby avoiding the first switch and the second switch from turning on at the same time. This method has high reliability and a simple implementation principle.

[0151] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of protection of the above claims.

Claims

1. A power conversion device, characterized in that, The power conversion device includes a sampling circuit, a controller, and at least one bridge arm. The sampling circuit is connected to the midpoint of the bridge arm. The bridge arm includes a first switch and a second switch connected in series. During the operation of the power conversion device, the first switch and the second switch are alternately turned on. The sampling circuit is used to sample the voltage at the midpoint of the bridge arm and send it to the controller; The controller is configured to, during the first and second switching cycles of the first switching transistor, when the second switching transistor is turned off and the voltage difference across the first switching transistor is less than or equal to a voltage difference threshold, control the first switching transistor to turn on; the magnitude of the voltage difference across the first switching transistor is positively or negatively correlated with the magnitude of the voltage at the midpoint of the bridge arm. Wherein, the first switching cycle and the second switching cycle are two adjacent switching cycles of the first switching transistor, and the absolute value of the difference between the cycle duration of the first switching cycle and the cycle duration of the second switching cycle is greater than or equal to the first duration.

2. The power conversion device according to claim 1, characterized in that, The controller is also used for: During the first switching cycle and the second switching cycle, when the second switch is turned off, and the duration experienced after the second switch is turned off is greater than or equal to the second duration, and the absolute value of the voltage difference across the first switch is less than or equal to the voltage difference threshold, the first switch is controlled to turn on.

3. The power conversion device according to claim 1, characterized in that, When the duration of the second switching cycle is greater than or equal to the duration of the first switching cycle, Within the first switching cycle, the time elapsed from the second switch being turned off to the first switch being turned on is equal to the third time elapsed. Within the second switching cycle, the time elapsed from the second switch being turned off to the first switch being turned on is equal to the fourth time elapsed, and the fourth time elapsed is greater than or equal to the third time elapsed.

4. The power conversion device according to claim 1, characterized in that, When the duration of the second switching cycle is less than the duration of the first switching cycle, Within the first switching cycle, the time elapsed from the second switch being turned off to the first switch being turned on is equal to the fifth time elapsed. Within the second switching cycle, the time elapsed from the second switch being turned off to the first switch being turned on is equal to the sixth time elapsed, and the sixth time elapsed is less than the fifth time elapsed.

5. The power conversion device according to any one of claims 1 to 4, characterized in that, The sampling circuit is also connected to the other end of the first switching transistor and the midpoint of the bridge arm; The sampling circuit is also used to sample the voltage at the other end of the first switch connected to the midpoint of the bridge arm, and output the voltage difference between the two ends of the first switch to the controller based on the difference between the voltage at the other end of the first switch connected to the midpoint of the bridge arm and the voltage at the midpoint of the bridge arm.

6. The power conversion device according to claim 1, characterized in that, When the second switch is turned off, and the voltage difference across the first switch is less than or equal to a voltage difference threshold, the controller controls the first switch to turn on, specifically including: The pulse width modulation reference signal of the second switch is obtained according to the switching frequency and duty cycle of the bridge arm; within the reference turn-off interval of the second switch, the pulse width modulation reference signal of the second switch is equal to the first level; The soft-open signal of the first switch is obtained based on the voltage difference across the first switch; wherein, when the voltage difference across the first switch is less than or equal to the voltage difference threshold, the soft-open signal of the first switch is equal to the second level. When the pulse width modulation signal of the second switch is equal to the first level, and the soft-on signal of the first switch is equal to the second level, the first switch is controlled to be turned on.

7. The power conversion device according to claim 2, characterized in that, When the second switch is turned off, and the duration of time elapsed after the second switch is turned off is greater than or equal to a second duration, and the absolute value of the voltage difference across the first switch is less than or equal to a voltage difference threshold, the controller controls the first switch to turn on, specifically including: The pulse width modulation (PWM) reference signals of the first and second switching transistors are obtained based on the switching frequency and duty cycle of the bridge arm; wherein, the time interval between the falling edge of the PWM reference signal of the second switching transistor and the rising edge of the adjacent PWM reference signal of the first switching transistor is equal to the second time interval; within the reference off interval of the second switching transistor, the PWM signal of the second switching transistor is equal to the first level; within the reference on interval of the first switching transistor, the PWM signal of the first switching transistor is equal to the third level. The soft-open signal of the first switch is obtained based on the voltage difference across the first switch; wherein, when the voltage difference across the first switch is less than or equal to the voltage difference threshold, the soft-open signal of the first switch is equal to the second level. When the pulse width modulation signal of the first switch is equal to the third level, and the soft-on signal of the first switch is equal to the second level, and the pulse width modulation signal of the second switch is equal to the first level, the first switch is controlled to be turned on.

8. The power conversion device according to claim 1, characterized in that, The controller includes a comparison module, a logic module, a protection module, a waveform generation module, and a drive module; the input terminal of the comparison module is connected to the sampling circuit, the comparison module, the logic module, the protection module, and the drive module are connected in sequence, the output terminal of the drive module is connected to the control electrode of the first switching transistor, and the waveform generation module is connected to the protection module; The comparison module is used to output a second level to the logic module when the voltage difference across the first switch is less than or equal to the voltage difference threshold. The logic module is used to output a fourth level to the protection module upon receiving the second level. The wave-generating module is used to output a first level to the protection module within the reference turn-off interval of the second switching transistor. The protection module is used to output a fifth level to the driving module when it receives the fourth level and the first level. The driving module is used to control the first switch to turn on when the fifth level is received.

9. The power conversion device according to claim 2, characterized in that, The controller includes a comparison module, a logic module, a protection module, a waveform generation module, and a drive module; the input terminal of the comparison module is connected to the sampling circuit, the comparison module, the logic module, the protection module, and the drive module are connected in sequence, the output terminal of the drive module is connected to the control electrodes of the first switch and the second switch, and the waveform generation module is connected to the protection module and the logic module respectively. The comparison module is used to output a second level to the logic module when the voltage difference across the first switch is less than or equal to the voltage difference threshold. The wave-generating module is used to output a first level to the protection module within the reference turn-off interval of the second switching transistor. And within the reference conduction range of the first switch, the third level is output to the logic module; wherein, the interval between the output of the first level and the output of the third level by the waveform generation module is equal to the second duration; The logic module is configured to output a fourth level to the protection module upon receiving the second level and the third level. The protection module is used to output a fifth level to the driving module when it receives the fourth level and the first level. The driving module is used to control the first switch to turn on when the fifth level is received.

10. The power conversion device according to any one of claims 1 to 9, characterized in that, The at least one bridge arm includes one bridge arm, and the first switching transistor and the second switching transistor are connected in series between the positive and negative terminals of the DC input terminal; the power conversion device further includes a first inductor, a first capacitor, a first transformer, and a first rectifier circuit; the first inductor is connected to the midpoint of the bridge arm, the first capacitor is connected to the negative terminal of the DC input terminal, and the primary coil of the transformer is connected between the first inductor and the first capacitor; the rectifier circuit is connected to the secondary coil of the transformer, and the rectifier circuit is also used to connect a load.

11. The power conversion device according to any one of claims 1 to 9, characterized in that, The at least one bridge arm includes two bridge arms, and the first switch and the second switch in each bridge arm are connected in series between the positive and negative terminals of the DC input terminal; the power conversion device further includes a second inductor, a second capacitor, a second transformer, and a second rectifier circuit; the second inductor is connected to the midpoint of one bridge arm, the second capacitor is connected to the midpoint of the other bridge arm, and the primary coil of the second transformer is connected between the second inductor and the second capacitor; the second rectifier circuit is connected to the secondary coil of the second transformer, and the second rectifier circuit is also used to connect a load.

12. The power conversion device according to any one of claims 1 to 9, characterized in that, The at least one bridge arm includes three bridge arms, in which the first switch and the second switch in each bridge arm are connected in series between the positive and negative terminals of the DC input terminal; the power conversion device further includes three resonant circuits, three third transformers, and a third rectifier circuit; each resonant circuit includes a third capacitor, a third inductor, and a fourth inductor; the third capacitor is connected to the midpoint of a corresponding bridge arm, the third inductor is connected between the third capacitor and the fourth inductor, and the fourth inductor is also connected in parallel with the primary coil of a corresponding third transformer; the third rectifier circuit is connected to the secondary coil of each third transformer, and the third rectifier circuit is also used to connect a load.

13. The power conversion device according to any one of claims 1 to 9, characterized in that, The at least one bridge arm includes one bridge arm, and the first switch and the second switch are connected in series between the positive and negative terminals of the DC input terminal; the power conversion device further includes a fifth inductor and a fourth capacitor; the fifth inductor is connected to the midpoint of the bridge arm, the four ends of the fourth capacitor are connected to the fifth inductor, the other end of the fourth capacitor is connected to the negative terminal of the DC input terminal, and the two ends of the fourth capacitor are also used to connect the load.

14. The power conversion device according to any one of claims 1 to 9, characterized in that, The at least one bridge arm includes one bridge arm, and the power conversion device further includes a sixth inductor and a fifth capacitor; one end of the sixth inductor is connected to the midpoint of the bridge arm, and the other end of the sixth inductor is used to connect to the positive terminal of the DC input terminal; the fifth capacitor is connected in parallel with the bridge arm, and both ends of the fifth capacitor are also used to connect to the load, and the end of the fifth capacitor connected to the negative terminal of the load is also used to connect to the negative terminal of the DC input terminal.

15. A control method for a power conversion device, applied to the power conversion device, the power conversion device including a sampling circuit and at least one bridge arm, the sampling circuit being connected to the midpoint of the bridge arm, the bridge arm including a first switch and a second switch connected in series; during operation of the power conversion device, the first switch and the second switch are alternately turned on; characterized in that, The method includes: The voltage at the midpoint of the bridge arm is sampled by the sampling circuit. During the first and second switching cycles of the first switch, when the second switch is turned off and the voltage difference across the first switch is less than or equal to a voltage difference threshold, the first switch is turned on; the magnitude of the voltage difference across the first switch is positively or negatively correlated with the voltage at the midpoint of the bridge arm. Wherein, the first switching cycle and the second switching cycle are two adjacent switching cycles of the first switching transistor, and the absolute value of the difference between the cycle duration of the first switching cycle and the cycle duration of the second switching cycle is greater than or equal to the first duration.

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