Analog calculation circuit in pixel

Abstract

The invention belongs to the technical field of detector front-end reading integrated circuits. The invention provides an in-pixel analog calculation circuit. According to the analog calculation circuit in the pixel, the data size of the source end of the detector can be remarkably reduced, and analog convolution calculation is achieved in an array parallel architecture and used for feature map extraction. Compared with other methods, the data volume output by the pixel array can be reduced, and the larger the convolution step length is, the more significant the reduction of the pixel array output nodes is. Moreover, simulation neural network calculation in a large-array pixel type read-out chip becomes possible, and when the array is continuously increased, the size of the super-pixel circuit can be properly increased, so that the pressure of the number of analog voltage nodes output by the array and the complexity of interconnection lines are reduced.

Description

Technical Field

[0001] This disclosure relates to the field of detector front-end readout integrated circuit technology, and more particularly to an in-pixel analog computing circuit. Background Technology

[0002] Hybrid pixel detectors are widely used in high-energy physics experiments, nuclear physics experiments, and photonics experiments. The pixel-type readout integrated circuit is the core device of a hybrid pixel detector. Its readout circuit is arranged in two dimensions and vertically integrated with the pixel detector via flip-chip bonding, reading out the information acquired by the detector pixels point-to-point. As the pixel size of the detector shrinks, the impact of incident particles or photons on the detector generates a charge-sharing effect, meaning that multiple pixels generate induced charges, making it difficult to determine the accurate impact position of the incident particles in actual measurements. The paper "Di Giacomo, S., et al. "Experimental Validation of ANNA: Analog Neural Network ASIC for Event Positioning in Monolithic Scintillation Detectors." IEEE Transactions on Radiation and Plasma Medical Sciences, 2025." proposes a computational architecture using an on-chip analog neural network to determine the position of incident photons, such as... Figure 1 As shown.

[0003] Artificial neural network-based localization and reconstruction methods have demonstrated superior performance, robustness, and the ability to handle massive amounts of data. Neural networks offer the potential to simplify algorithmic complexity and handle large-scale parallel in-memory computations, significantly improving energy efficiency and speed associated with data transmission and processing. Neural networks can transform the position calculation problem into a pattern recognition and nonlinear regression problem. Training a neural network allows it to directly interpret the incident position (X, Y coordinates) of a photon from the pattern output by a silicon photomultiplier (SiPM) array. Integrating a CMOS-implemented analog artificial neural network with the analog front-end circuitry of a scintillator detector can be used in gamma-ray cameras to locate incident gamma-ray photons within a monolithic scintillation crystal.

[0004] In this circuit structure, the analog voltage signal of each pixel unit is transmitted outside the pixel array for analog calculation. However, as the pixel array grows, the complexity of the interconnects increases, and the number of input nodes in the neural network also increases, leading to an increase in the area of ​​the neural network hardware accelerator implemented with analog circuits, and consequently, an increase in static power consumption.

[0005] Therefore, it is necessary to improve one or more of the problems existing in the above-mentioned related technical solutions.

[0006] It should be noted that this section is intended to provide background or context for the technical solutions of this disclosure as set forth in the claims. The description herein does not constitute an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0007] The purpose of this disclosure is to provide an in-pixel analog computing circuit, thereby overcoming at least to some extent one or more problems caused by the limitations and defects of related technologies.

[0008] According to embodiments of this disclosure, an in-pixel analog computing circuit is provided, comprising: M×M pixel analog front-end circuits and superpixel circuits, wherein... Pixel analog front-end circuitry is used to receive detector signals; The superpixel circuit includes M×M multiplication circuits, one accumulation circuit, and one nonlinear activation function circuit. The multiplication circuit is used to perform analog multiplication operations on the analog signal of the pixel analog front-end circuit and the preset weight parameters; The accumulator circuit is connected to the output terminals of M×M multiplier circuits and is used to perform analog accumulation of the output signals of all multiplier circuits; The nonlinear activation function circuit is connected to the output of the accumulator circuit and is used to perform nonlinear activation operations on the accumulation result.

[0009] Furthermore, the sliding step size S of the superpixel circuit is the same as the convolution kernel size M, and the preset weights of all superpixels in the superpixel circuit are consistent. The feature extraction calculation of the first layer of the convolutional neural network is completed in one time step through the array parallel architecture.

[0010] Furthermore, the number of output nodes of the pixel array composed of superpixel circuits is:

[0011] in, Enter the height. For input width, M The size of the sliding window for the convolution kernel. P For fill size, S The step size.

[0012] Furthermore, the sliding window is scalable. If the sliding window is set to M×M, then after in-pixel processing, the number of layers in the first neural network is reduced to 1 / M of the original size. 2 .

[0013] Furthermore, when M is 2, the corresponding superpixel circuit is a 2×2 structure, consisting of 4 pixel analog front-end circuits, 4 in-situ multiplication circuits within the pixel, 1 accumulation circuit, and 1 nonlinear activation function circuit. The number of analog signal nodes output by the pixel array is reduced to 1 / 4 of the original.

[0014] Furthermore, the preset weights are input digitally and can be programmably adjusted to suit the feature extraction needs of different input images.

[0015] Furthermore, the preset weights include single-bit weights and multi-bit weights; among them, the single-bit weights correspond to the smallest area of ​​the analog convolution calculation circuit, while the multi-bit weights are implemented by proportionally increasing the number of multiplication units.

[0016] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: In the embodiments of this disclosure, the above-described intra-pixel analog computing circuit, on the one hand, places the multiplication circuit, the accumulation circuit, and the nonlinear activation function at the center of the pixel, ensuring that the connection length from the intra-pixel analog computing output to the superpixel accumulation circuit input is almost uniform, thus completing the convolution calculation while maintaining the consistency of the pixel array calculation signal. The intra-pixel analog front-end circuit is responsible for amplifying and filtering the signal input from the detector. The voltage signal output by this circuit serves as the input to the multiplication circuit. The multiplication circuit performs the multiplication operation between voltage and weight. The multiplication result output by the pixel is accumulated by the subsequent accumulation circuit and converted into a voltage signal. The output voltage obtained from the multiplication and accumulation operation is then processed by the ReLU circuit to complete the nonlinear activation, ultimately outputting the voltage signal obtained from the convolution calculation. On the other hand, this circuit can reduce the amount of data output by the pixel array, and the larger the convolution stride, the more significant the reduction in the number of output nodes of the pixel array. This makes it possible to implement analog neural network calculations in large-array pixel-type readout chips. As the array continues to increase in size, the size of the superpixel circuit can be appropriately increased, such as to 4×4, thereby reducing the pressure on the number of array output analog voltage nodes and the complexity of interconnections. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 This diagram illustrates an existing analog neural network computing circuit architecture in an exemplary embodiment of this disclosure. Figure 2This illustration shows the architecture and layout routing of the analog computing circuitry within a pixel when M=2 in an exemplary embodiment of this disclosure; Figure 3 This diagram illustrates a 2×2 superpixel circuit structure with a built-in analog convolution calculation circuit in an exemplary embodiment of this disclosure. Figure 4 This illustrates a pixel-type readout circuit architecture based on analog computation in an exemplary embodiment of this disclosure; Figure 5 Show Figure 2 Circuit diagram of the mid-pixel analog front-end circuit; Figure 6 Show Figure 2 Circuit diagram of a mid-pixel level multiply-accumulate circuit; Figure 7 Show Figure 2 Circuit diagram of a nonlinear activation function circuit; Figure 8 This paper shows a comparison of the pixel array output data volume of this application and other methods under the same conditions. Detailed Implementation

[0019] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0020] Furthermore, the accompanying drawings are merely illustrative diagrams of embodiments of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0021] This example implementation provides an in-pixel analog computing circuit. (See reference...) Figure 2 As shown, the in-pixel analog computing circuitry may include: M×M pixel analog front-end circuits and superpixel circuits, wherein... Pixel analog front-end circuitry is used to receive detector signals; The superpixel circuit includes M×M multiplication circuits, one accumulation circuit, and one nonlinear activation function circuit. The multiplication circuit is used to perform analog multiplication operations on the analog signal of the pixel analog front-end circuit and the preset weight parameters; The accumulator circuit is connected to the output terminals of M×M multiplier circuits and is used to perform analog accumulation of the output signals of all multiplier circuits; The nonlinear activation function circuit is connected to the output of the accumulator circuit and is used to perform nonlinear activation operations on the accumulation result.

[0022] Through the aforementioned intra-pixel analog computing circuit, on the one hand, the multiplication circuit, accumulation circuit, and nonlinear activation function are located at the center of the pixel, ensuring that the connection length from the intra-pixel analog computing output to the superpixel accumulation circuit input is almost uniform, thus guaranteeing the consistency of the pixel array computing signal while completing the convolution calculation. The intra-pixel analog front-end circuit is responsible for amplifying and filtering the signal input from the detector. The voltage signal output by this circuit serves as the input to the multiplication circuit. The multiplication circuit performs voltage and weight multiplication operations, and the multiplication result from the pixel output is accumulated by the subsequent accumulation circuit and converted into a voltage signal. The output voltage obtained from the multiplication and accumulation operation is then processed by the ReLU circuit to complete nonlinear activation, ultimately outputting the voltage signal obtained from the convolution calculation. On the other hand, this circuit can reduce the amount of data output by the pixel array, and the larger the convolution stride, the more significant the reduction in the number of pixel array output nodes. This makes it possible to implement analog neural network calculations in large-array pixel-type readout chips. As the array continues to increase in size, the size of the superpixel circuit can be appropriately increased, such as to 4×4, thereby reducing the pressure on the number of array output analog voltage nodes and the complexity of interconnections.

[0023] Below, we will refer to Figures 2 to 8 The various parts of the intra-pixel analog computing circuit described in this example embodiment will be explained in more detail.

[0024] In one embodiment, leveraging the characteristics of convolutional neural network models, the deployment of the first layer of the neural network within a pixel is completed through neural network algorithms, hardware deployment schemes, and circuit implementation. The main features of this scheme are: (1) Convolution calculation includes multiplication-accumulation calculation and nonlinear activation function. The number of input and output nodes of the convolutional layer is shown in formula (1), H in To input the height, W in Where M is the input width, P is the size of the convolution kernel sliding window, S is the stride, and N is the number of output nodes. Assuming the sliding window is 2×2 and the stride is 2, when the input image is 8×8, the convolution calculation outputs 16 nodes. The common nonlinear activation function ReLU is expressed as shown in formula (2).

[0025] (1) (2) (2) The built-in analog computing superpixel circuit structure provided in this application is as follows: Figure 3As shown, the superpixel array consists of a 2×2 pixel analog front-end circuit, an in-situ multiplication circuit within each pixel, an in-superpixel accumulator circuit, and a nonlinear activation function circuit. The multiplication circuit is deployed in each pixel circuit, and the results of the multiplication circuits are fed into an accumulator for accumulation. Finally, a nonlinear activation function circuit is used to complete the nonlinear activation. Therefore, using a 2×2 convolution kernel allows the analog convolution calculation circuit to be completely integrated into the superpixel array, while ensuring the consistency of the multiplication signals output from the four pixels at the output of the accumulator circuit.

[0026] (3) The pixel-type readout circuit architecture based on the superpixel circuits implemented in (2) is as follows: Figure 4 As shown, each superpixel circuit processes a 2×2 pixel analog signal, and the hardware implementation of the first layer computation in the convolutional neural network is achieved through parallel processing. The output of the pixel array is the output after feature extraction through convolution calculation. This scheme reduces the number of nodes in the output analog signal to 1 / 4 of the original.

[0027] (4) The simulated convolution calculation weights in this application are input digitally, and all superpixels within the pixel array have the same weights, which is equivalent to implementing a sliding convolution window. The sliding stride is the same as the convolution kernel size, and the first layer of convolution calculation can be completed in one time step. The intra-pixel simulated calculation in this application supports programmable weight parameters, and the weights can be adjusted to adapt to feature extraction from different input images. A lightweight weight mapping is adopted. Considering the limitation of pixel area, the area for intra-pixel simulated convolution calculation is minimized by a single-bit weight, and multi-bit weights can be achieved by proportionally increasing the multiplication units.

[0028] (5) Based on (1) to (4), the sliding window has scalability. If the sliding window is set to M×M and the sliding step size S is the same as the sliding window M, then after intra-pixel processing, the number of layers of the first neural network is reduced to 1 / M of the original size. 2 .

[0029] In a specific embodiment, taking a 2×2 sliding window as an example, the specific implementation of the circuit is as follows.

[0030] (1) Superpixel circuit architecture This application proposes the architecture and layout of a 2×2 superpixel circuit as follows: Figure 2 As shown, the multiply-accumulate circuit and the nonlinear activation function are located in the center of the four pixels, ensuring that the connection lengths from the analog calculation output to the input of the superpixel accumulator circuit are almost identical, thus guaranteeing the consistency of the pixel array calculation signal while completing the convolution calculation. The analog front-end circuit within the pixel is responsible for amplifying and filtering the signal input from the detector; its specific circuit structure is shown below. Figure 5As shown, the voltage signals V1 to V4 output by this circuit will serve as the input to the analog multiplication circuit within each pixel. The analog multiplication circuit is used to perform the multiplication operation between voltage and weights, and the multiplication result I output from the four pixels... out0 ~I out4 The signals are accumulated by a subsequent accumulation circuit and converted into voltage signals, such as... Figure 6 As shown. The output voltage obtained from the above multiplication and accumulation operation is then processed by a ReLU circuit to complete the nonlinear activation process. This part of the circuit is as follows. Figure 7 As shown. The pixel array of the pixel readout integrated circuit consists of, as... Figure 4 The superpixel circuit shown is arranged in a two-dimensional manner and ultimately outputs a voltage signal obtained from convolution calculation.

[0031] (2) Pixel-level analog front-end circuit The architecture of the pixel-level readout circuit (i.e., pixel-level analog front-end circuit) of the radiation detector is as follows: Figure 5 As shown, the detector signal is usually in the form of a current pulse in the SiPM, which is amplified by a low-noise analog front-end circuit, converted into a voltage, and filtered by an analog filter to improve the signal-to-noise ratio.

[0032] Specifically, the pixel analog front-end circuit includes: Diode, capacitor C F Capacitor C D Operational amplifiers and filters; among them, the cathode of the diode and the capacitor C F The first terminal is electrically connected to the inverting input terminal of the operational amplifier, and capacitor C... D The first terminal and the non-inverting input terminal of the operational amplifier are connected by capacitor C. D The operational amplifier is grounded, and its output is electrically connected to the input of the filter. The output of the filter is electrically connected to the multiplication circuit within each pixel.

[0033] (3) Pixel-level multiply-accumulate circuit The schematic diagram of the pixel-level multiply-accumulate circuit is as follows: Figure 6 As shown, it consists of an intra-pixel multiplication circuit and a superpixel intra-accumulation circuit. The analog voltage output from the analog front end is used as the input voltage for the intra-pixel analog multiplication circuit, W. P and W N W represents the positive and negative weights of the binary neural network. P A value of 1 represents a positive weight, W N A value of 1 represents a negative weight; the digital weight value controls the weight transistor to generate the multiplicative output current. The superpixel's internal accumulator circuit accumulates the multiplicative currents of the four pixels and outputs the voltage.

[0034] Specifically, the multiplication circuit includes: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor; among which, The gates of the first and second transistors are electrically connected to the output of the pixel analog front-end circuit. The drains of the first, third, and third transistors and the gate of the sixth transistor are electrically connected. The drains of the second, fourth, and fifth transistors and the gate of the fifth transistor are electrically connected. The sources of the third, fourth, fifth, and sixth transistors are all electrically connected to the power supply VDD. The source of the first transistor is electrically connected to the drain of the seventh transistor. The source of the second transistor is electrically connected to the drain of the eighth transistor. The drains of the sixth, ninth, and tenth transistors and the gate of the tenth transistor are electrically connected. The sources of the seventh, eighth, ninth, and tenth transistors are all electrically connected to the power supply VSS. The gates of the seventh and eighth transistors are electrically connected to the positive and negative weight outputs of the binary neural network, respectively. The drains of the fifth and ninth transistors are electrically connected to form the output of the multiplication circuit.

[0035] The outputs of each multiplication circuit are connected in parallel and electrically connected to the input of the accumulator circuit.

[0036] The accumulator circuit includes: The first accumulator transistor, the second accumulator transistor, the third accumulator transistor, and the fourth accumulator transistor; wherein, The gate, drain, gate, and drain of the first accumulator transistor are electrically connected to the output of the multiplication circuit. The source and source of the first and second accumulator transistors are electrically connected to the power supply VDD. The gate, gate, and source of the third and fourth accumulator transistors are electrically connected to the power supply VSS. The drains of the second and fourth accumulator transistors are electrically connected to form the output of the accumulator circuit.

[0037] (4) Pixel-level nonlinear activation function Pixel-level ReLU circuits such as Figure 7 As shown, the output of the multiply-accumulate circuit is then activated nonlinearly through an analog ReLU circuit. In summary, the voltage VAFE output from the analog front-end within the pixel is processed by the analog calculation circuit within the pixel to output an analog voltage, which is then output outside the pixel array.

[0038] Specifically, transistors M1 and M2; among them, The source of transistor M1 and the gate of transistor M2 are electrically connected to the output of the accumulator circuit. The gate of transistor M1 and the drain of transistor M2 are electrically connected to ReLU_VREF. The drain of transistor M1 and the source of transistor M2 constitute the output terminal of the nonlinear activation function circuit.

[0039] It is understandable that the size M of the sliding window is a positive integer greater than 1, and is not limited to M=2; the non-linear activation function is not limited to the ReLU activation function, but can also be sigmoid, etc.

[0040] In one specific embodiment, the built-in analog computing superpixel circuit structure provided in this application has the following effects: Figure 8 As shown. The superpixel circuit structure of this application can significantly reduce the amount of data at the detector source end. The simulated convolution calculation is implemented in an array parallel architecture for feature map extraction. Compared with the literature "Di Giacomo, S., et al. "ExperimentalValidation of ANNA: Analog Neural Network ASIC for Event Positioning in Monolithic Scintillation Detectors." IEEE Transactions on Radiation and Plasma Medical Sciences, 2025. (i.e., the literature [1] in the figure), the scheme of this application can reduce the amount of data output by the pixel array, and the larger the convolution step size, the more significant the reduction in the number of output nodes of the pixel array. This application makes it possible to implement simulated neural network calculation in a large array pixel type readout chip. When the array continues to increase, the size of the superpixel circuit can be appropriately increased, such as 4×4, thereby reducing the pressure of the number of analog voltage nodes output by the array and the complexity of the interconnection.

[0041] It should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise" in the above description indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0043] In the embodiments of this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0044] In embodiments of this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0045] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0046] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An in-pixel analog computing circuit, characterized in that, include: M×M pixel analog front-end circuits and superpixel circuits, wherein... Pixel analog front-end circuitry is used to receive detector signals; The superpixel circuit includes M×M multiplication circuits, one accumulation circuit, and one nonlinear activation function circuit. The multiplication circuit is used to perform analog multiplication operations on the analog signal of the pixel analog front-end circuit and the preset weight parameters; The accumulator circuit is connected to the output terminals of M×M multiplier circuits and is used to perform analog accumulation of the output signals of all multiplier circuits; The nonlinear activation function circuit is connected to the output of the accumulator circuit and is used to perform nonlinear activation operations on the accumulation result.

2. The intra-pixel analog computing circuit according to claim 1, characterized in that, The sliding step size S of the superpixel circuit is the same as the convolution kernel size M. The preset weights of all superpixels in the superpixel circuit are the same. The feature extraction calculation of the first layer of the convolutional neural network is completed in one time step through the array parallel architecture.

3. The intra-pixel analog computing circuit according to claim 2, characterized in that, The number of output nodes of the pixel array composed of superpixel circuits is: in, Enter the height. For input width, M The size of the sliding window for the convolution kernel. P For fill size, S The step size.

4. The intra-pixel analog computing circuit according to claim 3, characterized in that, The sliding window is scalable. If the sliding window is set to M×M, then after in-pixel processing, the number of layers in the first neural network is reduced to 1 / M of the original size. 2 .

5. The intra-pixel analog computing circuit according to claim 4, characterized in that, When M is 2, the corresponding superpixel circuit is a 2×2 structure, consisting of 4 pixel analog front-end circuits, 4 in-situ multiplication circuits within the pixel, 1 accumulation circuit and 1 nonlinear activation function circuit. The number of analog signal nodes output by the pixel array is reduced to 1 / 4 of the original.

6. The intra-pixel analog computing circuit according to claim 5, characterized in that, The preset weights are input numerically and can be adjusted programmatically to suit the feature extraction needs of different input images.

7. The intra-pixel analog computing circuit according to claim 6, characterized in that, The preset weights include single-bit weights and multi-bit weights; among them, the single-bit weights correspond to the smallest area of ​​the analog convolution calculation circuit, while the multi-bit weights are implemented by increasing the multiplication units proportionally.

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