Semiconductor memory device

Abstract

There is provided a semiconductor memory device including: a substrate including a first region and a second region arranged along a first direction; an active pattern disposed in the first region and including a first portion and a second portion; a gate electrode extending in a second direction intersecting the first direction and spanning between the first portion and the second portion; a conductive pattern disposed on the substrate and connected to the first portion, extending in the first direction, and having an end portion located on the second region; a buried contact disposed on a side surface of the conductive pattern on the first region to be connected to the second portion; a capacitor structure connected to the buried contact; and an edge insulating film disposed on a side surface of the conductive pattern on the second region, and surrounding the end portion of the conductive pattern.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor memory device and a method for manufacturing the same. More particularly, the present disclosure relates to a semiconductor memory device including a capacitor and a method for manufacturing the same. BACKGROUND

[0002] As semiconductor memory devices become more highly integrated, individual circuit patterns become smaller to implement a large number of semiconductor memory devices in the same area. However, the miniaturization of individual circuit patterns increases the level of difficulty of processes and causes defects. SUMMARY

[0003] Aspects of the present disclosure provide a semiconductor memory device with improved yield and productivity.

[0004] Aspects of the present disclosure also provide a method for manufacturing a semiconductor memory device, which is capable of manufacturing a semiconductor memory device with improved yield and productivity.

[0005] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more readily apparent to those of ordinary skill in the art by referring to the following detailed description of the present disclosure taken in conjunction with the accompanying drawings.

[0006] According to aspects of the present disclosure, there is provided a semiconductor memory device including: a substrate including a first region and a second region arranged along a first direction; an active pattern disposed in the first region and including a first portion and a second portion; a gate electrode extending in a second direction intersecting the first direction and spanning between the first portion and the second portion; a conductive pattern disposed on the substrate and connected to the first portion, extending in the first direction, and having an end portion on the second region; a buried contact disposed on a side surface of the conductive pattern on the first region and connected to the second portion; a capacitor structure connected to the buried contact; and an edge insulating film disposed on a side surface of the conductive pattern on the second region and surrounding the end portion of the conductive pattern. Wherein the edge insulating film includes a seam extending in the first direction.

[0007] According to an aspect of the present disclosure, there is provided a semiconductor memory device including: a substrate including a first region and a second region arranged along a first direction; an active pattern disposed in the first region and including a first portion and a second portion; a gate electrode extending in a second direction intersecting the first direction and straddling between the first portion and the second portion; a conductive pattern disposed on the substrate and connected to the first portion, extending in the first direction, and having an end portion on the second region; a spacer structure disposed on and extending along a side surface of the conductive pattern; a buried contact disposed on the spacer structure on the first region and connected to the second portion; a capacitor structure connected to the buried contact; and an edge insulating film disposed on the spacer structure on the second region. A portion of the spacer structure is interposed between the substrate and the edge insulating film.

[0008] According to an aspect of the present disclosure, there is provided a semiconductor memory device including: a substrate including a cell region and a peripheral region surrounding the cell region, wherein the cell region includes a first region and a second region interposed between the first region and the peripheral region in a first direction; an active pattern disposed in the first region and including a first portion and a second portion; a gate electrode extending in a second direction intersecting the first direction and straddling between the first portion and the second portion; a first wire disposed on the substrate, connected to the first portion, and extending in the first direction; a second wire disposed on the substrate, extending in the first direction, and spaced apart from the first wire in the second direction; a buried contact disposed between the first wire and the second wire and connected to the second portion; a capacitor structure connected to the buried contact; and an edge insulating film disposed on the second region. Wherein the first wire includes: a first line portion disposed on the first region; and a first edge portion disposed on the second region and having an end portion of the first wire. Wherein the second wire includes: a second line portion disposed on the first region; and a second edge portion disposed on the second region, having an end portion of the second wire, and protruding beyond the first edge portion toward the peripheral region. Wherein the edge insulating film includes: a first fill portion interposed between the first edge portion and the second edge portion in the second direction; and a second fill portion overlapping the first edge portion in the first direction and overlapping the second edge portion in the second direction. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which: Figure 1 is an example block diagram illustrating a semiconductor memory device according to some embodiments; Figure 2 is an example layout diagram illustrating an R region of Figure 1 Figure 3 is a cross-sectional view taken along lines A1-A1 and A2-A2 of Figure 2 Figure 4 is a cross-sectional view taken along line B-B of Figure 2 Figure 5 ​​​is a partial layout diagram illustrating a semiconductor memory device according to some embodiments. Figure 6 is a partial layout diagram illustrating a semiconductor memory device according to some embodiments. Figure 7 is a cross-sectional view taken along Figure 6 line A2-A2 of Figures 8 to 48 is a diagram of an intermediate structure according to some embodiments corresponding to an intermediate step of a method for manufacturing a semiconductor memory device. DETAILED DESCRIPTION

[0010] Hereinafter, with reference to Figures 1 to 7 , a semiconductor memory device according to some embodiments is described.

[0011] Figure 1 is an example block diagram illustrating a semiconductor memory device according to some embodiments. Figure 2 is an example layout diagram illustrating the R region of Figure 1 Figure 3 is a cross-sectional view taken along Figure 2 lines A1-A1 and A2-A2 of Figure 4 is a cross-sectional view taken along Figure 2 line B-B of Figure 5 is a partial layout diagram illustrating a semiconductor memory device according to some embodiments.

[0012] With reference to Figures 1 to 5 , a semiconductor memory device according to some embodiments includes a substrate 100, an element isolation pattern 105, a word line structure 110, a base insulating film 120, a direct contact DC, a bit line structure BLS, a buried contact BC, a fence insulating film 170, an edge insulating film 175, a landing pad LP, an isolation insulating film 180, a capacitor structure 190, and a contact plug CP.

[0013] The substrate 100 can be a semiconductor substrate such as a silicon wafer. The substrate 100 can be in a structure in which a base substrate and an epitaxial layer are stacked. However, embodiments of the present disclosure are not limited thereto. The substrate 100 can be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, or an SOI (Silicon On Insulator) substrate. An example in which the substrate 100 is embodied as a silicon substrate is described below.

[0014] ​The substrate 100 can include a cell region CR and a peripheral region PR. The cell region CR can be a memory cell array region provided with memory cells. The peripheral region PR can be a core / peripheral region formed around the cell region CR. A peripheral circuit element can be formed on the peripheral region PR to control a function of the memory cells formed on the cell region CR. Only that the peripheral region PR surrounds the cell region CR in a horizontal plane (e.g., an XY plane including a first direction Y and a second direction X intersecting each other) is illustrated. However, this is merely an example, and the cell region CR and the peripheral region PR can be placed in various other forms.

[0015] The cell region CR can include a first region I and a second region II. The first region I and the second region II can be arranged along the first direction Y. The second region II can be interposed between the first region I and the peripheral region PR in the first direction Y. The second region II can be a boundary region provided at an edge of the cell region CR.

[0016] The cell region CR of the substrate 100 can include an active pattern AP. The active pattern AP can be defined by an element isolation pattern 105 within the cell region CR. The element isolation pattern 105 can include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and combinations thereof. However, embodiments of the present disclosure are not limited thereto. The element isolation pattern 105 can be embodied as a single layer film made of one type of insulating material, or can be embodied as a stack of multiple layer films made of several types of insulating materials, respectively.

[0017] The active pattern AP can be in a plurality of strips extending in parallel to each other. In some embodiments, a center of one of the plurality of active patterns AP can be disposed adjacent to an end of another of the plurality of active patterns AP. In some embodiments, the active pattern AP can be formed in a diagonal strip. For example, as shown in FIG. 1A, the active pattern AP can be in a strip extending in a third direction W different from the second direction X and the first direction Y in a plane extending along the first direction Y and the second direction X. Figure 2

[0018] The active pattern AP can include a first portion (e.g., a center portion) and a second portion (e.g., an end portion). Each of the first portion and the second portion can contain impurities and be provided as a source / drain region. In some embodiments, the first portion (e.g., the center portion) can be connected to the bit line structure BLS via a direct contact DC, and the second portion (e.g., the end portion) can be connected to the capacitor structure 190 via a buried contact BC and / or a landing pad LP.

[0019] ​The word line structure 110 can be formed on the cell region CR of the substrate 100. The word line structure 110 can extend in an elongated manner in a second direction X parallel to the upper surface of the substrate 100. For example, the word line structure 110 can extend obliquely across the active pattern AP and extend across the bit line structure BLS in a perpendicular manner thereto. A plurality of word line structures 110 can be spaced apart from each other in the first direction Y and can extend in a parallel manner to each other in the second direction X, and can be arranged side by side. In some embodiments, the plurality of word line structures 110 can be equally spaced apart from each other.

[0020] The word line structure 110 can span the active pattern AP between the direct contact DC and the buried contact BC. For example, the word line structure 110 can span the active pattern AP between a first portion (e.g., a central portion of the active pattern AP) and a second portion (e.g., an end portion of the active pattern AP).

[0021] In some embodiments, two word line structures 110 can span one active pattern AP. For example, two word line structures 110 can be respectively disposed on two opposite sides of the direct contact DC. The two word line structures 110 can share one direct contact DC.

[0022] As Figure 4 illustrated, the word line structure 110 can include a gate dielectric film 112, a gate electrode 114, and a gate cover film 116. The gate dielectric film 112, the gate electrode 114, and the gate cover film 116 can be sequentially stacked on the substrate 100.

[0023] The gate dielectric film 112 can be interposed between the active pattern AP and the gate electrode 114. The gate dielectric film 112 can be interposed between the element isolation pattern 105 and the gate electrode 114. The gate dielectric film 112 can include, but is not limited to, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a dielectric constant higher than that of silicon oxide.

[0024] The gate electrode 114 can be formed on the gate dielectric film 112. The gate electrode 114 can extend in the second direction X. The gate electrode 114 can be embodied as a single layer film, or can be embodied as a stack of a plurality of layer films as illustrated. For example, the gate electrode 114 can include a first electrode film 114a and a second electrode film 114b sequentially stacked on the gate dielectric film 112. Each of the first electrode film 114a and the second electrode film 114b can include a conductive material, for example, at least one of polysilicon, TiN, TiSiN, tungsten, tungsten silicide, and a combination thereof. However, embodiments of the present disclosure are not limited thereto.

[0025] The gate electrode 114 can be provided as a word line of the semiconductor storage device. Each of the first portion (e.g., the central portion) and the second portion (e.g., the end portion) of the active pattern AP can be provided as a source / drain region of a field effect transistor using the gate electrode 114 as a gate electrode. The region between the first portion and the second portion of the active pattern AP can be provided as a channel region of the field effect transistor.

[0026] The gate cover film 116 can extend along the upper surface of the gate electrode 114. The gate cover film 116 can include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and a combination thereof. However, embodiments of the present disclosure are not limited thereto. The gate cover film 116 can be embodied as a single layer film or a stack of multiple layer films made of various types of insulating materials, respectively.

[0027] In some embodiments, the word line structure 110 can be embedded in the substrate 100. For example, a gate trench WLt extending in the second direction X can be formed within the active pattern AP and the element isolation pattern 105. The gate dielectric film 112 can extend along the profile of the gate trench WLt. The gate electrode 114 can fill a portion of the gate trench WLt while being disposed on the gate dielectric film 112. The gate cover film 116 can fill another portion of the gate trench WLt while being disposed on the gate dielectric film 112 and the gate electrode 114. In this case, the vertical level of the upper surface of the gate electrode 114 can be lower than the vertical level of each of the upper surface of the active pattern AP and the upper surface of the element isolation pattern 105.

[0028] In some embodiments, some of the plurality of word line structures 110 can be disposed on the second region II. The word line structure 110 disposed on the second region II can be provided as a dummy word line D110 that does not constitute a storage cell. The dummy word line D110 can be used to improve the uniformity of a pattern in a patterning process for forming the word line structure 110.

[0029] The base insulating film 120 can be formed on the substrate 100. The base insulating film 120 can extend along the upper surface of the active pattern AP, the upper surface of the element isolation pattern 105, and the upper surface of the word line structure 110. The base insulating film 120 can be embodied as a single layer film, or can be embodied as a stack of multiple layer films made of various types of insulating materials, as described above. Figure 3A stack of the multi-layer film is illustrated. For example, the base insulating film 120 can include a first insulating film 122, a second insulating film 124, and a third insulating film 126, which are sequentially stacked on the active pattern AP and the element isolation pattern 105. The second insulating film 124 can include a material having an etching selectivity different from that of the first insulating film 122. For example, the first insulating film 122 can include a silicon oxide film, and the second insulating film 124 can include a silicon nitride film. The third insulating film 126 can include a material having a dielectric constant lower than that of the second insulating film 124. For example, the second insulating film 124 can include a silicon nitride film, and the third insulating film 126 can include a silicon oxide film.

[0030] The direct contact DC can be connected to the active pattern AP. The direct contact DC can connect the active pattern AP and the bit line structure BLS to each other. For example, the first contact trench CT1 can be formed in the substrate 100, and the first contact trench CT1 extends through the base insulating film 120 to expose a first portion (e.g., a central portion) of the active pattern AP. The direct contact DC can be formed in the first contact trench CT1 to electrically connect the first portion of the active pattern AP and the conductive pattern 130 to each other.

[0031] The bit line structure BLS can be formed on the cell region CR of the substrate 100. The bit line structure BLS can extend in an elongated manner in a first direction Y parallel to the upper surface of the substrate 100. For example, the bit line structure BLS can extend obliquely through the active pattern AP and in a perpendicular manner to the word line structure 110. A plurality of bit line structures BLS can be spaced apart from each other in a second direction X and extend in parallel to each other in the first direction Y, and can be arranged side by side. In some embodiments, the plurality of bit line structures BLS can be spaced apart from each other by equal spacing.

[0032] As Figure 3 illustrated, the bit line structure BLS can include the conductive pattern 130, the cover pattern 135, and the spacer structure 140.

[0033] The conductive pattern 130 can be formed on the substrate 100. The conductive pattern 130 can extend in an elongated manner in the first direction Y and along the upper surface of the base insulating film 120. The conductive pattern 130 can be embodied as a single layer film, or can be embodied as a stack of multi-layer films, as Figure 3The conductive pattern 130 can include a first conductive film 131, a second conductive film 132, and a third conductive film 133 sequentially stacked on the base insulating film 120. Each of the first conductive film 131, the second conductive film 132, and the third conductive film 133 can include a conductive material, for example, at least one of poly-Si, TiN, TiSiN, tungsten, tungsten silicide, and a combination thereof. However, embodiments of the disclosure are not limited thereto. For example, the first conductive film 131 can include a poly-Si film, the second conductive film 132 can include a TiSiN film, and the third conductive film 133 can include a tungsten (W) film. The conductive pattern 130 can be disposed as a bit line of a semiconductor memory device.

[0034] The conductive pattern 130 can have an end portion located on the second region II. For example, as shown in FIG. 1B, the conductive pattern 130 can include line portions L1 and L2 and edge portions E1 and E2. The line portions L1 and L2 can extend in an elongated manner in the first direction Y while being disposed on the first region I. The edge portions E1 and E2 can further extend from the line portions L1 and L2, respectively, toward the peripheral region PR. The edge portions E1 and E2 can have an end of the conductive pattern 130 while being disposed on the second region II. For example, the edge portions E1 and E2 can be spaced apart from the peripheral region PR. Figure 5

[0035] The conductive pattern 130 can extend along the first direction Y over the first region I and the second region II, and an end of the conductive pattern 130 formed on the second region can be spaced apart from the peripheral region PR.

[0036] The cap pattern 135 can extend along an upper surface of the conductive pattern 130. The cap pattern 135 can be embodied as a single layer film, or can be embodied as a stack of multiple layer films as shown in FIG. 1C. For example, the cap pattern 135 can include a first cap film 136, a second cap film 137, and a third cap film 138 sequentially stacked on the conductive pattern 130. The first cap film 136, the second cap film 137, and the third cap film 138 can include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and a combination thereof. However, embodiments of the disclosure are not limited thereto. For example, each of the first cap film 136, the second cap film 137, and the third cap film 138 can include a silicon nitride film. Figure 3 The spacer structure 140 can extend along side surfaces of the conductive pattern 130 and side surfaces of the cap pattern 135. The spacer structure 140 can include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and a combination thereof. However, embodiments of the disclosure are not limited thereto.

[0037] ​​In some embodiments, the spacer structure 140 can be embodied as a stack of multiple layers of films made of various types of insulating materials, respectively. For example, the spacer structure 140 can include a base spacer 141, a first lower spacer 142, a second lower spacer 143, a first side spacer 144, and a second side spacer 145.

[0038] The base spacer 141 can extend along the side surfaces of the conductive pattern 130, directly contact the side surfaces of the DC, and cover the side surfaces of the pattern 135.

[0039] In some embodiments, the base spacer 141 can be the innermost spacer of the spacer structure 140 that contacts the conductive pattern 130, directly contacts the DC, and covers the pattern 135.

[0040] In some embodiments, the base spacer 141 can further extend along the upper surface of the base insulating film 120. In some embodiments, the base spacer 141 can extend along the first contact trench CT1.

[0041] The first lower spacer 142 can be formed on the base spacer 141 and within the first contact trench CT1. For example, the first lower spacer 142 can extend conformally along the profile of the base spacer 141 and within the first contact trench CT1.

[0042] The second lower spacer 143 can be formed on the first lower spacer 142 and within the first contact trench CT1. For example, the second lower spacer 143 can fill the area of the first contact trench CT1 that remains after the base spacer 141 and the first lower spacer 142 have been formed therein.

[0043] The first side spacer 144 can be formed on the outer side surfaces of the base spacer 141. In addition, the first side spacer 144 can be formed on the upper surfaces of the first lower spacer 142 and the second lower spacer 143.

[0044] The second side spacer 145 can be formed on the outer side surfaces of the first side spacer 144. In addition, the second side spacer 145 can be formed on the upper surface of the second lower spacer 143. In some embodiments, the second side spacer 145 can be the outermost spacer of the spacer structure 140 that contacts the buried contact BC and / or the landing pad LP.

[0045] In some embodiments, the second side spacer 145 can also extend along the side surfaces of the base insulating film 120, the upper surface of the active pattern AP, the upper surface of the element isolation pattern 105, and the upper surface of the word line structure 110. In some embodiments, the vertical level of the lowermost surface of the second side spacer 145 can be lower than the vertical level of the uppermost surface of the second lower spacer 143.

[0046] Each of the base spacer 141, the first lower spacer 142, the second lower spacer 143, the first side spacer 144, and the second side spacer 145 can include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and combinations thereof. However, embodiments of the present disclosure are not limited thereto.

[0047] In some embodiments, the first lower spacer 142 can include a material having a lower dielectric constant than the dielectric constant of the base spacer 141 and / or the second lower spacer 143. For example, the first lower spacer 142 can include a silicon oxide film, and each of the base spacer 141 and the second lower spacer 143 can include a silicon nitride film.

[0048] In some embodiments, the first side spacer 144 can include a material having a lower dielectric constant than the dielectric constant of the base spacer 141 and / or the second side spacer 145. For example, the first side spacer 144 can include a silicon oxide film, and each of the base spacer 141 and the second side spacer 145 can include a silicon nitride film.

[0049] The buried contact BC can be formed on the first region I of the substrate 100. The buried contact BC can not be formed on the second region II of the substrate 100. The buried contact BC can be connected to the active pattern AP. For example, a second contact trench CT2 can be formed in the first region I of the substrate 100, and the second contact trench CT2 extends through the base insulating film 120 to expose a second portion (e.g., an end portion) of the active pattern AP. The buried contact BC can be formed in the second contact trench CT2 to be electrically connected to the second portion of the active pattern AP.

[0050] The buried contact BC can be formed on a side surface of the bit line structure BLS. In addition, the buried contact BC can be spaced apart from the conductive pattern 130 by the spacer structure 140. For example, as shown, the buried contact BC can extend along a portion of an outer side surface of the spacer structure 140. Figure 3

[0051] The buried contact BC can include a conductive material, for example, at least one of polysilicon, TiN, TiSiN, tungsten, tungsten silicide, and combinations thereof. However, embodiments of the present disclosure are not limited thereto. For example, the buried contact BC can include a conductive semiconductor material, such as poly-Si doped with an impurity.

[0052] In some embodiments, the buried contact BC can include the first fill conductive film 152 and the silicide film 154.

[0053] ​The first filled conductive film 152 can fill the second contact trench CT2. The first filled conductive film 152 can extend along a portion of a side surface of the bit line structure BLS. The first filled conductive film 152 can include a conductive semiconductor material, for example, poly-Si doped with an impurity.

[0054] The silicide film 154 can be interposed between the first filled conductive film 152 and the landing pad LP. The silicide film 154 can be formed based on a reaction between a semiconductor element (for example, silicon (Si)) included in the first filled conductive film 152 and a metal element (for example, a metal element included in the landing pad LP). The silicide film 154 can include, for example, a metal silicide such as nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, niobium silicide, or tantalum silicide. However, embodiments of the present disclosure are not limited thereto.

[0055] The fence insulating film 170 can be formed on the first region I of the substrate 100. The fence insulating film 170 can be formed on a side surface of the bit line structure BLS. The fence insulating film 170 can be spaced apart from the conductive pattern 130 by the spacer structure 140.

[0056] In some embodiments, the fence insulating film 170 can overlap the word line structure 110 in the fourth direction Z intersecting the upper surface of the substrate 100. On the first region I of the substrate 100, the buried contact BC and the fence insulating film 170 can be alternately arranged along the first direction Y from each other.

[0057] The fence insulating film 170 can include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and a combination thereof. However, embodiments of the present disclosure are not limited thereto. For example, the fence insulating film 170 can include a silicon nitride film.

[0058] The bit line structure BLS and the fence insulating film 170 can define a plurality of isolation regions arranged in a lattice structure. The buried contacts BC can be respectively formed within the isolation regions and spaced apart from each other. For example, based on the upper surface of the substrate 100, a vertical level of an upper surface of the cover pattern 135 can be higher than a vertical level of an upper surface of the buried contact BC. Adjacent buried contacts of the plurality of buried contacts BC arranged along the second direction X can be spaced apart from each other via each bit line structure of the plurality of bit line structures BLS arranged along the second direction X. Further, for example, based on the upper surface of the substrate 100, a vertical level of an upper surface of the fence insulating film 170 can be higher than a vertical level of an upper surface of the buried contact BC. Adjacent buried contacts of the plurality of buried contacts BC arranged along the first direction Y can be spaced apart from each other via each fence insulating film of the plurality of fence insulating films 170 arranged along the first direction Y.

[0059] An edge insulating film 175 can be formed on the second region II of the substrate 100. The edge insulating film 175 can be formed on side surfaces of the bit line structure BLS. The edge insulating film 175 can be spaced apart from the conductive pattern 130 by the spacer structure 140. The edge insulating film 175 can extend along end portions of the conductive pattern 130 formed on the second region. For example, as shown in FIG. 16B, the edge insulating film 175 can extend along the edge portions E1 and E2. Figure 5

[0060] In some embodiments, the conductive pattern 130 can include a first conductive line 1301, a second conductive line 1302, a third conductive line 1303, and a fourth conductive line 1304 spaced apart from each other and sequentially arranged in the second direction X. The second conductive line 1302 and the fourth conductive line 1304 can protrude beyond the first conductive line 1301 and the third conductive line 1303 in the first direction Y. For example, each of the first conductive line 1301 and the third conductive line 1303 can include a first line portion L1 and a first edge portion E1, and each of the second conductive line 1302 and the fourth conductive line 1304 can include a second line portion L2 and a second edge portion E2. An end portion of the second edge portion E2 can be closer to the peripheral region PR than an end portion of the first edge portion E1. The edge insulating film 175 can be formed on side surfaces of the first edge portion E1 and the second edge portion E2.

[0061] In some embodiments, a width of the first line portion L1 and a width of the second line portion L2 can be equal to each other. In the present disclosure, the term "equal" means not only complete equality but also a slight difference that can occur due to a process margin or the like. For example, a width W1 of the first line portion L1 in the second direction X and a width W2a of the second line portion L2 in the second direction X can be equal to each other.

[0062] In some embodiments, the edge insulating film 175 can include a first filling portion 175A, a second filling portion 175B, and a third filling portion 175C. Each of the first filling portion 175A and the second filling portion 175B can overlap the first edge portion E1 in the second direction X. The first edge portion E1 can be interposed between the first filling portion 175A and the second filling portion 175B in the second direction X. The third filling portion 175C can overlap the first edge portion E1 in the first direction Y and can overlap the second edge portion E2 in the second direction X. The third filling portion 175C can be connected to the first filling portion 175A and the second filling portion 175B to constitute the integral edge insulating film 175. That is, the first filling portion 175A, the second filling portion 175B, and the third filling portion 175C can continuously extend without being separated by other components to form an approximate "Y" shape structure in a plan view. ​

[0063] In some embodiments, a portion of the spacer structure 140 can be between the edge insulating film 175 and the peripheral region PR. For example, a fill insulating film 210 can be formed on the peripheral region PR. A portion of the spacer structure 140 can further extend in the second direction X and along the fill insulating film 210, and can be between the edge insulating film 175 and the fill insulating film 210.

[0064] In some embodiments, a portion of the second side spacer 145 can be between the substrate 100 and the edge insulating film 175. For example, as shown in FIG. 1B, the second side spacer 145 can further extend along an upper surface of the active pattern AP of the second region II, an upper surface of the element isolation pattern 105 of the second region II, and an upper surface of the word line structure 110 of the second region II. The edge insulating film 175 can extend along an outer side surface and an upper surface of the second side spacer 145. Figure 3 Figure 4 As shown, the second side spacer 145 can further extend along an upper surface of the active pattern AP of the second region II, an upper surface of the element isolation pattern 105 of the second region II, and an upper surface of the word line structure 110 of the second region II. The edge insulating film 175 can extend along an outer side surface and an upper surface of the second side spacer 145.

[0065] The edge insulating film 175 is shown as contacting the buried contact BC only in the first direction Y. However, this is merely an example, and the edge insulating film 175 can contact the barrier insulating film 170 in the first direction Y. For example, unlike shown, the barrier insulating film 170 can be between the buried contact BC and the edge insulating film 175.

[0066] The landing pad LP can be formed on the first region I and the second region II. The landing pad LP can be formed on an upper surface of the buried contact BC, an upper surface of the barrier insulating film 170, and an upper surface of the edge insulating film 175. The landing pad LP can electrically contact the buried contact BC. The landing pad LP can define a plurality of isolated regions spaced apart from each other. For example, a pad trench LPt defining each of the plurality of landing pads LP spaced apart from each other can be formed.

[0067] The landing pad LP can include a conductive material, for example, at least one of polysilicon, TiN, TiSiN, tungsten, tungsten silicide, and combinations thereof. However, embodiments of the present disclosure are not limited thereto. For example, the landing pad LP can include tungsten (W).

[0068] ​In some embodiments, a landing pad LP on the first region I can be formed across the bit line structure BLS and the buried contact BC. For example, a portion of the landing pad LP can overlap the buried contact BC in the fourth direction Z, and another portion of the landing pad LP can overlap the cap pattern 135 and the spacer structure 140 in the fourth direction Z. A vertical level of a lower surface of the pad trench LPt on the first region I can be lower than a vertical level of an upper surface of the cap pattern 135, and can be higher than a vertical level of an upper surface of the conductive pattern 130. In some embodiments, a portion of the pad trench LPt can overlap the cap pattern 135 and the spacer structure 140 in the fourth direction Z. Thus, the pad trench LPt on the first region I can define each of a plurality of landing pads LP on the first region I spaced apart from each other.

[0069] In some embodiments, a landing pad LP on the second region II can be formed on the edge insulating film 175. For example, the landing pad LP can extend along an upper surface of the edge insulating film 175. A vertical level of a lower surface of the pad trench LPt on the second region II can be lower than a vertical level of an upper surface of the edge insulating film 175. Thus, the pad trench LPt on the second region II can define each of a plurality of landing pads LP on the second region II spaced apart from each other.

[0070] In some embodiments, a landing pad LP on the second region II can be provided as a dummy landing pad DLP not constituting a memory cell. The dummy landing pad DLP can be used to improve uniformity of a pattern in a patterning process for forming the landing pad LP.

[0071] In some embodiments, a plurality of landing pads LP can be arranged in a honeycomb structure. The landing pads LP arranged in the honeycomb structure can further improve the degree of integration of the semiconductor memory device.

[0072] In some embodiments, a landing pad LP can include a lower pad 156 and an upper pad 158.

[0073] The lower pad 156 can be formed on the first region I. The lower pad 156 can not be formed on the second region II. The lower pad 156 can be formed on the upper surface of the buried contact BC and the side surface of the bit line structure BLS. For example, the lower pad 156 can fill a space located on the upper surface of the buried contact BC and the side surface of the bit line structure BLS. The vertical level of the uppermost surface of the lower pad 156 can be equal to or lower than the vertical level of the uppermost surface of the cover pattern 135. In some embodiments, the vertical level of the uppermost surface of the lower pad 156 can be equal to the vertical level of the uppermost surface of the cover pattern 135 based on the upper surface of the substrate 100. Adjacent lower pads among the plurality of lower pads 156 arranged along the second direction X can be spaced apart from each other via each bit line structure among the plurality of bit line structures BLS arranged along the second direction X.

[0074] In some embodiments, the lower pad 156 can include a barrier conductive film 156a and a second fill conductive film 156b.

[0075] The barrier conductive film 156a can conformingly extend along the profile of the combination of the upper surface of the buried contact BC and the side surface of the spacer structure 140. In some embodiments, the vertical level of the uppermost surface of the barrier conductive film 156a can be equal to the vertical level of the uppermost surface of the bit line structure BLS. The barrier conductive film 156a can include a metal or a metal nitride to prevent diffusion of a metal element included in the second fill conductive film 156b. For example, the barrier conductive film 156a can include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), an alloy thereof, and a nitride thereof. However, embodiments of the present disclosure are not limited thereto. In one example, the barrier conductive film 156a can include a titanium nitride (TiN) film.

[0076] The second fill conductive film 156b can be formed on the barrier conductive film 156a. The second fill conductive film 156b can fill a space located on the upper surface of the buried contact BC and the side surface of the bit line structure BLS. The second fill conductive film 156b can include a conductive metal, for example, tungsten (W).

[0077] An upper pad 158 can be formed on the first region I and the second region II. The upper pad 158 can be formed in each of a plurality of isolation regions spaced apart from each other via the pad trench LPt. The upper pad 158 located on the first region I can extend along an upper surface of the lower pad 156, an upper surface of the bit line structure BLS, and an upper surface of the fence insulating film 170. In some embodiments, the upper pad 158 located on the first region I can be in contact with an upper surface of the barrier conductive film 156a and an upper surface of the second fill conductive film 156b. The upper pad 158 located on the second region II can extend along an upper surface of the bit line structure BLS and an upper surface of the edge insulating film 175.

[0078] The upper pad 158 can include a conductive material, for example, at least one of polysilicon, TiN, TiSiN, tungsten, tungsten silicide, and a combination thereof. However, embodiments of the disclosure are not limited thereto. In some embodiments, the upper pad 158 can include the same conductive metal as that of the second fill conductive film 156b. For example, the upper pad 158 can include tungsten (W).

[0079] Although it is illustrated that a boundary is defined between the lower pad 156 and the upper pad 158, this is merely an example. According to a process of forming the lower pad 156 and the upper pad 158, a boundary can not be defined between the lower pad 156 and the upper pad 158.

[0080] An isolation insulating film 180 can be formed on the landing pad LP. The isolation insulating film 180 can fill the pad trench LPt. A plurality of landing pads LP can be spaced apart from each other via the isolation insulating film 180, and thus can respectively correspond to a plurality of isolation regions. The isolation insulating film 180 can include, but is not limited to, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k material having a dielectric constant lower than that of silicon oxide.

[0081] A capacitor structure 190 can be formed on the isolation insulating film 180 and the landing pad LP. The capacitor structure 190 can electrically contact the landing pad LP. For example, the isolation insulating film 180 can be patterned to expose at least a portion of an upper surface of the landing pad LP. The capacitor structure 190 can extend through the isolation insulating film 180 to connect to at least a portion of the upper surface of the landing pad LP.

[0082] The capacitor structure 190 can store data in each memory cell formed on the cell region CR by being controlled by the conductive pattern 130 provided as a bit line and the gate electrode 114 provided as a word line. In some embodiments, the capacitor structure 190 can include a lower electrode 192, a capacitor dielectric film 194, and an upper electrode 196 sequentially stacked on the landing pad LP. The capacitor structure 190 can store an electric charge in the capacitor dielectric film 194 based on a potential difference between the potentials of the lower electrode 192 and the upper electrode 196.

[0083] Each of the lower electrode 192 and the upper electrode 196 can include, for example, doped polysilicon, metal, or metal nitride. However, embodiments of the present disclosure are not limited thereto. Also, the capacitor dielectric film 194 can include, for example, silicon oxide or a high-k material. However, embodiments of the present disclosure are not limited thereto.

[0084] A contact plug CP can be formed on the second region II of the substrate 100. The contact plug CP can electrically contact the conductive pattern 130. Some peripheral circuit elements (e.g., a sense amplifier) formed on the peripheral region PR can be connected to the conductive pattern 130 via the contact plug CP, and can control the memory cells formed on the cell region CR. For example, as shown in FIG. 1B, the contact plug CP can be electrically connected to the second wire 1302 and / or the fourth wire 1304 by contacting the second edge portion E2. Although not specifically shown, the contact plug CP can be electrically connected to the first wire 1301 and / or the third wire 1303. For example, the contact plug CP can be disposed on a boundary region surrounding the first region I opposite the second region II, and can be electrically connected to the first wire 1301 and / or the third wire 1303. Figure 5

[0085] In some embodiments, the second edge portion E2 can include an extension portion E2a and an extension portion E2b. The extension portion E2a can overlap the first edge portion E1, the first fill portion 175A, and the second fill portion 175B in the second direction X. The extension portion E2b can further extend from the extension portion E2a toward the peripheral region PR. The extension portion E2b can overlap the third fill portion 175C in the second direction X. A width W2b of the extension portion E2b in the second direction X can be greater than a width W2a of the extension portion E2a in the second direction X. The extension portion E2b can more easily contact the contact plug CP.

[0086] Figure 6 FIG. 1A is a partial layout view illustrating a semiconductor memory device according to some embodiments. Figure 7 FIG. 1B is a cross-sectional view taken along line A2-A2 of FIG. 1A. For ease of description, the same reference numerals are used for the same components as those used in FIG. 1A. Figure 6 Figures 1 to 5 ​​The above-described content that is repetitive is briefly described or its description is omitted.

[0087] Referring to Figure 1 , Figure 6 and Figure 7 , in the semiconductor storage device according to some embodiments, the edge insulating film 175 includes a seam.

[0088] The seam S can be spaced apart from the spacer structure 140. The seam S can be a boundary of the edge insulating film 175 between the conductive patterns 130 adjacent to each other in the second direction X. For example, the seam S can be a boundary surface at which a portion of the edge insulating film 175 stacked on a side surface of the first conductive line 1301 and another portion of the edge insulating film 175 stacked on a side surface of the second conductive line 1302 intersect with each other. Or, for example, the seam S can be a boundary surface at which a portion of the edge insulating film 175 stacked on a side surface of the second conductive line 1302 and another portion of the edge insulating film 175 formed on a side surface of the fourth conductive line 1304 intersect with each other.

[0089] At least a portion of the seam S can extend in the first direction Y and can be located within the edge insulating film 175. For example, each of the seam S within the first fill portion 175A, the seam S within the second fill portion 175B, and the seam S within the third fill portion 175C can extend in the first direction Y in an elongated manner. In some embodiments, the seam S within the first fill portion 175A can be connected to the seam S within the third fill portion 175C. The seam S within the second fill portion 175B can be connected to the seam S within the third fill portion 175C.

[0090] Hereinafter, referring to Figures 1 to 48 , a method for manufacturing a semiconductor storage device according to some embodiments is described. For ease of description, content that is repetitive of the above-described content using Figures 1 to 7 is briefly described or its description is omitted.

[0091] Figures 8 to 48 is a diagram of an intermediate structure corresponding to an intermediate step of the method for manufacturing a semiconductor storage device according to some embodiments.

[0092] Referring to Figures 8 to 10 , the element isolation pattern 105, the word line structure 110, the base insulating film 120, the pre-conductive pattern 130p, the direct contact DC, and the first cover film 136 are formed on the substrate 100.

[0093] The element isolation pattern 105 can be formed within the substrate 100. The element isolation pattern 105 can define an active pattern AP within the substrate 100.

[0094] The word line structure 110 can be formed on the cell region CR of the substrate 100. The word line structure 110 can extend in the second direction X. In some embodiments, the word line structure 110 can be embedded in the substrate 100.

[0095] The base insulating film 120 can be formed on the substrate 100. The base insulating film 120 can extend along the upper surface of the active pattern AP, the upper surface of the element isolation pattern 105, and the upper surface of the word line structure 110.

[0096] The pre-conductive pattern 130p can be formed on the cell region CR. The pre-conductive pattern 130p can cover the upper surface of the base insulating film 120. In some embodiments, the pre-conductive pattern 130p can include a first conductive film 131, a second conductive film 132, and a third conductive film 133 sequentially stacked on the base insulating film 120.

[0097] The direct contact DC can electrically connect the active pattern AP and the pre-conductive pattern 130p to each other. For example, after the first conductive film 131 is formed on the base insulating film 120, a first contact trench CT1 exposing a first portion (e.g., a central portion) of the active pattern AP can be formed. The direct contact DC can fill the first contact trench CT1. After the direct contact DC is formed, the second conductive film 132 and the third conductive film 133 can be sequentially stacked on the first conductive film 131 and the direct contact DC.

[0098] The first cover film 136 can extend along the upper surface of the pre-conductive pattern 130p.

[0099] Referring to FIG. 1C, Figures 11 to 13 The conductive pattern 130 and the cover pattern 135 are formed.

[0100] For example, the second cover film 137 and the third cover film 138 can be sequentially formed on the first cover film 136. Subsequently, a patterning process can be performed on the first conductive film 131 to the third conductive film 133 and the first cover film 136 to the third cover film 138. When the patterning process is performed, the conductive pattern 130 extending in an elongated manner in the first direction Y and the cover pattern 135 extending along the upper surface of the conductive pattern 130 can be formed.

[0101] Referring to FIG. 1D, Figures 14 to 16 The spacer structure 140 is formed.

[0102] The spacer structure 140 can extend along the side surface of the conductive pattern 130 and the side surface of the cover pattern 135. In some embodiments, the spacer structure 140 can include a base spacer 141, a first lower spacer 142, a second lower spacer 143, a first side spacer 144, and a second side spacer 145.

[0103] The base spacer 141 can extend along the side surface of the conductive pattern 130, the side surface directly contacting the DC, and the side surface covering the pattern 135.

[0104] The first lower spacer 142 can be formed on the base spacer 141 and within the first contact trench CT1. The second lower spacer 143 can be formed on the first lower spacer 142 and within the first contact trench CT1. The first side spacer 144 can be formed on the outer side surface of the base spacer 141.

[0105] The second side spacer 145 can extend along the outer side surface of the first side spacer 144, the side surface of the base insulating film 120, the upper surface of the active pattern AP, the upper surface of the element isolation pattern 105, and the upper surface of the word line structure 110. For example, an etching process can be performed on the base insulating film 120 using the first side spacer 144 as an etching mask. After the etching process has been performed, the second side spacer 145 can be stacked on the first side spacer 144.

[0106] Referring to Figures 17 to 19 A sacrificial film 175S is formed on the spacer structure 140.

[0107] The sacrificial film 175S can be formed on the first region I and the second region II. The sacrificial film 175S can cover the spacer structure 140. The sacrificial film 175S can be formed to fill a space located on the side surface of the conductive pattern 130. For example, the sacrificial film 175S can fill a space located on the outer side surface and the upper surface of the second side spacer 145.

[0108] The sacrificial film 175S can include a material having etching selectivity with respect to the spacer structure 140. In one example, the second side spacer 145 can include a silicon nitride film, and the sacrificial film 175S can include a silicon oxide film.

[0109] Referring to Figures 20 to 22 A portion of the sacrificial film 175S located on the first region I is removed.

[0110] For example, a first mask pattern 310 can be formed on the sacrificial film 175S. The first mask pattern 310 can cover the sacrificial film 175S located on the second region II, and can expose the sacrificial film 175S located on the first region I. The first mask pattern 310 can include, for example, a photoresist pattern. However, embodiments of the disclosure are not limited thereto.

[0111] Next, an etching process using the first mask pattern 310 as an etching mask can be performed. When the etching process is performed, a portion of the sacrificial film 175S located on the first region I can be removed, and a portion of the spacer structure 140 located on the first region I can be exposed.

[0112] Referring to Figure 23 and Figure 24 A second contact trench CT2 is formed in the first region I.

[0113] The second contact trench CT2 can extend through a portion of the second side spacer 145 located on the first region I to expose a second portion (e.g., an end portion) of the active pattern AP. For example, an etching process using the bit line structure BLS as an etching mask can be performed. When the above-described etching process is performed, a portion of the second side spacer 145 extending along a horizontal plane (e.g., an XY plane) can be removed to expose the second portion of the active pattern AP. A portion of the second side spacer 145 located on the second region II can be protected with the sacrificial film 175S and thus can not be etched in the etching process.

[0114] Referring to Figures 25 to 27 A pre-contact film pBC is formed.

[0115] The pre-contact film pBC can cover a side surface and an upper surface of a portion of the bit line structure BLS located on the first region I. In addition, the pre-contact film pBC can fill the second contact trench CT2. Accordingly, the pre-contact film pBC can be connected to the second portion (e.g., an end portion) of the active pattern AP.

[0116] The pre-contact film pBC can include a conductive material, for example, at least one of polysilicon, TiN, TiSiN, tungsten, tungsten silicide, and a combination thereof. However, embodiments of the disclosure are not limited thereto. For example, the pre-contact film pBC can include a conductive semiconductor material, for example, poly-Si doped with an impurity.

[0117] Referring to Figure 28 and Figure 29 A planarization process is performed.

[0118] The planarization process can include, for example, a chemical mechanical polishing (CMP) process. However, embodiments of the disclosure are not limited thereto. When the planarization process is performed, an upper surface of the bit line structure BLS can be exposed. For example, when the planarization process is performed, the upper surface of the bit line structure BLS, the upper surface of the pre-contact film pBC, and the upper surface of the sacrificial film 175S can be coplanar with each other. In addition, when the planarization process is performed, adjacent pre-contact films among the plurality of pre-contact films pBC arranged along the second direction X can be spaced apart from each other via each of the plurality of bit line structures BLS arranged along the second direction X.

[0119] Referring to Figures 30 to 32 A buried contact BC is formed.

[0120] The buried contact BC can be formed in each of the plurality of isolation regions spaced apart from each other. For example, a plurality of second mask patterns 320 can be formed on the first region I and the second region II. The plurality of second mask patterns 320 can be spaced apart from each other in the first direction Y and can extend in the second direction X in a manner parallel to each other, and can be arranged side by side. Subsequently, an etching process can be performed on the pre-contact film pBC using the plurality of second mask patterns 320 as an etching mask, and thus a plurality of fence trenches 170t can be formed. Adjacent ones of the plurality of buried contacts BC arranged along the first direction Y can be spaced apart from each other via each of the plurality of fence trenches 170t arranged along the first direction Y.

[0121] Referring to Figures 33 to 35 , the fence insulating film 170 is formed.

[0122] The fence insulating film 170 can fill the fence trench 170t. Thus, the bit line structure BLS and the fence insulating film 170 can define a plurality of isolation regions arranged in a lattice structure. The buried contact BC can be formed within the isolation regions, respectively, and can be spaced apart from each other.

[0123] Referring to Figures 36 to 38 , the sacrificial film 175S is removed.

[0124] The sacrificial film 175S can be selectively removed from the bit line structure BLS, the buried contact BC, and the fence insulating film 170. When the sacrificial film 175S is removed, a portion of the bit line structure BLS located on the second region II can be exposed.

[0125] Referring to Figures 39 to 41 , the edge insulating film 175 is formed.

[0126] The edge insulating film 175 can be formed on the second region II of the substrate 100. The edge insulating film 175 can replace the region from which the sacrificial film 175S has been removed. Thus, the edge insulating film 175 extending along the end portion of the conductive pattern 130 can be formed.

[0127] Referring to Figure 42 and Figure 43 , an etch-back process is performed on the buried contact BC.

[0128] In the etch-back process, the buried contact BC can be etched selectively with respect to the bit line structure BLS, the fence insulating film 170, and the edge insulating film 175. When the etch-back process is performed, an upper portion of the buried contact BC can be removed. For example, after the etch-back process is performed, a vertical level of an upper surface of the buried contact BC can be lower than a vertical level of an upper surface of the cap pattern 135.

[0129] Referring to Figure 44 andFigure 45 The lower pad 156 and the upper pad 158 are formed.

[0130] The lower pad 156 can be formed on the first region I. The lower pad 156 can be formed on the upper surface of the buried contact BC and the side surface of the bit line structure BLS. The lower pad 156 can be connected to the buried contact BC.

[0131] The upper pad 158 can be formed on the first region I and the second region II. The upper pad 158 located on the first region I can extend along the upper surface of the lower pad 156, the upper surface of the bit line structure BLS, and the upper surface of the fence insulating film 170. The upper pad 158 located on the first region I can be connected to the lower pad 156. The upper pad 158 located on the second region II can extend along the upper surface of the bit line structure BLS and the upper surface of the edge insulating film 175.

[0132] Referring to Figures 46 to 48 The pad trench LPt is formed.

[0133] The pad trench LPt can be formed on the first region I and the second region II. The vertical level of the lower surface of the pad trench LPt located on the first region I can be lower than the vertical level of the upper surface of the cover pattern 135 and can be higher than the vertical level of the upper surface of the conductive pattern 130. The vertical level of the lower surface of the pad trench LPt located on the second region II can be lower than the vertical level of the upper surface of the edge insulating film 175. The landing pad LP can be formed in each of a plurality of isolated regions spaced apart from each other via the pad trench LPt.

[0134] Next, referring to Figures 2 to 4 The isolation insulating film 180 and the capacitor structure 190 are formed. Accordingly, a semiconductor memory device as described above using Figures 1 to 5 may be manufactured.

[0135] As semiconductor memory devices become more highly integrated, individual circuit patterns become smaller in order to implement a greater number of semiconductor memory devices in the same area. However, the miniaturization of individual circuit patterns increases process difficulty and causes defects. For example, in the manufacturing process of a semiconductor memory device, a pattern defect can occur at the end portion of a bit line adjacent to a peripheral region. This pattern defect causes bridging between the pattern and a conductive pattern (e.g., dummy buried contact) formed adjacent thereto, thereby causing a reduction in yield and productivity of the semiconductor memory device.

[0136] In the semiconductor memory device according to some embodiments, the edge insulating film 175 can prevent a pattern defect that can occur at the end portion of the bit line. Specifically, as described above, the edge insulating film 175 can extend along the end portion (e.g., the first edge portion E1 and the second edge portion E2) of the conductive pattern 130 to prevent the buried contact BC from being formed around the end portion of the conductive pattern. Accordingly, it is possible to prevent a bridge from being formed between the end portion of the conductive pattern 130 and the buried contact BC, so that a semiconductor memory device with improved yield and productivity can be provided.

[0137] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above-described embodiments, but can be implemented in various different forms. It will be understood by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical spirit or essential characteristics of the present disclosure. Therefore, it should be understood that the above-described embodiments are not restrictive, but are illustrative in all aspects.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A substrate, the substrate comprising a first region and a second region arranged along a first direction; An active pattern is disposed in the first region and includes a first portion and a second portion; A gate electrode that extends in a second direction intersecting the first direction and spans between the first portion and the second portion; A conductive pattern is disposed on the substrate and connected to the first portion, extends in the first direction, and has an end located on the second region; An embedded contact is disposed on the side surface of the conductive pattern located on the first region and connected to the second portion; A capacitor structure connected to the buried contact; as well as An edge insulating film is disposed on the side surface of the conductive pattern located on the second region and surrounding the end of the conductive pattern.

2. The semiconductor memory device according to claim 1, wherein, The edge insulating film includes: A first filling portion, the first filling portion overlapping the conductive pattern in the second direction; and The second filling portion overlaps with the conductive pattern in the first direction.

3. The semiconductor memory device according to claim 2, wherein, The edge insulating film includes a seam extending in the first filling portion along the first direction and in the second filling portion along the first direction.

4. The semiconductor memory device according to claim 1, further comprising: A gate insulating film, the gate insulating film being on the side surface of the conductive pattern located in the first region, and overlapping the gate electrode upwards at a third direction intersecting with the upper surface of the substrate.

5. The semiconductor memory device according to claim 4, wherein, The buried contact is located between the edge insulating film and the fence insulating film in the first direction.

6. The semiconductor memory device according to claim 1, further comprising: A spacer structure is disposed between the conductive pattern and the buried contact, and between the conductive pattern and the edge insulating film, and extends along the side surface of the conductive pattern.

7. The semiconductor memory device according to claim 6, wherein, A portion of the spacer structure is located between the substrate and the edge insulating film.

8. The semiconductor memory device according to claim 1, further comprising: A landing pad is disposed on the upper surface of the buried contact, connecting the buried contact to the capacitor structure; as well as A dummy landing pad is disposed on the upper surface of the edge insulating film and spaced apart from the landing pad.

9. The semiconductor memory device according to claim 1, wherein, The edge insulating film includes a silicon nitride film.

10. The semiconductor memory device according to claim 1, wherein, The substrate includes a gate trench extending in the second direction and spanning between the first portion and the second portion. The gate electrode is buried in the gate trench.

11. A semiconductor memory device, the semiconductor memory device comprising: A substrate, the substrate comprising a first region and a second region arranged along a first direction; An active pattern is disposed in the first region and includes a first portion and a second portion; A gate electrode that extends in a second direction intersecting the first direction and spans between the first portion and the second portion; A conductive pattern is disposed on the substrate and connected to the first portion, extends in the first direction, and has an end located on the second region; A spacer structure is disposed on the side surface of the conductive pattern and extends along the side surface of the conductive pattern; A buried contact is disposed on the spacer structure in the first region and connected to the second portion; A capacitor structure connected to the buried contact; as well as An edge insulating film is disposed on the spacer structure in the second region. A portion of the spacer structure is located between the substrate and the edge insulating film.

12. The semiconductor memory device according to claim 11, wherein, The edge insulating film includes seams spaced apart from the spacer structure.

13. The semiconductor memory device according to claim 11, wherein, The spacer structure includes a first side spacer and a second side spacer sequentially stacked on the side surfaces of the conductive pattern. A portion of the second side spacer extends along the upper surface of the substrate in the second region to be disposed between the substrate and the edge insulating film.

14. The semiconductor memory device according to claim 13, wherein, The buried contact extends through another portion of the second side spacer in the first region to connect to the second portion.

15. The semiconductor memory device according to claim 13, wherein, The first side spacer includes a silicon oxide film. The second side spacer includes a silicon nitride film.

16. A semiconductor memory device, the semiconductor memory device comprising: A substrate, the substrate including a cell region and a peripheral region surrounding the cell region, wherein the cell region includes a first region and a second region located in a first direction between the first region and the peripheral region; An active pattern is disposed in the first region and includes a first portion and a second portion; A gate electrode that extends in a second direction intersecting the first direction and spans between the first portion and the second portion; A first conductive line is disposed on the substrate, connected to the first portion, and extends in the first direction; A second conductive line is disposed on the substrate, extends in the first direction, and is spaced apart from the first conductive line in the second direction; A buried contact is disposed between the first conductor and the second conductor and connected to the second portion; A capacitor structure, the capacitor structure being connected to the buried contact; and An edge insulating film is disposed on the second region. The first wire includes: A first line portion, the first line portion being disposed on the first region; and A first edge portion, which is disposed on the second region and has the end of the first wire, The second conductor includes: The second line portion is disposed on the first region; and A second edge portion, disposed on the second region, having the end of the second conductor, and protruding beyond the first edge portion toward the peripheral region. The edge insulating film includes: A first filling portion, the first filling portion being located between the first edge portion and the second edge portion in the second direction; and The second filling portion overlaps with the first edge portion in the first direction and overlaps with the second edge portion in the second direction.

17. The semiconductor memory device according to claim 16, wherein, The edge insulating film includes a seam extending in the first filling portion along the first direction and in the second filling portion along the first direction.

18. The semiconductor memory device of claim 16, wherein, The second edge portion includes: The extension portion overlaps with the first filling portion in the second direction; and The extended portion overlaps with the second filling portion in the second direction; Wherein, the width of the extended portion in the second direction is greater than the width of the extended portion in the second direction.

19. The semiconductor memory device of claim 18, further comprising a contact plug in contact with the extension portion.

20. The semiconductor memory device according to claim 16, wherein, The edge insulating film is an integral component.

Images