Semiconductor device and method of manufacturing the same

Abstract

According to the semiconductor device, the manufacturing method of the semiconductor device and the provided manufacturing method of the semiconductor device, a dielectric structure containing an air gap is arranged between adjacent bit line structures, and the dielectric constant (k is approximately equal to 1) of air far lower than that of a traditional solid insulating material is utilized, so that stray capacitance between the bit line structures can be greatly reduced. The effective reduction of the parasitic capacitance can reduce the signal crosstalk between the bit line structures, reduce the RC delay, and increase the sensing margins of the device, thereby improving the speed and accuracy of data reading and writing, reducing the power consumption, and enhancing the overall performance and reliability of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] The current global data volume is growing exponentially, creating continuous demands for upgrades in storage density and read / write speeds for Dynamic Random Access Memory (DRAM). To continue the evolution of integration revealed by Moore's Law, the industry generally regards process node miniaturization as a core strategy. However, as feature sizes approach physical limits, traditional two-dimensional planar DRAM architectures experience diminishing marginal returns in performance, power consumption, and cost.

[0003] Currently, mainstream DRAM products still widely adopt the 6F² cell architecture, with the Buried Channel Array Transistor (BCAT) structure as a typical implementation. In this two-dimensional layout, each memory cell includes one access transistor and one capacitor: the bit line (BL) is formed on the source side of the transistor, and the memory node capacitor (Cap) is formed on the drain side. As process nodes continue to shrink, scaling down the 6F² BCAT architecture proportionally becomes increasingly difficult, and further reduction in cell area has led to a series of performance degradations.

[0004] To overcome the limitations of the 6F² cell architecture, the 4F² architecture cell was explored, but its performance still needs further improvement. Summary of the Invention

[0005] The problem solved by the present invention is to provide a semiconductor device and a method for manufacturing the same, which reduces parasitic effects and improves the reliability of the semiconductor device.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate having a first side and a second side facing away from each other; the semiconductor substrate including a device layer located on the first side; the device layer having an insulating isolator and an array of transistors formed therein; the sources of the transistors being separated by the insulating isolator; the sources and the insulating isolator being distributed on a surface of the device layer near the first side; performing a first etching on the insulating isolator to form a first groove on the first side, the bottom surface of the first groove exposing the remaining insulating isolator; forming a dielectric material layer on the first side of the semiconductor substrate; the dielectric material layer including a plurality of dielectric structures containing air gaps and a second groove located between the dielectric structures; the second groove exposing corresponding regions of the plurality of sources; in a projection from the first side to the second side, the plurality of dielectric structures overlapping the first groove; and filling the second groove with a conductive material to form a bit line structure electrically connected to the sources.

[0007] Optionally, the step of providing a semiconductor substrate includes: providing a device wafer, the device wafer including a third side and a fourth side opposite to each other, the device wafer including a wafer device layer located on the third side and a wafer substrate located on the fourth side, the wafer device layer having a wafer insulating spacer and an array of wafer transistors formed therein, the sources of the wafer transistors being separated by the wafer insulating spacer, the sources of the wafer transistors and the wafer insulating spacer being distributed on the surface of the wafer device layer near the wafer substrate; providing a carrier wafer, bonding the carrier wafer to the third side of the device wafer; thinning the device wafer from the fourth side to expose the wafer insulating spacer; wherein the insulating spacer includes the remaining wafer insulating spacer, the source of the transistor includes the source of the wafer transistor, the semiconductor substrate including the remaining device wafer and the carrier wafer, the carrier wafer being located on the second side.

[0008] Optionally, in the step of providing the device wafer, the depth of the wafer insulating spacer extending into the wafer substrate is greater than that of the source of the wafer transistor; the step of thinning the device wafer from the fourth side to expose the wafer insulating spacer includes removing a portion of the thickness of the wafer insulating spacer, and retaining a portion of the wafer substrate at the top of the source of the wafer transistor, the source of the transistor also including the portion of the wafer substrate.

[0009] Optionally, before forming the bit line structure, the wafer substrate of the specified thickness is doped, and the type of doping is the same as that of the source of the wafer transistor.

[0010] Optionally, the first etching step includes back etching; or the step of performing the first etching on the insulating isolator to form a first groove on the first side includes: forming a first photoresist layer on the surface of the device layer near the first side, exposing and developing the first photoresist layer to form a patterned first photoresist layer, performing the first etching using the patterned first photoresist layer as a mask, the first groove including a plurality of sub-grooves distributed along the first side surface of the semiconductor substrate; in the step of forming a dielectric material layer on the first side of the semiconductor substrate, in the projection from the first side to the second side, the sub-grooves overlap the dielectric structure one-to-one.

[0011] Optionally, the step of forming a dielectric structure including an air gap on the semiconductor substrate includes: after forming the first groove, sequentially forming an insulating dielectric layer and a patterned mask layer on the surface of the first side of the semiconductor substrate, and performing a second etching on the insulating dielectric layer using the patterned mask layer as a mask to form the dielectric structure.

[0012] Optionally, the step of forming the insulating dielectric layer includes: conformally forming an etch stop layer on a first side of the device layer, the thickness of the etch stop layer being less than the depth of the first groove; forming a first insulating layer with a flat top on the surface of the etch stop layer; forming a liner on the first insulating layer; patterning the liner and the first insulating layer with the etch stop layer as the endpoint to form an initial opening; laterally etching the first insulating layer on the sidewall of the initial opening to form the initial opening as an opening with a concave profile; and forming a second insulating layer containing an air gap in the opening; the insulating dielectric layer includes the etch stop layer, the patterned first insulating layer, the patterned liner, and the second insulating layer.

[0013] Optionally, in the step of laterally etching the first insulating layer of the initial opening sidewall to form an opening with a concave profile, the lateral dimension of the longitudinal middle section of the opening is greater than the lateral dimension of the top of the opening.

[0014] Optionally, the first insulating layer and the second insulating layer are made of the same material.

[0015] Optionally, the step of forming the insulating dielectric layer further includes: forming a hard mask layer on the second insulating layer; the step of filling the second groove with conductive material to form a bit line structure electrically connected to the source includes: filling the second groove with excess conductive material and planarizing it with the patterned hard mask layer as a stop layer, and the remaining conductive material in the second groove forming the bit line structure.

[0016] Optionally, the step of performing a second etching on the insulating dielectric layer using the patterned mask layer as a mask to form the dielectric structure includes forming a second photoresist layer on the insulating dielectric layer and exposing and developing the second photoresist layer to form the patterned mask layer; wherein the photomask used for exposing and developing the first photoresist layer is the same as the photomask used for exposing and developing the second photoresist layer, and the first photoresist layer and the second photoresist layer are respectively a positive photoresist and a negative photoresist.

[0017] Optionally, in the step of providing the semiconductor substrate, the transistor further includes a channel region disposed on the second side of the source, a drain disposed on the side of the channel region away from the source, a gate insulating layer disposed on the surface of the channel region, and a gate disposed on the gate insulating layer away from the channel region; in the step of providing the semiconductor substrate, the semiconductor device further includes a word line structure, the word line structure being electrically connected to the gates of the plurality of transistors, and the word line structure being formed in the insulating isolator.

[0018] This invention also provides a semiconductor device formed using the manufacturing method of the semiconductor device.

[0019] This invention also provides a semiconductor device, comprising: a device layer and a wiring layer, the device layer having a first side and a second side facing away from each other, the wiring layer being located on the first side of the device layer; an insulating isolator and an array of transistors formed in the device layer, the sources of the transistors being separated by the insulating isolator, the sources and the insulating isolator being distributed on the surface of the device layer near the first side; the wiring layer including a plurality of bit line structures and a plurality of dielectric structures including air gaps, the bit line structures being located on and electrically connected to the plurality of sources, the dielectric structures having the same extension direction as the bit line structures, and the dielectric structures and the bit line structures being alternately arranged along the surface of the first side of the device layer; wherein, the insulating isolator is in contact with the dielectric structure, with the lateral direction being parallel to the device layer and perpendicular to the extension direction of the bit line structure, the end of the dielectric structure near the insulating isolator overlapping the lateral projection of the end of the source near the bit line structure.

[0020] Optionally, the source includes a contact layer that contacts the bit line structure, the contact layer including a doped semiconductor layer.

[0021] Optionally, the surface of the insulating isolator is flat; or the surface of the insulating isolator is formed with grooves, and the dielectric structures are embedded in the grooves one by one.

[0022] Optionally, the dielectric structure includes a first dielectric layer and a second dielectric layer, the second dielectric layer being located on the side of the first dielectric layer near the insulating isolator, the thickness of the second dielectric layer being less than the depth of the groove, the first dielectric layer and the second dielectric layer coinciding in a projection from the first side to the second side, and the first dielectric layer including the air gap.

[0023] Optionally, the insulating isolator has a groove formed on its surface, and the dielectric structure is embedded in the groove; the second dielectric layer includes a first portion located on the bottom surface of the groove and a second portion located on the sidewall of the groove.

[0024] Optionally, in the projection from the first side to the second side, the dielectric structure coincides with the groove; the second portion of the second dielectric layer is further away from the device layer than the source electrode.

[0025] Optionally, the dielectric structure includes a first dielectric layer and a third dielectric layer, the third dielectric layer being located on the side of the first dielectric layer away from the insulating isolator, the first dielectric layer and the third dielectric layer coinciding in a projection from the first side to the second side, the first dielectric layer including the air gap; the surface of the bit line structure away from the device layer is flush with the surface of the third dielectric layer away from the device layer.

[0026] Optionally, the transistor further includes a channel region disposed on the second side of the source, a drain disposed on the side of the channel region away from the source, a gate insulating layer disposed on the surface of the channel region, and a gate disposed on the gate insulating layer away from the channel region; the semiconductor device further includes a word line structure electrically connected to the gates of the plurality of transistors, the word line structure being located in the insulating isolation member.

[0027] Compared with the prior art, the technical solution of the present invention has the following advantages: The semiconductor device manufacturing method provided in this embodiment of the invention provides a semiconductor substrate having a first side and a second side facing away from each other. The semiconductor substrate includes a device layer located on the first side, in which an insulating isolator and an array of transistors are formed. The sources of the transistors are separated by the insulating isolator, and the sources and the insulating isolator are distributed on the surface of the device layer near the first side. Then, a first groove is formed on the first side by performing a first etching on the insulating isolator, and then a plurality of dielectric structures containing air gaps are formed on the first groove. The corresponding region of the source is exposed by a second groove between the dielectric structures. Subsequently, conductive material is filled in the second groove to form a bit line structure electrically connected to the source. The semiconductor device manufacturing method provided in this embodiment of the invention increases the proportion of air gaps in the portion of the dielectric structure located between the bit line structures by setting dielectric structures containing air gaps between adjacent bit line structures. Air has a much lower dielectric constant than conventional solid insulating materials (k≈1), and the first groove causes the end of the dielectric structure near the insulating isolator to overlap with the projection of the source in the lateral direction, thereby greatly reducing the parasitic capacitance between the bit line structures. Effective reduction of parasitic capacitance can reduce signal crosstalk between bit line structures, reduce RC (resistance-capacitance) delay, and increase the sensing margin of the device, thereby improving the speed and accuracy of data reading and writing, reducing power consumption, and enhancing the overall performance and reliability of semiconductor devices.

[0028] The semiconductor device provided in this invention comprises multiple bit line structures extending in the same direction and arranged alternately, and multiple dielectric structures containing air gaps, in the wiring layer. By introducing dielectric structures containing air gaps between adjacent bit line structures, the low dielectric constant (k≈1) of air is utilized to significantly reduce the parasitic capacitance between the bit line structures. This helps to reduce the RC delay of signal transmission, thereby improving the operating speed of the device. On the other hand, for devices such as memory, it can effectively increase the signal difference during cell read operations, thereby improving the sensing margin and enhancing the reliability and accuracy of data reading. Furthermore, the dielectric structure is in contact with the underlying insulating isolator, and in the lateral direction, the projections of the ends of the dielectric structure and the ends of the source overlap. Therefore, the dielectric structure containing air gaps can have larger air gaps, which can more effectively constrain the electric field, suppress the fringing effect of the electric field and the signal crosstalk between adjacent bit line structures, thereby maximizing the effect of air gaps in reducing parasitic capacitance. Attached Figure Description

[0029] Figures 1 to 17This is a schematic diagram of the structure of each step in the manufacturing method of the semiconductor device according to an embodiment of the present invention; Figure 18 and Figure 19 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0030] As the background technology indicates, the 4F² architecture cell is key to the current pursuit of high integration in memory technology, but its performance still needs further improvement. In traditional planar or front-side interconnect architectures, bit lines (BLs) and word lines (WLs) are typically formed on the same side of the wafer. As cell size approaches the 4F² limit, the bit line pitch is drastically compressed, leading to a sharp increase in parasitic capacitance between bit lines. This high capacitance causes serious problems such as crosstalk, RC delay, and deterioration of the sensing margin, becoming a major bottleneck limiting device speed, power consumption, and reliability. Therefore, existing technologies urgently need a solution that can effectively suppress parasitic effects and improve the reliability of semiconductor devices while achieving high 4F² density.

[0031] To address the technical problem, the semiconductor device manufacturing method provided in this embodiment of the invention provides a semiconductor substrate having a first side and a second side facing away from each other. The semiconductor substrate includes a device layer located on the first side, in which insulating isolators and an array of transistors are formed. The sources of the transistors are separated by the insulating isolators, and the sources and insulating isolators are distributed on the surface of the device layer near the first side. Then, a first groove is formed on the first side by performing a first etching on the insulating isolators, and then a plurality of dielectric structures containing air gaps are formed on the first groove. The corresponding region of the source is exposed by a second groove between the dielectric structures. Subsequently, conductive material is filled in the second groove to form a bit line structure electrically connected to the source. The semiconductor device manufacturing method provided in this embodiment of the invention increases the proportion of air gaps in the portion of the dielectric structure located between the bit line structures by setting dielectric structures containing air gaps between adjacent bit line structures, and by using the first groove to make the end of the dielectric structure near the insulating isolator overlap with the projection of the source in the lateral direction. By utilizing the fact that the dielectric constant of air is much lower than that of conventional solid insulating materials (k≈1), the parasitic capacitance between the bit line structures can be greatly reduced. Effective reduction of parasitic capacitance can reduce signal crosstalk between bit line structures, reduce RC delay, and increase the sensing margin of the device, thereby improving the speed and accuracy of data reading and writing, reducing power consumption, and enhancing the overall performance and reliability of semiconductor devices.

[0032] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] Accordingly, the present invention provides a method for manufacturing a semiconductor device. Figures 1 to 17 This is a schematic diagram of the structure corresponding to the key steps in the semiconductor device manufacturing method of the present invention.

[0034] refer to Figures 1 to 4 Provides a semiconductor substrate 100 (such as...) Figure 4 As shown), the semiconductor substrate 100 has a first side 100A and a second side 100B facing away from each other. The semiconductor substrate 100 includes a device layer 101 located on the first side 100A. An insulating isolator 1011 and an array of transistors are formed in the device layer 101. The source 1012 of the transistors is separated by the insulating isolator 1011. The source 1012 and the insulating isolator 1011 are distributed on the surface of the device layer 101 near the first side 100A. Specifically, with the direction from the first side 100A to the second side 100B as the longitudinal direction, multiple source electrodes 1012 are arrayed on a plane perpendicular to the longitudinal direction. Insulating isolation members 1011 are located between adjacent source electrodes 1012 to separate the source electrodes 1012. The source electrodes 1012 and the insulating isolation members 1011 are interconnected on the surface of the first side 100A to jointly form the surface of the device layer 101 near the first side 100A, so that the source electrodes 1012 and the insulating isolation members 1011 are distributed on the surface of the device layer 101 near the first side 100A.

[0035] The semiconductor substrate 100 is a substrate with completed front-end-of-line (FEOL) processes, including a pre-fabricated device layer 101. That is, the device layer 101, which includes the active region of the transistor (including the source 1012) and the isolation structure (including the insulating isolation member 1011), is pre-constructed to prepare for the subsequent bit line structure 105 process formed from the first side 100A of the semiconductor substrate 100. Therefore, the structure of the semiconductor substrate 100 is the starting point for subsequent processing on the first side 100A of the semiconductor substrate 100, so that subsequent processes can be directly operated on the source 1012 and the insulating isolation member 1011.

[0036] The insulating isolator 1011 is used to isolate the source 1012 in an adjacent transistor. As an example, the insulating isolator 1011 includes a shallow trench isolation structure (STI).

[0037] As an example, the top surface of the insulating spacer 1011 on the first side 100A may be flush with the surface of the device layer 101.

[0038] In some embodiments, the insulating separator 1011 is made of silicon oxide. Silicon oxide is a dielectric material that is simple to manufacture and has low cost, and it has good process compatibility.

[0039] In some embodiments, during the step of providing the semiconductor substrate 100, an array of vertical channel transistors (VCTs) is integrated within the device layer 101. As an example, the vertical channel transistor is used in a 1T1C (1 Transistor 1 Capacitor) DRAM structure, where its source is connected to the bit line structure, its gate is connected to the word line structure, and its drain is connected to the capacitor.

[0040] The transistors are arranged in an array, and the source 1012 of each transistor is formed on the surface of the device layer 101 near the first side 100A, so that the bit line structure 105 formed later can be electrically connected to the source 1012 of a row of transistors. Thus, the bit line structure 105 can serve as a signal line shared by a row of transistors, used to simultaneously access or sense an entire row of memory cells, which is the basis for realizing the addressing function of the memory array.

[0041] It should be noted that in the step of providing the semiconductor substrate 100, the transistor also includes a channel region 1013 disposed on the second side 100B of the source 1012, a drain 1014 disposed on the side of the channel region 1013 away from the source 1012, a gate insulating layer (not shown in the figure) disposed on the surface of the channel region 1013, and a gate (not shown in the figure) disposed on the gate insulating layer away from the channel region 1013.

[0042] The gate, gate insulating layer, channel region 1013, source 1012, and drain 1014 together constitute the gate transistor of the memory cell. In memory cells such as DRAM, this transistor acts as an access device, controlling the conduction state of the channel region 1013 by applying a voltage to the gate structure, thereby selectively connecting or disconnecting the charge path between the bit line and the storage capacitor (usually electrically connected to the drain 1014), realizing data writing and reading operations for specific memory cells.

[0043] Specifically, the transistor in device layer 101 is a vertical channel transistor (VCT). From the second side 100B of the semiconductor substrate 100 towards the first side 100A, the drain 1014 is located at the bottom of the transistor; the channel region 1013 is located above the drain 1014, serving as a channel for carrier flow, and may include cylindrical or prismatic semiconductor pillars; a gate insulating layer and a gate at least partially surround the sidewalls of the channel region 1013. The gate insulating layer electrically isolates the gate from the channel region 1013, and the gate controls the on / off state of the channel region 1013 by applying a voltage; the source 1012 is located above the channel region 1013 and is the top layer of the transistor, used for connection to the subsequently formed bit line structure 105.

[0044] It should also be noted that, in the step of providing the semiconductor substrate 100, the semiconductor substrate 100 further includes a plurality of word line structures 1015, which are electrically connected to the gates of a plurality of transistors, for example, electrically connected to the gates of a row of transistors. The word line structures 1015 are formed in the insulating isolation member 1011. It should be noted that the electrical connection between the word line structures 1015 and the gates of the plurality of transistors includes either the word line structures 1015 and the gates of the plurality of transistors being formed integrally and electrically connected, or the two being fabricated separately and electrically connected.

[0045] Word line structures 1015 are formed in insulating isolation member 1011 and electrically connected to the gates of multiple transistors (e.g., a row of transistors in an array). Thus, multiple word line structures 1015 constitute the gate control structure of a vertical channel transistor (VCT) array. Integrating word line structures 1015 inside device layer 101 improves the integration of semiconductor devices. Furthermore, the bit line structures are located outside device layer 101, resulting in a larger spacing between the bit line structures and word line structures, which can avoid crosstalk and coupling.

[0046] Specifically, the step of providing the semiconductor substrate 100 includes: as follows Figure 1 As shown, a device wafer 106 is provided, which includes a third side 106A and a fourth side 106B opposite to each other. The device wafer 106 includes a wafer device layer 1061 located on the third side 106A and a wafer substrate 1062 located on the fourth side 106B. A wafer insulating spacer 1061a and an array of wafer transistors are formed in the wafer device layer 1061. The source 1061b of the wafer transistors is separated by the wafer insulating spacer 1061a. The source 1061b of the wafer transistors and the wafer insulating spacer 1061a are distributed on the surface of the wafer device layer 1061 near the wafer substrate 1062. Figure 2 The diagram shows a carrier wafer 114 bonded to a third side 106A of a device wafer 106, and the device wafer 106 thinned from a fourth side 106B to expose a wafer insulating spacer 1061a.

[0047] By bonding the carrier wafer 114 to the third side 106A of the device wafer 106, the wafer device layer 1061 is transferred onto the carrier wafer 114 and flipped, thereby exposing the wafer substrate 1062 of the fourth side 106B of the device wafer 106. The wafer substrate 1062 of the fourth side 106B of the device wafer 106 is then thinned, achieving thinning of the device wafer 106 from the fourth side 106B. Therefore, without damaging the wafer transistors in the wafer device layer 1061 already formed on the third side 106A of the device wafer 106, the wafer insulating spacer 1061a in the wafer device layer 1061 is exposed from the back side, and the wafer transistor source 1061b is close to the back side, which is beneficial for the subsequent formation of the bit line structure 105 on the first side 100A of the semiconductor substrate 100.

[0048] In some embodiments, the carrier wafer 114 includes a substrate of semiconductor material, such as a silicon wafer, for providing mechanical support during subsequent semiconductor device fabrication. In other embodiments, the carrier wafer 114 may also include a substrate of insulating material, such as a glass sheet.

[0049] In some embodiments, the carrier wafer 114 and the device wafer 106 with the third side 106A of the wafer device layer 1061 formed thereon are bonded together by wafer-on-wafer bonding technology, which can realize large-area, high-quality integration of heterogeneous or homogeneous materials and provide solid mechanical support for subsequent back-side thinning and processing.

[0050] In some embodiments, after the carrier wafer 114 is bonded to the third side 106A of the device wafer 106, the assembly of the carrier wafer 114 and the device wafer 106 is flipped. Thinning techniques such as etching, grinding, or chemical mechanical polishing (CMP) are used to thin the wafer substrate 1062 from the fourth side 106B (i.e., the wafer substrate 1062 side) until most of the wafer substrate 1062 is removed, exposing the wafer insulating spacer 1061a in the wafer device layer 1061 from the direction of the fourth side 106B. Because the wafer insulating spacer 1061a is made of a different material than the wafer substrate 1062, it exhibits a different removal rate during the thinning process and can serve as a stop layer for the thinning process.

[0051] Thus, the insulating isolator 1011 includes the remaining wafer insulating isolator 1061a, the source of the transistor 1012 includes the source of the wafer transistor 1061b, and the semiconductor substrate 100 includes the remaining device wafer 106 and the carrier wafer 114, the carrier wafer 114 being located on the second side 100B.

[0052] In some embodiments, in the step of providing the device wafer, the depth of the wafer insulating spacer 1061a extending into the wafer substrate 1062 is greater than that of the source 1061b of the wafer transistor. The step of thinning the device wafer 106 from the fourth side 106B to expose the wafer insulating spacer 1061a includes removing a portion of the thickness of the wafer insulating spacer 1061a, and retaining a portion of the thickness of the wafer substrate 1062 on top of the source 1061b of the wafer transistor. The source 1012 of the transistor also includes a portion of the thickness of the wafer substrate 1063.

[0053] However, this is not the only one. In some embodiments, the step of thinning the device wafer 106 from the fourth side 106B to expose the wafer insulating spacer 1061a includes exposing the source 1061b of the wafer transistor and removing the wafer substrate 1063 of a certain thickness.

[0054] It is understood that a partially thick wafer substrate 1063 located on top of the source 1061b of the wafer transistor, when its doping type is the same as that of the source 1061b of the wafer transistor and its doping concentration is high, can be directly formed as part of the source 1012 of the transistor. When its doping type is opposite to that of the source 1061b of the wafer transistor, and it is undoped or shallowly doped, it can be formed as part of the source 1012 of the transistor through subsequent doping process steps.

[0055] The depth to which the wafer insulating isolation member 1061a extends into the wafer substrate 1062 is greater than that of the source 1061b of the wafer transistor. That is, the end of the wafer insulating member 1061a in the device wafer 106 near the fourth side 106B is closer to the fourth side than the end of the source 1061b of the wafer transistor near the fourth side 106B. By extending the wafer insulating isolator 1061a to a depth greater than that of the source 1061b of the wafer transistor, the endpoint control margin for thinning the wafer substrate 1062 can be improved. Specifically, during the exposure of the wafer insulating isolator 1061a, a portion of its thickness can be removed, thereby reducing the difficulty of the thinning process. Simultaneously, a portion of the wafer substrate 1063 is retained above the source 1061b of the wafer transistor. This retained portion of the wafer substrate 1063 protects the source 1061b of the underlying wafer transistor during thinning, preventing damage. It also forms the contact layer between the source 1012 of the transistor and the bit line structure 105, reducing the contact resistance between the subsequently formed bit line structure 105 and the source 1012, which is beneficial for forming a low-resistance ohmic contact. Furthermore, the insulating isolator 1011 can also achieve isolation between the sources 1012 of the transistor.

[0056] It should be noted that when using processes such as chemical mechanical polishing (CMP) for thinning, different polishing selectivity ratios are utilized between the wafer insulating isolator 1061a and the wafer substrate 1062. When polishing reaches the top of the wafer insulating isolator 1061a, the polishing rate changes. By monitoring this change or setting a fixed polishing time, the accuracy of stopping the thinning can be improved.

[0057] As an example, the material of the wafer substrate 1062 includes silicon, and the material of the wafer insulating spacer 1061a includes silicon oxide. During the thinning process of the wafer substrate 1062, because the material properties of silicon and silicon oxide are different, the material removal rates of silicon and silicon oxide are inconsistent, which allows the wafer insulating spacer 1061a to serve as a stop layer for the thinning process.

[0058] As an example, in the step of providing device wafer 106, wafer substrate 1062 is P-type doped and the source 1061b of wafer transistor is N-type doped.

[0059] In the step of providing semiconductor substrate 100, semiconductor substrate 100 includes remaining device wafer 106 and carrier wafer 114, carrier wafer 114 being located on second side 100B; insulating isolation member 1011 in the step of providing semiconductor substrate 100 includes remaining wafer insulating isolation member 1061a, and the source of transistor 1012 includes the source of wafer transistor 1061b.

[0060] refer to Figure 5 The insulating spacer 1011 is etched first to form a first groove 102 on the first side 100A, the bottom surface of the first groove 102 exposing the remaining insulating spacer 1011.

[0061] By performing a first etching on the insulating isolator 1011 to form a first groove 102, a predetermined physical space is provided for the subsequent deposition of the dielectric material layer. This allows a dielectric structure 103 containing air gaps to be formed within the first groove 102, providing a spatial basis for the final formation of a low dielectric constant insulating structure between adjacent bit line structures 105. This increases the length of the air gap extending in the direction from the first side 100A to the second side 100B, and increases the proportion of air gaps in the portion of the dielectric structure 103 located between the bit lines, which helps to reduce the parasitic capacitance between the bit line structures 105 in the final semiconductor device.

[0062] In some embodiments, the first etching step includes back etching. The back etching process can directly etch the insulating spacer 1011 without forming an additional etching mask layer, and can effectively control the recess depth of the first groove 102, forming a first groove 102 with high depth uniformity. Therefore, it provides a flat and consistent bottom structure foundation for the subsequent deposition of dielectric material layers, simplifying the process flow.

[0063] Specifically, during the etching process, an anisotropic dry etching process is employed to etch the insulating isolator 1011 longitudinally. By selecting a specific etching gas, an etching selectivity ratio can be maintained between the insulating isolator 1011 and the source electrode 1012 of the transistor during anisotropic dry etching, avoiding significant damage to the source electrode 1012 of the transistor caused by the anisotropic dry etching process. Furthermore, the etching depth of the insulating isolator 1011 can be precisely controlled, removing only a portion of the thickness of the insulating isolator 1011 without completely penetrating it. After etching is completed, a groove structure with a specific depth, namely the first groove 102, is formed in the insulating isolator 1011. The bottom surface of the first groove 102 exposes the remaining insulating isolator, and the sidewalls of the first groove 102 expose the sidewalls of the source electrode 1012.

[0064] For example, the bottom surface of the first recess 102 overlaps with the source 1012 in its lateral (perpendicular to the longitudinal) projection. In some embodiments, the bottom of the first recess 102 is flush with the top of the source 1061b of the wafer transistor (e.g., Figure 5 (As shown). However, in other embodiments, by controlling the thickness of the material removed by the insulating isolator 1011, the bottom of the first groove 102 can be made higher than the top of the source 1061b of the wafer transistor, or the bottom of the first groove 102 can be lower than the top of the source 1061b of the wafer transistor.

[0065] In other embodiments, the step of performing a first etching on the insulating isolator 1011 to form a first groove 102 on the first side 100A may further include: forming a first photoresist layer on the surface of the device layer 101 near the first side 100A; exposing and developing the first photoresist layer to form a patterned first photoresist layer; and performing a first etching using the patterned first photoresist layer as a mask. The first groove 102 includes a plurality of sub-grooves 102a distributed along the surface of the semiconductor substrate 100 on the first side 100A. Correspondingly, in the subsequent step of forming a dielectric material layer on the first side 100A of the semiconductor substrate 100, in the projection from the first side 100A to the second side 100B, the sub-grooves 102a overlap with the dielectric structure 103 in a one-to-one correspondence.

[0066] The first etching is performed by forming a patterned first photoresist layer as a mask through photolithography, thereby precisely defining the position and size of the first groove 102 and the sub-groove 102a. Since the first groove 102 is formed in the insulating isolator 1011, the first groove 102 overlaps with the dielectric structure 103 to be formed later in the projection, providing a positioning reference for the dielectric structure 103 with air gap.

[0067] In one example, sub-grooves 102a extend along the column direction, and multiple sub-grooves 102a are parallel to each other and spaced apart along the surface plane of device layer 101. The sub-grooves 102a are located between the sources 1012 of two adjacent columns of transistors. The width of the sub-grooves 102a can be greater than, equal to, or less than the width of the gap between the sources 1012 of two adjacent columns of transistors. The bottom surface of the sub-grooves 102a exposes the remaining insulating spacer 1011, and the sidewalls of the sub-grooves 102a expose the remaining insulating spacer 1011. When the width of the sub-grooves 102a is greater than the width of the gap between the sources 1012 of two adjacent columns of transistors, the sidewalls of the sub-grooves 102a also expose the sidewalls of the sources 1012 of the transistors.

[0068] Specifically, on the first side 100A of the device layer 101, a first photoresist layer (e.g., positive photoresist) is first coated using a spin-coating process. Next, a first photomask is used to selectively expose the first photoresist layer using an exposure device. The pattern of the first photomask is designed to be transparent in areas corresponding to the first groove 102, while areas outside the first groove 102 are opaque. After exposure and development, a patterned first photoresist layer is left on the first side 100A of the device layer 101. Then, using this patterned first photoresist layer as a mask, an anisotropic dry etching process is used to etch the insulating spacer 1011, forming a first groove 102 in the insulating spacer 1011 whose position and size are determined by the pattern of the first photomask.

[0069] It should be noted that before spin-coating the first photoresist layer on the first side 100A of the device layer 101, a first bottom anti-reflective coating can be formed on the first side 100A of the device layer 101 to reduce reflection and improve photolithography quality. The first bottom anti-reflective coating may include a silicon-containing bottom anti-reflective coating (Si-BARC).

[0070] refer to Figures 6 to 16A dielectric material layer is formed on a first side 100A of a semiconductor substrate 100. The dielectric material layer includes a plurality of dielectric structures 103 with air gaps, and a second groove 104 located between the dielectric structures 103. The second groove 104 exposes corresponding regions of a plurality of sources 1012. In a projection from the first side 100A to the second side 100B, the plurality of dielectric structures 103 overlap with the first groove 102. It should be noted that the second groove 104 exposing the corresponding regions of the plurality of sources 1012 includes: the second groove 104 exposing the plurality of sources 1012 in the corresponding regions. For example, the corresponding regions of the plurality of sources 1012 are formed as strip regions extending along the column direction. The arrayed sources 1012, i.e., the plurality of sources 1012 are distributed in an array along rows and columns, and the strip region at least partially overlaps with the longitudinal projection of a column of sources 1012 in the arrayed distribution. It should also be noted that the entirety of the plurality of dielectric structures 103 overlaps with the first groove 102, that is, at least one dielectric structure 103 overlaps with the first groove 102. Thus, the air gap in the dielectric structure 103 can be extended in the direction from the first side 100A to the second side 100B through the first groove 102, thereby increasing the volume of the air gap in the dielectric structure 103 and increasing the proportion of the air gap in the part of the dielectric structure 103 located between the bit lines.

[0071] In this embodiment of the invention, a first etching is performed on the insulating isolator 1011 to form a first groove 102 on the first side 100A. Then, a dielectric structure 103 containing an air gap is formed on the first groove 102. The corresponding area of ​​the source electrode 1012 is exposed by the second groove 104 between the dielectric structures 103. Subsequently, conductive material is filled in the second groove 104 to form a bit line structure 105 electrically connected to the source electrode 1012. The semiconductor device manufacturing method provided in this embodiment of the invention, by setting a dielectric structure 103 including an air gap between the finally formed adjacent bit line structures 105, and since the dielectric structure 103 is formed on the first groove 102, the air gap in the dielectric structure 103 can extend in the direction from the first side 100A to the second side 100B, thereby increasing the volume of the air gap in the dielectric structure 103 and increasing the proportion of the air gap in the portion of the dielectric structure 103 located between the bit lines. Utilizing the fact that air has a much lower dielectric constant (k≈1) than traditional solid insulating materials, the parasitic capacitance between the bit line structures 105 can be greatly reduced. The effective reduction of parasitic capacitance can reduce signal crosstalk between bit line structures, reduce RC delay, and increase the sensing margin of the device, thereby improving the speed and accuracy of data read / write, reducing power consumption, and enhancing the overall performance and reliability of the semiconductor device.

[0072] In some embodiments, the second groove 104 exposes the source 1012, which includes the source 1061b of the wafer transistor and a wafer substrate 1063 of a partial thickness on the source 1061b. Thus, during the step of forming the dielectric material layer, the formation of the bottom of the second groove 104 does not remove or completely remove the wafer substrate 1063 of that partial thickness, preventing direct exposure of the source 1061b of the wafer transistor. This protects the source of the wafer transistor from etching damage during the formation of the dielectric material layer, and the partial thickness of the wafer substrate 1063 protects the source 1061b of the wafer transistor.

[0073] In some embodiments, the step of forming a dielectric structure 103 including an air gap on a first side 100A of a semiconductor substrate 100 includes: after forming a first groove 102, sequentially forming an insulating dielectric layer 108 (e.g., ...) on the surface of the first side 100A of the semiconductor substrate 100. Figure 6-13 (as shown) and patterned mask layer 109 (as shown) Figure 14 As shown), the patterned mask layer 109 is used as a mask to mask the insulating dielectric layer 108 (e.g. Figure 13 (As shown) Perform a second etching to form dielectric structure 103 (as shown) Figure 15 (as shown) and the second groove 104 (as shown) Figure 15 (As shown).

[0074] By first depositing an insulating dielectric layer 108 and then using a patterned mask layer 109 to perform a second etching on the insulating dielectric layer 108 to form a dielectric structure 103 and a second groove 104, the process of forming the dielectric structure 103 with air gaps and the process of forming the second groove 104 for forming the bit line structure 105 can be combined into one process step, thereby improving process efficiency.

[0075] In some embodiments, the insulating dielectric layer 108 includes an etch stop layer 1081, a patterned first insulating layer 1082, a patterned substrate 1083, and a second insulating layer 1084. The step of forming the insulating dielectric layer 108 includes: conformally forming an etch stop layer 1081 (e.g., on a first side 100A of the device layer 101) on a first side 100A. Figure 6 As shown), the thickness of the etch stop layer 1081 is less than the depth of the first groove 102. A first insulating layer 1082 with a flat top is formed on the surface of the etch stop layer 1081. A liner 1083 is formed on the first insulating layer 1082. The liner 1083 and the first insulating layer 1082 are patterned with the etch stop layer 1081 as the endpoint to form the initial opening 110 (as shown). Figure 10 As shown), the first insulating layer 1082 on the sidewall of the initial opening 110 is laterally etched to form the initial opening 110 into an opening 111 with a concave profile (as shown). Figure 11As shown), a second insulating layer 1084 containing an air gap is formed in the opening 111 (as shown). Figure 12 (As shown).

[0076] As an example, an etch stop layer 1081 is conformally formed on the first side 100A of device layer 101 using a chemical vapor deposition (CVD) process. In other embodiments, an atomic layer deposition (ALD) process can also be used to conformally form the etch stop layer 1081 on the first side 100A of device layer 101.

[0077] Specifically, the etch stop layer 1081 is made of a different material than the first insulating layer 1082. For example, the material of the etch stop layer 1081 includes silicon nitride, which is used to protect the underlying structure (e.g., insulating spacer 1011) of the etch stop layer 1081 in the subsequent step of forming the initial opening.

[0078] The etch stop layer 1081 serves to stop the etching process during the formation of the initial opening 110, protecting the underlying structure. The conformally formed etch stop layer 1081, with a thickness less than the depth of the first groove 102, protects the device layer in subsequent process steps while avoiding occupying too much depth of the first groove 102. This allows the second insulating layer 1084, including the air gap 1084a, formed in subsequent processes to extend further into the device layer 101, reducing coupling between bit line structures 105. It can be understood that the depth of the first groove 102 is the vertical distance between the source 1012 of the transistor on the end face of the first side 100A and the bottom of the first groove 102.

[0079] As an example, a first insulating layer 1082 with a flat top is formed on the surface of the etch stop layer 1081 using a flowable chemical vapor deposition (FCVD) process. To improve the flatness of the top of the first insulating layer 1082, it can also be planarized using processes such as chemical mechanical planarization (CMP). The material of the first insulating layer 1082 includes silicon oxide, which is a dielectric material with simple fabrication processes and low cost, and has good process compatibility.

[0080] As an example, a chemical vapor deposition process is used to form a liner 1083 on top of the first insulating layer 1082. In other embodiments, a physical vapor deposition process can also be used to form the liner 1083 on top of the first insulating layer 1082. Specifically, the first insulating layer 1082 and the liner 1083 are made of different materials; for example, the material of the liner 1083 includes silicon nitride, which is used to form a narrower filling opening in the subsequent step of forming the opening 111 with a concave profile.

[0081] In some embodiments, with the etch stop layer 1081 as the etch stop location, the substrate 1083 and the first insulating layer 1082 are patterned to form an initial opening 110. Specifically, a third photoresist layer 113 (e.g., ...) is coated on the substrate 1083 of the device layer 101 by a spin coating process. Figure 9 (As shown). Then, using a second photomask, the third photoresist layer 113 is selectively exposed and developed using an exposure device, leaving a patterned third photoresist layer 113 on the substrate 1083. The third photoresist layer 113 covers the corresponding position of the source electrode 1012 and exposes the corresponding position of the insulating isolator 1011 outside the corresponding position of the source electrode 1012. Then, using this patterned third photoresist layer 113 as a mask, an anisotropic dry etching process is used to etch the insulating dielectric layer 108 to form the initial opening 110.

[0082] Specifically, the initial opening 110 corresponds one-to-one with the dielectric structure 103, thereby allowing each dielectric structure to have an air gap.

[0083] It should be noted that before spin-coating the third photoresist layer 113 onto the substrate 1083, a third bottom anti-reflective coating 107 can also be formed on the substrate 1083 to reduce the standing wave effect between the photoresist and the underlying film and improve the patterning accuracy. The third bottom anti-reflective coating 107 includes a silicon-containing bottom anti-reflective coating (Si-BARC).

[0084] After forming the initial opening 110, the first insulating layer 1082 on the sidewall of the initial opening 110 is laterally etched to form an opening 111 with a concave profile. This allows for a wider air gap 1084a within the second insulating layer 1084, while maintaining the same sealing difficulty during the deposition of the second insulating layer 1084. This further reduces the dielectric constant of the final dielectric material layer and decreases coupling between bit line structures. The etch stop layer 1081 protects the underlying structure during the lateral etching process.

[0085] In some embodiments, the step of laterally etching the first insulating layer 1082 on the sidewall of the initial opening 110 to form an opening 111 with a concave profile includes a wet etching process.

[0086] The wet etching process has isotropic etching characteristics. By selecting a specific etching solution, the etching rate of the first insulating layer 1082 is greater than that of the substrate 1083 and the etching stop layer 1081, forming an opening 111 with a concave profile.

[0087] Specifically, in the step of laterally etching the first insulating layer of the initial opening sidewall to form an opening with a concave profile, the lateral dimension of the longitudinal middle section of the opening 111 is greater than the lateral dimension of the top of the opening 111.

[0088] During the lateral etching process, the etching rate of the first insulating layer 1082 is much greater than that of the substrate 1083 and the etching stop layer 1081, resulting in a lateral dimension L1 (e.g., in the longitudinal middle section of the opening 111) that is significantly larger than that of the substrate 1083 and the etching stop layer 1081. Figure 11 (As shown) is greater than the lateral dimension L2 of the top of opening 111 (as shown) Figure 11 As shown), that is, an opening 111 with a concave profile is intentionally formed.

[0089] During the formation of the second insulating layer 1084 in the opening 111, a deposition process with poor step coverage can be used to make it easier to form a seal when the second insulating layer 1084 is formed in the opening 111, and an air gap 1084a is wrapped inside the second insulating layer 1084.

[0090] As an example, the step of forming a second insulating layer 1084 containing an air gap 1084a in the opening 111 includes: forming an insulating material layer (not shown) on top of the opening 111 and the liner 1083 using a flowable chemical vapor deposition (FCVD) process. Due to the poor step coverage of the FCVD process, the material of the insulating material layer preferentially closes at the top of the opening 111, resulting in an air gap 1084a in the insulating material layer formed in the opening 111. Using the top of the liner 1083 as the planarization stop position, the insulating material layer is planarized by chemical mechanical polishing (CMP), leaving the remaining insulating material layer in the opening 111 as the second insulating layer 1084.

[0091] In some embodiments, the second insulating layer 1084 and the first insulating layer 1082 are made of the same material. Using the same material for both simplifies the equipment and processes of the deposition process, reduces process changes required due to material differences, and mitigates stress, defects, or electrical instability issues that may arise from material interface mismatch. Therefore, when forming the dielectric structure 103 with the air gap 1084a, material compatibility in the process is improved, making the manufacturing process more stable and contributing to increased reliability and production efficiency of the final product. Furthermore, it reduces the difficulty of the subsequent etching process to form the second groove 104.

[0092] like Figure 14 As shown, the step of performing a second etching on an insulating dielectric layer 108 using a patterned mask layer 109 as a mask to form a dielectric structure 103 includes forming a second photoresist layer (not shown in the figure) on the insulating dielectric layer 108 and exposing and developing the second photoresist layer to form a patterned mask layer 109.

[0093] A patterned second photoresist layer is formed on the insulating dielectric layer 108 as a mask for the second etching, thereby enabling the use of photolithography to define the pattern of the dielectric structure 103 and the second groove 104, so that the position, width and spacing of the formed bit line structure 105 are aligned with the source of the array transistor below.

[0094] Specifically, a second photoresist layer is coated onto the insulating dielectric layer 108 using a spin-coating process, and then exposed using a third photomask. In areas where the second groove 104 needs to be formed (for filling with conductive material to form bitline structures 105), the photomask is opaque, while in areas where it needs to remain as dielectric structures 103, it is transparent. After exposure, a developer is used to remove some of the photoresist, thereby forming a patterned second photoresist layer on the insulating dielectric layer 108. This patterned second photoresist layer serves as a patterning mask layer 109, and in the second etching step, the insulating dielectric layer 108 is etched downwards through the second photoresist layer to form the second groove 104.

[0095] It should be noted that before coating the second photoresist layer on the insulating dielectric layer 108 by spin coating, a second bottom anti-reflective coating 112 is also formed on the insulating dielectric layer 108 to reduce reflection and improve photolithography quality. The second bottom anti-reflective coating 112 includes a silicon-containing bottom anti-reflective coating (Si-BARC).

[0096] In some embodiments, it should be noted that the photomask used for exposing and developing the first photoresist layer is the same as the photomask used for exposing and developing the second photoresist layer, and the first photoresist layer and the second photoresist layer are respectively one of positive photoresist and negative photoresist.

[0097] By using the same set of photomasks for exposing the first and second photoresist layers, but selecting photoresists with opposite properties (positive and negative), two complementary patterns can be generated using a single photomask. This reduces the number of photomasks required in the manufacturing process, simplifies the process flow, and lowers manufacturing costs. Furthermore, an etch stop layer 1081 is conformally formed on the surface of the first side 100A of the device layer 101, such that the etch stop layer 1081 is formed on the sidewall of the first recess 102. By using the same set of photomasks for the first and second photoresist layers, but selecting photoresists with opposite properties (positive and negative), the alignment requirements of the photomask during the exposure of the second photoresist layer can be reduced, avoiding damage to the insulating isolator 1011 by the second etching within a certain alignment deviation range. Correspondingly, the dielectric structure 103 is aligned one-to-one with the sub-recesses 102a in the first recess 102. Alignment means complete overlap.

[0098] It should be noted that the sub-groove 102a extends along the column direction, and the dielectric structure also extends along the column direction. In the projection from the first side 100A to the second side 100B, the sub-groove and the dielectric structure overlap one-to-one.

[0099] As an example, when forming the first groove 102, a positive photoresist is used as the first photoresist layer. The first photomask used has an opaque area corresponding to the corresponding area of ​​the source 1012 (i.e., the bit line structure 105 to be formed), and a transparent area corresponding to the position of the underlying insulating spacer 1011 (i.e., the dielectric structure 103 to be formed). After exposure, the positive photoresist under the transparent area is removed, and the insulating spacer 1011 is etched using the patterned first photoresist layer as a mask to form the first groove 102.

[0100] When forming the second groove 104, a negative photoresist is used as the second photoresist layer, and the third photomask used is exactly the same as the first photomask, or the third photomask reuses the first photomask. During exposure, light still passes through the light-transmitting area of ​​the photomask (corresponding to the position of the dielectric structure 103). For negative photoresist, the exposed area will undergo cross-linking and remain. After development, the photoresist in the unexposed area (corresponding to the position of the bit line structure 105) is removed, and a second etching is performed through the patterned mask layer 109 to form multiple dielectric structures 103 and the second groove 104 located between the dielectric structures 103.

[0101] It should be noted that in the step of etching the insulating dielectric layer 108 using the patterned mask layer 109 as a mask, the formed dielectric structure 103 includes a first dielectric layer 1031 and a second dielectric layer 1032 located between the first dielectric layer 1031 and the insulating isolator 1011, wherein the first dielectric layer 1031 includes an air gap 1084a.

[0102] As an example, when etching the first insulating layer 1082 to form the first dielectric layer 1031, a second insulating layer 1084 is also etched, and the first dielectric layer 1031 includes the remaining second insulating layer 1084; optionally, the first dielectric layer 1031 is formed by etching the first insulating layer 1082, and the first dielectric layer 1031 includes the second insulating layer 1084 and the remaining first insulating layer 1082.

[0103] The second dielectric layer 1032 is formed by etching the etch stop layer 1081. The second dielectric layer 1032 includes the remaining etch stop layer 1081. The thickness of the second dielectric layer 1032 is less than the depth of the first groove 102.

[0104] The second dielectric layer 1032 includes a sub-groove 102a (e.g., ... Figure 5 The first portion of the bottom surface (as shown) and the second portion located on the sidewall of the sub-groove 102a. Since the photomasks used for exposure and development of the first and second photoresist layers are the same, and the first and second photoresist layers are one of positive and negative photoresists respectively, a second dielectric layer 1032 comprising the first portion and the second portion is generated accordingly.

[0105] In some embodiments, the dielectric structure 103 further includes a remaining liner located on the side of the first dielectric layer 1031 away from the device layer 101.

[0106] After the second groove 104 is formed by the second etching, a pre-cleaning step is usually performed first to remove any natural oxide layer or etching residue that may be present in the second groove 104, to ensure that the bit line structure 105 and the source electrode 1012 formed subsequently have good electrical contact.

[0107] refer to Figure 16 and Figure 17 The second groove 104 is filled with conductive material to form a bit line structure 105 electrically connected to the source 1012 (e.g., Figure 17 (As shown).

[0108] The semiconductor device manufacturing method provided in this embodiment of the invention fills the second groove 104 with conductive material to form a bit line structure 105 electrically connected to the source 1012. By setting a dielectric structure 103 including an air gap 1084a between adjacent bit line structures 105, the parasitic capacitance between the bit line structures 105 can be greatly reduced by utilizing the fact that air has a much lower dielectric constant (k≈1) than conventional solid insulating materials. The effective reduction of parasitic capacitance can reduce signal crosstalk between bit line structures, reduce RC delay, and increase the sensing margin of the device, thereby improving the speed and accuracy of data read and write, reducing power consumption, and enhancing the overall performance and reliability of the semiconductor device.

[0109] Furthermore, by filling the second groove 104 with conductive material, a continuous conductive path is formed in the region corresponding to the source 1012, thereby forming a bit line structure 105 that electrically connects to the source 1012 of multiple transistors in the region corresponding to the source 1012. This completes the connection in the memory array for data reading, writing, and addressing, enabling the memory cells to be selected and for data status sensing or writing, which is beneficial for constructing a fully functional dynamic random access memory.

[0110] As an example, the step of filling the second groove 104 with conductive material includes: conformally forming a barrier layer 1051 on the second groove 104 and the dielectric structure 103; filling the barrier layer 1051 and the dielectric structure 103 with a conductive layer 1052; removing the barrier layer 1051 and the conductive layer 1052 above the top of the dielectric structure 103, and the remaining barrier layer 1051 and the conductive layer 1052 in the second groove 104 serve as a bit line structure 105.

[0111] Specifically, the conformal formation of the barrier layer 1051 includes physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes. The material of the barrier layer 1051 includes, but is not limited to, titanium nitride (TiN) or tantalum nitride (TaN). The function of the barrier layer 1051 is to prevent the diffusion of the conductive layer 1052 metal (such as tungsten) into the surrounding medium.

[0112] Specifically, the step of filling the barrier layer 1051 and the dielectric structure 103 with the conductive layer 1052 includes an electrochemical plating process, a physical vapor deposition (PVD) process, or a chemical vapor deposition (CVD) process. The material of the conductive layer 1052 includes tungsten (W).

[0113] In some embodiments, after filling the second groove 104 with conductive material to form a bit line structure 105 electrically connected to the source 1012, the semiconductor device is cleaned to remove residual polishing slurry, metal particles or other contaminants from the planarization process, ensuring the cleanliness of the device surface and preparing for subsequent packaging or other process steps.

[0114] It should be noted that the method for manufacturing a semiconductor device may further include: filling the second recess 104 with conductive material to form a bit line structure 105 electrically connected to the source 1012, and then removing the carrier wafer 114. This allows for the fabrication of other film layer structures on the second side 100B of the device layer 101. For example, a capacitor layer can be formed on the second side of the device layer 101, comprising an array of capacitors, each capacitor being connected to the drain of a transistor in the device layer 101, thereby forming a DRAM memory.

[0115] As an example, methods for removing carrier wafers include mechanical stripping, chemical etching, or laser stripping.

[0116] It should be noted that, as Figure 16 As shown, the method for manufacturing a semiconductor device further includes: before forming the bit line structure 105, doping a portion of the thickness of the wafer substrate 1063, wherein the type of doping is the same as that of the source of the wafer transistor.

[0117] Before forming the bit line structure 105, the exposed portion of the wafer substrate 1063 is doped with the same type of doping as the source of the wafer transistor. This compensates for or dedops any residual substrate doping in the exposed portion of the wafer substrate 1063 and increases the carrier concentration in this region, thereby ensuring a low-resistance ohmic contact between the source 1012 and the subsequently formed bit line structure 105. Therefore, a low-impedance electrical path is provided between the bit line structure 105 and the transistor, reducing signal transmission loss and improving device read / write speed and signal integrity.

[0118] Specifically, a contact layer 1021 is formed by doping a portion of the wafer substrate 1063. The contact layer 1021 acts as a bridge connecting the source of the wafer transistor and the bit line structure 105, reducing the low-resistance ohmic contact between the source 1012 and the subsequently formed bit line structure 105.

[0119] In some embodiments, the doping step of a portion of the wafer substrate 1063 includes an ion implantation process. The implanted ion type is the same as the doping type of the source of the wafer transistor; for example, if the source of the wafer transistor is N-type, an N-type dopant (such as phosphorus or arsenic) is implanted. If P-type doping is present in the portion of the wafer substrate 1063, the implanted N-type impurity neutralizes the P-type impurity and converts the conductivity type of that region to N-type, eliminating any potential PN junction formation.

[0120] It should be noted that the manufacturing method of the semiconductor device also includes: performing an annealing process to activate the implanted dopant ions and repair the lattice damage that may be caused to the contact layer 1021 and the source of the wafer transistor during the implantation process.

[0121] In some embodiments, the step of forming the bit line structure 105 further includes: performing an annealing process to react the contact layer 1021 of the bottom portion thickness of the second groove 104 with the metal in the bit line structure 105 to generate a metal silicide layer 1053, wherein the bit line structure 105 includes the metal silicide layer 1053.

[0122] As an example, the material of the metal silicide layer 1053 includes titanium silicide (TiSi).

[0123] like Figure 13As shown, the step of forming the insulating dielectric layer 108 further includes forming a hard mask layer 1085 on the second insulating layer 1084. In one embodiment, the hard mask layer 1085 is formed on the plane jointly formed by the top surface of the second insulating layer 1084 and the top surface of the substrate 1083. When the insulating dielectric layer is etched to form a dielectric structure, the hard mask layer 1085 is simultaneously etched to form a patterned hard mask layer 1085. The step of filling the second groove 104 with conductive material to form a bit line structure 105 electrically connected to the source 1012 includes filling the second groove 104 with excess conductive material and planarizing it with the patterned hard mask layer 1085 as a stop layer. The remaining conductive material in the second groove 104 is formed into the bit line structure 105.

[0124] By forming a hard mask layer 1085 on the second insulating layer 1084, and subsequently forming conductive material on the second groove 104 and dielectric structure 103, planarization is performed using the hard mask layer 1085 as a stop layer, thereby providing a stop interface for the planarization process, so that the conductive material below the hard mask layer 1085 is retained in the second groove 104 to form bit line structure 105.

[0125] Accordingly, in one embodiment, the dielectric structure 103 includes a first dielectric layer 1031 and a third dielectric layer 1033. The third dielectric layer 1033 is located on the side of the first dielectric layer 1031 away from the insulating isolator 1011. In a projection from the first side to the second side, the first dielectric layer and the third dielectric layer coincide, and the surface of the bit line structure away from the device layer is flush with the surface of the third dielectric layer away from the device layer. The third dielectric layer 1033 includes a patterned hard mask layer 1085 remaining after planarization.

[0126] As an example, using the hard mask layer 1085 as a stop layer, chemical mechanical polishing (CMP) is employed to remove conductive material above the hard mask layer 1085. This facilitates flushing the top of the bit line structure 105 with the top of the dielectric structure 103, ensuring the smoothness of the device surface morphology and supporting subsequent processes. During the CMP process, the removal rate of conductive materials (such as tungsten) by the polishing slurry is much higher than that of hard mask layers (such as silicon nitride). Therefore, when polishing reaches the surface of the hard mask layer, the polishing rate decreases, effectively "stopping" the process. This stops the polishing at the surface of the hard mask layer, ensuring that the top of the bit line structure 105 is flush with the hard mask layer 1085, resulting in a flat bit line structure 105.

[0127] In some embodiments, the step of forming a hard mask layer on the second insulating layer 1084 includes a chemical vapor deposition process. The material of the hard mask layer 1085 includes silicon nitride (SiN) or silicon carbide (SiC), and correspondingly, the material of the third dielectric layer 1033 includes silicon nitride (SiN) or silicon carbide (SiC).

[0128] It should be noted that when the dielectric structure 103 also includes a remaining liner, the remaining liner is located between the first dielectric layer 1031 and the third dielectric layer 1033, and is located laterally close to the edge of the second groove 104 of the dielectric structure 103.

[0129] This invention also provides a semiconductor device manufactured by the above method.

[0130] Accordingly, refer to Figure 18 and Figure 19 ,in Figure 18 The schematic diagram shows the structure of the device layer and the wiring layer. Figure 19 This is a schematic diagram of the structure of a formed semiconductor device. An embodiment of the present invention also provides a semiconductor device, including: a device layer 200 and a wiring layer 300. The device layer 200 has a first side 200A and a second side 200B opposite to each other. The wiring layer 300 is located on the first side 200A of the device layer 200. An insulating isolation member 201 and an array of transistors are formed in the device layer 200. The sources 202 of the transistors are separated by the insulating isolation member 201. The sources 202 and the insulating isolation member 201 are distributed on the surface of the device layer 200 near the first side 200A. The wiring layer 300... The device layer 200 includes multiple bit line structures 301 and multiple dielectric structures 302 containing air gaps. The bit line structures 301 are located on and electrically connected to the multiple sources 202. The dielectric structures 302 extend in the same direction as the bit line structures 301 (e.g., along the column direction in the transistor array), and the dielectric structures 302 and bit line structures 301 are alternately arranged along the surface of the first side 200A of the device layer 200. An insulating spacer 201 contacts the dielectric structure 302, with its lateral direction X (e.g., parallel to the device layer 200 and perpendicular to the extension direction of the bit line structures 301) defined as X. Figure 19 As shown, the end of the dielectric structure 302 near the insulating isolator 201 overlaps with the projection of the end of the source electrode 202 near the bit line structure 301 in the transverse X direction.

[0131] The wiring layer 300 of the semiconductor device provided in this embodiment of the invention is provided with a plurality of bit line structures 301 extending in the same direction and arranged alternately, and a plurality of dielectric structures 302 containing air gaps. By introducing dielectric structures 302 containing air gaps between adjacent bit line structures 301, the low dielectric constant (k≈1) of air is utilized to significantly reduce the parasitic capacitance between bit line structures 301. This helps to reduce the RC delay of signal transmission, thereby improving the operating speed of the device. On the other hand, for devices such as memory, it can effectively increase the signal difference during cell read operation, thereby improving the sensing margin and enhancing the reliability and accuracy of data reading. Furthermore, the dielectric structure 302 is in contact with the underlying insulating isolator 201, and in the transverse X direction, the end projection of the dielectric structure 302 overlaps with the end projection of the source electrode 202, thereby enabling the dielectric structure 302 to have a larger air gap, and the air gap extends further into the device layer 200. This increases the proportion of the air gap in the portion of the dielectric structure 302 located between adjacent bit line structures 301, thereby more effectively confining the electric field, suppressing the fringing effect of the electric field and signal crosstalk between adjacent bit line structures 301, and thus maximizing the effect of the air gap in reducing parasitic capacitance.

[0132] Device layer 200 includes an array of transistors, which form the basis of memory cells or logic cells.

[0133] In some embodiments, the transistors in device layer 200 include vertical channel transistors (VCTs) for forming transistors in a DRAM with a 1T1C structure.

[0134] The transistors are arranged in an array, and the source 202 of each transistor is formed on the surface area of ​​the device layer 200 near the first side 200A, so that the bit line structure 301 formed later can be electrically connected to the source 202 of a row of transistors. The bit line structure 301 serves as a signal line shared by a row of transistors, used to simultaneously access or sense a row of memory cells, which is the basis for realizing the addressing function of the memory array.

[0135] It should be noted that the transistor also includes a channel region 203 disposed on the second side 200B of the source 202, a drain 204 disposed on the side of the channel region 203 away from the source 202, a gate insulating layer (not shown in the figure) disposed on the surface of the channel region 203, and a gate (not shown in the figure) disposed on the gate insulating layer away from the channel region 203.

[0136] The insulating isolator 201 is used to isolate the source 202 in an adjacent transistor. As an example, the insulating isolator 201 includes shallow trench isolation (STI).

[0137] In some embodiments, the insulating separator 201 is made of silicon oxide. Silicon oxide is a dielectric material that is simple to process and has low cost, and it has good process compatibility.

[0138] The gate, gate insulating layer, channel region 203, source 202, and drain 204 together constitute a transistor. The transistor is used as a selection transistor for memory cells. When working, the voltage applied to the gate controls the conduction and turn-off of the channel region 203, thereby controlling the conduction state between the source 202 and the drain 204. Therefore, the transistor acts as an access device in a dynamic random access memory (DRAM) cell, enabling the selective connection or disconnection of the charge path between the bit line and the storage capacitor (which typically includes two plates, one of which is electrically connected to the drain, and the other plate is used to connect to a fixed potential), which is beneficial for realizing data writing and reading operations for specific memory cells.

[0139] Specifically, the transistors in device layer 200 are vertical channel transistors (VCTs). From the second side 200B of device layer 200 towards the first side 200A, the drain 204 is located at the bottom of the transistor; the channel region 203 is located above the drain 204, serving as a channel for carrier flow, and includes cylindrical or prismatic semiconductor pillars; a gate insulating layer and a gate surround or are adjacent to the sidewalls of the channel region 203. The gate insulating layer electrically isolates the gate from the channel region 203, and the gate controls the on / off state of the channel region 203 by applying a voltage; the source 202 is located above the channel region 203, forming the top layer of the transistor, and is used to connect to the bit line structure 301.

[0140] It should also be noted that the device layer 200 further includes a word line structure 205, which is electrically connected to the gates of a plurality of transistors. For example, the word line structure 205 is formed in an insulating isolator.

[0141] The word line structure 205 is located in the insulating isolator 201 and is electrically connected to the gates of multiple transistors. The word line structure 205 is disposed within the device layer 200, and the bit line structure 301 is located on the first side 200A of the device layer 200. The word line structure and bit line structure, which were originally crowded on the same side of the device layer, are distributed in different film layers, which greatly frees up the layout space and is a key technology for realizing the 4F² cell architecture.

[0142] Bit line structure 301 is connected to the source 202 of a row of transistors in the array of distributed transistors, serving as a connection for data reading, writing, and addressing in the memory array. This enables memory cells to be selected and their data status sensed or written, facilitating the construction of a fully functional dynamic random access memory. Correspondingly, word line structure 205 is electrically connected to the gate of a row of transistors in the array of distributed transistors.

[0143] In some embodiments, the bit line structure 301 includes a stack of a metal silicide layer 3011, a barrier layer 3012, and a conductive layer 3013. The metal silicide layer 3011 reduces the contact resistance between the bit line structure 301 and the source electrode 202 in the transistor. The metal silicide material includes titanium silicide (TiSi), and the metal silicide layer 3011 is disposed along the surface of the bit line structure 301 that contacts the source electrode 202. The barrier layer 3012 prevents the diffusion of metal (such as tungsten) from the conductive layer 3013. The material of the barrier layer 3012 includes, but is not limited to, titanium nitride (TiN) or tantalum nitride (TaN). The barrier layer 3012 includes a portion located between the metal silicide layer 3011 and the conductive layer 3013, and a portion located between the dielectric structure 302 and the conductive layer 3013. The conductive layer 3013 is made of tungsten (W) and fills the space enclosed by the barrier layer 3012 away from the surface of the device layer 200 and the dielectric structure 302.

[0144] In some embodiments, in a semiconductor device: the source 202 includes a contact layer 2021 that contacts the bit line structure 301, the contact layer 2021 including a doped semiconductor layer.

[0145] The contact layer 2021 acts as a bridge connecting the source 202 of the transistor and the bit line structure 301. The contact layer 2021 in the source 202 contacts the bit line structure 301. The contact layer 2021 includes a doped semiconductor layer. It is understood that the doping type (P-type or N-type) of the contact layer 2021 is the same as other parts of the source 202. Optionally, the contact layer 2021 is a heavily doped semiconductor layer, thereby reducing the contact impedance between the source 202 and the bit line structure 301. During the formation of the semiconductor device, the doped semiconductor layer is derived from the wafer substrate. Doping can eliminate pn junctions that may be caused by doping in the original wafer substrate (e.g., formed by the source of a wafer transistor with opposite doping types and the wafer substrate), reducing the contact impedance at the interface between the bit line structure 301 and the source 202. This reduces electrical losses in the current transmission path, enabling a low-impedance ohmic contact to be formed between the source 202 and the bit line structure 301, which is beneficial for improving the response speed and data read / write accuracy of the semiconductor device.

[0146] As an example, source 202 is N-type, and the doped semiconductor layer is doped with N-type ions (such as phosphorus or arsenic).

[0147] In some embodiments, a plurality of grooves 2011 are formed on the surface of the insulating isolator 201, and the dielectric structure 302 is embedded in the grooves 2011 in a corresponding manner. It can be understood that the grooves 2011 formed on the surface of the insulating isolator 201 mean that the bottom surface and sidewalls of the grooves 2011 are exposed on the surface of the insulating isolator 201.

[0148] It should be noted that the direction from the first side 200A to the second side 200B is the longitudinal direction, and the direction perpendicular to the longitudinal direction and the extension direction of the bit line structure 301 is the transverse direction. The dielectric structure 302 is embedded in the groove 2011, which means that a portion of the length of the dielectric structure 302 in the longitudinal direction is embedded in the groove 2011, and at least a portion of the width of the dielectric structure 302 in the transverse direction is embedded in the groove 2011.

[0149] By creating a groove 2011 on the surface of the insulating isolator 201, and partially forming the dielectric structure 302 within the groove 2011, the dielectric structure 302 containing the air gap 3021a and the insulating isolator 201 exhibit strong physical holding force and structural stability. Furthermore, the proportion of the air gap 3021a in the portion of the dielectric structure 302 located between the bit line structures 301 is increased, extending towards the device layer 200. This provides more effective isolation between the bit line structures 301, thereby more effectively confining the electric field, suppressing the fringing effect of the electric field, and reducing signal crosstalk between adjacent bit line structures 301. This enhances the effectiveness of the air gap 3021a in reducing parasitic capacitance.

[0150] In some embodiments, the dielectric structure 302 includes a first dielectric layer 3021 and a second dielectric layer 3022. The thickness of the second dielectric layer 3022 is less than the depth of the groove 2011. The second dielectric layer 3022 is located on the side of the first dielectric layer 3021 near the insulating isolator 201. In the projection from the first side 200A to the second side 200B, the first dielectric layer 3021 and the second dielectric layer 3022 coincide. The first dielectric layer 3021 includes an air gap 3021a.

[0151] The dielectric structure 302 includes a first dielectric layer 3021 containing an air gap 3021a, and a second dielectric layer 3022 located between the first dielectric layer 3021 and the insulating isolator 201. The air gap 3021a in the first dielectric layer 3021 achieves a low dielectric constant and reduces the parasitic capacitance between adjacent bit line structures 301. Therefore, the second dielectric layer 3022 is used to protect the device layer 200 during the manufacturing process of the first dielectric layer 3021 containing the air gap 3021a.

[0152] As an example, the material of the first dielectric layer 3021 includes silicon oxide. Silicon oxide is a dielectric material that is simple to prepare and has low cost, and it has good process compatibility.

[0153] As an example, the material of the second dielectric layer 3022 is different from that of the first dielectric layer 3021. For example, the material of the first dielectric layer 3021 includes silicon oxide, while the material of the second dielectric layer 3022 includes silicon nitride.

[0154] In some embodiments, a groove 2011 is formed on the surface of the insulating separator 201, and the dielectric structure 302 is embedded in the groove 2011; the second dielectric layer 3022 includes a first portion located on the bottom surface of the groove 2011 and a second portion located on the sidewall of the groove 2011. Accordingly, in the lateral direction, the width of the dielectric structure 302 is greater than or equal to the width of the groove 2011.

[0155] The first part of the second dielectric layer 3022 is located on the bottom surface of the groove 2011, and the second part of the second dielectric layer 3022 is located on the side wall of the groove 2011. That is, the second dielectric layer 3022 is conformally formed on the surface of the groove 2011. Thus, damage to the device layer 200, especially the insulating isolation member 201, can be avoided during the formation of the dielectric structure 302.

[0156] Specifically, in the projection from the first side 200A to the second side 200B, the dielectric structure 302 coincides with the groove 2011, and the second part of the second dielectric layer 3022 is farther away from the end of the device layer 200 and closer to the first side 200A of the device layer 200 than the source 202.

[0157] In the projection from the first side 200A to the second side 200B, the dielectric structure 302 coincides with the groove 2011, which can reduce the number of photomasks required to fabricate semiconductor devices and reduce production costs.

[0158] During the formation of the first dielectric layer 3021, the etch stop layer protects the device layer 200. During the formation of the dielectric structure 301, the etch stop layer on the surface of the region corresponding to the source 202 (i.e. the region where the bit line structure 301 is formed) is removed. The remaining etch stop layer forms the second dielectric layer 3022 on the surface of the device layer, such that the second part of the second dielectric layer 3022 is further away from the end of the device layer 200 than the source 202.

[0159] In some embodiments, the dielectric structure 302 includes a first dielectric layer 3021 and a third dielectric layer 3023. The third dielectric layer 3023 is located on the side of the first dielectric layer 3021 away from the insulating isolator 201. In the projection from the first side 200A to the second side 200B, the first dielectric layer 3021 and the third dielectric layer 3023 coincide. The first dielectric layer 3021 includes an air gap 3021a.

[0160] The third dielectric layer 3023 is located on the side of the first dielectric layer 3021 away from the insulating isolator 201. In the projection from the first side 200A to the second side 200B, the first dielectric layer 3021 and the third dielectric layer 3023 coincide. That is to say, the first dielectric layer 3021 is completely shielded by the third dielectric layer 3023, so that the third dielectric layer 3023 can protect the air gap 3021a with loose structure and poor mechanical properties, thereby improving mechanical strength.

[0161] Bit line structure 301 is flush with the surface of the third dielectric layer 3023 away from device layer 200. During the formation of bit line structure 301, the top of the third dielectric layer 3023 is used as the stop position for chemical mechanical polishing (CMP), so that the surface of bit line structure 301 is flush with the surface of the third dielectric layer 3023 away from device layer 200, which facilitates subsequent process integration.

[0162] As an example, the material of the third dielectric layer 3023 includes silicon nitride (SiN) or silicon carbide (SiC).

[0163] In other embodiments, the surface of the insulating isolator 201 is flat. In the device layer 200, the surface of the insulating isolator 201 facing the wiring layer 300 is flat, and the source of the transistor protrudes from the surface of the insulating isolator 201 facing the wiring layer 300. The wiring layer 300 is located on the first side 200A of the device layer 200, which simplifies the manufacturing of the insulating isolator 201 and helps to reduce the manufacturing difficulty of the semiconductor device.

[0164] The semiconductor device can be formed using the manufacturing method of the foregoing embodiments, or it can be formed using other manufacturing methods. For a detailed description of the semiconductor structure of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0165] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor substrate is provided having a first side and a second side opposite to each other. The semiconductor substrate includes a device layer located on the first side, in which an insulating isolator and an array of transistors are formed. The sources of the transistors are separated by the insulating isolator, and the sources and the insulating isolator are distributed on the surface of the device layer near the first side. A first etching is performed on the insulating spacer to form a first groove on the first side, the bottom surface of the first groove exposing the remaining insulating spacer; A dielectric material layer is formed on the first side of the semiconductor substrate. The dielectric material layer includes a plurality of dielectric structures containing air gaps and a second groove located between the dielectric structures. The second groove exposes corresponding regions of the plurality of sources. In a projection from the first side to the second side, the plurality of dielectric structures overlap the first groove. The second groove is filled with conductive material to form a bit line structure electrically connected to the source electrode.

2. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, The step of providing the semiconductor substrate includes: A device wafer is provided, the device wafer including a third side and a fourth side opposite to each other, the device wafer including a wafer device layer located on the third side and a wafer substrate located on the fourth side, a wafer insulating isolation device and an array of wafer transistors formed in the wafer device layer, the source of the wafer transistors being separated by the wafer insulating isolation device, the source of the wafer transistors and the wafer insulating isolation device being distributed on the surface of the wafer device layer near the wafer substrate; A carrier wafer is provided, and the carrier wafer is bonded to the third side of the device wafer; the device wafer is thinned from the fourth side to expose the wafer insulating spacer; Wherein, the insulating isolation component includes the remaining wafer insulating isolation component, the source of the transistor includes the source of the wafer transistor, the semiconductor substrate includes the remaining device wafer and the carrier wafer, and the carrier wafer is located on the second side.

3. The method as described in claim 2, characterized in that, In the step of providing a device wafer, the depth of the wafer insulating spacer extending into the wafer substrate is greater than that of the source of the wafer transistor; The step of thinning the device wafer from the fourth side to expose the wafer insulating isolation includes removing a portion of the thickness of the wafer insulating isolation and retaining a portion of the wafer substrate at the top of the source of the wafer transistor, the source of the transistor also including the portion of the wafer substrate.

4. The method as described in claim 3, characterized in that, Before forming the bit line structure, the wafer substrate of the specified thickness is doped, and the type of doping is the same as that of the source of the wafer transistor.

5. The method as described in claim 1, characterized in that, The first etching step includes etch-back; or The step of performing a first etching on the insulating isolator to form a first groove on the first side includes: forming a first photoresist layer on the surface of the device layer near the first side; exposing and developing the first photoresist layer to form a patterned first photoresist layer; and performing the first etching using the patterned first photoresist layer as a mask. The first groove includes a plurality of sub-grooves distributed along the first side surface of the semiconductor substrate. In the step of forming a dielectric material layer on the first side of the semiconductor substrate, the sub-grooves overlap with the dielectric structure in a one-to-one correspondence in the projection from the first side to the second side.

6. The method as described in claim 5, characterized in that, The step of forming a dielectric structure including an air gap on the semiconductor substrate includes: After the first groove is formed, an insulating dielectric layer and a patterned mask layer are sequentially formed on the surface of the first side of the semiconductor substrate. The insulating dielectric layer is then etched using the patterned mask layer as a mask to form the dielectric structure.

7. The method as described in claim 6, characterized in that, The step of forming the insulating dielectric layer includes: An etch stop layer is conformally formed on a first side of the device layer, the thickness of which is less than the depth of the first groove. A first insulating layer with a flat top is formed on the surface of the etch stop layer, and a liner is formed on the first insulating layer. The liner and the first insulating layer are patterned with the etch stop layer as the endpoint to form an initial opening. The first insulating layer on the sidewall of the initial opening is laterally etched to form the initial opening as an opening with a concave profile. A second insulating layer containing an air gap is formed in the opening. The insulating dielectric layer includes the etch stop layer, the patterned first insulating layer, the patterned substrate, and the second insulating layer.

8. The method as described in claim 7, characterized in that, In the step of laterally etching the first insulating layer of the initial opening sidewall to form an opening with a concave profile, the lateral dimension of the longitudinal middle section of the opening is greater than the lateral dimension of the top of the opening.

9. The method as described in claim 7, characterized in that, The first insulating layer and the second insulating layer are made of the same material.

10. The method as described in claim 7, characterized in that, The step of forming the insulating dielectric layer further includes: forming a hard mask layer on the second insulating layer; The step of filling the second groove with conductive material to form a bit line structure electrically connected to the source includes filling the second groove with excess conductive material and planarizing it with the patterned hard mask layer as a stop layer, and the remaining conductive material in the second groove forming the bit line structure.

11. The method as described in claim 7, characterized in that, The step of performing a second etching on the insulating dielectric layer using the patterned mask layer as a mask to form the dielectric structure includes forming a second photoresist layer on the insulating dielectric layer and exposing and developing the second photoresist layer to form the patterned mask layer. The photomask used for exposing and developing the first photoresist layer is the same as the photomask used for exposing and developing the second photoresist layer, and the first photoresist layer and the second photoresist layer are respectively one of positive photoresist and negative photoresist.

12. The method as described in claim 1, characterized in that, In the step of providing a semiconductor substrate, the transistor further includes a channel region disposed on the second side of the source, a drain disposed on the side of the channel region away from the source, a gate insulating layer disposed on the surface of the channel region, and a gate disposed on the gate insulating layer away from the channel region. In the step of providing a semiconductor substrate, the semiconductor device further includes a word line structure electrically connected to the gates of the plurality of transistors, the word line structure being formed in the insulating isolator.

13. A semiconductor device, characterized in that, Formed using the manufacturing method of a semiconductor device as described in any one of claims 1 to 12.

14. A semiconductor device, characterized in that, include: A device layer and a wiring layer, wherein the device layer has a first side and a second side opposite to each other, and the wiring layer is located on the first side of the device layer; The device layer has an insulating isolator and an array of transistors. The source of the transistor is separated by the insulating isolator. The source and the insulating isolator are distributed on the surface of the device layer near the first side. The wiring layer includes multiple bit line structures and multiple dielectric structures containing air gaps. The bit line structures are located on and electrically connected to the multiple sources. The dielectric structures extend in the same direction as the bit line structures, and the dielectric structures and bit line structures are alternately arranged along the surface of the first side of the device layer. The insulating isolator is in contact with the dielectric structure, with the extension direction parallel to the device layer and perpendicular to the bit line structure as the lateral direction. The end of the dielectric structure near the insulating isolator overlaps with the end of the source electrode near the bit line structure in the lateral direction.

15. The apparatus as claimed in claim 14, characterized in that, The source electrode includes a contact layer that contacts the bit line structure, and the contact layer includes a doped semiconductor layer.

16. The apparatus as claimed in claim 14, characterized in that, The surface of the insulating element is flat; or The insulating isolation component has grooves formed on its surface, and the dielectric structure is embedded in the grooves one by one.

17. The apparatus as claimed in claim 16, characterized in that, The dielectric structure includes a first dielectric layer and a second dielectric layer, the second dielectric layer being located on the side of the first dielectric layer near the insulating isolator, the thickness of the second dielectric layer being less than the depth of the groove, and the first dielectric layer and the second dielectric layer coinciding in a projection from the first side to the second side, the first dielectric layer including the air gap.

18. The apparatus as claimed in claim 17, characterized in that, The insulating insulating element has a groove formed on its surface, and the dielectric structure is embedded in the groove; The second medium layer includes a first portion located on the bottom surface of the groove and a second portion located on the sidewall of the groove.

19. The apparatus as claimed in claim 18, characterized in that, In the projection from the first side to the second side, the dielectric structure coincides with the groove; The second portion of the second dielectric layer is further away from the device layer than the source electrode.

20. The apparatus as claimed in claim 14, characterized in that, The dielectric structure includes a first dielectric layer and a third dielectric layer, the third dielectric layer being located on the side of the first dielectric layer away from the insulating isolator, and in a projection from the first side to the second side, the first dielectric layer and the third dielectric layer coincide, the first dielectric layer including the air gap; The surface of the bit line structure away from the device layer is flush with the surface of the third dielectric layer away from the device layer.

21. The apparatus as claimed in claim 14, characterized in that, The transistor further includes a channel region disposed on the second side of the source, a drain disposed on the side of the channel region away from the source, a gate insulating layer disposed on the surface of the channel region, and a gate disposed on the gate insulating layer away from the channel region. The semiconductor device further includes a word line structure electrically connected to the gates of the plurality of transistors, the word line structure being located within the insulating isolator.

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