Flash memory device and forming method thereof
By forming a tunneling dielectric layer and a floating gate in a coded flash memory, and then using an etching process to define the shape of the floating gate and fill the isolation components, the problem of voids or seams caused by poor gap filling is solved, thereby improving the electrical performance and reliability of the memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2026-04-07
AI Technical Summary
In coded flash memory, when the critical size of the memory cell is miniaturized, the process of self-aligned floating gate or control gate may lead to poor gap filling, forming voids or seams, which affect electrical performance and reliability.
After forming a tunneling dielectric layer and floating gates on the substrate, the shape of the floating gates is defined using an etching process, and isolation components are formed between the floating gates. Dielectric materials are filled using deposition and planarization processes to avoid the formation of voids or seams.
It improves the electrical performance and reliability of flash memory devices, avoids voids or seams caused by poor gap filling, and enhances the accuracy and stability of the process.
Smart Images
Figure CN121815661A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to a flash memory device and a method for forming the same, and more particularly to an isolation structure of a NOR flash memory device and a method for forming the same. BACKGROUND
[0002] In a NOR flash memory, the critical dimension of a memory cell can cause problems when scaled down. For example, the process of forming a self-aligned floating gate or control gate can form voids or seams due to poor gap fill, which can cause electrical and reliability problems. Therefore, there is a need to design a flash memory device and a method for forming the same to solve the aforementioned problems. SUMMARY
[0003] The present invention provides a method for forming a flash memory device, comprising providing a substrate; forming a tunnel dielectric layer on the substrate; forming a plurality of stack structures on the tunnel dielectric layer, each stack structure comprising a floating gate and a mask pattern on the floating gate; performing a first etching process to form a plurality of first trenches in the substrate; performing a second etching process to remove a portion of the substrate exposed from the first trenches to form a plurality of second trenches in the substrate; and forming a dielectric material over the substrate. The dielectric material fills the second trenches and covers the stack structures. The mask pattern and the dielectric material on a first top surface and a first side surface of each floating gate are removed. The remaining dielectric material forms a plurality of isolation structures in the second trenches.
[0004] The present invention provides a flash memory device, comprising a substrate, a tunnel dielectric pattern, a floating gate, a plurality of insulating spacers, and a plurality of isolation structures. The substrate has a mesa. The mesa has a first top surface and a plurality of first side surfaces connected to the first top surface. The tunnel dielectric pattern is disposed on the first top surface of the mesa. The floating gate is disposed on the tunnel dielectric pattern. The floating gate has a second bottom surface contacting the tunnel dielectric pattern and a plurality of second side surfaces connected to the second bottom surface. The insulating spacers are disposed on a portion of the second side surfaces of the floating gate proximate to the second bottom surface. The isolation structures are disposed on the first side surfaces of the mesa. A plurality of third top surfaces of the insulating spacers and a plurality of fourth top surfaces of the isolation structures are coplanar, and the third top surfaces and the fourth top surfaces are higher than the second bottom surface of the floating gate. BRIEF DESCRIPTION OF DRAWINGS
[0005] Figures 1 to 9 Perspective views of various process stages of a method for forming a flash memory device according to some embodiments of the present invention.
[0006] Glossary of symbols
[0007] 100, 110, 120: directions
[0008] 200: base
[0009] 200M1, 200M2: mesa
[0010] 200M1B, 200M2B, 218B, 220B: bottom
[0011] 200M1S, 200M2S, 206PS, 210S: side
[0012] 200T, 202T, 206PT, 200M1T, 200M2T, 210T, 214R2T, 214R3T, 224T, 224R1T, 224R2T: top
[0013] 202: tunnel dielectric layer
[0014] 202P: tunnel dielectric pattern
[0015] 202PB, 206PB: bottom surface
[0016] 206: floating gate layer
[0017] 206P: floating gate
[0018] 208: mask layer
[0019] 208P: mask pattern
[0020] 210: stack structure
[0021] 214: insulating liner
[0022] 214R1, 214R2, 214R3: insulating spacer
[0023] 214R1S: outer side surface
[0024] 218, 220: trench
[0025] 224, 224R1: dielectric material
[0026] 224R2: isolation component
[0027] 228: gate dielectric layer
[0028] 229: void
[0029] 230: control gate layer
[0030] 500: flash memory device
[0031] 1000, 1200: etching process
[0032] L1, L2: lateral dimension
[0033] A1: Bottom corner
[0034] D1: Distance
[0035] S1: Spacing
[0036] θ1, θ2: included angle Detailed Implementation
[0037] In the fabrication process of coded flash memory, shallow trench isolation components are first formed in a substrate. These shallow trench isolation components have tops protruding from the substrate. Next, a pull-back process is performed to widen the gaps between the tops of the shallow trench isolation components, creating space to accommodate the floating gate. Using a deposition process and subsequent planarization, the floating gate is self-aligned and formed in this space. Then, the tops of the shallow trench isolation components are removed to create space between the floating gates to accommodate the gate dielectric layer and the control gate. Finally, the gate dielectric layer and the control gate are formed on the floating gate to form the flash memory. However, the size and bottom corner shape of the floating gate are defined by the pulled-back tops of the shallow trench isolation components. During floating gate formation, voids or seams may form in the floating gate due to poor gap filling. Furthermore, because the pull-back process isotropically removes part of the top of the shallow trench isolation components, the bottom corners of the self-aligned floating gate will have a rounded corner shape. The aforementioned multiple floating gates with rounded corners create gaps that are narrower at the top and wider at the bottom. During the formation of the control gate, poor gap filling can lead to voids or seams in the control gate, affecting the electrical performance and reliability of the final flash memory device. Therefore, a flash memory device and its formation method are needed to solve the aforementioned problems.
[0038] Figures 1 to 9 This is a perspective view of each process stage in the method for forming the encoded flash memory device 500 according to the present invention. Figure 1 In the subsequent diagrams, directions 100, 110, and 120 are shown as the x, y, and z directions, respectively. Directions 100 and 110 are substantially parallel to the base 200. Figure 1 The directions of the top surface 200T of the substrate 200 are the width and length directions of the flash memory device 500, respectively. Direction 120 is substantially perpendicular to the top surface 200T of the substrate 200 (also referred to as the longitudinal direction 120). In the method of forming the flash memory device 500, firstly using... Figure 1 , Figure 2 The process includes a stacked structure 210 of the floating gate 206P, which serves as an etching mask for the subsequent formation of the isolation component 224R2. Then, using... Figures 3 to 7 The process forms the isolation component 224R2 of the flash memory device 500, and then uses... Figure 8 and Figure 9The process forms the gate dielectric layer 228 and the control gate layer 230 of the flash memory device 500, and forms... Figure 9 Flash memory device 500.
[0039] like Figure 1 As shown, a substrate 200 is provided. The substrate 200 can be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. The substrate 200 can be an insulator-on-silicon substrate. The substrate 200 is a silicon substrate.
[0040] A tunneling dielectric layer 202 is formed uniformly on the top surface 200T of the substrate 200 by thermal oxidation or chemical vapor deposition. The tunneling dielectric layer 202 is silicon oxide.
[0041] Following this, several deposition processes are performed to sequentially and comprehensively form a floating gate layer 206 and a mask layer 208 on the top surface 202T of the tunneling dielectric layer 202. The floating gate layer 206 completely covers the tunneling dielectric layer 202, and the mask layer 208 completely covers the floating gate layer 206. The floating gate layer 206 is, for example, polysilicon. The mask layer 208 is, for example, silicon oxide, silicon nitride, silicon oxynitride, titanium nitride, photoresist, or other suitable mask materials.
[0042] like Figure 2 As shown, photolithography and subsequent anisotropic etching processes are performed to form a mask pattern (not shown) on mask layer 208. Then, mask layer 208 and floating gate layer 206 are patterned sequentially until tunneling dielectric layer 202 is exposed. Multiple spaced-apart stacked structures 210 are formed on tunneling dielectric layer 202. Stacked structures 210 define the formation locations of isolation components 224R2 of flash memory device 500 and allow a portion of the top surface 202T of tunneling dielectric layer 202 to be exposed between stacked structures 210. Stacked structure 210 includes floating gate 206P and a mask pattern 208P located on floating gate 206P. The patterning process forming stacked structure 210 defines the final shape and size of floating gate 206P of flash memory device 500. Figure 2 As shown, the cross-sectional shape of the floating gate 206P can be rectangular. Each floating gate 206P has a bottom surface 206PB close to the substrate 200, a top surface 206PT away from the substrate 200, and a side surface 206PS connecting the bottom surface 206PB and the top surface 206PT and facing each other. Since the floating gates 206P of the stacked structure 210 are formed by photolithography and anisotropic etching processes, the bottom corner A1 formed by the bottom surface 206PB and the side surface 206PS of the floating gate 206P is a sharp corner rather than a rounded corner. Furthermore, the spacing S1 between the floating gates 206P is uniform near the top surface 206PT or the bottom surface 206PB, and a spacing S1 that is narrower at the top and wider at the bottom will not be formed.
[0043] After forming the stacked structure 210, a low-temperature atomic layer deposition process is performed to conformally form an insulating liner 214 on the stacked structure 210 and on the top surface 202T of the tunneling dielectric layer 202 not covered by the stacked structure 210. The insulating liner 214 can be used to protect the opposite side surfaces 206PS of the floating gate 206P, preventing the floating gate 206P from being damaged during the subsequent etching process to form the isolation component 224R2. The insulating liner 214 and the mask pattern 208P can have the same material, for example, both being silicon oxide.
[0044] like Figure 3 As shown, etching process 1000 uses the stacked structure 210 as an etching mask to perform anisotropic etching. The portion of the tunneling dielectric layer 202 not covered by the stacked structure 210 is removed. Figure 2 The etching process 1000 removes a portion of the insulating liner 214 on the top surface 210T of the stacked structure 210 and on the top surface 202T of the tunneling dielectric layer 202 between the stacked structures 210. After the etching process 1000, a plurality of trenches 218 and a plurality of pedestals 200M1 sandwiched between the trenches 218 are formed in the substrate 200. The remaining tunneling dielectric layer 202 forms a plurality of tunneling dielectric patterns 202P on the substrate 200, and the remaining insulating liner 214 forms a plurality of insulating spacers 214R1 in self-alignment on the opposite sides 210S of the stacked structure 210. The insulating spacers 214R1 and the floating gate 206P cover different portions of the tunneling dielectric patterns 202P.
[0045] like Figure 3 As shown, each platform 200M1 has a top surface 200M1T and multiple side surfaces 200M1S connected to and opposite to the top surface 200M1T. Multiple outer side surfaces 214R1S of the insulating spacer 214R1 are aligned with the corresponding side surfaces 200M1S of the platform 200M1. Furthermore, the bottom surface 202PB of each tunneling dielectric pattern 202P is completely covered by the corresponding platform 200M1. In direction 100, the top surface 200M1T of the platform 200M1 and the bottom surface 202PB of the tunneling dielectric pattern 202P may have the same lateral dimension L1.
[0046] like Figure 3 As shown, a portion of the side surface 200M1S near the bottom 200M1B of the platform 200M1 (adjacent to the bottom 218B of the trench 218) has an angle θ1 between it and the direction substantially parallel to the top surface 200M1T of the platform 200M1. The angle θ1 is an acute angle close to 90 degrees, for example, it may be between 82 degrees and 88 degrees.
[0047] Etching process 1000 is a selective etching process. Since the silicon substrate 200 has a high etching selectivity relative to the silicon oxide insulating liner 214 and the mask pattern 208P, the formation of the trench 218 will not damage the top surface 206PT and the side surface 206PS of the floating gate 206P.
[0048] like Figure 4 As shown, using the stacked structure 210 and insulating spacer 214R1 as an etching mask, an isotropic etching process 1200 is performed to remove the portion of the substrate 200 exposed from the trench 218, thereby expanding the lateral and longitudinal dimensions of the trench along direction 100 and along the direction substantially perpendicular to the top surface 200M1T of the platform 200M1. After the etching process 1000, a plurality of trenches 220 and a plurality of platforms 200M2 sandwiched between the trenches 220 are formed in the substrate 200.
[0049] Each of the elevated platforms 200M2 has a top surface 200M2T and multiple side surfaces 200M2S connected to and opposite to the top surface 200M2T. For example... Figure 4 As shown, the top surface 200M2T of the platform 200M2 has a lateral dimension L2 in direction 100. The lateral dimension L1 of the bottom surface 202PB of the tunneling dielectric pattern 202P is greater than the lateral dimension L2. Therefore, after etching process 1200, the tunneling dielectric pattern 202P completely covers the top surface 200M2T of the corresponding platform 200M2, and a portion of the bottom surface 202PB of each tunneling dielectric pattern 202P is exposed from the corresponding platform 200M2. In direction 100, the opposite side surface 200M2S of the platform 200M2 and the corresponding side surface 210S of the stacked structure 210 can have the same distance D1.
[0050] Compared to Platform 200M1, Platform 200M2 can have a tapered cross-sectional profile. For example... Figure 4 As shown, a portion of the side surface 200M2S of the platform 200M2 near the bottom 200M2B (adjacent to the bottom 220B of the trench 220) has an angle θ2 between it and a direction substantially parallel to the top surface 200M2T. The angle θ2 is smaller than the angle θ1, and the angle θ2 may be less than or equal to 75 degrees, for example.
[0051] Etching process 1200 is a selective etching process. Since the silicon substrate 200 has a high etching selectivity relative to the silicon oxide insulating liner 214 and the mask pattern 208P, the formation of the trench 220 will not damage the top surface 206PT and the side surface 206PS of the floating gate 206P.
[0052] Etching process 1000 and etching process 1200 can be performed sequentially on the same etching machine. Therefore, etching processes 1000 and 1200 can be in-situ etching processes. After etching processes 1000 and 1200, the floating gate 206P and the platform 200M2 below it can have a hammer-shaped cross-sectional profile.
[0053] Next, as Figure 5 As shown, a deposition process is performed to comprehensively form dielectric material 224. Dielectric material 224 fills the space between trench 220 and stacked structure 210, and covers stacked structure 210 and insulating spacer 214R1. The top surface 224T of dielectric material 224 is higher than the top surface 210T of stacked structure 210 and is substantially planar. Dielectric material 224 includes, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or combinations thereof. After forming the dielectric material 224 of the spin-coated glass, an annealing process can be performed to remove the solvent within the spin-coated glass, converting it into a solid silicon oxide dielectric material.
[0054] Next, as Figure 6 As shown, a planarization process involving chemical mechanical polishing removes a portion of the dielectric material 224 and mask pattern 208P from the top surface 206PT of the floating gate 206P until the top surface 206PT of the floating gate 206P is exposed. This allows dielectric material 224R1 to be formed in the trench 220 and between the floating gates 206P, and insulating spacers 214R2 to be formed on the opposite side surface 206PS of the floating gate 206P. After the planarization process, the top surface 206PT of the floating gate 206P is flush with the top surface 224R1T of the dielectric material 224R1 and the top surface 214R2T of the insulating spacer 214R2.
[0055] like Figure 7 As shown, dielectric material 224R1 and insulating spacer 214R2 are recessed from the top surface 206PT of the floating gate 206P. A wet chemical cleaning process is performed to remove a portion of the dielectric material 224R1 located on the side surface 206PS of the floating gate 206P. The above cleaning process partially removes the dielectric material 224R1 and insulating spacer 214R2 between the floating gates 206P. Figure 6The remaining insulating spacer 214R3 partially covers the side surface 206PS of the floating gate 206P. The insulating spacer 214R3 covers the lower part of the side surface 206PS of the floating gate 206P, leaving the upper part of the side surface 206PS of the floating gate 206P exposed. At this time, the tunneling dielectric pattern 202P is still completely covered by the floating gate 206P and the insulating spacer 214R3. The remaining dielectric material forms a plurality of isolation members 224R2 in the trench 220. The isolation members 224R2 are separated from the floating gate 206P by the insulating spacer 214R3 and the tunneling dielectric pattern 202P. The top surface 224R2T of the isolation member 224R2 is substantially flush with the top surface 214R3T of the insulating spacer 214R3 and is located above the bottom surface 206PB of the floating gate 206P along direction 120. Compared to the top surface 206PT of the floating gate 206P, the top surface 224R2T of the isolation member 224R2 and the top surface 214R3T of the insulating spacer 214R3 are closer to the bottom surface 206PB of the floating gate 206P. The isolation member 224R2 is, for example, a shallow trench isolation member.
[0056] like Figure 8 As shown, a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process is used to conformally form a gate dielectric layer 228 on the top surface 206PT and part of the side surface 206PS of the isolation component 224R2, the insulating spacer 214R3, and the floating gate 206P. The gate dielectric layer 228 covers the top surface 224R2T of the isolation component 224R2 and the top surface 214R3T of the insulating spacer 214R3, but does not fill the gaps 229 between the floating gates 206P. The gate dielectric layer 228 does not contact the platform 200M2. The gate dielectric layer 228 comprises silicon oxide, silicon nitride, silicon oxynitride, or a three-layer structure comprising silicon oxide / silicon nitride / silicon oxide.
[0057] like Figure 9 As shown, a chemical vapor deposition process is performed to form a control gate layer 230 on the gate dielectric layer 228, and the control gate layer 230 fills the gaps 229 between the floating gates 206P. After the above process, a flash memory device 500 is formed. The control gate layer 230 includes a polysilicon or other conductive material layer.
[0058] like Figure 9As shown, the flash memory device 500 includes a substrate 200, a tunneling dielectric pattern 202P, a floating gate 206P, a plurality of insulating spacers 214R3, and a plurality of isolation members 224R2. The substrate 200 has a platform 200M2, which has a top surface 200M2T and a plurality of side surfaces 200M2S connected to the top surface 200M2T. The tunneling dielectric pattern 202P is disposed on the top surface 200M2T of the platform 200M2. The floating gate 206P is disposed on the tunneling dielectric pattern 202P. The floating gate 206P has a bottom surface 206PB that contacts the tunneling dielectric pattern 202P and a side surface 206PS connected to the bottom surface 206PB. The insulating spacers 214R3 are disposed on a portion of the side surface 206PS of the floating gate 206P near the bottom surface 206PB. The isolation member 224R2 is disposed on the side surface 200M2S of the platform 200M2. Multiple top surfaces 214R3T of the insulating spacer 214R3 are coplanar with multiple top surfaces 224R2T of the isolation member 224R2. Furthermore, the top surfaces 214R3T of the insulating spacer 214R3 and the top surfaces 224R2T of the isolation member 224R2 are higher than the bottom surface 206PB of the floating gate 206P. Multiple sharp-angled bottom angles A1 are formed by the bottom surface 206PB of the floating gate 206P and the side surface 206PS. The angle θ2 between the side surface 200M2S near the bottom 200M2B of the platform 200M2 (adjacent to the bottom 220B of the trench 220) and the direction 100 substantially parallel to the top surface 200M2T is less than or equal to 75 degrees. The lateral dimension L2 of the top surface 200M2T of the platform 200M2 is smaller than the lateral dimension L1 of the bottom surface 206PB of the floating gate 206P. The flash memory device 500 further includes a gate dielectric layer 228 and a control gate layer 230. The gate dielectric layer 228 is formed on the isolation member 224R2 and the floating gate 206P. The control gate layer 230 is formed on the gate dielectric layer 228.
[0059] This invention uses deposition and subsequent patterning processes to fabricate a stacked structure of floating gates as an etching mask for shallow trench isolation components. The floating gates are formed before the shallow trench isolation components, saving process steps and avoiding voids or seams caused by poor gate material filling when forming self-aligned floating gates in existing processes. An in-situ isotropic etching process defines the trench shape of the shallow trench isolation components, allowing the floating gates and their underlying ramps to form a hammer-shaped cross-sectional profile. The floating gates formed by anisotropic etching processes have a rectangular cross-sectional shape with sharp, non-rounded bottom corners, preventing gaps between floating gates that are narrow at the top and wide at the bottom. Forming the control gate layer in the gaps between floating gates avoids voids or seams caused by poor gate material filling. This improves the electrical performance and reliability of flash memory devices.
[0060] The above embodiments are not intended to limit the present invention. Those skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.
Claims
1. A method for forming a flash memory device, characterized in that, include: Provide a base; A tunneling dielectric layer is formed on the substrate; Multiple stacked structures are formed on the tunneling dielectric layer, wherein each stacked structure includes a floating gate and a mask pattern located on the floating gate; A first etching process is performed to form a plurality of first trenches in the substrate; A second etching process is performed to remove the portion of the substrate exposed from the first trench, thereby forming a plurality of second trenches in the substrate; A dielectric material is formed comprehensively, wherein the dielectric material fills the second trench and covers the stacked structure; and The mask pattern and dielectric material located on a first top surface and a first side surface of each of the floating gates are removed, wherein the remaining dielectric material forms a plurality of isolation components in the second trench.
2. The method for forming a flash memory device as claimed in claim 1, characterized in that, The stacked structure includes: A floating gate layer and a mask layer are sequentially formed on the tunneling dielectric layer; and The floating gate layer and the mask layer are patterned until the tunneling dielectric layer is exposed, wherein after the stacked structure is formed, each floating gate forms a sharp angle with a first bottom surface and a first side surface of the substrate.
3. The method for forming a flash memory device as described in claim 1, characterized in that, Including: Before performing the first etching process, an insulating liner is formed on the stacked structure; as well as After the first etching process, the remaining tunneling dielectric layer forms multiple tunneling dielectric patterns on the substrate, and the remaining insulating liner forms multiple insulating spacers on the opposite sides of each stacked structure.
4. The method for forming a flash memory device as described in claim 3, characterized in that, After the first etching process is performed, a plurality of first tiers are formed in the substrate between the first trenches, wherein each of the first tiers has a second top surface and a plurality of second side surfaces connected to the second top surface, wherein the plurality of outer side surfaces of the insulating spacer are aligned with the second side surfaces of the corresponding first tier.
5. The method for forming a flash memory device as described in claim 4, characterized in that, After the second etching process, a plurality of second tiers are formed in the substrate between the second trenches, wherein each of the second tiers has a fourth top surface and a plurality of fourth side surfaces connected to the fourth top surface, wherein the second top surface has a first lateral dimension, the fourth top surface has a second lateral dimension, and the first lateral dimension is larger than the second lateral dimension.
6. The method for forming a flash memory device as described in claim 3, characterized in that, Removing the mask pattern and the dielectric material located on the first top surface and the first side surface of each of the floating gates includes: Perform a planarization process to remove the dielectric material and the mask pattern from the first top surface of the floating gate; and A cleaning process is performed to partially remove the dielectric material and the insulating spacer between the floating gates, and to make the remaining insulating spacer partially cover the first side of the floating gate, wherein the plurality of fifth top surfaces of the remaining insulating spacer are coplanar with the plurality of sixth top surfaces of the isolation member, and the fifth top surfaces and the sixth top surfaces are located above a first bottom surface of each floating gate near the substrate.
7. The method for forming a flash memory device as described in claim 6, characterized in that, Including: A gate dielectric layer is compliantly formed on the floating gate; and A control gate layer is formed on the gate dielectric layer, wherein the gate dielectric layer covers the fifth top surface and the sixth top surface, and the control gate layer fills the multiple gaps between the floating gates.
8. A flash memory device, characterized in that, include: A base, wherein the base has a platform, the platform having a first top surface and a plurality of first side surfaces connected to the first top surface; A tunneling dielectric pattern is set on the first top surface of the platform; A floating gate is disposed on the tunneling dielectric pattern, wherein the floating gate has a second bottom surface that contacts the tunneling dielectric pattern and a plurality of second side surfaces connected to the second bottom surface; Multiple insulating spacers are disposed on the second side surface of the floating grid near the second bottom surface; as well as Multiple isolation components are disposed on the first side of the platform, wherein multiple third top surfaces of the insulating spacer are coplanar with multiple fourth top surfaces of the isolation components, and the third top surfaces and the fourth top surfaces are higher than the second bottom surface of the floating grid.
9. The flash memory device as claimed in claim 8, characterized in that, The second bottom surface and the second side surface of the floating gate form multiple sharp angles, and the angle between each of the first side surfaces near the first bottom of each of the raised platforms and a first direction substantially parallel to the first top surface is less than or equal to 75 degrees.
10. The flash memory device as claimed in claim 8, characterized in that, A first lateral dimension of the first top surface is smaller than a second lateral dimension of the second bottom surface.