Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a forming method thereof. In one embodiment, a method includes providing a structure including a bottom source / drain feature, a bottom interlayer dielectric (ILD) layer disposed over the bottom source / drain feature, a top source / drain feature disposed over the bottom ILD layer and the bottom source / drain feature, and a top ILD layer disposed over the top source / drain feature. The method further includes forming a trench extending in the top ILD layer and the bottom ILD layer. The trench exposes a top surface and sidewalls of the top source / drain feature and a top surface of the bottom source / drain feature. The method further includes forming a first silicide layer on the top surface and sidewalls of the top source / drain feature and the top surface of the bottom source / drain feature, forming a second silicide layer on the first silicide layer, and forming a metal fill layer in the trench. The first silicide layer and the second silicide layer have different compositions.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each with smaller and more complex circuitry than its predecessor. Throughout this evolution, functional density (the number of interconnects per chip area) has generally increased, while geometry (the smallest component (or line) that can be produced using manufacturing processes) has decreased. This scaling down process typically provides benefits through increased production efficiency and reduced associated costs.

[0003] This scaling down also increases the complexity of integrated circuit processing and manufacturing, and similar advancements in integrated circuit processing and manufacturing are needed to achieve these progresses. For example, stacked device structures have been introduced to further reduce the density of advanced integrated circuit technology nodes. However, manufacturing such stacked device structures presents additional challenges. Therefore, existing implementations are not satisfactory in all aspects. Summary of the Invention

[0004] According to one aspect of the embodiments of this application, a method for forming a semiconductor structure is provided, comprising: providing a structure including: a bottom source / drain component, a bottom interlayer dielectric (ILD) layer disposed above the bottom source / drain component, a top source / drain component disposed above the bottom ILD layer and the bottom source / drain component, and a top ILD layer disposed above the top source / drain component; forming a trench extending in the top ILD layer and the bottom ILD layer, wherein the trench exposes the top surface and sidewalls of the top source / drain component and the top surface of the bottom source / drain component; forming a first silicide layer located on the top surface and sidewalls of the top source / drain component and on the top surface of the bottom source / drain component; forming a second silicide layer located on the first silicide layer, wherein the first silicide layer and the second silicide layer have different compositions; and forming a metal filling layer in the trench.

[0005] According to another aspect of the embodiments of this application, a method for forming a semiconductor structure is provided, comprising: providing a structure including source / drain components and an interlayer dielectric (ILD) layer disposed on the source / drain components; forming a contact trench in the ILD layer to expose a top surface and sidewalls of the source / drain components; forming a first silicide layer including a first horizontal portion on the top surface of the source / drain components and a first vertical portion on the sidewalls of the source / drain components; forming a second silicide layer on the first silicide layer, wherein the second silicide layer includes a second horizontal portion on the first horizontal portion and a second vertical portion along the first vertical portion; and forming a metal filler layer in the contact trench, wherein the first horizontal portion has a first thickness, the first vertical portion has a second thickness, the second horizontal portion has a third thickness, and the second vertical portion has a fourth thickness, wherein the first thickness is greater than the second thickness, and the third thickness is less than the fourth thickness.

[0006] According to another aspect of the embodiments of this application, a semiconductor structure is provided, comprising: a bottom transistor and a top transistor, the top transistor being disposed above the bottom transistor, wherein the bottom transistor includes a bottom source / drain component, and the top transistor includes a top source / drain component; a first silicide layer disposed on the top source / drain component and the bottom source / drain component; a second silicide layer disposed on the first silicide layer; and a metal filling layer disposed on the second silicide layer; wherein the first silicide layer and the second silicide layer have different compositions; wherein the first silicide layer includes a first horizontal portion on the top surface of the top source / drain component and a first vertical portion along the sidewall of the top source / drain component; and wherein the first horizontal portion has a first thickness, and the first vertical portion has a second thickness, the second thickness being less than the first thickness. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A flowchart of a method for forming a semiconductor structure according to one or more aspects of this disclosure is shown.

[0009] Figure 2 This illustrates one or more aspects of the present disclosure. Figure 1 A partial top view of an exemplary semiconductor structure during each manufacturing stage of the method.

[0010] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 10 , Figure 11 , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14 and Figure 15 This illustrates one or more aspects of the present disclosure. Figure 1 Partial cross-sectional views of exemplary semiconductor structures during various manufacturing stages of the method.

[0011] Figure 9A-1 , Figure 9A-2 , Figure 9A-3 , Figure 9B-1 and Figure 9B-2 This illustrates one or more aspects of the present disclosure. Figure 1 Partial schematic cross-sectional view of an exemplary semiconductor structure during each manufacturing stage of the method.

[0012] Figure 16 A flowchart of a method for forming a semiconductor structure according to one or more aspects of this disclosure is shown.

[0013] Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 and Figure 25 This illustrates one or more aspects of the present disclosure. Figure 16 Partial cross-sectional views of exemplary semiconductor structures during various manufacturing stages of the method. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. To simplify this disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to be limiting. For example, the formation of a first component on or over a second component in the following description may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components may not be formed in direct contact.

[0015] Furthermore, reference numerals and / or characters may be repeated in various instances of this disclosure. This repetition is for the purpose of brevity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed. Moreover, embodiments in this disclosure where a component is formed on, connected to, and / or coupled to another component may include embodiments where the components are formed in direct contact, and may also include embodiments where additional components can be inserted between the components, such that the components may not be formed in direct contact. Additionally, spatially relative terms (e.g., “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” etc.) and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to conveniently describe the relationship between one component and another in this disclosure. Spatially relative terms are intended to cover different orientations of the device including the component. Furthermore, when numerical values ​​or ranges are described using terms such as “about,” “approximately,” etc., these terms are intended to cover values ​​that are within a reasonable range considering the inherent variations in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a component having characteristics associated with that value, the value or range of values ​​covers a reasonable range including said value, such as within + / - 10% of said value. For example, a material layer with a thickness of “about 5 nm” can cover a size range of 4.25 nm to 5.75 nm, where a manufacturing tolerance of + / - 15% is known to those skilled in the art to be associated with depositing such a material layer.

[0016] Stacked transistor structures offer further density reductions for advanced integrated circuit (IC) technology nodes, particularly as technology nodes advance to 3 nanometers (N3) and below, especially when the stacked transistor structure includes multi-gate devices such as FinFETs, gate-all-around (GAA) transistors comprising nanowires and / or nanosheets, and other types of multi-gate devices. Stacked transistor structures include vertically stacked transistors. For example, a stacked transistor structure may include a first transistor (i.e., an upper / top transistor) positioned above a second transistor (i.e., a lower / bottom transistor). When the first and second transistors are of opposite conductivity types (i.e., an n-type transistor and a p-type transistor), the transistor stack can provide a complementary field-effect transistor (CFET).

[0017] Stacked transistor structures may include source / drain contacts. In some cases, stacked n-type and p-type transistors share a common source / drain (S / D) contact. This common S / D contact may be a local interconnect used to connect the n-type and p-type source / drain (S / D) epitaxial components together. Because the n-type and p-type epitaxial components are stacked on top of each other in the vertical direction, this local interconnect may need to penetrate through the top epitaxial component until it lands on the bottom epitaxial component. However, forming source / drain contacts in stacked devices presents various challenges, such as high resistance, high aspect ratio, and poor metal filling. Therefore, while existing stacked device structures (such as CFET structures) and their associated fabrication processes are generally sufficient to meet their intended purpose, they are not entirely satisfactory in all aspects.

[0018] This disclosure generally relates to stacked transistor structures having source / drain contacts. In an exemplary process, a structure (e.g., a CFET) is provided. This structure includes a bottom transistor disposed above a substrate and a top transistor disposed above the bottom transistor. The bottom transistor includes bottom source / drain components, and the top transistor includes a top source / drain component vertically positioned above the bottom source / drain components. A trench is formed to expose the bottom source / drain components and the top source / drain components. A first silicide layer comprising a first metal is formed on the exposed surfaces of the bottom source / drain components and the top source / drain components. A second silicide layer comprising a second metal is formed on the first silicide layer. Subsequently, a metal-filled layer is formed in the trench, and a planarization process is performed to remove excess material, thereby forming the source / drain contacts. The first silicide layer may be thicker on a horizontal surface (e.g., the horizontal surface of the top source / drain component) than on a vertical surface (e.g., the vertical surface of the top source / drain component). The second silicide layer can be thinner on a horizontal surface (e.g., the horizontal surface of the first silicide layer) than on a vertical surface (e.g., the vertical surface of the first silicide layer). By using different metals for the first and second silicide layers, the dipole effect can be improved, thereby reducing the resistance of the source / drain contact. Furthermore, since the first silicide layer is thinner on the vertical surface, the total thickness of the first and second silicide layers on the vertical surface is reduced, thus providing more space for the metal filler layer and avoiding voids in the metal filler layer. According to some other embodiments, a third silicide layer is formed instead of the first and second silicide layers, and a immersion process and post-treatment are performed after the formation of the third silicide layer to remove metal residues on the trench sidewalls. A metal filler layer is then formed in the trench. By removing metal residues from the trench sidewalls, the filling of the metal filler layer in the trench is improved, and the reliability and integrity of the source / drain contact can be enhanced.

[0019] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1This is a flowchart illustrating a method 100 for forming a semiconductor structure according to an embodiment of the present disclosure. The following is combined with... Figures 2 to 15 Description method 100. Figures 2 to 8 and Figures 10 to 15 It is based on Figure 1 Partial top views or cross-sectional views of the structure 200 of the embodiment of method 100 at different stages of manufacturing. Figures 9A-1 to 9B-2 It is based on Figure 1 A partial schematic cross-sectional view of the structure 200 of the embodiment of method 100 at different stages of manufacturing. Figure 16 This is a flowchart illustrating a method 300 for forming a semiconductor structure according to an embodiment of the present disclosure. The following is combined with... Figure 2 and Figures 17 to 25 Description method 300, Figures 17 to 25 It is based on Figure 16 Partial top views or cross-sectional views of the structure 400 of the embodiment of method 300 at different stages of manufacturing. Figure 3 , Figure 5 , Figure 7 , Figure 10 , Figure 14 , Figure 17 , Figure 19 , Figure 21 and Figure 24 It is along Figure 2 A partial cross-sectional view taken from line A-A'. Figure 4 , Figure 6 , Figure 8 , Figures 11 to 13B , Figure 15 , Figure 18 , Figure 20 , Figures 22-23 and Figure 25 It is along Figure 2 A partial cross-sectional view taken by line B-B'. Method 100 (or 300) is merely an example and is not intended to limit this disclosure to what is expressly shown in method 100 (or 300). Additional steps may be provided before, during, and after method 100 (or 300), and some of the steps described may be replaced, eliminated, or adapted for additional embodiments of method 100 (or 300). For brevity, not all steps are described in detail herein. Since structure 200 (or 400) will be fabricated as a semiconductor structure, structure 200 (or 400) may be referred to herein, depending on the context, as semiconductor structure 200 (or 400) or semiconductor device 200 (or 400). To avoid ambiguity, Figures 2 to 8 , Figures 10 to 15 and Figures 17 to 25The X, Y, and Z directions are perpendicular to each other and are used consistently throughout this disclosure. Throughout this disclosure, the same reference numerals denote the same parts, unless otherwise specified. That is, for various numbered elements described in association with a method or drawing, their material properties and comparisons should be applied to the same numbered elements described in association with different methods or different drawings.

[0020] refer to Figures 1-4 Method 100 includes a frame 102 in which a structure 200 is formed or provided. Figures 2-4 The invention has been simplified for clarity in order to better understand the inventive concept of this disclosure. Additional components may be added to structure 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of structure 200.

[0021] refer to Figure 2 Structure 200 includes an active region 204 extending longitudinally along the X direction and a gate structure 250 extending longitudinally along the Y direction. As will be further described below, the active region 204 includes a vertical stack of nanostructures (or channel components) stacked along the Z direction.

[0022] refer to Figures 3-4 Structure 200 includes a substrate 202 and various components (e.g., a stacked device structure 210) fabricated on the substrate 202. Structure 200 includes a fin-based structure 202B protruding from the substrate 202. Along the X direction, an active region 204 includes a channel region 204C interleaved with source / drain regions 204SD. The stacked device structure 210 includes a stack of devices disposed above the substrate 202, such as a top device 212T vertically stacked above a bottom device 212B. An insulating structure 216 is disposed between and separates devices 212T and 212B. The insulating structure 216 may be a single-layer / component or multi-layer / component structure, and in the depicted embodiment includes insulating structures 226M and 236. In the depicted embodiment, the stacked device structure 210 is monolithically fabricated and therefore may be referred to as a monolithic stacked device structure 210. According to some embodiments, the stacked device structure 210 is manufactured sequentially, and therefore may be referred to as a sequentially stacked device structure 210.

[0023] Devices 212T and 212B each include at least one electrical functional device, such as a top transistor 220T and a bottom transistor 220B, respectively. Therefore, the stacked device structure 210 includes a stack of transistors having a top transistor (e.g., transistor 220T) and a bottom transistor (e.g., transistor 220B), which are separated and / or electrically isolated from each other by an isolation structure 216. According to some embodiments, transistors 220B and 220T are transistors of opposite conductivity types. For example, transistor 220B is a p-type transistor and transistor 220T is an n-type transistor, or vice versa. In such embodiments, transistors 220B and 220T form a CFET. According to some embodiments, transistors 220B and 220T are transistors of the same conductivity type. For example, transistors 220B and 220T are both n-type transistors or both are p-type transistors.

[0024] Device 212T includes various components and / or assemblies, such as semiconductor layer 2080T, semiconductor layer 2080M, gate spacer 222, inner spacer 228, source / drain component 244 (also referred to as top source / drain component 244), contact etch stop layer (CESL) 246, interlayer dielectric (ILD) layer 248, and gate structure segment 250T. Device 212B also includes various components and / or assemblies, such as fin base structure 202B, semiconductor layer 2080B, semiconductor layer 2080M, isolation component 212, inner spacer 228, source / drain component 230 (also referred to as bottom source / drain component 230), substrate epitaxial region 224, CESL 232, ILD layer 234, and gate structure segment 250B. Gate structure segment 250T and gate structure segment 250B are collectively referred to as gate structure 250 of stacked device structure 210, such as the metal gate or high-k / metal gate of CFET. Semiconductor layers 2080B, 2080M and 2080T may be referred to individually or collectively as semiconductor layer 2080, depending on the context.

[0025] In the depicted embodiment, transistor 220B is a GAA transistor. For example, transistor 220B has two channels provided by semiconductor layer 2080B (also referred to as a channel layer), which is suspended over substrate 202 and extends between corresponding source / drain components (e.g., source / drain components 230). According to some embodiments, transistor 220B includes more or fewer channels (and therefore more or fewer semiconductor layers 2080B). Transistor 220B also has a gate structure segment 250B disposed above its semiconductor layer 2080B and between its source / drain components 230, with an inner spacer 228 disposed between its gate structure segment 250B and its source / drain components 230. Along the gate width direction (e.g., in the XZ plane), the gate structure segment 250B is located above the top semiconductor layer 2080B, between the semiconductor layers 2080B, and between the bottom semiconductor layer 2080B and the fin base structure 202B. Along the gate length direction (e.g., in the YZ plane), the gate structure segment 250B surrounds the semiconductor layer 2080B. During full-to-the-loop transistor operation, current can flow through the semiconductor layer 2080B and between the source / drain components 230. The semiconductor layer 2080M is suspended above the substrate 202 and extends between corresponding insulating structures 236, with insulating structures 226M disposed between the semiconductor layer 2080M of device 212B and the semiconductor layer 2080M of device 212T.

[0026] In the depicted embodiment, transistor 220T is also a GAA transistor. For example, transistor 220T has two channels provided by semiconductor layer 2080T (also referred to as a channel layer), which is suspended above substrate 202 and extends between corresponding source / drain components (e.g., source / drain components 244). According to some embodiments, transistor 220T includes more or fewer channels (and therefore more or fewer semiconductor layers 2080T). Transistor 220T also has a gate structure segment 250T disposed above its semiconductor layer 2080T and between its source / drain components 244, the gate structure segment 250T being disposed between corresponding gate spacers 222, and an inner spacer 228 being disposed between the gate structure segment 250T of transistor 220T and the source / drain components 244 of transistor 220T. Along the gate width direction, the gate structure segment 250T is located above the top semiconductor layer 2080T, between semiconductor layers 2080T, and between the bottom semiconductor layer 2080T and semiconductor layer 2080M. Along the gate length direction, the gate structure segment 250T surrounds the semiconductor layer 2080T. During operation of the all-around gate transistor, current can flow through the semiconductor layer 2080T and between the source / drain components 244.

[0027] Substrate 202, fin structure 202B, and semiconductor layer 2080 comprise elemental semiconductors (e.g., silicon and / or germanium); compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof); alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof); or combinations thereof. In the depicted embodiments, substrate 202, fin structure 202B, and semiconductor layer 2080 comprise silicon. According to some embodiments, the top semiconductor layer 2080T and the bottom semiconductor layer 2080B comprise different semiconductor materials, such as silicon and silicon-germanium, respectively, or vice versa. According to some embodiments, substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate. Substrate 202 and fin structure 202B may include various doped regions, such as p-wells and n-wells. n-wells are doped with n-type dopants, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. p-wells are doped with p-type dopants, such as boron, indium, other p-type dopants, or combinations thereof.

[0028] Isolation component 212 electrically isolates active device regions and / or passive device regions. For example, isolation component 212 separates the fin base structure 202B and electrically isolates it from each other and / or from other device regions / components. Isolation component 212 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, etc.) or combinations thereof. Isolation component 212 may have a multilayer structure. For example, isolation component 212 includes a bulk dielectric (e.g., an oxide layer) over a dielectric pad (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, or combinations thereof). In another example, isolation component 212 includes a bulk dielectric over a doped pad (e.g., borosilicate glass (BSG) pad and / or phosphosilicate glass (PSG) pad). The dimensions and / or characteristics of isolation component 212 are configured to provide shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, localized oxidation of silicon (LOCOS) structures, other suitable isolation structures, or combinations thereof. In the depicted embodiment, the isolation component 212 may be an STI.

[0029] Gate spacer 222 is disposed along the upper sidewall of gate structure segment 250T, inner spacer 228 is disposed below gate spacer 222 along the sidewall of gate structure segment 250T and / or gate structure segment 250B, and fin spacer 218 is disposed along the sidewall of base epitaxial region 224. Inner spacer 228 is located between semiconductor layers 2080B and 2080T and between the bottom semiconductor layer 2080B and fin base structure 202B. Gate spacer 222, inner spacer 228, and fin spacer 218 comprise a dielectric material, which may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, silicon carbide oxynitride, silicon carbide oxynitride, or combinations thereof). Gate spacer 222, inner spacer 228, and fin spacer 224 may comprise different materials and / or different configurations (e.g., different numbers of layers). According to some embodiments, the gate spacer 222, the inner spacer 228, the fin spacer 218, or combinations thereof have a multilayer structure. According to some embodiments, the gate spacer 222 and / or the fin spacer 218 include multiple sets of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or combinations thereof. Each set of spacers may have a different composition.

[0030] Bottom source / drain component 230 and top source / drain component 244 have the same or different compositions and / or materials depending on the configuration of their respective transistors. Bottom source / drain component 230 and top source / drain component 244 may be doped with n-type dopant and / or p-type dopant. According to some embodiments, bottom source / drain component 230 and / or top source / drain component 244 comprise silicon (e.g., Si:C epitaxial source / drain, Si:P epitaxial source / drain, or Si:C:P epitaxial source / drain) that may be doped with carbon, phosphorus, arsenic, other n-type dopant, or combinations thereof. According to some embodiments, bottom source / drain component 230 and / or top source / drain component 244 comprise silicon germanium or germanium, which may be doped with boron, other p-type dopant, or combinations thereof (e.g., Si:Ge:B epitaxial source / drain). According to some embodiments, the bottom source / drain component 230 and the top source / drain component 244 are of opposite conductivity types (e.g., n-type and p-type). According to some embodiments, the bottom source / drain component 230 is a p-type source / drain component (e.g., silicon-germanium comprising boron doping), and the top source / drain component 244 is an n-type source / drain component (e.g., silicon comprising phosphorus doping). According to some embodiments, the bottom source / drain component 230 and / or the top source / drain component 244 include multiple epitaxial semiconductor layers, wherein the epitaxial semiconductor layers may include the same or different materials and / or the same or different dopant concentrations. According to some embodiments, the bottom source / drain component 230 and / or the top source / drain component 244 include materials and / or dopants that achieve the desired tensile and / or compressive stresses in adjacent channel regions (e.g., formed by semiconductor layers 2080T and 2080B). As used herein, source / drain region, source / drain component, epitaxial source / drain, epitaxial source / drain component, etc., may refer to the source of a device, the drain of a device, or the source and / or drain of multiple devices.

[0031] The pedestal epitaxial region 224 may be disposed below the bottom source / drain component 230. The epitaxial region 224 serves to reduce leakage to the substrate 202. The pedestal epitaxial region 224 may include undoped semiconductor material. In the depicted embodiment, the pedestal epitaxial region 224 includes undoped silicon (Si), undoped silicon germanium (SiGe), or undoped germanium (Ge). The pedestal epitaxial region 224 may be deposited using vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable epitaxial deposition processes. The top surface of the pedestal epitaxial region 224 may be at the same level as the top surface of the fin base structure 202B.

[0032] Interlayer dielectric (ILD) layers 248 and 234 comprise dielectric materials such as silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, oxides formed from tetraethyl orthosilicate (TEOS), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorosilicate glass (FSG), degelatin, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutenyl (BCB) dielectric materials, polyimide, other suitable dielectric materials, or combinations thereof. According to some embodiments, ILD layer 248 and / or ILD layer 234 comprise dielectric materials with a dielectric constant less than that of silicon dioxide. Contact etch stop layers (CESL) 232 and CESL 246 comprise materials different from those of ILD layers 234 and 248, respectively. According to some embodiments, CESL 232 and CESL 246 comprise silicon nitride, and ILD layers 234 and 248 comprise silicon oxide. ILD layer 234, ILD layer 248, CESL232, CESL246, or combinations thereof may comprise a multilayer structure. ILD layer 234, ILD layer 248, CESL232, and CESL246 may be collectively referred to as the dielectric structure.

[0033] According to some embodiments, the insulating structure 226M includes a dielectric material that may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, silicon carbide oxynitride, silicon carbide oxynitride, or combinations thereof). In a further description of the depicted embodiments, the source / drain component 244 is separated and / or electrically isolated from the source / drain component 230 by the insulating structure 236. According to some embodiments, the insulating structure 236 may be formed from a portion of CESL 232 and ILD layer 234.

[0034] The gate structure 250 may include an interface layer 252 bordering the semiconductor layer 2080 and the fin structure 202B in the channel region 204C, a gate dielectric layer 254 above the interface layer 252, and a gate electrode 256 above the gate dielectric layer 254. The interface layer 252 may include a dielectric material, such as SiO2 or SiGeO. x HfSiO, SiON, other dielectric materials, or combinations thereof. According to some embodiments, the gate dielectric layer 254 includes a high-k dielectric layer. This high-k dielectric layer includes a high-k dielectric material, which typically refers to a dielectric material with a dielectric constant greater than that of silicon dioxide (k≈3.9), such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, and HfAlO. xZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, HfO2-Al2O3, other high-k dielectric materials, or combinations thereof. For example, the gate dielectric layer 254 comprises a hafnium-based oxide (e.g., HfO2) layer and / or a zirconium-based oxide (e.g., ZrO2) layer. According to some embodiments, the interface layer 252 and / or the gate dielectric layer 254 have a multilayer structure.

[0035] Gate electrode 256 may be disposed above gate dielectric layer 254. Gate electrode 256 includes at least one conductive gate layer. The conductive gate layer includes a conductive material, such as Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. According to some embodiments, gate electrode 256 includes a work function layer. This work function layer is a conductive layer tuned to have a desired work function (e.g., an n-type work function or a p-type work function for an n-type transistor or a p-type transistor, respectively). The work function layer comprises a work function metal and / or its alloy, such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, TiAlN, or combinations thereof. According to some embodiments, the gate electrode 256 comprises a bulk layer above the gate dielectric layer 254 and / or the work function layer. This bulk layer comprises a suitable conductive material, such as Al, W, Cu, Ti, Ta, TiN, TaN, polysilicon, other suitable metals and / or their alloys or combinations thereof. According to some embodiments, the gate electrode 256 comprises a barrier layer above the work function layer and / or the gate dielectric layer 254. The barrier layer includes materials that prevent or eliminate component diffusion and / or reactions between adjacent layers and / or materials that promote adhesion between adjacent layers (e.g., between a work function layer and a bulk layer). According to some embodiments, the barrier layer includes metals and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride (e.g., W₂N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), other suitable metal nitrides, or combinations thereof.

[0036] According to some embodiments, reference Figure 2 and Figure 4Structure 200 includes a gate isolation structure 260. In a top view, the gate isolation structure 260 may extend longitudinally along the X direction. In the depicted embodiment, the gate isolation structure 260 is disposed between two active regions 204. The gate isolation structure 260 may separate the gate structure 250 into two parts and electrically isolate the two parts. According to some embodiments, the gate isolation structure 260 includes silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbide oxynitride, silicon carbide nitride, or combinations thereof. In one embodiment, the gate isolation structure 260 includes a silicon nitride pad and a dielectric filler surrounded by the silicon nitride pad.

[0037] refer to Figure 1 , Figures 5-6 Method 100 includes a frame 104 in which a trench 268 is formed to expose a top source / drain component 244 and a bottom source / drain component 230.

[0038] Trench 268 may include a first type trench 268-1 and a second type trench 268-2. The first type trench 268-1 extends vertically through ILD layers 248 and 234 and CESLs 246 and 232 to expose both the top source / drain component 244 and the bottom source / drain component 230. The top surface and sidewalls (e.g., at least two facets) of the top source / drain component 244 and the top surface of the bottom source / drain component 230 are exposed in the first type trench 268-1. Therefore, the first type trench 268-1 has a first depth to the top surface of the top source / drain component 244 and a second depth to the top surface of the bottom source / drain component 230. The second type trench 268-2 extends through ILD layers 248 and CESL 246 to expose only the top source / drain component. Figure 5 and Figure 6 The second type of trench 268-2 can be configured to be the same or different. For clarity, the top source / drain component 244 and the bottom source / drain component 230 exposed in the first type of trench 268-1 are referred to as top source / drain component 244-1 and bottom source / drain component 230-1, respectively. Figure 6 The top source / drain component 244 exposed in the second type of trench 268-2 and the bottom source / drain component 230 below it are referred to as the top source / drain component 244-2 and the bottom source / drain component 230-2, respectively. Figure 5 The top source / drain component 244 exposed in the second type trench 268-2 and the bottom source / drain component 230 below it are referred to as the top source / drain component 244-3 and the bottom source / drain component 230-3, respectively.

[0039] According to some embodiments, a patterning process is performed on the dielectric layers (e.g., ILD layers 248 and 234 and CESL 246 and 232) to form trench 268. According to some embodiments, a portion of the top source / drain component 244 is removed during the patterning process. A first type trench 268-1 and a second type trench 268-2 may be formed in different patterning processes. Forming the first type trench 268-1 may include more than one patterning process to extend the first type trench 268-1 to a first depth and a second depth.

[0040] The patterning process may include multiple photolithography and etching processes. The photolithography process may include forming a patterned mask layer (e.g., patterned mask layer 266) over ILD layer 248. Patterned mask layer 266 may include multiple dielectric layers, such as etch stop layers (ESL) 262-1, ILD layers 264-1, ESL 262-2, and ILD layers 264-2 stacked on top of each other as shown. Patterned mask layer 266 has openings, each opening overlapping a portion of a corresponding source / drain region 204SD in a top view. The etching process may include transferring the pattern in patterned mask layer 266 to the dielectric layers and / or source / drain components 244 / 230 beneath it, for example by removing portions of ILD layers 248 and 234, ESL 246 and 232, and / or source / drain components 244 / 230 exposed by the openings. The etching process may include dry etching, wet etching, other suitable etching processes, or combinations thereof.

[0041] Still referencing Figure 1 , Figures 5-6 Method 100 includes a frame 106, wherein a dielectric pad 270 is formed on the sidewall of a trench 268.

[0042] The dielectric pad 270 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon carbide oxide, SiOCN film, and / or combinations thereof. According to some embodiments, the dielectric pad 270 includes silicon nitride. For example, the dielectric pad 270 may be formed by conformally depositing a dielectric material layer over the structure 200 using a chemical vapor deposition (CVD) process, a sub-atmospheric pressure CVD (SACVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, or other suitable processes. In the illustrated embodiment, an etch-back (e.g., anisotropic) process is performed after the dielectric material layer is deposited to remove the dielectric material layer from the bottom portions of the horizontal surface and sidewall surfaces of the trench 268. According to some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or combinations thereof. According to some embodiments, the etch-back process includes a directional etching process (e.g., tilted plasma etching), wherein the ion beam may be oriented at a tilt angle relative to the Z-direction to the surface of the structure 200. In one embodiment, the bottom portion of the trench 268 sidewalls beneath the top source / drain component 244-1 is exposed after the etch-back process. A dielectric material layer may be retained on the exposed sidewalls of the ILD layer 248, CESL 246, and gate isolation structure 260 as a dielectric pad 270. The dielectric pad 270 prevents diffusion between the metal filler layer (described below) and the dielectric layer (e.g., ILD layer 248, CESL 246). According to some embodiments, the deposited dielectric pad 270 is first processed to alter its composition. In this case, the processed portion of the dielectric pad 270 is retained during the etch-back process, while the unprocessed portion is removed by the etch-back process. In a further description of the embodiment, the dielectric pad 270 comprises silicon oxide, and the processing includes tilted ion implantation using appropriate ions (e.g., nitrogen ions) to introduce nitrogen into the bottom portion of the dielectric pad 270. Subsequently, the processed portion of the dielectric pad 270 is selectively removed by the etch-back process using an appropriate etchant (e.g., phosphoric acid).

[0043] Still referencing Figure 1 , Figure 5 and Figure 6 Method 100 includes block 108, wherein a first silicide layer is formed on the exposed surfaces of source / drain components 230-1, 244-1, 244-2, and 244-3. Prior to forming the first silicide layer, a cleaning process may be performed to remove any debris from the surface of trench 268. According to some embodiments, the cleaning process includes purging a carrier gas (e.g., an inert gas) to clean the surface of structure 200.

[0044] exist Figure 5 and Figure 6In this configuration, the first silicide layer 272 may include first silicide layers 272-3, 272-2, 272T, and 272B respectively disposed on source / drain components 244-3, 244-2, 244-1, and 230-1. The first silicide layers 272-3, 272-2, 272T, and 272B may be collectively referred to as the first silicide layer 272 or individually, depending on the context. Forming the first silicide layer 272 may include depositing a first metal layer 274 onto the structure 200 (including the exposed surfaces of the source / drain components 230 and 244 in the trench 268) and performing a first thermal process (e.g., annealing) on ​​the structure 200 to cause the components of the source / drain components 230 and 244 to react with the metal components in the first metal layer 274.

[0045] Depositing a first metal layer 274 on the exposed surfaces of source / drain components 230 and 244 in trench 268 can be performed using a suitable deposition process (e.g., physical vapor deposition (PVD)). A first thermal process can be performed at a first temperature greater than about 400°C, for example, about 400°C to about 500°C. According to some embodiments, the first thermal process consumes and converts portions of source / drain components 244-3, 244-2, 244-1, and 230-1 to form first silicide layers 272-3, 272-2, 272T, and 272B, respectively. The first metal layer 274 may include any metal component suitable for promoting silicide formation, such as zirconium, nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, other suitable metals, or combinations thereof. When the source / drain components are n-type, the metal component may include Ti, Zr, Hf, Sc, Y, Yb, La, Er, Dy, Ce, or combinations thereof. When the source / drain component is p-type, the metal composition may include Al, W, Mo, Co, Ru, Re, Rh, Ir, Pt, Ni, Pd, Nb, V, or combinations thereof. The metal composition may be selected based on the conductivity type (or type, e.g., p-type or n-type) of the source / drain component 244 or the source / drain component 230. According to some embodiments, the metal composition is selected based on the conductivity type of the respective source / drain component 244. For example, the source / drain component 244 is n-type, and the metal composition of the first silicide layer includes Ti, Zr, Hf, Sc, Y, Yb, La, Er, Dy, Ce, or combinations thereof. Therefore, the first silicide layer 272 includes the metal composition and the composition of the source / drain components 244-3, 244-2, 244-1, and 230-1 (e.g., silicon and / or germanium). According to some embodiments, the first metal layer 274 is a zirconium-containing layer, and the first silicide layer 272 comprises zirconium and silicon, and may be referred to as a zirconium silicide layer. In the PVD process, the deposition direction can be controlled such that the deposition amount of the first metal layer 274 on a horizontal surface (e.g., the top surface) can be selectively greater than the deposition amount on a vertical surface (e.g., the sidewalls). Therefore, the thickness of the first metal layer 274 on the horizontal surface is greater than its thickness on the vertical surface. The thickness of the first metal layer 274 on the sidewalls of the trench 268 can be less than about 3 nm. Any unreacted metal (e.g., any remaining portion of the first metal layer 274) can be selectively removed by any suitable process.

[0046] refer to Figure 1 , Figures 7-8 Method 100 includes block 110, wherein a second silicide layer 276 is formed over a first silicide layer 272.

[0047] exist Figures 7-8In this configuration, the second silicide layer 276 may include second silicide layers 276-3, 276-2, 276T, and 276B respectively disposed on the first silicide layers 272-3, 272-2, 272T, and 272B. The second silicide layers 276-3, 276-2, 276T, and 276B may be collectively referred to as the second silicide layer 276 or individually, depending on the context. Forming the second silicide layer 276 may include depositing a second metal layer (not shown) onto the structure 200 (including the first silicide layer 272) at a second temperature of about 350°C to about 450°C, allowing the components of the source / drain components 230 and 244 to diffuse through the first silicide layer 272 and react with the metal components in the second metal layer. Any unreacted metal (e.g., remaining portions of the second metal layer) may be selectively removed by any suitable process. Removing the remaining portion of the second metal layer may also remove portions of the first silicide layer 272 at the bottom of the trench 268 and the source / drain components 230 and / or 240, thereby exposing the sides of the source / drain components 244-3, 230-1 and 244-2.

[0048] The deposition of the second metal layer can be performed using a suitable deposition process, such as chemical vapor deposition (CVD) or plasma-enhanced CVD. According to some embodiments, the components (e.g., silicon) of the source / drain components 244-3, 244-2, 244-1, and 230-1 diffuse through the first silicide layers 272-3, 272-2, 272T, and 272B, respectively, and react with the metal components in the second metal layer to form second silicide layers 276-3, 276-2, 276T, and 276B, respectively. In embodiments where the sides of the surfaces of the source / drain components 244-3, 244-2, and 230-1 are exposed, the components of that portion of the source / drain components 244-3, 244-2, and 230-1 on the surface can react with the second metal layer to form a portion of the second silicide layer 276. The second metal layer may include any metal component suitable for promoting silicide formation, such as titanium (Ti), zirconium (Zr), nickel (Ni), platinum (Pt), palladium (Pd), vanadium (V), cobalt (Co), tantalum (Ta), ytterbium (Yb), other suitable metals, or combinations thereof. When the source / drain component is n-type, the metal component may include Ti, Zr, hafnium (Hf), scandium (Sc), yttrium (Y), Yb, lanthanum (La), erbium (Er), dysprosium (Dy), cerium (Ce), or combinations thereof. When the source / drain component is p-type, the metal component may include aluminum (Al), tungsten (W), molybdenum (Mo), Co, ruthenium (Ru), rhenium (Re), rhodium (Rh), iridium (Ir), Pt, Ni, Pd, niobium (Nb), V, or combinations thereof. Therefore, the second silicide layer 276 includes the metal component and the component of the source / drain component 244 or 230 (e.g., silicon and / or germanium). According to some embodiments, the second metal layer is a titanium-containing layer, and the second silicide layer 276 comprises titanium and silicon, and may be referred to as a titanium silicide layer. The second metal layer may differ from the first metal layer 274. For example, when the source / drain component is n-type, the electronegativity of the second metal layer may be greater than that of the first metal layer 274. For example, when the source / drain component is p-type, the electronegativity of the second metal layer may be lower than that of the first metal layer 274. This difference in electronegativity can lead to an improved dipole effect, thereby reducing the resistance between the metal fill layer to be formed in the trench 268 and the source / drain components 230 and / or 244. The metal composition of the first metal layer 274 and the second metal layer may be selected according to the conductivity type (e.g., p-type or n-type) of the source / drain component 244 or the source / drain component 230. According to some embodiments, the metal composition of the first metal layer 274 and the second metal layer is selected according to the conductivity type of the source / drain component 244. For example, the source / drain component 244 is an n-type source / drain component, and the metal composition of the second metal layer includes Ti, Zr, Hf, Sc, Y, Yb, La, Er, Dy, Ce or combinations thereof, and the electronegativity of the second metal layer can be greater than that of the first metal layer 274.According to some embodiments, the first silicide layer 272 includes zirconium silicide and the second silicide layer 276 includes titanium silicide.

[0049] The silicide layers (e.g., first silicide layer 272-2 and second silicide layer 276-2) on the source / drain component 244-2, the silicide layers (e.g., first silicide layer 272-3 and second silicide layer 276-3) on the source / drain component 244-3, and the silicide layers (e.g., first silicide layer 272T / 272B and second silicide layer 276T / 276B) on the source / drain components 244-1 and 230-1 may be formed simultaneously or separately. According to some embodiments, the source / drain components 244 are of the same type (e.g., n-type), and the source / drain components 230 are of the opposite type (e.g., p-type). According to some embodiments, the first silicide layer 272 on the source / drain components 244-2, 244-1, 230-1, and 244-3 comprises the same metal (e.g., selected from Ti, Zr, Hf, Sc, Y, Yb, La, Er, Dy, Ce, or combinations thereof), and the second silicide layer 276 on the source / drain components 244-2, 244-1, 230-1, and 244-3 comprises the same metal (e.g., selected from Ti, Zr, Hf, Sc, Y, Yb, La, Er, Dy, Ce, or combinations thereof). According to some embodiments, the silicide layer on source / drain component 244-2, the silicide layer on source / drain component 244-3, and the silicide layers on source / drain components 244-1 and 230-1 comprise different metals (e.g., independently selected from Ti, Zr, Hf, Sc, Y, Yb, La, Er, Dy, Ce, or combinations thereof). According to other embodiments, source / drain component 244-2 is of the opposite type to source / drain components 244-1 and 244-3. For example, source / drain component 244-2 is p-type, and its silicide layer comprises a metal composition selected from Al, W, Mo, Co, Ru, Re, Rh, Ir, Pt, Ni, Pd, Nb, V, or combinations thereof. For example, source / drain components 244-1 and 244-3 are n-type, and the silicide layer thereon includes a metal composition selected from Ti, Zr, Hf, Sc, Y, Yb, La, Er, Dy, Ce or combinations thereof.

[0050] According to some embodiments, the operation of block 110 further includes performing a nitriding process on the second silicide layer 276. This nitriding process is optional. The nitriding process includes purging nitrogen gas over the second silicide layer 276, thereby converting a surface portion of the second silicide layer 276 into a nitrogen-containing layer 276'. Therefore, the nitrogen-containing layer 276' further comprises nitrogen compared to the second silicide layer 276. According to some embodiments, the nitrogen-containing layer 276' comprises titanium, silicon, and nitrogen. According to some embodiments, the nitrogen-containing layer 276' comprises titanium silicon nitride (TiSiN). The thickness of the nitrogen-containing layer 276' may be less than about 3 nm and may protect the underlying second silicide layer 276 from oxidation in subsequent processes. According to some embodiments, the formation of the second silicide layer 276 and the performance of the nitriding process are carried out in situ at a second temperature. For simplicity, the nitrogen-containing layer 276' is not depicted further.

[0051] According to some embodiments, performing the first thermal process and forming the second silicide layer 276 are combined in the same process. Figure 9A-1 , Figure 9A-2 , Figure 9A-3 A partial schematic cross-sectional view of the surface of the source / drain components 230 or 244 is shown during operation of blocks 108 and 110. According to some embodiments, a first metal layer 274 (such as...) is deposited. Figure 9A-1 (As shown) is performed at a temperature below approximately 60°C (e.g., room temperature). According to some embodiments, a first thermal process (such as...) is carried out. Figure 9A-2 (as shown) and forming a second silicide layer 276 (as shown) Figure 9A-3 The process (as shown) is performed simultaneously at temperatures greater than about 400°C (e.g., about 400°C to about 500°C). If the temperature is too low (e.g., below about 400°C), the formation of the first silicide layer 272 and the second silicide layer 276 may be too slow. If the temperature is too high (e.g., greater than about 500°C), existing components of structure 200 (e.g., source / drain components 230 and 244) may be damaged. The first thermal process and the operation of execution block 110 can be performed in situ (e.g., in the same chamber). According to some embodiments, depositing the second metal layer includes applying a precursor, such as a metal halide (e.g., TiCl4), to structure 200. This precursor can remove any remaining portion of the first metal layer 274 (e.g., ...). Figure 9A-2 (As shown) and a second silicide layer 276 is formed. The metal halide may include the metal of the second silicide layer 276. Optionally, a nitrogen-containing layer 276' may be formed. Figure 9A-1 , Figure 9A-2 , Figure 9A-3 In the illustrated embodiment, the total thermal energy consumed can be reduced because the deposition of the first metal layer 274 is performed at a relatively low temperature, and the execution of the first thermal process and the operation of the execution block 110 are performed in situ and / or simultaneously.

[0052] According to some other embodiments, a first thermal process is performed at block 108 before the operation of block 110. Figure 9B-1 , Figure 9B-2 A partial schematic cross-sectional view of the surface of the source / drain components 230 or 244 is shown during operation of blocks 108 and 110. In such embodiments, a first metal layer 274 is deposited and a first thermal process (such as...) is performed at block 108. Figure 9B-1 (As shown) can be performed simultaneously in the same chamber at a temperature greater than about 400°C (e.g., about 400°C to about 500°C). In such embodiments, depositing the first metal layer 274 and performing the first thermal process can be collectively referred to as performing a high-temperature PVD process. After performing the high-temperature PVD process, any suitable process can be performed to remove any remaining portion of the first metal layer 274. For example, by purging the halide gas and / or applying the aforementioned precursor. A second silicide layer 276 is formed (e.g. Figure 9B-2 (As shown) can be performed in the same or different chambers as box 108. Optionally, a nitrogen-containing layer 276' can be formed.

[0053] Various parameters of the operation of blocks 108 and 110 (e.g., PVD process, CVD process) can be tuned to achieve the designed thickness of the first silicide layer 272 and the second silicide layer 276 (described below), such as gas composition, temperature, duration, pressure, gas flow rate, source power, bias power, bias voltage, other suitable parameters or combinations thereof.

[0054] refer to Figure 1 , Figures 10-13B Method 100 includes a frame 112, wherein a metal filler layer 278 is filled in a trench 268. Figure 12A and Figure 13A Various embodiments are shown. Figure 11 Enlarged view of part C of structure 200. Figure 12B and Figure 13B Illustrations are shown according to some embodiments Figure 11 Enlarged view of part E of structure 200.

[0055] A metal filler layer 278 may be formed over the second silicide layer 276. The metal filler layer 278 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by chemical CVD, PVD, ALD, electroplating, or other suitable processes. According to some embodiments, the metal filler layer 278 includes tungsten (W). According to some embodiments, the metal filler layer 278 includes multiple layers. According to some embodiments, the structure 200 further includes a metal pad between the metal filler layer 278 and the surrounding dielectric material. According to some embodiments, the metal pad is located between the metal filler layer 278 and the second silicide layer 276.

[0056] reference Figure 12AA first silicide layer 272T on the sidewalls 244-1s and top surface 244-1a of the source / drain component 244-1 has different thicknesses, and a second silicide layer 276T above the sidewalls 244-1s and top surface 244-1a has different thicknesses. The top surface 244-1a of the source / drain component 244-1 may be curved and descend towards the sidewalls 244-1s as shown. According to some embodiments, the first silicide layer 272T has a thickness T1 (or vertical thickness T1) along a vertical line 280 and a thickness T2 (or horizontal thickness T2) along a horizontal line 282. The vertical line 280 intersects the top surface 244-1a, and the horizontal line 282 intersects the sidewalls 244-1s. According to some embodiments, T2 is less than about 3 nm, for example, about 1 nm. T1 may be greater than T2. ​​The ratio of T1 to T2 is about 2 to about 10. This can stem from the deposition of a first metal layer 274 at frame 108, wherein the amount of the first metal layer 274 deposited on the top surface 244-1a can be greater than the amount deposited on the sidewalls 244-1s. The relatively thin T2 leaves more space for the metal filler layer 278 in the trench 268-1 (e.g., the region between the second silicide layer 276T and the opposite sidewalls of the trench 268-1), thereby mitigating the necking profile therein. Therefore, filling the trench 268-1 with the metal filler layer 278 can be improved. According to some embodiments, no air gaps are formed in the metal filler layer 278. According to some embodiments, the second silicide layer 276T has a thickness T3 (or vertical thickness T3) along the vertical line 280 and a thickness T4 (or horizontal thickness T4) along the horizontal line 282. T3 can be less than T4. The ratio of T3 to T4 can be from about 2:3 to about 1:10. This can stem from the different thicknesses (e.g., T1 and T2) of the first silicide layer 272T. In an example, when the second silicide layer 276T is formed, the amount of component (e.g., Si) of the source / drain component 244-1 diffused through the thinner portion (e.g., the portion with thickness T2) of the first silicide layer 272T is greater than the amount of component of the source / drain component 244-1 diffused through the thicker portion (e.g., the portion with thickness T1) of the first silicide layer 272T. According to some embodiments, the ratio of T1 to T3 is approximately 3:2 to approximately 20:1. If this ratio is too small (e.g., less than approximately 3:2), T1 may be too small, and the dipole effect at silicide layers 272T and 276T may be too small; or T3 may be too large, and the resistance of the source / drain contact may be too large. If the ratio is too large (e.g., greater than about 20:1), T3 may be too small, resulting in an insufficient dipole effect; or T1 may be too large, leading to excessive resistance in the source / drain contacts. According to some embodiments, the ratio of T2 to T4 may be from about 1:2 to about 1:20.If the ratio is too small (e.g., less than about 1:20), T2 may be too small, resulting in an insufficient dipole effect; or T4 may be too large, causing the second silicide layer 276T to occupy too much space, which could lead to failure of the metal filling layer 278 in the trench 268-1 to fill (e.g., the formation of voids). If the ratio is too large (e.g., greater than about 1:2), T2 may be too large, which could lead to failure of the metal filling layer 278 in the trench 268-1 to fill; or T4 may be too small, resulting in an insufficient dipole effect.

[0057] refer to Figure 12B For similar reasons, the first silicide layer 272B may have various thicknesses at different locations along the Y direction. For example, along vertical lines 284 and 286, the first silicide layer 272B has a thickness T5 (or vertical thickness T5) and a thickness T6 (or vertical thickness T6), respectively. Vertical line 286 is closer to the vertical centerline of the first silicide layer 272B than vertical line 284. Therefore, the first silicide layer 272B may be thicker in the middle portion than on the sides. According to some embodiments, along vertical lines 284 and 286, the second silicide layer 276B has a thickness T7 (or vertical thickness T7) and a thickness T8 (or vertical thickness T8), respectively. According to some embodiments, the ratio of T5 to T7 is approximately 1:2 to approximately 1:20. If the ratio is too small (e.g., less than about 1:20), T5 may be too small, resulting in an insufficient dipole effect at silicide layers 272T and 276T; or T7 may be too large, leading to excessive resistance in the source / drain contacts. If the ratio is too large (e.g., greater than about 1:2), T5 may be too large, resulting in excessive resistance in the source / drain contacts; or T7 may be too small, resulting in insufficient dipole effect. The ratio of T6 to T8 can be from about 1:1.5 to about 1:5. If the ratio is too small (e.g., less than about 1:5), T8 may be too large, resulting in excessive resistance in the source / drain contacts, and potentially excessive time and cost; or T6 may be too small, resulting in insufficient dipole effect. If the ratio is too large (e.g., greater than about 1:1.5), T6 may be too large, resulting in excessive resistance in the source / drain contacts, and potentially excessive time and cost; or T8 may be too small, resulting in insufficient dipole effect.

[0058] Figure 13A and Figure 13B Alternate enlarged views of portions C and E are shown respectively. (Reference) Figure 13AThe top surface 244-1a and sidewall 244-1s are connected by rounded corners. In the depicted embodiment, the thickness of the first silicide layer 272T gradually decreases from top to bottom. The thickness of the layer is measured in a direction perpendicular to the surface (e.g., top surface 244-1a, sidewall 244-1s, rounded corners), depending on the location of the thickness. In the depicted embodiment, the thickness of the second silicide layer 276T gradually increases from top to bottom. According to some embodiments, the sum of the thicknesses of the first silicide layer 272T and the second silicide layer 276T is approximately the same from top to bottom. For example, the sum at a point on the top surface 244-1a is approximately the same as the sum at a point on the sidewall 244-1s. (See reference...) Figure 13B The first silicide layer 272B and the second silicide layer 276B may each have an arcuate shape. According to some embodiments, the thickness of the second silicide layer 276B is greater than the thickness of the first silicide layer 272B.

[0059] It should be noted that the thickness of the nitrogen-containing layer 276' (if present) is included in the thickness of the second silicide layer 276 described above. The thicknesses of the first silicide layer 272 and the second silicide layer 276 disclosed above can improve the dipole effect at the interface between the first silicide layer 272, the second silicide layer 276 and the source / drain components 244 and / or 230, thereby reducing the resistance of the source / drain contacts (described below).

[0060] refer to Figure 1 , Figures 14-15 Method 100 includes block 114, in which a planarization operation (e.g., a CMP process) is performed to remove excess material. The planarization process may be performed until the ESL (e.g., ESL 262-2) is reached and exposed, which serves as a planarization stop layer. The remaining portions of the metal filler layer 278, the first silicide layer 272, and the second silicide layer 276 form the source / drain contacts 288-1, 288-2, and 288-3 shown.

[0061] Structure 200 may undergo further processes to form various components and regions known in the art. For example, subsequent processes may form additional interlayer dielectric (ILD) layers, contacts / vias / wires, and multilayer interconnect components (e.g., metal layers and interlayer dielectric layers) over substrate 202, configured to connect various components to form a functional circuit that may include one or more devices (including semiconductor device 200). In a further illustration of this example, the multilayer interconnects may include vertical interconnects (e.g., vias or contacts) and horizontal interconnects (e.g., metal lines). The various interconnect components may be made of various conductive materials, including copper, tungsten, and / or silicides. In one example, a copper-associated multilayer interconnect structure is formed using a damascene process and / or a dual damascene process.

[0062] although Figures 2-15The illustration shows a stacked transistor structure with an all-ring gate transistor, but other examples of semiconductor devices (such as multi-gate devices, stacked transistor structures with any combination of transistors, such as planar transistors, fin field-effect transistors, nanosheet transistors, and nanowire transistors) can benefit from various aspects of this disclosure.

[0063] refer to Figure 16 , Figures 2-4 Method 300 includes block 302, in which structure 400 is provided or formed. The operation of block 302 is similar to the operation of block 102 of method 100 described above. At this stage, structure 400 is similar to structure 200 at block 102.

[0064] refer to Figures 16-18 Method 300 includes frame 304, in which a trench 268 is formed to expose a top source / drain component 244 and a bottom source / drain component 230; and frame 306, in which a dielectric pad 270 is formed. The operation of frames 304 and 306 is similar to that of frames 104 and 106, respectively.

[0065] Still referencing Figures 16-18 Method 300 includes block 308, wherein a third silicide layer 290 is formed on the exposed surfaces of source / drain components 230 and 244. A cleaning process similar to that in block 108 may be performed prior to the formation of the third silicide layer 290.

[0066] exist Figures 17-18 In this embodiment, the third silicide layer 290 may include third silicide layers 290-3, 290-2, 290T, and 290B respectively disposed on source / drain components 244-3, 244-2, 244-1, and 230-1. The third silicide layers 290-3, 290-2, 290T, and 290B may be collectively referred to as the third silicide layer 290 or individually, depending on the context. Forming the third silicide layer 290 may include depositing a third metal layer 292 over structure 400 (including the exposed surfaces of source / drain components 230 and 244 in trench 268) at a third temperature of about 400°C to about 450°C, such that the components of source / drain components 230 and 244 react with the metal components in the third metal layer 292.

[0067] Depositing a third metal layer 292 above the exposed surfaces of the source / drain components 230 and 244 in trench 268 can be performed using a suitable deposition process (e.g., CVD process, plasma-enhanced CVD process). According to some embodiments, the deposition of the third metal layer 292 includes a CVD process. The third metal layer 292 may also be deposited on the sidewalls of the dielectric material (e.g., CESL 246 and 232, dielectric pad 270, ILD layer 234) of trench 268, and above the gate isolation structure 260 and the patterned mask layer 266. According to some embodiments, the third metal layer 292 on the dielectric sidewalls is thicker than the third metal layer 292 on the exposed surfaces of the source / drain components 230 and 244.

[0068] According to some embodiments, at a third temperature, portions of the source / drain components 244-3, 244-2, 244-1, and 230-1 are consumed and transformed into third silicide layers 290-3, 290-2, 290T, and 290B, respectively. The third metal layer 292 may include any metal component suitable for promoting silicide formation, such as zirconium, nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, other suitable metals, or combinations thereof. When the source / drain components are n-type, the metal component may include Ti, Zr, Hf, Sc, Y, Yb, La, Er, Dy, Ce, or combinations thereof. When the source / drain components are p-type, the metal component may include Al, W, Mo, Co, Ru, Re, Rh, Ir, Pt, Ni, Pd, Nb, V, or combinations thereof. The metal composition of the third metal layer 292 can be selected based on the conductivity type (e.g., p-type or n-type) of the source / drain component 244 or the source / drain component 230. According to some embodiments, the metal composition is selected based on the conductivity type of the source / drain component 244. Therefore, the third silicide layer 290 includes the metal composition and the composition of the source / drain components 244-3, 244-2, 244-1, and 230-1 (e.g., silicon and / or germanium). According to some embodiments, the third metal layer 292 is a zirconium-containing layer, and the third silicide layer 290 includes zirconium and silicon, and may be referred to as a zirconium silicide layer. According to some embodiments, after the third silicide layer 290 is formed, unreacted metal (e.g., the remaining portion of the third metal layer 292) is retained in the trench 268.

[0069] refer to Figure 16 , Figures 19-20 Method 300 includes block 310, in which a soaking process is performed. This soaking process removes unreacted metal (e.g., the remainder of the third metal layer 292).

[0070] According to some embodiments, the immersion process includes purging a halide gas over structure 400 at a temperature of about 350°C to about 450°C. This halide gas may react with the remainder of the third metal layer 292. The halide gas may include hydrogen chloride (HCl), hydrogen fluoride (HF), chlorine (Cl2), boron trichloride (BCl3), or combinations thereof. According to some embodiments, the halide gas includes metal halides, such as the precursor described above with respect to block 110. In such embodiments, a fourth silicide layer comprising a metal from the metal halide may be formed over the third silicide layer, similar to forming a second silicide layer 276 over the first silicide layer 272. Byproduct residues containing halide from the immersion process may remain on the dielectric surface (e.g., sidewalls) of trench 268.

[0071] According to some embodiments, method 300 includes multiple cycles of depositing a third metal layer 292 and performing an immersion process. This improves control over the formation of the third silicide layer 290 and the removal of excess third metal layer 292, while protecting the third silicide layer 290 from halide gases. According to some embodiments, the deposition of the third metal layer 292 and the immersion process are performed simultaneously. In other words, while the third metal layer 292 is deposited at a third temperature, halide gases flow over the structure 400. Simultaneous flow of halide gases can mitigate the deposition of the third metal layer 292 on the dielectric material of the trench 268.

[0072] Still referencing Figure 16 , Figures 19-20 Method 300 includes block 312, wherein a post-processing step is performed to remove byproduct residues containing halide gases (e.g., Cl, F). Removing byproduct residues reduces the resistance of the source / drain contacts to be formed.

[0073] According to some embodiments, the post-processing includes performing a plasma process. According to some embodiments, the plasma process uses an inert gas (e.g., argon (Ar) and helium (He)) to generate plasma to remove byproduct residues. According to some embodiments, the plasma process uses a reactive gas (e.g., hydrogen (H2), ammonia (NH3), hydrazine (N2H4), or a combination thereof). In such embodiments, the reactive gas may react with the byproduct residues and / or may generate plasma to remove the byproduct residues. In embodiments where the reactive gas includes a nitrogen-containing gas (e.g., NH3, N2H4), the nitrogen-containing gas may react with a surface portion of the third silicide layer 290 to form a nitrogen-containing layer, similar to the formation of the nitrogen-containing layer 276' described above in block 110. In embodiments where the reactive gas does not include a nitrogen-containing gas (e.g., NH3, N2H4), a nitriding process similar to that described above may be performed on the structure 400. According to some embodiments, the plasma process uses both inert and reactive gases simultaneously. The post-processing may be performed at a temperature of about 350°C to about 450°C.

[0074] Operations on frames 308, 310, and 312 can be performed in situ. According to some embodiments, deposition of the third metal layer 292, immersion processing, and post-processing are performed in the same chamber, thereby reducing associated time and cost. By performing the immersion process and post-processing, a significant portion (e.g., more than about 95%) of the remaining portion of the third metal layer 292 is removed from the sidewalls of the dielectric material in trench 268. Therefore, more space is left for the metal fill layer to be formed in trench 268, resulting in improved integration of the source / drain contacts in planarization processes (e.g., CMP), reduced resistance of the source / drain contacts, and improved reliability of structure 400. Performing the immersion process and post-processing is particularly advantageous when the third metal layer 292 on the sidewalls of the dielectric material in frame 308 is thicker than the third metal layer 292 on the exposed surfaces of the source / drain components 230 and 244.

[0075] refer to Figure 16 , Figures 21-23 Method 300 includes box 314, in which a metal filler layer 278 is filled in the trench 268, similar to the description of box 112 above. Figure 23 Various embodiments are shown. Figure 22 Enlarged view of part F of the 400 structure in the middle.

[0076] refer to Figure 23In trench 268, a significant portion (e.g., greater than about 95%) of the third metal layer 292 is removed during the immersion process. According to some embodiments, the thickness T9 of the remaining portion 292' of the third metal layer 292 on the sidewalls of the dielectric material (e.g., dielectric pad 270, CESL 232, and ILD layer 234) is less than about 1 nm, for example, about 0.5 nm. In the depicted embodiment, the vertical thickness T10 of the third silicide layer 290B is approximately 5 nm to about 7 nm. According to some embodiments, the ratio of T10 to T9 is approximately 10 to about 100. If this ratio is too small (e.g., less than about 10), T9 may be too large, resulting in excessive remaining portion 292' and insufficient removal of the third metal layer 292, which could affect the reliability and integrity of the source / drain contacts. If this ratio is too large (e.g., greater than about 100), T10 may be too large, resulting in excessive resistance of the source / drain contacts and potentially excessive time and cost.

[0077] refer to Figure 16 , Figures 24-25 Method 300 includes block 316, in which a planarization process is performed, similar to that described in block 114 above. The differences from structure 200 at block 114 include the following: the metal filler layer 278, the third silicide layer 290, and the remaining portion 292' of the third metal layer 292 (if any). Figure 23 (As shown) the source / drain contacts 288-1', 288-2', and 288-3' are formed. Structure 400 may undergo further processes similar to those described above for structure 200.

[0078] While not intended to be limiting, one or more embodiments of this disclosure offer numerous advantages to semiconductor structures. For example, by forming silicide layers with different compositions and disclosed dimensions, dipole effects can be increased to reduce the resistance of the source / drain contacts, necking profiles in trenches can be mitigated, and the heat energy consumed in forming the silicide layer can be reduced. For example, by performing a immersion process and post-processing after forming the silicide layer, metal residues on the trench sidewalls can be removed, metal filling in the trench can be improved, the resistance of the source / drain contacts can be reduced, the integration density of the structure in subsequent planarization processes (e.g., CMP processes) can be improved, and device reliability can be enhanced. Therefore, the overall performance of the semiconductor device can be improved.

[0079] In one exemplary aspect, this disclosure relates to a method of forming a semiconductor structure. The method includes providing a structure. The structure includes a bottom source / drain component, a bottom interlayer dielectric (ILD) layer disposed over the bottom source / drain component, a top source / drain component disposed over the bottom ILD layer and the bottom source / drain component, and a top ILD layer disposed over the top source / drain component. The method further includes forming a trench extending in the top ILD layer and the bottom ILD layer. The trench exposes the top surface and sidewalls of the top source / drain component and the top surface of the bottom source / drain component. The method further includes forming a first silicide layer on the top surface and sidewalls of the top source / drain component and the top surface of the bottom source / drain component, forming a second silicide layer on the first silicide layer, and forming a metal filling layer in the trench. The first silicide layer and the second silicide layer have different compositions.

[0080] According to some embodiments, the first silicide layer comprises zirconium silicide, and the second silicide layer comprises titanium silicide. According to some embodiments, forming the first silicide layer includes performing a physical vapor deposition (PVD) process, and forming the second silicide layer includes performing a chemical vapor deposition (CVD) process. According to some embodiments, the PVD process is performed at a first temperature, and the CVD process is performed at a second temperature, the second temperature being higher than the first temperature. According to some embodiments, forming the second silicide layer includes depositing a metal layer over the first silicide layer to react with silicon diffused through the first silicide layer. According to some embodiments, forming the first silicide layer and forming the second silicide layer includes: depositing a first metal on the top surface and sidewalls of the top source / drain component and on the top surface of the bottom source / drain component at a first temperature; performing a thermal process on the structure at a second temperature, the second temperature being higher than the first temperature, to form the first silicide layer; and depositing a second metal on the first silicide layer at the second temperature to form the second silicide layer, wherein the thermal process and the deposition of the second metal are performed within the same chamber. The thermal process and the deposition of the second metal are performed in the same chamber. According to some embodiments, the second temperature is approximately 400°C to approximately 500°C. According to some embodiments, the method further includes purging nitrogen gas over the second silicide layer.

[0081] In another exemplary aspect, this disclosure relates to a method of forming a semiconductor structure. The method includes providing a structure including source / drain components and an interlayer dielectric (ILD) layer disposed above the source / drain components; forming a contact trench in the ILD layer to expose a top surface and sidewalls of the source / drain components; forming a first silicide layer including a first horizontal portion on the top surface of the source / drain components and a first vertical portion on the sidewalls of the source / drain components; forming a second silicide layer on the first silicide layer; and forming a metal fill layer in the contact trench. The second silicide layer includes a second horizontal portion on the first horizontal portion and a second vertical portion along the first vertical portion. The first horizontal portion has a first thickness, the first vertical portion has a second thickness, the second horizontal portion has a third thickness, and the second vertical portion has a fourth thickness. The first thickness is greater than the second thickness, and the third thickness is less than the fourth thickness.

[0082] According to some embodiments, forming a first silicide layer includes performing a physical vapor deposition process. According to some embodiments, forming a second silicide layer includes performing a chemical vapor deposition process. According to some embodiments, the ratio of a first thickness to a third thickness is in the range of about 3:2 to about 20:1. According to some embodiments, the ratio of a second thickness to a fourth thickness is in the range of about 1:2 to about 1:20. According to some embodiments, the ratio of a first thickness to a second thickness is about 2 to about 10. According to some embodiments, forming a first silicide layer includes depositing a first metal on a source / drain component, and forming a second silicide layer includes depositing a second metal on the first silicide layer, wherein the second metal is different from the first metal. According to some embodiments, the electronegativity of the second metal is greater than that of the first metal.

[0083] In another exemplary aspect, this disclosure relates to a semiconductor structure. The semiconductor structure includes a bottom transistor and a top transistor disposed above the bottom transistor. The bottom transistor includes a bottom source / drain component, and the top transistor includes a top source / drain component. The semiconductor structure also includes a first silicide layer disposed on the top source / drain component and the bottom source / drain component, a second silicide layer disposed on the first silicide layer, and a metal filler layer disposed on the second silicide layer. The first silicide layer and the second silicide layer have different compositions. The first silicide layer includes a first horizontal portion on the top surface of the top source / drain component and a first vertical portion along the sidewall of the top source / drain component, wherein the first horizontal portion has a first thickness, and the first vertical portion has a second thickness less than the first thickness.

[0084] According to some embodiments, a first silicide layer includes a first metal having a first electronegativity, and a second silicide layer includes a second metal having a second electronegativity greater than the first electronegativity. According to some embodiments, the second silicide layer includes a second horizontal portion on a first horizontal portion and a second vertical portion along a first vertical portion, the second horizontal portion having a third thickness, and the second vertical portion having a fourth thickness greater than the third thickness. According to some embodiments, the first sum of the first and third thicknesses is substantially the same as the second sum of the second and fourth thicknesses.

[0085] The foregoing outlines components of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: A structure is provided, the structure comprising: Bottom source / drain components, A bottom interlayer dielectric layer is disposed above the bottom source / drain components. The top source / drain component is disposed above the bottom interlayer dielectric layer and the bottom source / drain component. A top interlayer dielectric layer is disposed above the top source / drain component; A trench is formed extending in the top interlayer dielectric layer and the bottom interlayer dielectric layer, wherein the trench exposes the top surface and sidewalls of the top source / drain component and the top surface of the bottom source / drain component; A first silicide layer is formed on the top surface and sidewall of the top source / drain component, and on the top surface of the bottom source / drain component; A second silicide layer is formed, the second silicide layer being located on the first silicide layer, wherein the first silicide layer and the second silicide layer have different compositions; and A metal filling layer is formed in the trench.

2. The method according to claim 1, wherein, The first silicide layer comprises zirconium silicide, and the second silicide layer comprises titanium silicide.

3. The method according to claim 1, wherein, Forming the first silicide layer includes performing a physical vapor deposition process, and forming the second silicide layer includes performing a chemical vapor deposition process.

4. The method according to claim 3, wherein, The physical vapor deposition process is performed at a first temperature, and the chemical vapor deposition process is performed at a second temperature, which is higher than the first temperature.

5. The method according to claim 1, wherein, Forming the second silicide layer includes depositing a metal layer over the first silicide layer to react with silicon that diffuses through the first silicide layer.

6. The method according to claim 1, wherein, Forming the first silicide layer and forming the second silicide layer include: A first metal is deposited on the top surface and sidewall of the top source / drain component and on the top surface of the bottom source / drain component at a first temperature; A thermal process is performed on the structure at a second temperature, which is higher than the first temperature, to form the first silicide layer; and A second metal is deposited on the first silicide layer at the second temperature to form the second silicide layer. The thermal process and the deposition of the second metal are performed in the same chamber.

7. A method for forming a semiconductor structure, comprising: A structure is provided, the structure including source / drain components and an interlayer dielectric layer disposed on the source / drain components; Contact trenches are formed in the interlayer dielectric layer to expose the top surface and sidewalls of the source / drain components; A first silicide layer is formed, the first silicide layer including a first horizontal portion on the top surface of the source / drain component and a first vertical portion on the sidewall of the source / drain component; A second silicide layer is formed on the first silicide layer, wherein the second silicide layer includes a second horizontal portion on the first horizontal portion and a second vertical portion along the first vertical portion; as well as A metal filling layer is formed in the contact trench. The first horizontal portion has a first thickness, the first vertical portion has a second thickness, the second horizontal portion has a third thickness, and the second vertical portion has a fourth thickness. The first thickness is greater than the second thickness, and the third thickness is less than the fourth thickness.

8. The method according to claim 7, wherein, Forming the first silicide layer includes depositing a first metal on the source / drain components. The formation of the second silicide layer includes depositing a second metal on the first silicide layer. The second metal is different from the first metal.

9. The method according to claim 8, wherein, The electronegativity of the second metal is greater than that of the first metal.

10. A semiconductor structure comprising: A bottom transistor and a top transistor, the top transistor being disposed above the bottom transistor, wherein the bottom transistor includes a bottom source / drain component, and the top transistor includes a top source / drain component; A first silicide layer is disposed on the top source / drain component and the bottom source / drain component; A second silicide layer is disposed on the first silicide layer; as well as A metal filler layer is disposed on the second silicide layer; The first silicide layer and the second silicide layer have different compositions; The first silicide layer includes a first horizontal portion on the top surface of the top source / drain component and a first vertical portion along the sidewall of the top source / drain component; and The first horizontal portion has a first thickness, and the first vertical portion has a second thickness, the second thickness being less than the first thickness.

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