Silicon-on-insulator radio frequency switch device and radio frequency module

Abstract

This invention provides a silicon-on-insulator (SiI) RF switch and an RF module. The SiI RF switch is implemented by sequentially connecting stacked units. Each stacked unit includes two multi-finger units, which are T-shaped interdigitated structures. Each multi-finger unit is formed by stacking an active layer, a polysilicon layer, a first metal layer, and a second metal layer from bottom to top. The interdigitated structure is formed on the polysilicon layer, and the interdigitated fingers and connecting portions are electrically connected to the active layer to form MOSFETs. In the stacked unit, the source or drain of the MOSFET in one multi-finger unit is shared with the drain or source of the MOSFET in the other multi-finger unit on the active layer. This invention arranges the interdigitated fingers of different MOSFETs in a cross-layout, thereby increasing device density. Simultaneously, the gap between silicon layers is reduced, the gap between metal layers is increased, and the parasitic resistance and capacitance of the device are optimized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an insulating silicon-on-insulator radio frequency switch device and radio frequency module. Background Technology

[0002] In the fields of radio frequency (RF) technology applications such as wireless communication and radio frequency identification (RFID), RF switches are core control components responsible for key functions such as signal path switching and frequency band selection. Their performance directly affects the signal transmission efficiency and operational stability of the RF system. As RF technology develops towards higher frequencies and higher power, higher requirements are placed on the voltage withstand capability, conduction loss, isolation performance, and other indicators of RF switches.

[0003] The core performance of an RF switch is determined by its equivalent resistance (Ron) when on and its equivalent capacitance (Coff) when off. Low equivalent resistance reduces signal attenuation and ensures transmission efficiency; small equivalent capacitance avoids signal crosstalk and improves isolation performance and switching speed. Meanwhile, in high-power scenarios, RF switches must have sufficient RF voltage tolerance to prevent device breakdown and failure.

[0004] Currently, the industry widely adopts silicon-on-insulator (SOI) RF switch structures based on MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). The core device consists of multiple stacked MOSFETs, with each MOSFET having a T-shaped interdigitated structure. From a layout implementation perspective, existing RF switch structures mainly include... Figure 1 The implementation shown has the following equivalent circuit: Figure 2 As shown, where:

[0005] Figure 1 Figure (A) shows a single-layer metal interconnection structure between an active layer, polysilicon, contact holes, and a first metal layer in a conventional RF switch structure. In different multi-finger structures, the active layer is interconnected with the first metal layer through contact holes. Figure 1 (B) shows a double-layer metal connection structure in which the first metal layer is further interconnected with the second metal layer through metal vias; furthermore, in the existing RF switch structure, different MOS transistors are arranged in the same direction along the extension direction of the interdigitated fingers, and the active layers used by the different MOS transistors are interconnected by the H-shaped second metal layer.

[0006] However, in existing RF switch designs, the source and drain of the T-type MOSFET are implemented using interdigitated pins, such as... Figure 1In the layout shown, the spacing between different interdigits is fixed, making it difficult to optimize the device size, the interstage parasitic resistance between the source and drain of different MOSFETs, and the parasitic capacitance. How to further reduce device size and lower parasitic resistance and capacitance on the existing structure are pressing issues that need to be addressed in the current field. Summary of the Invention

[0007] This invention provides an insulating silicon-on-insulator radio frequency switch device and a radio frequency module, aiming to solve the technical problems of large size and difficulty in optimizing parasitic resistance and capacitance of existing radio frequency switch devices.

[0008] To address the aforementioned technical problems, in a first aspect, the present invention provides a silicon-on-insulator (SiI-IS) radio frequency (RF) switch device. The SiI-IS RF switch device is implemented by sequentially connecting multiple stacked units. Each stacked unit includes two multi-finger units, each multi-finger unit having a T-shaped interdigitated structure. Each interdigitated structure includes multiple interdigitated fingers and a connecting portion connecting the same end of the multiple interdigitated fingers. The multiple interdigitated fingers are spaced apart along the length direction of the connecting portion. The two connecting portions of two multi-finger units in the same stacked unit are spaced opposite each other, such that the interdigitated fingers of each unit are located between the two connecting portions and are arranged at cross intervals along the length direction of the connecting portion. Wherein:

[0009] The multi-finger unit is formed by stacking an active layer, a polysilicon layer, a first metal layer, and a second metal layer from bottom to top. The interdigitated structure is formed on the polysilicon layer. The interdigitated fingers and the corresponding connection portions of the polysilicon layer are electrically connected to the active layer to form a MOS transistor. The source and drain of the MOS transistor are both located on the active layer, and the gate of the MOS transistor is located on the polysilicon layer. The first metal layer and the second metal layer are used to realize the electrical connection between different MOS transistors and the multi-finger unit.

[0010] In the same stacked cell, the source or drain of the MOS transistor in one of the multi-finger cells is shared with the drain or source of the MOS transistor in the other multi-finger cell on the active layer.

[0011] Furthermore, the multi-finger unit includes multiple MOS transistors, which are arranged sequentially along the length of the connection portion, with their interdigitated fingers spaced apart from each other. The active layers containing the source and drain of each of the multiple MOS transistors are electrically connected to the first metal layer through contact holes, and the first metal layers corresponding to each of the multiple MOS transistors are electrically connected to each other after being connected to the second metal layer through metal holes.

[0012] Furthermore, the different stacked units are electrically connected via the first metal layer in their respective multi-finger units.

[0013] Furthermore, the interdigitated fingers of the different MOS transistors arranged in a cross-spaced manner have a spacing region that satisfies a preset minimum design spacing, and the source and drain of the multi-finger unit are both disposed at the position of the active layer corresponding to the spacing region.

[0014] Furthermore, along the stacking direction of the multi-finger unit, the projection of the first metal layer and the projection of the polycrystalline silicon layer do not overlap.

[0015] Furthermore, the polysilicon layers containing the gates of the plurality of MOS transistors in the multi-finger unit are electrically connected to each other.

[0016] Furthermore, the active layers of the substrates of the multiple MOS transistors in the multi-finger unit are connected to the first metal layer through contact holes and then electrically connected to each other.

[0017] Secondly, the present invention also provides a radio frequency module, the radio frequency module including the silicon-on-insulator radio frequency switch device as described above.

[0018] The beneficial effects achieved by this invention are that it proposes an insulated silicon-on-a-layer (ISBN) radio frequency (RF) switch device. This RF switch device is based on a T-type interdigitated MOS transistor. In the layout, the interdigitated fingers of different MOS transistors are arranged in a cross pattern, which improves the device density. At the same time, the gap between silicon layers is reduced and the gap between metal layers is increased. The parasitic resistance and parasitic capacitance of the device are optimized. Compared with the prior art, the RF switch device proposed in this invention has better RF performance. Attached Figure Description

[0019] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0020] Figure 1 This is a layout of existing radio frequency switching devices; in which Figure 1 (A) in the diagram is a layout of the active layer to the first metal layer of a prior art RF switching device. Figure 1 (B) in the diagram is a layout of the first to second metal layers of a prior art radio frequency switching device;

[0021] Figure 2 This is a schematic diagram of the equivalent circuit of a prior art radio frequency switching device;

[0022] Figure 3 This is a three-dimensional structural diagram of the silicon-on-insulator radio frequency switch device provided in an embodiment of the present invention;

[0023] Figure 4 This is a three-dimensional structural diagram of the stacked unit of the silicon-on-insulator radio frequency switch device provided in an embodiment of the present invention;

[0024] Figure 5 This is an equivalent circuit diagram of the silicon-on-insulator radio frequency switch device provided in an embodiment of the present invention;

[0025] Figure 6 These are schematic diagrams illustrating the metal layer connections of the MOS transistors in the existing technology and the embodiments of the present invention, respectively; wherein, Figure 6 (A) in the diagram is a schematic diagram of the metal layer connection of a prior art MOSFET. Figure 6 (B) in the figure is a schematic diagram of the metal layer connection of the MOS transistor in an embodiment of the present invention;

[0026] Figure 7 These are schematic diagrams showing the interdigitated arrangement of MOS transistors in the existing technology and embodiments of the present invention, respectively; wherein... Figure 7 (A) in the diagram is a schematic diagram of the interdigitated arrangement of a MOSFET in the prior art. Figure 7 (B) in the figure is a schematic diagram of the interdigitated arrangement of the MOS transistor in an embodiment of the present invention;

[0027] Figure 8 These are comparison diagrams showing the metal layer arrangement of the MOS transistors in the existing technology and the embodiments of the present invention, respectively. Figure 8 (A) in the diagram shows the spacing of the first metal layer used by different MOSFETs. Figure 8 (B) in the figure is a schematic diagram of the spacing of the first metal layer used by different MOS transistors in the embodiments of the present invention. Detailed Implementation

[0028] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0029] The specific embodiments / examples described herein are specific implementations of the present invention, used to illustrate the concept of the invention, and are illustrative and exemplary, and should not be construed as limiting the implementation methods or scope of the present invention. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein, all of which are within the protection scope of the present invention.

[0030] Example 1

[0031] Please refer to Figures 3 to 5 , Figure 3 This is a three-dimensional structural diagram of the silicon-on-insulator radio frequency switch device provided in an embodiment of the present invention. Figure 4This is a three-dimensional structural diagram of the stacked unit of the silicon-on-insulator radio frequency switch device provided in an embodiment of the present invention. Figure 5 This is an equivalent circuit diagram of a silicon-on-insulator (SiI) radio frequency (RF) switch device 100 provided in an embodiment of the present invention. The SiI RF switch device 100 is implemented by multiple stacked units 200 connected in series. Each stacked unit 200 includes two multi-finger units 300. The multi-finger units 300 are T-shaped interdigitated structures. Each interdigitated structure includes multiple interdigitated fingers and a connecting portion connecting the same end of the multiple interdigitated fingers. The multiple interdigitated fingers are spaced apart along the length direction of the connecting portion. The two connecting portions of two multi-finger units 300 in the same stacked unit 200 are spaced apart and opposite each other, such that the interdigitated fingers of each unit are located between the two connecting portions and are arranged at intervals along the length direction of the connecting portion, wherein:

[0032] The multi-finger unit 300 is formed by stacking an active layer 1, a polysilicon layer 2, a first metal layer 3, and a second metal layer 4 from bottom to top. The interdigitated structure is formed on the polysilicon layer 2. The interdigitated fingers 21 and the corresponding connection portions 22 of the polysilicon layer 2 are electrically connected to the active layer 1 to form a MOS transistor 400. The source and drain of the MOS transistor 400 are both located on the active layer 1, and the gate of the MOS transistor 400 is disposed on the polysilicon layer 2. The first metal layer 3 and the second metal layer 4 are used to realize the electrical connection between different MOS transistors 400 and the multi-finger unit 300.

[0033] In the same stacked unit 200, the source or drain of the MOS transistor of one of the multi-finger units 300 is shared with the drain or source of the MOS transistor of the other multi-finger unit 300 on the active layer 1.

[0034] like Figure 5 As shown, with Figure 3Correspondingly, the silicon-on-insulator (SiI-IS) RF switch device 100 includes two stacked units 200 connected in series, and the different stacked units 200 are electrically connected through the first metal layer 3 in their respective multi-finger units 300. It is understood that the number of stacked units can be determined according to actual needs, depending on the application of the RF switch device. In this embodiment of the invention, in two multi-finger units 300 within the same stacked unit 200, the source or drain of the MOS transistor in one multi-finger unit 300 is shared with the drain or source of the MOS transistor in the other multi-finger unit 300 on the active layer. This means, from a circuit design perspective, that the drain of the MOS transistor in the preceding multi-finger unit is connected to the source of the MOS transistor in the following multi-finger unit (or the source of the MOS transistor in the preceding multi-finger unit is connected to the drain of the MOS transistor in the following multi-finger unit). In physical layout implementation, by arranging the interdigitated fingers of the MOS transistors, the drain or source of the MOS transistor in the preceding multi-finger unit is physically adjacent to the source or drain of the MOS transistor in the following multi-finger unit. In this embodiment of the invention, merging the electrodes of these two MOS transistors into one eliminates the need for electrode interconnections between different MOS transistors implemented using metal layers. This design is only achievable with the MOS transistor arrangement proposed in this embodiment of the invention.

[0035] Specifically, such as Figure 3 and Figure 4 As shown, a plurality of MOS transistors 400 are arranged sequentially along the length of the connection portion 22, with their respective interdigitated fingers 21 spaced apart from each other. The active layer 1 where the source and drain of each plurality of MOS transistors 400 are located is electrically connected to the first metal layer 3 through contact holes 5. The first metal layer 3 corresponding to each plurality of MOS transistors 400 is connected to the second metal layer 4 through metal holes 6 and then electrically connected to each other.

[0036] The polysilicon layer 2 containing the gates of the plurality of MOS transistors 400 in the multi-finger unit 300 is electrically connected to each other.

[0037] The active layer 1 of the substrates of the multiple MOS transistors 400 in the multi-finger unit 300 is connected to the first metal layer 3 through contact holes 5 and then electrically connected to each other.

[0038] Please combine Figure 5 The equivalent circuit diagram shown shows that for MOS transistors belonging to the same multi-finger unit, the interdigitated connection is shared (i.e., the gate is interconnected through the polysilicon layer 2), while the source and drain are also connected through the active layer 1 and electrically connected.

[0039] Please refer to Figure 6 , Figure 6This is a comparison diagram of the metal layer connections of the MOS transistors in the RF switching devices of the prior art and the embodiments of the present invention. For ease of distinction, in the embodiments of the present invention and the accompanying drawings, the active layer, polysilicon layer, first metal layer, second metal layer, contact holes, and metal holes of the prior art RF switching device layout are labeled as 1', 2', 3', 4', 5', and 6', respectively. Figure 6 As shown in (A), because the prior art arranges MOS transistors side by side along the interdigital extension direction, even for MOS transistors sharing the same gate in the same column, their source and drain must be connected through the first metal layer 3' and the second metal layer 4'. That is, in the prior art, the path that affects the interstage parasitic metal resistance between different MOS transistors is as follows: the contact hole 5' of this stage, the first metal layer 3' of this stage, the metal hole 6' of this stage, the second metal layer 4' of this stage, the trace of the second metal layer 4', the metal hole 6' of the next stage, the first metal layer 3' of the next stage, and finally the contact hole 5' of the next stage.

[0040] In embodiments of the present invention, such as Figure 6 As shown in (B), by merging and sharing the source and drain of different MOS transistors in the active layer 1, the source and drain of MOS transistors sharing the same gate in the same column are naturally electrically connected without needing to pass through a metal layer. In actual implementation, the channel-to-channel structure of the source and drain of different MOS transistors is only a flat and elongated active layer structure, typically with a width of more than 10 μm and a length of less than 0.5 μm. Due to the self-aligned silicide process, the resistivity of the active layer 1 is low. Therefore, compared with the parasitic resistance of the prior art, the channel-to-channel resistance of the embodiment of the present invention can be ignored.

[0041] Please refer to Figure 7 , Figure 7 This is a comparison diagram of the interdigitated arrangement of MOS transistors in the RF switching devices of the prior art and embodiments of the present invention, wherein the shaded area represents the equivalent area of ​​the source and drain regions. In the embodiments of the present invention, the interdigitated fingers of adjacent different MOS transistors are arranged in a staggered pattern, and there is a spacing region between the interdigitated fingers that satisfies a preset minimum design spacing. The source and drain of the multi-finger unit are both disposed at the position of the active layer corresponding to the spacing region. It can be seen that, compared to... Figure 7 The arrangement shown in (A) of the prior art is different from the arrangement proposed in the embodiments of the present invention. Figure 7 The arrangement shown in (B) minimizes the spacing between the interdigitated fingers without affecting the functionality of the MOSFETs. Objectively, this achieves a higher MOSFET device density while maintaining the same number of MOSFETs used in the RF switching devices. In actual implementation, the preset minimum design spacing between the MOSFET interdigitated fingers is determined by the minimum design rules of the factory manufacturing process.

[0042] Please refer toFigure 8 , Figure 8 These are comparison diagrams showing the metal layer arrangement of the MOS transistors in the existing technology and the embodiments of the present invention, respectively. Figure 8 The spacing D2 shown in (A) is the spacing of the first metal layer 3' used in different MOS transistors in the prior art. Figure 8 In (B) shown, the spacing D1 represents the spacing of the first metal layers 3 used by different MOS transistors in this embodiment of the invention. It can be seen that, compared to the arrangement methods of the prior art, the arrangement method proposed in this embodiment of the invention, through its interdigitated design, ensures that the first metal layers 3 used by different MOS transistors are spaced at least two interdigital widths apart, increasing the spacing without affecting the functionality of the RF switching device. This also reduces the equivalent parasitic capacitance of the metal between the two stages of different MOS transistors. Furthermore, along the stacking direction of the multi-finger unit 300, the projection of the first metal layer 3 does not overlap with the projection of the polysilicon layer 2, further reducing the area of ​​the first metal layer 3 and decreasing its parasitic capacitance.

[0043] The beneficial effects achieved by this invention are that it proposes an insulated silicon-on-a-layer (ISBN) radio frequency (RF) switch device. This RF switch device is based on a T-type interdigitated MOS transistor. In the layout, the interdigitated fingers of different MOS transistors are arranged in a cross pattern, which improves the device density. At the same time, the gap between silicon layers is reduced and the gap between metal layers is increased. The parasitic resistance and parasitic capacitance of the device are optimized. Compared with the prior art, the RF switch device proposed in this invention has better RF performance.

[0044] Example 2

[0045] The present invention also provides a radio frequency (RF) module, which includes the silicon-on-insulator (SiI) RF switch device 100 as described in Embodiment 1 above. It is understood that the RF module, based on the special structure of the SiI RF switch device 100, can achieve better RF performance. Refer to the technical effects described in Embodiment 1 above; they will not be repeated here.

[0046] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0047] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims, and all such changes are within the protection scope of the present invention.

Claims

1. A silicon-on-insulator radio frequency switch device, characterized in that, The silicon-on-insulator (SiI) RF switch device is implemented by multiple stacked units connected in series. Each stacked unit includes two multi-finger units, which are T-shaped interdigitated structures. Each interdigitated structure includes multiple interdigitated fingers and a connecting portion connecting the same end of the multiple interdigitated fingers. The multiple interdigitated fingers are spaced apart along the length of the connecting portion. The two connecting portions of two multi-finger units in the same stacked unit are spaced apart and opposite each other, such that the interdigitated fingers of each unit are located between the two connecting portions and are arranged at cross intervals along the length of the connecting portion, wherein: The multi-finger unit is formed by stacking an active layer, a polysilicon layer, a first metal layer, and a second metal layer from bottom to top. The interdigitated structure is formed on the polysilicon layer. The interdigitated fingers and the corresponding connection portions of the polysilicon layer are electrically connected to the active layer to form a MOS transistor. The source and drain of the MOS transistor are both located on the active layer, and the gate of the MOS transistor is located on the polysilicon layer. The first metal layer and the second metal layer are used to realize the electrical connection between different MOS transistors and the multi-finger unit. In the same stacked cell, the source or drain of the MOS transistor in one of the multi-finger cells is shared with the drain or source of the MOS transistor in the other multi-finger cell on the active layer.

2. The silicon-on-insulator radio frequency switch device according to claim 1, characterized in that, The multi-finger unit includes multiple MOS transistors, which are arranged sequentially along the length of the connection portion, with their interdigitated fingers spaced apart from each other. The active layers containing the source and drain of each of the multiple MOS transistors are electrically connected to the first metal layer through contact holes. The first metal layers corresponding to each of the multiple MOS transistors are all connected to the second metal layer through metal holes and then electrically connected to each other.

3. The silicon-on-insulator radio frequency switch device according to claim 1, characterized in that, The different stacked units are electrically connected through the first metal layer in their respective multi-finger units.

4. The silicon-on-insulator radio frequency switch device according to claim 1, characterized in that, The interdigitated fingers of the different MOS transistors arranged in a cross-spaced manner have a spacing region that satisfies a preset minimum design spacing. The source and drain of the multi-finger unit are both located at the position of the active layer corresponding to the spacing region.

5. The silicon-on-insulator radio frequency switch device according to claim 1, characterized in that, Along the stacking direction of the multi-finger unit, the projection of the first metal layer and the projection of the polycrystalline silicon layer do not overlap.

6. The silicon-on-insulator radio frequency switch device according to claim 1, characterized in that, The polysilicon layers containing the gates of the multiple MOS transistors in the multi-finger unit are electrically connected to each other.

7. The silicon-on-insulator radio frequency switch device according to claim 1, characterized in that, The active layers of the substrates of the multiple MOS transistors in the multi-finger unit are connected to the first metal layer through contact holes and then electrically connected to each other.

8. A radio frequency module, characterized in that, The radio frequency module includes the silicon-on-insulator radio frequency switch device as described in any one of claims 1-7.

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