Array substrate, manufacturing method thereof and display panel
By designing channel portions with exposed drains and vias on the same layer on the array substrate, and combining this with a single photolithography process to fabricate vertical and planar channel transistors, the problem of high fabrication cost of array substrates is solved, achieving low-cost, high-performance array substrates.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-07
AI Technical Summary
In the prior art, planar and vertical channel transistors on the array substrate require different manufacturing processes, resulting in higher manufacturing costs.
An array substrate is designed to combine vertical and planar channels by setting a first drain and a second drain on the same layer on the substrate and exposing the channel portion of the transistor using vias in the insulating layer. The drain is fabricated in one photolithography process and the gate is fabricated in one photolithography process, simplifying the process flow.
This reduces the manufacturing cost of the array substrate, improves current driving capability and charging rate, enables a narrow bezel design, and enhances product competitiveness.
Smart Images
Figure CN121815744A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to an array substrate and its manufacturing method, and a display panel. Background Technology
[0002] As the core channel for the flow of charge carriers (electrons or holes) in semiconductor devices (such as field-effect transistors), channels are broadly classified into planar channels and vertical channels based on their relative relationship to the substrate surface. Vertical channels typically allow for shorter channel lengths, enabling charge carriers to pass through the channel more quickly. This increases the drive current of the semiconductor device, allowing for higher resolution and refresh rates when applied to display products. Planar channels typically have lower parasitic capacitance, improving charging rates and ensuring the reliability of the semiconductor device.
[0003] In related technologies, transistors with planar channels are typically placed in the display area of the array substrate, while transistors with vertical channels are placed in the non-display area, enabling the array substrate to achieve both narrow bezels and good display performance. However, when the two different types of transistors are placed on the array substrate, they often require different manufacturing processes, resulting in higher manufacturing costs for the array substrate. Summary of the Invention
[0004] This application provides an array substrate and its manufacturing method, as well as a display panel, to at least alleviate the technical problem of high manufacturing cost of array substrates in related technologies.
[0005] To achieve the above objectives, according to a first aspect of this application, an array substrate is provided, comprising: Substrate; A first transistor is disposed on the substrate, and the first transistor includes a first drain, a first active layer, and a first source. A second transistor is disposed on the substrate, the second transistor including a second drain, a second active layer, and a second source; and A first insulating layer is disposed on the substrate, and the first insulating layer has a first via and a second via; The first drain and the second drain are located on the substrate and disposed in the same layer. The first via exposes the first drain, and the second via exposes the second drain. The first source is located on the first insulating layer. The first active layer includes a first channel portion and a first connection portion and a second connection portion located at both ends of the first channel portion. The first channel portion is located on the sidewall inside the first via. The first connection portion is connected to the first source, and the second connection portion is connected to the first drain. The second active layer includes a second channel portion and a third connection portion and a fourth connection portion located at both ends of the second channel portion. The second channel portion is disposed on the first insulating layer and located outside the second via. The third connection portion is connected to the second source, and the fourth connection portion is at least partially located inside the second via and connected to the second drain.
[0006] In some embodiments, the array substrate further includes a second insulating layer located on the first insulating layer and a third insulating layer located on the second insulating layer; the first transistor further includes a first gate located between the second insulating layer and the third insulating layer, and the orthogonal projection of the first gate on the substrate at least covers the orthogonal projection of the first channel portion on the substrate; the second transistor further includes a second gate located on the third insulating layer, and the orthogonal projection of the second gate on the substrate covers the orthogonal projection of the second channel portion on the substrate.
[0007] In some embodiments, the array substrate further includes a fourth insulating layer located on the third insulating layer, the second source electrode being located on the fourth insulating layer, and a portion of the second source electrode being located within a third via penetrating the fourth insulating layer, the third insulating layer, and the second insulating layer and connected to the third connection portion.
[0008] In some embodiments, the array substrate further includes a transfer electrode located on the fourth insulating layer, wherein the transfer electrode is partially located within a fourth via penetrating the fourth insulating layer, the third insulating layer, and the second insulating layer and is connected to the first source electrode.
[0009] In some embodiments, the array substrate further includes a second insulating layer located on the first insulating layer, the first transistor further includes a first gate located on the second insulating layer, and the orthogonal projection of the first gate on the substrate at least covers the orthogonal projection of the first channel portion on the substrate, the second transistor further includes a second gate located on the second insulating layer and disposed in the same layer as the first gate, and the orthogonal projection of the second gate on the substrate covers the orthogonal projection of the second channel portion on the substrate.
[0010] In some embodiments, the length of the first channel portion is less than or equal to 0.8 μm.
[0011] In some embodiments, the length of the second channel portion is greater than or equal to 2.5 μm.
[0012] In some embodiments, the first channel portion and the second channel portion are made of the same material.
[0013] In some embodiments, the array substrate has a display area and a non-display area, the first transistor is located in the non-display area, and the second transistor is located in the display area.
[0014] In some embodiments, the third connection portion includes a metal oxide and doped ions.
[0015] According to a second aspect of this application, a method for manufacturing an array substrate is provided, comprising: Provide substrate; A first metal layer is formed on the substrate, the first metal layer including a first drain and a second drain; A first insulating layer and a second metal layer are formed on the first metal layer, the first insulating layer being located between the first metal layer and the second metal layer, the first insulating layer having a first via exposing the first drain and a second via exposing the second drain, the second metal layer including a first source; and A first active layer and a second active layer are formed on the second metal layer. The first active layer includes a first channel portion and a first connection portion and a second connection portion located at both ends of the first channel portion. The first channel portion is located on the sidewall inside the first via. The first connection portion is connected to the first source electrode, and the second connection portion is connected to the first drain electrode. The second active layer includes a second channel portion located on the first insulating layer and a third connection portion and a fourth connection portion located at both ends of the second channel portion. The third connection portion is connected to the second source electrode, and the fourth connection portion is at least partially located inside the second via and connected to the second drain electrode.
[0016] In some embodiments, the method for fabricating the array substrate further includes: A second insulating layer is formed on the first active layer and the second active layer; A third metal layer is formed on the second insulating layer, the third metal layer including a first gate, the orthogonal projection of the first gate on the substrate at least covering the orthogonal projection of the first channel portion on the substrate; A third insulating layer is formed on the third metal layer; and A fourth metal layer is formed on the third insulating layer, the fourth metal layer including a second gate, the orthogonal projection of the second gate on the substrate covering the orthogonal projection of the second channel portion on the substrate.
[0017] According to a third aspect of this application, a display panel is also provided, the display panel comprising an array substrate as described in any embodiment of the first aspect, or an array substrate prepared by a method for manufacturing an array substrate as described in any embodiment of the second aspect.
[0018] In the array substrate of this application embodiment, since the first channel portion of the first transistor is located on the sidewall within the first via, the first transistor has a vertical channel. This allows for a smaller channel length, thereby reducing the size of the first transistor and facilitating a narrow bezel design for the array substrate. Furthermore, since the second channel portion of the second transistor is located outside the second via, the second transistor has a planar channel. This results in a smaller parasitic capacitance and improved charging rate. Additionally, since the first drain and the second drain are disposed on the same layer, they can be fabricated simultaneously in a single photolithography process, reducing the manufacturing cost of the array substrate. Therefore, the array substrate provided in this application embodiment has a lower manufacturing cost, which enhances its product competitiveness.
[0019] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 This is a schematic diagram of the structure of an array substrate provided in some embodiments of this application; Figure 2 These are schematic diagrams of the array substrate provided in other embodiments of this application; Figure 3 This is a flowchart of a method for fabricating an array substrate according to some embodiments of this application; Figures 4A to 4H These are step diagrams illustrating the fabrication process of the array substrate provided in some embodiments of this application; Figure 5 This is a schematic diagram of the structure of a display panel provided in some embodiments of this application. Detailed Implementation
[0022] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.
[0023] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," and similar words do not indicate any order, quantity, or importance, but are only used to distinguish different technical features. The term "multiple" and similar words indicate two or more unless otherwise expressly defined. Additionally, "source" and "drain" can be used interchangeably; for example, the source of a transistor in this application can be used as a drain, and the source of a transistor can be used as a source.
[0024] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.
[0025] In this application, the descriptions of the various embodiments each have their own emphasis. Parts not described in detail in a particular embodiment can be found in the relevant descriptions of other embodiments. The embodiments, implementation methods, examples, and related technical features of this application can be combined and substituted for each other without conflict.
[0026] Some embodiments of this application provide an array substrate, such as Figure 1 and Figure 2 As shown, the array substrate 100 has a display area AA and a non-display area NA. The non-display area NA is located on at least one side of the display area AA. For example, the non-display area NA may be disposed around the display area AA. It should be noted that... Figure 1 and Figure 2 Only the relative positional relationship between the display area AA and the non-display area NA is shown; their relative sizes are not limited.
[0027] Please continue reading. Figure 1 and Figure 2The array substrate 100 includes a substrate SUB, and a first transistor 10, a second transistor 20, and a first insulating layer 101 disposed on the substrate SUB. The first transistor 10 is located in the non-display area NA and includes a first drain 11, a first active layer 12, and a first source 13; the second transistor 20 is located in the display area AA and includes a second drain 21, a second active layer 22, and a second source 23. The first insulating layer 101 has a first via H1 and a second via H2.
[0028] In this embodiment, the first drain 11 and the second drain 21 are located on the substrate SUB and are disposed in the same layer. The first via H1 exposes the first drain 11, and the second via H2 exposes the second drain 21. The first source 13 is located on the first insulating layer 101. The first active layer 12 includes a first channel portion 121 and a first connecting portion 122 and a second connecting portion 123 located at both ends of the first channel portion 121. The first channel portion 121 is located on the sidewall inside the first via H1. The first connecting portion 122 is connected to the first source 13, and the second connecting portion 123 is connected to the first drain 11. The second active layer 22 includes a second channel portion 221 and a third connecting portion 222 and a fourth connecting portion 223 located at both ends of the second channel portion 221. The second channel portion 221 is disposed on the first insulating layer 101 and is located outside the second via H2. The third connecting portion 222 is connected to the second source 23, and the fourth connecting portion 223 is at least partially located inside the second via H2 and connected to the second drain 21.
[0029] For the array substrate 100 provided in this application embodiment, since the first channel portion 121 of the first transistor 10 is located on the sidewall inside the first via H1, the first transistor 10 has a vertical channel. This allows the first channel portion 121 of the first transistor 10 to have a smaller channel length, thereby reducing the size of the first transistor 10 and improving the current driving capability of the first transistor 10. Placing the first transistor 10 in the non-display area NA reduces the size of the non-display area NA and enables the display panel used on the array substrate 100 to have a relatively high resolution and refresh rate. In addition, since the second channel portion 221 of the second transistor 20 is located outside the second via H2, the second transistor 20 has a planar channel. This results in a smaller parasitic capacitance for the second transistor 20 and improves its charging rate. Placing the second transistor 20 in the display area AA ensures good display reliability of the display panel. Furthermore, since the first drain 11 and the second drain 21 are disposed on the same layer, the first drain 11 and the second drain 21 can be fabricated simultaneously in a single photolithography process, which helps to reduce the fabrication cost of the array substrate 100. Therefore, the array substrate 100 provided in this embodiment has a lower fabrication cost, which helps to improve its product competitiveness.
[0030] As an example, the first transistor 10 can be applied to an array substrate gate driver on array (GOA) circuit or a demux circuit. When the first transistor 10 is applied to a GOA circuit, it can effectively reduce the bezel size of the array substrate 100. When the first transistor 10 is applied to a demux circuit, it can reduce the number of driver chips, further reducing the manufacturing cost of the display panel.
[0031] In some examples, the first channel portion 121 and the first connecting portion 122 can be bent to connect. For example, the extending direction of the first channel portion 121 is the same as the extending direction of the sidewall inside the first via H1, and the extending direction of the first connecting portion 122 is perpendicular to the thickness direction of the substrate SUB. Furthermore, the extending direction of the second connecting portion 123 can be the same as the extending direction of the first connecting portion 122.
[0032] As an example, the first connection portion 122 is located on the side of the first source electrode 13 facing away from the substrate SUB and covers a portion of the first source electrode 13. Since the first connection portion 122 does not completely cover the first source electrode 13, another portion of the first source electrode 13 is exposed to the first active layer 12 to facilitate the connection of the first source electrode 13 with other electrodes (e.g., transition electrodes) or signal lines.
[0033] In some examples, both the second channel portion 221 and the third connection portion 222 are located outside the second via H2, with the third connection portion 222 located on the side of the second channel portion 221 away from the second via H2. The extension direction of the second channel portion 221 is perpendicular to the thickness direction of the substrate SUB. A portion of the fourth connection portion 223 is located on the sidewall inside the second via H2 and connected to the second channel portion 221, while another portion of the fourth connection portion 223 is located at the bottom of the second via H2 and connected to the fourth connection portion 223. Furthermore, the fourth connection portion 223 may be completely located inside the second via H2 or may partially extend outside the second via H2.
[0034] In some embodiments, the first channel portion 121 and the second channel portion 221 are made of the same material.
[0035] Since the first active layer 12 and the second active layer 22 are both disposed on the side of the first insulating layer 101 away from the substrate SUB, and the first channel portion 121 and the second channel portion 221 are made of the same material, the first active layer 12 and the second active layer 22 can be fabricated simultaneously in one photolithography process to form the first channel portion 121 and the second channel portion 221. This helps to further reduce the manufacturing cost of the array substrate 100 and thereby enhance the product competitiveness of the array substrate 100.
[0036] In some examples, the materials of the first active layer 12 and the second active layer 22 include metal oxides. For example, the first active layer 12 and the second active layer 22 can be made of materials such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), or indium gallium tin oxide (IGTO).
[0037] In some embodiments, the length of the first channel portion 121 is less than 0.8 μm. It is worth noting that the length of the first channel portion 121 refers to the dimension of the first channel portion 121 along its extension direction, and the extension direction of the first channel portion 121 is the same as the extension direction of the sidewall inside the first through hole H1.
[0038] By controlling the length of the first channel portion 121 to below 0.8μm, the first transistor 10 can have good current driving capability and fast switching response speed, thereby improving the resolution and refresh rate of the display panel.
[0039] In some examples, the length of the first channel portion 121 can be 0.3μm, 0.4μm, 0.5μm, 0.6μm, or 0.7μm, etc.
[0040] In some embodiments, the length of the second channel portion 221 is greater than 2.5 μm.
[0041] By controlling the length of the second channel portion 221 to be above 2.5μm, the off-state leakage current of the second transistor 20 can be effectively reduced, thereby improving the display reliability of the display panel.
[0042] In some examples, the length of the second channel 221 is less than or equal to 20 μm.
[0043] This configuration allows the length of the second channel 221 to be within a reasonable range, effectively balancing the on-resistance and parasitic capacitance, so that the second transistor 20 can improve the charging rate while ensuring good switching speed.
[0044] In some examples, the length of the second channel portion 221 can be 2.6μm, 2.8μm, 3μm, 3.2μm, 3.5μm, 3.7μm, 4μm, 4.2μm, 4.5μm, 4.7μm, 5μm, 5.2μm, 5.5μm, 5.7μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, or 20μm, etc.
[0045] In some embodiments, the third connection portion 222 includes a metal oxide and dopant ions. Exemplarily, the metal oxide may be one of IGZO, IZO, ZTO, or IGTO. The dopant ions may be n-type dopant ions, such as phosphorus ions or arsenic ions.
[0046] In this embodiment, since the third connection portion 222 includes metal oxide and doped ions, the conductivity of the third connection portion 222 is effectively improved, thereby improving the switching response speed and working stability of the second transistor 20.
[0047] In some embodiments, please continue reading Figure 1 and Figure 2 The array substrate 100 also includes a second insulating layer 102 located on the first insulating layer 101, and the first transistor 10 also includes a first gate 14 located on the second insulating layer 102, and the orthogonal projection of the first gate 14 on the substrate SUB at least covers the orthogonal projection of the first channel portion 121 on the substrate SUB.
[0048] In this embodiment, since the first gate 14 of the first transistor 10 and the first active layer 12 are separated by the second insulating layer 102, the first transistor 10 can be ensured to have strong gate control capability and improve the current drive capability of the first transistor 10.
[0049] In some examples, please refer to Figure 1 The array substrate 100 further includes a third insulating layer 103 located on the second insulating layer 102, and the second transistor 20 further includes a second gate 24 located on the third insulating layer 103. The orthogonal projection of the second gate 24 on the substrate SUB overlaps with the orthogonal projection of the second channel portion 221 on the substrate SUB. For example, the orthogonal projection of the second gate 24 on the substrate SUB and the orthogonal projection of the second channel portion 221 on the substrate SUB can coincide.
[0050] In this case, a second insulating layer 102 and a third insulating layer 103 are spaced between the second gate 24 and the second active layer 22 of the second transistor 20. Therefore, the thickness of the gate insulating layer between the second gate 24 and the second active layer 22 is relatively large, which can effectively suppress the leakage current problem of the second gate 24 and thus improve the reliability of the second transistor 20.
[0051] As an example, the thickness of the third insulating layer 103 is greater than the thickness of the second insulating layer 102. This can effectively ensure that the first transistor 10 has a strong gate control capability, thereby improving the current drive capability of the first transistor 10. On the other hand, it can effectively suppress the leakage current problem of the second gate 24, thereby improving the reliability of the second transistor 20.
[0052] In other examples, please refer to Figure 2 The second gate 24 of the second transistor 20 is located on the second insulating layer 102 and is disposed in the same layer as the first gate 14. The orthogonal projection of the second gate 24 on the substrate SUB covers the orthogonal projection of the second channel portion 221 on the substrate SUB.
[0053] In this case, the second gate 24 of the second transistor 20 and the first gate 14 of the first transistor 10 can be fabricated simultaneously in one photolithography process, thereby further reducing the manufacturing cost of the array substrate 100 and enhancing its product competitiveness.
[0054] In some embodiments, the first gate 14 and the second gate 24 may each comprise a metal such as molybdenum, aluminum, copper, or titanium, or a metal alloy thereof. Of course, the first gate 14 and the second gate 24 may also employ a stacked structure, and the different layers in the stacked structure may be made of metal materials such as molybdenum, aluminum, copper, or titanium; this application does not impose any limitations on this.
[0055] In some embodiments, please continue reading Figure 1 The array substrate 100 also includes a fourth insulating layer 104 located on the third insulating layer 103, a second source electrode 23 located on the fourth insulating layer 104, a third via H3 penetrating through the fourth insulating layer 104, the third insulating layer 103 and the second insulating layer 102, and a portion of the second source electrode 23 located in the third via H3 and connected to the third connecting portion 222.
[0056] In this embodiment, since the second source electrode 23 is located on the fourth insulating layer 104, it can also be fabricated simultaneously with the pixel electrode, etc., and the second source electrode 23 can be used as a connecting electrode, pixel electrode or anode at the same time. This simplifies the structure of the array substrate 100 and effectively reduces the manufacturing cost of the array substrate 100.
[0057] It is worth noting that when the second source electrode 23 is used as a pixel electrode, the array substrate 100 can be used in a liquid crystal display (LCD) panel. When the second source electrode 23 is used as an anode, the array substrate 100 can be used in an organic light-emitting diode (OLED) display panel. When the second source electrode 23 is used as a connecting electrode, the array substrate 100 can be used in a Mini LED display panel or a Micro LED display panel.
[0058] In some embodiments, please continue reading Figure 1 The array substrate 100 also includes a transfer electrode 31 located on the fourth insulating layer 104. The transfer electrode 31 is located in the non-display area NA. A fourth via H4 is also provided through the fourth insulating layer 104, the third insulating layer 103 and the second insulating layer 102. The transfer electrode 31 is partially located in the fourth via H4 and connected to the first source electrode 13.
[0059] In this embodiment, the transition electrode 31 and the second source electrode 23 are both located on the fourth insulating layer 104, so they can be fabricated simultaneously in one photolithography process. This helps to reduce the manufacturing cost of the array substrate 100 and enhance its product competitiveness.
[0060] Some embodiments of this application also provide a method for fabricating an array substrate, such as... Figure 3 As shown, the manufacturing method includes the following steps.
[0061] S11: Provides substrate SUB.
[0062] For example, the substrate SUB can be cleaned to ensure that the surface of the substrate SUB is clean, thereby facilitating the deposition of metal materials.
[0063] S12: As Figure 4A As shown, a first metal layer M1 is formed on the substrate SUB. The first metal layer M1 includes a first drain 11 located in the non-display area NA and a second drain 21 located in the display area AA.
[0064] For example, a first metal material layer can be deposited on a substrate SUB, and then the first metal material layer can be patterned to form a first drain 11 and a second drain 21. The thickness of the first metal material layer can be set between 1000 Å and 6000 Å, and its material can be metals such as molybdenum, chromium, aluminum, copper, and titanium, or metal alloys of the above materials.
[0065] S13: As Figure 4B and Figure 4CAs shown, a first insulating layer 101 and a second metal layer M2 are formed on a first metal layer M1. The first insulating layer 101 is located between the first metal layer M1 and the second metal layer M2. The first insulating layer 101 has a first via H1 that exposes the first drain electrode 11 and a second via H2 that exposes the second drain electrode 21. The second metal layer M2 includes a first source electrode 13 located in the non-display area NA.
[0066] For example, please refer to Figure 4B A first insulating material layer and a second metal material layer can be sequentially deposited on the first metal layer M1, with the second metal material layer located on the first insulating material layer. After the deposition of the second metal material layer is completed, the second metal material layer can be patterned to form a transition metal pattern 130. The transition metal pattern 130 includes a portion to be removed and a portion to be retained, with the retained portion exposing the first via H1.
[0067] Please see Figure 4C A photoresist layer is coated on the transition metal pattern 130. The photoresist layer is exposed and developed, so that the part to be removed in the transition metal pattern 130 and the part of the first insulating material layer corresponding to the second via H2 are exposed by the photoresist layer. Then, the part to be removed is etched away by a wet etching process, while the remaining part in the transition metal pattern 130 serves as the first source 13. Afterward, the part of the first insulating material layer corresponding to the first via H1 and the part corresponding to the second via H2 are etched away by a dry etching process, thereby forming the first via H1 and the second via H2 respectively.
[0068] In some examples, the first insulating layer can be made of silicon oxide. The thickness of the first insulating layer can be set between 2000 Å and 5000 Å.
[0069] In some examples, the second metallic layer can be made of metals such as molybdenum, chromium, aluminum, copper, and titanium, or metal alloys thereof. The thickness of the second metallic layer can be set between 800 Å and 1500 Å.
[0070] S14: As Figure 4DAs shown, a first active layer 12 and a second active layer 22 are formed on the second metal layer M2. The first active layer 12 is located in the non-display area NA and includes a first channel portion 121 and a first connecting portion 122 and a second connecting portion 123 located at both ends of the first channel portion 121. The first channel portion 121 is located on the sidewall inside the first via H1. The first connecting portion 122 is connected to the first source electrode 13, and the second connecting portion 123 is connected to the first drain electrode 11. The second active layer 22 is located in the display area AA and includes a second channel portion 221 and a third connecting portion 222 and a fourth connecting portion 223 located at both ends of the second channel portion 221. The second channel portion 221 is disposed on the first insulating layer 101 and is located outside the second via H2. The third connecting portion 222 is connected to the second source electrode 23, and the fourth connecting portion 223 is at least partially located inside the second via H2 and connected to the second drain electrode 21.
[0071] For example, an active material layer can be deposited on the second metal layer M2, with the active material layer partially located within the first via H1 and the second via H2; then the active material layer is patterned to form the first active layer 12 and the second active layer 22.
[0072] In some examples, the active material layer can be made of IGZO, where the atomic ratio of indium, gallium, and zinc is 1:1:1. The thickness of the active material layer can be set between 100 Å and 300 Å.
[0073] In some embodiments, the method for fabricating the array substrate 100 further includes the following steps.
[0074] S15: A second insulating layer 102 is formed on the first active layer 12 and the second active layer 22.
[0075] For example, a second insulating material layer can be deposited on the first active layer 12 and the second active layer 22, and the second insulating material layer can directly serve as the second insulating layer. The material of the second insulating material layer can be silicon oxide, and its thickness can be set between 100 Å and 500 Å.
[0076] S16: As Figure 4E As shown, a third metal layer M3 is formed on the second insulating layer 102. The third metal layer M3 includes a first gate 14 located in the non-display area NA. The orthogonal projection of the first gate 14 on the substrate SUB at least covers the orthogonal projection of the first channel portion 121 on the substrate SUB.
[0077] For example, a third metal material layer can be deposited on the second insulating layer 102, and then the third metal material layer can be patterned to form the first gate 14. Furthermore, the material of the third metal material layer can be a metal such as molybdenum, chromium, aluminum, copper, or titanium, or a metal alloy thereof. The thickness of the third metal material layer can be set between 2000 Å and 6000 Å.
[0078] S17: A third insulating layer 103 is formed on the third metal layer M3.
[0079] For example, a third insulating material layer can be deposited on the third metal layer M3, and the third insulating material layer can directly serve as the third insulating layer. The material of the third insulating material layer can be silicon oxide, and its thickness can be set between 1000 Å and 1500 Å. In this case, the thickness of the third insulating material layer is greater than the thickness of the second insulating material layer. This can effectively ensure that the first transistor 10 has a strong gate control capability, thereby improving the current drive capability of the first transistor 10; on the other hand, it can effectively suppress the leakage current problem of the second gate 24, thereby improving the reliability of the second transistor 20.
[0080] S18: As Figure 4F As shown, a fourth metal layer M4 is formed on the third insulating layer 103. The fourth metal layer M4 includes a second gate 24 located in the display area AA. The orthogonal projection of the second gate 24 on the substrate SUB covers the orthogonal projection of the second channel portion 221 on the substrate SUB.
[0081] For example, a fourth metal material layer can be deposited on the third insulating layer 103, and then the fourth metal material layer can be patterned to form the second gate 24. Furthermore, the material of the fourth metal material layer can be a metal such as molybdenum, aluminum, copper, or titanium, or a metal alloy thereof. The thickness of the fourth metal material layer can be set between 2000 Å and 6000 Å.
[0082] In some embodiments, the method for fabricating the array substrate 100 further includes step S19.
[0083] S19: Ion implantation is performed on the third connector 222 to make the third connector 222 conductive.
[0084] After the third connection portion 222 is made conductive, the third connection portion 222 includes doped ions, thereby effectively improving the conductivity of the third connection portion 222.
[0085] For example, the second gate 24 can be used to block the third connection portion 222 and the fourth connection portion 223, thereby implanting n-type doped ions (such as phosphorus ions or arsenic ions) to improve the conductivity of the third connection portion 222 and the fourth connection portion 223.
[0086] In some embodiments, the method for fabricating the array substrate 100 further includes the following steps.
[0087] S20: As Figure 4G As shown, a fourth insulating layer 104 is formed on the fourth metal layer M4. A third through hole H3 and a fourth through hole H4 are provided through the fourth insulating layer 104, the third insulating layer 103 and the second insulating layer 102. The third through hole H3 exposes the third connecting portion 222 and the fourth through hole H4 exposes the fourth connecting portion 223.
[0088] For example, a fourth insulating material layer can be deposited on the fourth metal layer M4, and then photolithography can be performed on the fourth insulating material layer, the third insulating layer 103, and the second insulating layer 102 to fabricate the third via H3 and the fourth via H4. The material of the fourth insulating material layer can be silicon oxide or silicon nitride. Alternatively, the fourth insulating material layer can also have a multilayer structure. The thickness of the fourth insulating material layer can be set between 1000 Å and 5000 Å.
[0089] S21: As Figure 4H As shown, a fifth metal layer M5 is formed on the fourth insulating layer 104. The fifth metal layer M5 includes a second source electrode 23 connected to the third connection portion 222 and a transfer electrode 31 connected to the fourth connection portion 223.
[0090] For example, a fifth metal material layer can be deposited on the fourth insulating layer 104, and then the fifth metal material layer can be patterned to form the second source electrode 23 and the transition electrode 31. The second source electrode 23 and the transition electrode 31 can be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).
[0091] Some embodiments of this application also provide a display panel, such as Figure 5 As shown, the display panel 200 includes the array substrate 100 described in any of the above embodiments.
[0092] Since it includes the array substrate 100, the display panel 200 has the technical effects of the array substrate 100, which will not be described in detail here.
[0093] In some examples, the display panel 200 can be an LCD display panel, an OLED display panel, a Mini LED display panel, or a Micro LED display panel, etc.
[0094] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. An array substrate, characterized in that, include: Substrate; A first transistor is disposed on the substrate, and the first transistor includes a first drain, a first active layer, and a first source. A second transistor is disposed on the substrate, and the second transistor includes a second drain, a second active layer, and a second source. as well as A first insulating layer is disposed on the substrate, and the first insulating layer has a first via and a second via; The first drain and the second drain are located on the substrate and disposed in the same layer. The first via exposes the first drain, and the second via exposes the second drain. The first source is located on the first insulating layer. The first active layer includes a first channel portion and a first connection portion and a second connection portion located at both ends of the first channel portion. The first channel portion is located on the sidewall inside the first via. The first connection portion is connected to the first source, and the second connection portion is connected to the first drain. The second active layer includes a second channel portion and a third connection portion and a fourth connection portion located at both ends of the second channel portion. The second channel portion is disposed on the first insulating layer and located outside the second via. The third connection portion is connected to the second source, and the fourth connection portion is at least partially located inside the second via and connected to the second drain.
2. The array substrate according to claim 1, characterized in that, The array substrate further includes a second insulating layer located on the first insulating layer, and a third insulating layer located on the second insulating layer; The first transistor further includes a first gate located between the second insulating layer and the third insulating layer, and the orthographic projection of the first gate on the substrate at least covers the orthographic projection of the first channel portion on the substrate; The second transistor further includes a second gate located on the third insulating layer, the orthogonal projection of the second gate on the substrate covering the orthogonal projection of the second channel portion on the substrate.
3. The array substrate according to claim 2, characterized in that, The array substrate further includes a fourth insulating layer located on the third insulating layer, the second source electrode is located on the fourth insulating layer, and a portion of the second source electrode is located in a third via penetrating the fourth insulating layer, the third insulating layer, and the second insulating layer and is connected to the third connection portion.
4. The array substrate according to claim 3, characterized in that, The array substrate further includes a transfer electrode located on the fourth insulating layer. The transfer electrode is partially located in a fourth via that penetrates the fourth insulating layer, the third insulating layer, and the second insulating layer and is connected to the first source electrode.
5. The array substrate according to claim 1, characterized in that, The array substrate further includes a second insulating layer located on the first insulating layer, the first transistor further includes a first gate located on the second insulating layer, and the orthogonal projection of the first gate on the substrate at least covers the orthogonal projection of the first channel portion on the substrate, the second transistor further includes a second gate located on the second insulating layer and disposed in the same layer as the first gate, and the orthogonal projection of the second gate on the substrate covers the orthogonal projection of the second channel portion on the substrate.
6. The array substrate according to claim 1, characterized in that, The length of the first channel portion is less than or equal to 0.8 μm; and / or The length of the second channel is greater than or equal to 2.5 μm.
7. The array substrate according to any one of claims 1-6, characterized in that, The first channel portion and the second channel portion are made of the same material; and / or The array substrate has a display area and a non-display area, the first transistor is located in the non-display area, and the second transistor is located in the display area.
8. The array substrate according to any one of claims 1-6, characterized in that, The third connection portion includes metal oxides and doped ions.
9. A method for fabricating an array substrate, characterized in that, include: Provide substrate; A first metal layer is formed on the substrate, the first metal layer including a first drain and a second drain; A first insulating layer and a second metal layer are formed on the first metal layer, the first insulating layer being located between the first metal layer and the second metal layer, the first insulating layer having a first via exposing the first drain and a second via exposing the second drain, the second metal layer including a first source. as well as A first active layer and a second active layer are formed on the second metal layer. The first active layer includes a first channel portion and a first connection portion and a second connection portion located at both ends of the first channel portion. The first channel portion is located on the sidewall inside the first via. The first connection portion is connected to the first source electrode, and the second connection portion is connected to the first drain electrode. The second active layer includes a second channel portion located on the first insulating layer and a third connection portion and a fourth connection portion located at both ends of the second channel portion. The third connection portion is connected to the second source electrode, and the fourth connection portion is at least partially located inside the second via and connected to the second drain electrode.
10. The method for fabricating an array substrate according to claim 9, characterized in that, Also includes: A second insulating layer is formed on the first active layer and the second active layer; A third metal layer is formed on the second insulating layer, the third metal layer including a first gate, the orthogonal projection of the first gate on the substrate at least covering the orthogonal projection of the first channel portion on the substrate; A third insulating layer is formed on the third metal layer; as well as A fourth metal layer is formed on the third insulating layer, the fourth metal layer including a second gate, the orthogonal projection of the second gate on the substrate covering the orthogonal projection of the second channel portion on the substrate.
11. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-8, or the array substrate prepared by the method for manufacturing the array substrate as described in any one of claims 9-10.