Photoelectric detector and preparation method thereof

Abstract

The invention provides a photoelectric detector and a preparation method thereof. The photoelectric detector comprises a substrate, a buried oxide layer, a silicon waveguide layer, an epitaxial layer and a germanium waveguide layer which are sequentially stacked along a first direction, the epitaxial layer comprises a first region, a second region and a third region which are sequentially arranged along a second direction, the germanium waveguide layer covers the surfaces of a part of the first region, the second region and a part of the third region, and the second direction is perpendicular to the first direction; a doping layer surrounding the germanium waveguide layer; the electrode layer is located on the sides, away from the silicon waveguide layer, of the first region and the third region and connected with the doping layer; the first conductive structure extends along the first direction and is connected with the silicon waveguide layer; and the second conductive structure extends along the first direction and is connected with the electrode layer.

Description

Technical Field

[0001] This application relates to receiving-end detector technology for silicon photonic interconnects, and more particularly to a photodetector and its fabrication method. Background Technology

[0002] Photodetectors are key components in optical communication and optical sensing systems, their core function being the conversion of incident light signals into electrical signals. In silicon-based optoelectronic integration technology, germanium-based waveguide photodetectors have attracted widespread attention due to their compatibility with CMOS processes and the ability to achieve high integration. Based on the pin junction distribution, photodetectors can be classified into vertical (VPD) and horizontal (LPD) types, each with different current transport paths and performance characteristics. Summary of the Invention

[0003] This application provides a photodetector and its fabrication method, which can avoid the formation of metal contacts on the germanium waveguide layer.

[0004] The technical solution of this application embodiment is implemented as follows: This application provides a photodetector, comprising: a substrate, a buried oxide layer, a silicon waveguide layer, an epitaxial layer, and a germanium waveguide layer sequentially stacked along a first direction; the epitaxial layer includes a first region, a second region, and a third region sequentially arranged along a second direction, the germanium waveguide layer covering a portion of the surface of the first region, the second region, and a portion of the third region, the second direction being perpendicular to the first direction; a doped layer surrounding the germanium waveguide layer; an electrode layer located on the side of the epitaxial layer away from the silicon waveguide layer and on at least one side of the germanium waveguide layer in the second direction, the electrode layer being connected to the doped layer; a first conductive structure extending along the first direction and connected to the silicon waveguide layer; and a second conductive structure extending along the first direction and connected to the electrode layer.

[0005] In some embodiments, the silicon waveguide layer and the second region have a first type of doped ions, and the doped layer and the electrode layer have a second type of doped ions, wherein the first type of doped ions are different from the second type of doped ions.

[0006] In some embodiments, the first type of doped ion includes P-type ions and the second type of doped ion includes N-type doped ions; or, the first type of doped ion includes N-type ions and the second type of doped ion includes P-type doped ions.

[0007] In some embodiments, the second region is electrically connected to the silicon waveguide layer and electrically isolated from the electrode layer.

[0008] In some embodiments, the width of the second region along the second direction is greater than or equal to 0.5 micrometers.

[0009] In some embodiments, the width of the epitaxial layer in the second direction is smaller than the width of the silicon waveguide layer in the second direction.

[0010] In some embodiments, the epitaxial layer is composed of silicon, the doped layer is composed of germanium, and the electrode layer is composed of silicon.

[0011] In some embodiments, the electrode layer is embedded in the first region and / or the third region; or, the electrode layer protrudes from the surface of the first region and / or the third region.

[0012] In some embodiments, the electrode layer includes a first electrode layer located on the side of the first region away from the silicon waveguide layer; and a second electrode layer located on the side of the third region away from the silicon waveguide layer; both the first electrode layer and the second electrode layer are connected to the second conductive structure.

[0013] This application provides a method for fabricating a photodetector, the method comprising: providing an SOI wafer, the SOI wafer comprising a substrate, a buried oxide layer, and a silicon waveguide layer stacked along a first direction; forming an epitaxial layer on the side of the silicon waveguide layer away from the buried oxide layer; the epitaxial layer comprising a first region, a second region, and a third region arranged sequentially along a second direction, the second direction being perpendicular to the first direction; forming a germanium waveguide layer on the side of the epitaxial layer away from the silicon waveguide layer; the germanium waveguide layer covering a portion of the surface of the first region, the second region, and a portion of the third region; forming a doped layer surrounding the germanium waveguide layer; forming an electrode layer connected to the doped layer on the side of the epitaxial layer away from the silicon waveguide layer and on at least one side of the germanium waveguide layer along the second direction; forming a first conductive structure and a second conductive structure, the first conductive structure extending along the first direction and connected to the silicon waveguide layer, and the second conductive structure extending along the first direction and connected to the electrode layer.

[0014] In some embodiments, the method further includes: performing a first doping on the silicon waveguide layer to give the silicon waveguide layer a first type of dopant ions.

[0015] In some embodiments, the method further includes: performing the first doping on the second region to give the second region doped ions of the first type.

[0016] In some embodiments, forming an epitaxial layer on the side of the silicon waveguide layer away from the buried oxide layer includes: forming an epitaxial layer on the side of the silicon waveguide layer away from the buried oxide layer with a width in the second direction smaller than the width of the silicon waveguide layer in the second direction.

[0017] In some embodiments, forming a germanium waveguide layer on the side of the epitaxial layer away from the silicon waveguide layer, and forming a doped layer surrounding the germanium waveguide layer, includes: forming a germanium material layer on the side of the epitaxial layer away from the silicon waveguide layer; the germanium material layer covering a portion of the surface of the first region, the second region, and a portion of the third region; performing a second doping on the germanium material layer to form a doped layer having a second type of dopant ions, the remaining germanium material layer forming the germanium waveguide layer; wherein the doped layer surrounds the germanium waveguide layer, and the second type of dopant ions are different from the first type of dopant ions.

[0018] In some embodiments, forming an electrode layer connected to the doped layer on the side of the epitaxial layer away from the silicon waveguide layer and on at least one side of the germanium waveguide layer along the second direction includes: performing a second doping on the side of the first region away from the silicon waveguide layer in the first direction and on the side of the third region away from the silicon waveguide layer in the second direction and / or on the side of the third region away from the silicon waveguide layer in the first direction and on the side of the third region away from the germanium waveguide layer in the second direction to form an electrode layer embedded in the first region and / or the third region, wherein the electrode layer is connected to the doped layer.

[0019] In some embodiments, forming an electrode layer connected to the doped layer on the side of the epitaxial layer away from the silicon waveguide layer and on at least one side of the germanium waveguide layer along the second direction includes: depositing a conductive material on the side of the first region away from the silicon waveguide layer along the first direction and on the side of the second region away from the germanium waveguide layer along the first direction and on the side of the third region away from the silicon waveguide layer along the first direction and on the side of the second direction away from the germanium waveguide layer to form an electrode layer protruding from the surface of the first region and / or the third region, wherein the electrode layer is connected to the doped layer.

[0020] The embodiments of this application have the following beneficial effects: by setting an epitaxial layer between the silicon waveguide layer and the germanium waveguide layer, and making the second region of the epitaxial layer the same as the silicon waveguide layer in terms of ion doping type, an electrical connection between the second region and the silicon waveguide layer is achieved; furthermore, by setting an electrode layer on the epitaxial layer, with the electrode layer located on at least one side of the germanium waveguide layer along the second direction, the silicon waveguide layer can be connected through a first conductive structure, and the electrode layer can be connected through a second conductive structure, thereby realizing the input and output of electrical signals of the photodetector. This allows the photodetector provided in this application to (1) avoid forming a metal contact (also known as an electrode contact) above the germanium waveguide layer, thereby reducing the width of the germanium waveguide layer in the second direction during the fabrication of the photodetector, thereby reducing the size of the active region and increasing the RC bandwidth; (2) since the electrode contact is not set above the germanium waveguide layer, there is no metal above the germanium waveguide layer, thereby reducing the overlap between the light field and the metal, reducing the absorption of light by the metal, and thus improving the responsivity of the photodetector; (3) during the fabrication of the photodetector, the thickness of the germanium waveguide layer in the first direction can also be reduced, thereby reducing the carrier transit time in the germanium waveguide layer and further increasing the bandwidth. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of the vertical PIN junction detector provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of the horizontal PIN junction detector provided in the embodiments of this application; Figure 3 This is a schematic flowchart of a photodetector fabrication method provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of the SOI wafer provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of forming an epitaxial layer on a silicon waveguide layer provided in an embodiment of this application; Figure 6 This is a schematic diagram of a germanium material layer formed on an epitaxial layer, provided in an embodiment of this application. Figure 7 This is a schematic diagram of the structure for forming a germanium waveguide layer, a doped layer, and an electrode layer provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure forming the first conductive structure and the second conductive structure provided in the embodiments of this application; Figure 9 This is a top view schematic diagram of a photodetector provided in an embodiment of this application; Figure 10 This is a partial cross-sectional structural diagram of a photodetector provided in an embodiment of this application.

[0022] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0025] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0026] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0027] In the implementation of this application, the collection and processing of relevant data should strictly comply with the requirements of relevant laws and regulations, obtain the informed consent or separate consent of the personal information subject, and carry out subsequent data use and processing within the scope of laws and regulations and the authorization of the personal information subject.

[0028] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0029] For vertical PIN photodetectors (VPDs), the reference... Figure 1Typically, doping is performed on top of a germanium (Ge) layer to form a doped Ge layer. For example, N-type ions are doped into the Ge layer, and P-type ions are doped into the silicon (Si) layer below the Ge layer to form a vertical PIN junction. Electrode contacts (or metal contacts, conductive structures, etc.) are then placed on top of the Ge layer. While this can achieve a wider bandwidth, it is limited by the alignment accuracy of the process. Ge When the size is reduced, the entire Ge layer structure may deform. For example, a square or rectangular Ge layer structure may gradually deform into a trapezoidal structure or even a semi-circular structure, and the thickness of the Ge layer (H) may also change. Ge The doped region may also become thinner, potentially leading to misalignment between the doped region and the electrode contact, affecting electrode contact alignment and device performance. Furthermore, since the electrode contact is positioned above the Ge layer, it introduces additional absorption losses, reducing responsivity.

[0030] For horizontal PIN junction photodetectors (LPDs), the reference is... Figure 2 A horizontal PIN junction is formed by doping in the Si layer, and the Ge layer is located above the undoped intrinsic Si in the middle, which passes through the doped region (N... ++ N + P ++ P + The electrode contacts are located in the silicon (Si) layer and on one side of the Ge layer. Although this avoids the problem of directly fabricating electrode contacts on top of the Ge layer and can improve the responsivity to a certain extent, since the doped region of the LPD is located in the Si layer, the strong electric field region is in the PIN junction of the Si layer. The Ge layer can only be covered by the electric field loop outside the junction region, making it difficult to achieve a high electric field effect. This makes it difficult to achieve a bandwidth improvement effect comparable to that of the vertical structure.

[0031] In summary, both LPD and VPD have problems in improving bandwidth and maintaining high responsivity. Furthermore, they face process limitations and performance degradation when designed with small-size Ge layer structures. Therefore, there is an urgent need for a new type of photodetector that can balance high performance and process feasibility in structural design.

[0032] To address one or more of the aforementioned problems, this application provides a vertical PIN junction photodetector and its fabrication method, which avoids placing the electrode contacts above the Ge layer, further reducing the width and thickness of the Ge layer, thereby improving the bandwidth and response speed of the photodetector. (Reference) Figure 3 , Figure 3 This is a schematic flowchart illustrating a method for fabricating a photodetector according to an embodiment of this application; wherein the method for fabricating the photodetector includes the following steps: Step S301: Provide an SOI wafer, the SOI wafer including a substrate, a buried oxide layer and a silicon waveguide layer stacked along a first direction.

[0033] Step S302: An epitaxial layer is formed on the side of the silicon waveguide layer away from the buried oxide layer; the epitaxial layer includes a first region, a second region and a third region arranged sequentially along a second direction, the second direction being perpendicular to the first direction.

[0034] Step S303: A germanium waveguide layer is formed on the side of the epitaxial layer away from the silicon waveguide layer; the germanium waveguide layer covers part of the surface of the first region, the second region and part of the third region.

[0035] Step S304: Form a doped layer surrounding the germanium waveguide layer.

[0036] Step S305: An electrode layer connected to the doped layer is formed on the side of the epitaxial layer away from the silicon waveguide layer and on at least one side of the germanium waveguide layer along the second direction.

[0037] Step S306: Form a first conductive structure and a second conductive structure, wherein the first conductive structure extends along a first direction and is connected to the silicon waveguide layer, and the second conductive structure extends along the first direction and is connected to the electrode layer.

[0038] It should be understood that Figure 3 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 3 The steps shown can be adjusted in order according to actual needs.

[0039] Thus, (1) it can avoid forming electrode contacts (such as a second conductive structure) above the germanium waveguide layer, thereby reducing the width of the germanium waveguide layer in the second direction during the fabrication of the photodetector, thereby reducing the size of the active region and increasing the RC bandwidth; (2) since the electrode contacts are not set above the germanium waveguide layer, there is no metal above the germanium waveguide layer, thereby reducing the overlap between the light field and the metal, reducing the absorption of light by the metal, thereby improving the responsivity of the photodetector; (3) during the fabrication of the photodetector, the thickness of the germanium waveguide layer in the first direction can also be reduced, thereby reducing the carrier transit time in the germanium waveguide layer and further improving the bandwidth.

[0040] To make the above-mentioned objects, features, and advantages of this application more apparent and understandable, specific embodiments of this application will be described in detail below with reference to the accompanying drawings. Before introducing the photodetector illustrated in the drawings, various directions that may be used in the following description are defined. Specifically, the stacking direction of each layer in the photodetector is defined as the first direction (i.e., the Z-axis direction), and intersecting second direction (i.e., the X-axis direction) and third direction (i.e., the Y-axis direction) are defined in a plane perpendicular to the first direction. In some embodiments, the first direction, the second direction, and the third direction can be mutually perpendicular, i.e., the X-axis direction, the Y-axis direction, and the Z-axis direction are mutually perpendicular.

[0041] In step S301, an SOI wafer is provided.

[0042] refer to Figure 4 The SOI wafer includes a substrate 401, a buried oxide layer 402, and a silicon waveguide layer 403 stacked along the Z-axis. It should be noted that in some embodiments, the SOI wafer may only include the stacked substrate 401 and buried oxide layer 402. Based on this, the method further includes forming the silicon waveguide layer 403 on the side of the buried oxide layer 402 opposite to each other along the Z-axis, away from the substrate 401. Methods for forming the silicon waveguide layer 403 include, but are not limited to, deposition processes. Here, deposition processes include, for example, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0043] The substrate 401 can be a silicon-based material, serving as the support platform for the entire photodetector and providing good thermal conductivity. The buried oxide layer (BOX) 402 can be a low dielectric constant material. A silicon dioxide layer (SiO2) formed by processes such as SIMOX (separation of oxides) or other methods is used to isolate the electrical connection between the silicon waveguide layer 403 and the substrate 401, preventing the generation of parasitic currents. The silicon waveguide layer 403 can serve as a channel for optical signal transmission, guiding the propagation of optical signals. Its constituent materials include, for example, undoped silicon, which has advantages such as low loss and high refractive index. It should be explained that the first direction refers to the stacking direction of the layers during the device manufacturing process, such as the Z-axis direction, which can also be understood as the vertical direction. The X-axis direction mentioned below can also be understood as the horizontal direction.

[0044] In some embodiments, the silicon waveguide layer 403 is first doped to give the silicon waveguide layer 403 a first type of dopant ions. Here, the first type of dopant ions refer to P-type or N-type dopant materials used to form the PIN junction, such as boron (B) for P-type doping and phosphorus (P) or arsenic (As) for N-type doping. That is, in this embodiment, the first type of dopant ions can be either N-type or P-type ions. For the sake of clarity, this embodiment uses P-type ions as an example for illustration. The doping methods for performing the first doping include, but are not limited to, ion implantation, thermal diffusion, etc.

[0045] In step S302, an epitaxial layer is formed on the side of the silicon waveguide layer away from the buried oxide layer.

[0046] refer to Figure 5 The epitaxial layer 404 can be formed by forming a mask layer on the silicon waveguide layer 403, and forming a mask pattern corresponding to the epitaxial layer in the mask layer, followed by etching and epitaxial growth (EPI) processes. The etching process includes, but is not limited to, dry etching; the epitaxial growth process can include homoepitaxial growth and heteroepitaxial growth, and in some specific embodiments, the epitaxial growth process is, for example, molecular beam epitaxy (MBE). The constituent materials of the epitaxial layer 404 include, but are not limited to, undoped silicon (Si).

[0047] Continue to refer to Figure 5The method further includes: dividing the epitaxial layer 404 into a first region 4041, a second region 4042, and a third region 4043 along the X-axis direction; and performing a first doping on the second region 4042 to ensure that the second region 4042 contains first-type doped ions. In this embodiment, the first region 4041 and the third region 4043 can serve as electrode connection points, and the second region 4042 can be used to carry out the light absorption process. The first doping method includes, but is not limited to, ion implantation, thermal diffusion, etc. For example, the first-type doped ions are p-type ions. It should be noted that during the first doping of the second region 4042, the first-type doped ions diffuse along the Z-axis direction to cover the entire epitaxial layer, so that the second region 4042 can be electrically connected to the silicon waveguide layer 403.

[0048] In some embodiments, the width of the second region 4042 along the X-axis is greater than or equal to 0.5 micrometers (µm). That is, the minimum process linewidth for the first type of doped ions can reach 0.5 µm. This allows for a reduction in the width of the germanium waveguide layer 406 along the X-axis in subsequent processes, improving device integration.

[0049] In some embodiments, forming an epitaxial layer on the side of the silicon waveguide layer away from the buried oxide layer includes: forming an epitaxial layer on the side of the silicon waveguide layer away from the buried oxide layer with a width in a second direction smaller than the width of the silicon waveguide layer in the second direction. That is, referring to... Figure 5 The width of the epitaxial layer 404 in the X-axis direction is smaller than the width of the silicon waveguide layer 403 in the X-axis direction. Thus, in subsequent processes, a first conductive structure can be formed on the surface of the silicon waveguide layer 403 in the region extending beyond the epitaxial layer 404, further improving the integration of the device.

[0050] In steps S303 and S304, a germanium waveguide layer is formed on the side of the epitaxial layer away from the silicon waveguide layer, and a doped layer surrounding the germanium waveguide layer is formed.

[0051] refer to Figure 6A germanium material layer 405 is formed on the side of the epitaxial layer 404 away from the silicon waveguide layer 403. The constituent material of the germanium material layer 405 includes undoped germanium (Ge). Methods for forming the germanium material layer 405 include, but are not limited to, etching and deposition processes. Etching processes include, but are not limited to, dry etching; deposition processes include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD. Here, the germanium material layer 405 does not completely cover the entire epitaxial layer 404, but only covers a portion of the surface of the first region 4041, the second region 4042, and a portion of the third region 4043 to facilitate subsequent second doping operations and the layout of electrode connections (such as the second conductive structure). The area of ​​the germanium material layer 405 covering the first region 4041 and the third region 4043 can be selected according to actual needs, while the surface of the second region 4042 is completely covered by the germanium material layer 405 (and the germanium waveguide layer 406 mentioned below). That is to say, the width of the germanium material layer 405 along the X-axis direction is at least greater than the width of the second part 4042 along the X-axis direction, that is, the width of the germanium material layer 405 in the X-axis direction is at least greater than the minimum linewidth of the first type of ion doping in the epitaxial layer 404.

[0052] As previously mentioned, the width of the second region 4042 in the X-axis direction can be as small as 0.5 micrometers. This means that the width of the germanium material layer 405 in the X-axis direction can be slightly greater than 0.5 micrometers; specifically, the width of the germanium material layer 405 in the X-axis direction can be less than 1 micrometer. This reduces the horizontal dimension of the germanium material layer 405, thereby reducing the horizontal dimension of the germanium waveguide layer 406 in subsequent processes. This reduces the overall size of the active region in the device, decreases the transit distance of photogenerated carriers in the germanium waveguide layer 406, enhances the average electric field strength in the central region of the germanium waveguide layer 406, and increases the drift velocity of photogenerated carriers under the built-in electric field, thus improving the device's bandwidth. Furthermore, it can further reduce the junction capacitance of the PIN junction, lower the series resistance, reduce the RC time of carriers in the loop, and improve the RC response bandwidth.

[0053] In some embodiments, reference Figure 7The germanium material layer 405 is second-doped to form a doped layer 407 with second-type dopant ions. The remaining germanium material layer forms a germanium waveguide layer 406, which can serve as the intrinsic layer (I) of a vertical PIN junction structure. The doped layer 407 surrounds the germanium waveguide layer 406. The second-type dopant ions differ from the first-type dopant ions; for example, if the first type is P-type, the second type is N-type. The second-type dopant ions form a heterojunction structure with the first-type dopant ions, which enhances the built-in electric field and improves the collection efficiency of photogenerated carriers. It should be understood that the second-type dopant ions can be either N-type or P-type. For clarity, this application is illustrated using N-type dopant ions as an example. The second doping method includes, but is not limited to, ion implantation and thermal diffusion. It should be noted that the constituent material of the doped layer 407 includes germanium (Ge). In some specific embodiments, the doped layer 407 is a germanium layer doped with P-type ions.

[0054] It should be noted that the size of the germanium waveguide layer 406 along the X-axis is larger than the size of the second region 4042 along the X-axis. Specifically, the germanium waveguide layer 406 covers part of the surface of the first region 4041, the second region 4042 and part of the third region 4043.

[0055] In step S305, an electrode layer connected to the doped layer is formed.

[0056] Continue to refer to Figure 7 The first region 4041, on the side away from the silicon waveguide layer 403 in the Z-axis direction and on the side away from the germanium waveguide layer 406 in the X-axis direction, and / or the third region 4043, on the side away from the silicon waveguide layer 403 in the Z-axis direction and on the side away from the germanium waveguide layer 406 in the X-axis direction, is subjected to a second doping to form an electrode layer 408. Here, the electrode layer 408 is connected to the doped layer 407 and electrically isolated from the second region 4042. The electrode layer 408 contains second-type doped ions; in other words, the doped ion types in the electrode layer 408 and the doped layer 407 are the same. Here, the second-type doped ions can be N-type ions or P-type ions. For the sake of clarity, this application is illustrated by taking N-type ions as an example of the second-type doped ions.

[0057] It should be noted that the second doping of germanium material layer 405 to form doped layer 407 and the second doping of first region 4041 and / or third region 4043 to form electrode layer 408 can be performed in the same process step to reduce the process flow and manufacturing cost.

[0058] In some embodiments of this application, reference is made to Figure 7Electrode layer 408 includes a first electrode layer 4081 and a second electrode layer 4082. That is, during the formation of electrode layer 408, a portion of both the first region 4041 and the third region 4043 undergoes a second doping. In other embodiments, the second doping may be performed only on the first region 4041 or only on the third region 4043; this application does not limit this. Here, both the first electrode layer 4081 and the second electrode layer 4082 are connected to the second conductive structure 410 described below.

[0059] like Figure 7 As shown, the first electrode layer 4081 is embedded in the first region 4041, and the second electrode layer 4082 is embedded in the third region 4043. In some embodiments, the electrode layer 408 may also protrude from the surface of the first region 4041 and / or the third region 4043; based on this, the method further includes: depositing conductive material on the side of the first region 4041 away from the silicon waveguide layer 403 along the Z-axis direction and away from the germanium waveguide layer 406 along the X-axis direction, and / or depositing conductive material on the side of the third region 4043 away from the silicon waveguide layer 403 along the Z-axis direction and away from the germanium waveguide layer 406 along the X-axis direction to form an electrode layer protruding from the surface of the first region 4041 and / or the third region 4043, where the electrode layer 408 is connected to the doped layer 407. The conductive material includes, but is not limited to, metals, such as copper (Cu), aluminum (Al), etc.; the deposition process includes, but is not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0060] In step S306, a first conductive structure and a second conductive structure are formed.

[0061] refer to Figure 8 The specific method may include: forming a dielectric layer 411 on the remaining surface of the silicon waveguide layer 403, the surface of the electrode layer 408, and the surface of the doped layer 407 through a deposition process; forming a first via and a second via extending along the Z-axis direction in the dielectric layer 411; the first via exposing the silicon waveguide layer 403 and the second via exposing the electrode layer 408; depositing conductive material in the first and second vias to form a first conductive structure 409 in the first via and a second conductive structure 410 in the second via; wherein the first conductive structure 409 is connected to the silicon waveguide layer 403 and the second conductive structure 410 is connected to the electrode layer 408. In some embodiments, the first conductive structure 409 and the second conductive structure 410 may further include a metal layer connected to the conductive material, and the shape of the metal layer may be selected according to requirements to adapt to different external devices. The number of the first conductive structure 409 and the second conductive structure 410 may be selected according to actual needs, and this application does not limit this.

[0062] Here, the constituent materials of the first dielectric layer 411 include, but are not limited to, silicon oxide (SiO2), which serve to provide protection, support, and electrical isolation. Conductive materials include, but are not limited to, metallic materials such as copper (Cu) and aluminum (Al). Methods for forming the first and second vias include, but are not limited to, etching, such as dry etching; methods for depositing conductive materials include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0063] It should be noted that, based on the silicon waveguide structure and the fact that the ions doped in the second region are P-type, while the ions doped in the doped layer and electrode layer are N-type, the first conductive structure 409 can serve as the anode of the photodetector, and the second conductive structure 410 can serve as the cathode of the photodetector. In other embodiments, when the silicon waveguide structure and the second region are doped with N-type ions, and the ions doped in the doped layer and electrode layer are P-type, the first conductive structure 409 can serve as the cathode of the photodetector, and the second conductive structure 410 can serve as the anode of the photodetector.

[0064] It should be noted that the first and second type dopant ions determine the direction and intensity of the electric field inside the device, thus affecting the carrier drift behavior and photoresponse performance. By selecting different doping types, the current direction and charge distribution can be controlled to optimize the detector's bandwidth and responsivity.

[0065] In this embodiment, P-type and N-type dopant ions are used to construct a vertical PIN junction structure. By placing the electrode contact, such as the second conductive structure, on at least one side of the germanium waveguide layer along the X-axis, it is possible to avoid placing it above the germanium waveguide structure along the Z-axis. This avoids the absorption loss of optical signals by the metal in the electrode contact, such as the second conductive structure, and allows for further reduction of the size of the germanium waveguide layer as needed, thereby improving bandwidth and responsivity. On the other hand, the PIN junction can generate a strong electric field distribution under an applied bias voltage. This electric field distribution helps to realize the FK effect under Fermi-Dirac statistical conditions. This effect causes the absorption edge in the germanium material to shift towards the longer wavelength direction, thereby improving the material's responsivity in the L-band (1565 nm–1625 nm). This enables high-speed, high-responsivity detection of the photodetector in the C-band (1530 nm–1565 nm) + L-band.

[0066] Based on the above-described method for manufacturing a photodetector, this application also provides a photodetector comprising a substrate, a buried oxide layer, a silicon waveguide layer, an epitaxial layer, and a germanium waveguide layer sequentially stacked along a first direction; the epitaxial layer includes a first region, a second region, and a third region sequentially arranged along a second direction, the germanium waveguide layer covering a portion of the surface of the first region, the second region, and the third region, the second direction being perpendicular to the first direction; a doped layer surrounding the germanium waveguide layer; an electrode layer located on the side of the epitaxial layer away from the silicon waveguide layer and on at least one side of the germanium waveguide layer in the second direction, the electrode layer being connected to the doped layer; a first conductive structure extending along the first direction and connected to the silicon waveguide layer; and a second conductive structure extending along the first direction and connected to the electrode layer.

[0067] refer to Figure 9 and Figure 10 , Figure 9 A top view of a photodetector in the XY plane is provided as an embodiment of this application; Figure 10 for Figure 9 The diagram shows a cross-sectional view indicated by the dashed line. The photodetector includes a substrate 401, a buried oxide layer 402 located on one side of the substrate 401 along the Z-axis, and silicon waveguide layers 403 located on opposite sides of the buried oxide layer 402 along the Z-axis, on the side furthest from the substrate 401. The substrate 401 can be a silicon-based material, serving as a support platform for the entire photodetector and providing good thermal conductivity. The buried oxide layer 402 can be a low dielectric constant material. A silicon dioxide layer (SiO2) or a silicon dioxide layer formed by processes such as SIMOX (separation of oxides) is used to isolate the electrical connection between the silicon waveguide layer 403 and the substrate 401, preventing the generation of parasitic currents. The silicon waveguide layer can serve as a channel for optical signal transmission, guiding the propagation of optical signals. Its constituent materials include, for example, undoped silicon.

[0068] Here, the silicon waveguide layer 403 has a first type of doped ions. The first type of doped ions can be either P-type or N-type doped ions. Specifically, P-type ion doping can be achieved by boron doping, and N-type ion doping can be achieved by phosphorus (P) or arsenic (As) doping. For ease of understanding, this embodiment of the application uses the silicon waveguide layer 403 having P-type doped ions as an example for illustrative explanation.

[0069] refer to Figure 10The photodetector further includes an epitaxial layer 404 located on the side of the silicon waveguide layer 403 opposite each other along the Z-axis, away from the buried oxide layer 402. The epitaxial layer 404 is composed of silicon. Here, the width of the epitaxial layer 404 along the X-axis is smaller than the width of the silicon waveguide layer 403 along the X-axis. The epitaxial layer 404 includes a first region 4041, a second region 4042, and a third region 4043 arranged sequentially along the X-axis. Figure 10 (Not shown in the text), wherein the second region 4042 contains first-type doped ions; here, a p-type doped ion is used as an example for illustration. Reference Figure 10 The second region 4042 is in contact with and electrically connected to the silicon waveguide layer 403.

[0070] In some embodiments, the width of the second region 4042 along the X-axis is greater than or equal to 0.5 micrometers.

[0071] In some embodiments, reference Figure 10 The photodetector further includes a germanium waveguide layer 406 located on the side of the epitaxial layer 404 away from the silicon waveguide layer 403 along the Z-axis direction, wherein the germanium waveguide layer 406 covers at least the surface of the second region 4042 along the X-axis direction, for example, covering part of the surface of the first region 4041, the second region 4042 and part of the third region 4043.

[0072] In some embodiments, reference Figure 10 The photodetector further includes a doped layer 407 surrounding the germanium waveguide layer 406. The doped layer is composed of germanium and contains second-type doped ions. It should be noted that the second-type doped ions are different from the first-type doped ions. For example, if the first type is P-type, then the second type is N-type, or vice versa. For ease of understanding, this embodiment uses N-type doped ions in the doped layer 407 as an example. Exemplarily, the doped layer 407, the germanium waveguide layer 406, the second region 4042, and the silicon waveguide layer 403 together constitute a NIP structure. The doped layer 407 serves as an N-type layer, the germanium waveguide layer 406 as an intrinsic I-layer, and the second region 4042 and the silicon waveguide layer 403 as P-type layers.

[0073] In some embodiments, the photodetector further includes an electrode layer 408, which is located on the side of the epitaxial layer 404 away from the silicon waveguide layer 403 and on at least one side of the germanium waveguide layer 406 in the X-axis direction. The electrode layer 408 is connected to the doped layer 407 and electrically isolated from the second region 4042. In some specific embodiments, the electrode layer 408 may be embedded in the first region 4041 and / or the third region (see reference). Figure 10The electrode layer 408 may also protrude from the surface of the first and / or third regions (not shown), which is not limited in this application. Here, the electrode layer 408 has second-type doped ions, such as N-type doped ions. The constituent material of the electrode layer 408 includes silicon.

[0074] In some embodiments, reference Figure 10 The photodetector further includes a first conductive structure 409 and a second conductive structure 410, both extending along the Z-axis. The first conductive structure 409 is connected to the silicon waveguide layer 403 and can serve as the anode of the photodetector; the second conductive structure 410 is connected to the electrode layer 408 and can serve as the cathode of the photodetector. It should be understood that when the NIP structure is replaced with a PIN structure (i.e., N-type doped ions and P-type doped ions exchange), the polarity of the first conductive structure 409 and the second conductive structure 410 also changes. The conductive materials constituting the first conductive structure 409 and the second conductive structure 410 include, but are not limited to, metals such as copper (Cu) and aluminum (Al). The number and shape of the first conductive structure 409 and the second conductive structure 410 can be selected according to actual conditions, and this application does not limit this.

[0075] In some embodiments, electrode layer 408 includes a first electrode layer 4081 located on the side of the first region away from the silicon waveguide layer; and a second electrode layer 4082 located on the side of the third region away from the silicon waveguide layer. Figure 10 (not shown in the image); both the first electrode layer 4081 and the second electrode layer 4082 are connected to the second conductive structure 410.

[0076] Based on this, (1) the vertical PIN junction photodetector (VPD) provided in this application can avoid forming electrode contacts (such as a second conductive structure) above the germanium waveguide layer (Ge), thereby reducing the width of the germanium waveguide layer (Ge) in the X-axis direction during fabrication, reducing the active region size of the device, and improving the RC bandwidth. (2) After reducing the width of the germanium waveguide layer (Ge), the thickness of the germanium waveguide layer (Ge) can also be reduced accordingly, thereby reducing the carrier transit time in the germanium waveguide layer (Ge) and improving the bandwidth. (3) The high-concentration PIN junction formed in the germanium waveguide layer (Ge) region can generate a strong electric field under an applied bias voltage, producing the FK effect, thereby causing the absorption sideband of the germanium waveguide layer (Ge) to drift towards the longer wavelength direction, thereby improving the responsivity of the germanium waveguide layer (Ge) in the L-band. (4) Since this VPD does not have electrode contacts above the germanium waveguide layer (Ge), the overlap between the light field and the metal in the electrode contact is also reduced, reducing the absorption of light by the metal and improving the responsivity.

[0077] It should be understood that the phrases "one embodiment" or "some embodiments" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0078] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A photodetector, characterized in that, The photodetector includes: A substrate, a buried oxide layer, a silicon waveguide layer, an epitaxial layer, and a germanium waveguide layer are sequentially stacked along a first direction; the epitaxial layer includes a first region, a second region, and a third region arranged sequentially along a second direction; the germanium waveguide layer covers the surface of a portion of the first region, the second region, and a portion of the third region; the second direction is perpendicular to the first direction. A doped layer surrounds the germanium waveguide layer; An electrode layer is located on the side of the epitaxial layer away from the silicon waveguide layer and on at least one side of the germanium waveguide layer in the second direction, and the electrode layer is connected to the doped layer; A first conductive structure extends along the first direction and is connected to the silicon waveguide layer; A second conductive structure extends along the first direction and is connected to the electrode layer.

2. The photodetector according to claim 1, characterized in that, The silicon waveguide layer and the second region have a first type of doped ions, and the doped layer and the electrode layer have a second type of doped ions, wherein the first type of doped ions are different from the second type of doped ions.

3. The photodetector according to claim 2, characterized in that, The first type of doped ion includes P-type ions, and the second type of doped ion includes N-type doped ions; or, the first type of doped ion includes N-type ions, and the second type of doped ion includes P-type doped ions.

4. The photodetector according to claim 3, characterized in that, The second region is electrically connected to the silicon waveguide layer and electrically isolated from the electrode layer.

5. The photodetector according to claim 4, characterized in that, The width of the second region along the second direction is greater than or equal to 0.5 micrometers.

6. The photodetector according to claim 1, characterized in that, The width of the epitaxial layer in the second direction is smaller than the width of the silicon waveguide layer in the second direction.

7. The photodetector according to claim 6, characterized in that, The epitaxial layer is composed of silicon, the doped layer is composed of germanium, and the electrode layer is composed of silicon.

8. The photodetector according to claim 7, characterized in that, The electrode layer is embedded in the first region and / or the third region; or, the electrode layer protrudes from the surface of the first region and / or the third region.

9. The photodetector according to claim 8, characterized in that, The electrode layer includes a first electrode layer located in the first region away from the silicon waveguide layer; and a second electrode layer located in the third region away from the silicon waveguide layer; both the first electrode layer and the second electrode layer are connected to the second conductive structure.

10. A method for fabricating a photodetector, characterized in that, The preparation method includes: An SOI wafer is provided, the SOI wafer comprising a substrate, a buried oxide layer and a silicon waveguide layer stacked along a first direction; An epitaxial layer is formed on the side of the silicon waveguide layer away from the buried oxide layer; the epitaxial layer includes a first region, a second region and a third region arranged sequentially along a second direction, the second direction being perpendicular to the first direction; A germanium waveguide layer is formed on the side of the epitaxial layer away from the silicon waveguide layer; the germanium waveguide layer covers a portion of the surface of the first region, the second region, and a portion of the third region. A doped layer is formed surrounding the germanium waveguide layer; An electrode layer connected to the doped layer is formed on the side of the epitaxial layer away from the silicon waveguide layer and on at least one side of the germanium waveguide layer along the second direction; A first conductive structure and a second conductive structure are formed, wherein the first conductive structure extends along the first direction and is connected to the silicon waveguide layer, and the second conductive structure extends along the first direction and is connected to the electrode layer.

11. The preparation method according to claim 10, characterized in that, The method further includes: The silicon waveguide layer is first doped to give it a first type of dopant ions.

12. The preparation method according to claim 11, characterized in that, The method further includes: The second region is subjected to the first doping to give the second region doped ions of the first type.

13. The preparation method according to claim 12, characterized in that, The formation of an epitaxial layer on the side of the silicon waveguide layer away from the buried oxide layer includes: An epitaxial layer with a width in the second direction smaller than the width of the silicon waveguide layer in the second direction is formed on the side of the silicon waveguide layer away from the buried oxide layer.

14. The preparation method according to claim 13, characterized in that, The formation of a germanium waveguide layer on the side of the epitaxial layer away from the silicon waveguide layer, and the formation of a doped layer surrounding the germanium waveguide layer, include: A germanium material layer is formed on the side of the epitaxial layer away from the silicon waveguide layer; the germanium material layer covers a portion of the surface of the first region, the second region, and a portion of the third region. The germanium material layer is subjected to a second doping to form a doped layer with a second type of dopant ions, and the remaining germanium material layer forms the germanium waveguide layer; wherein the doped layer surrounds the germanium waveguide layer, and the second type of dopant ions are different from the first type of dopant ions.

15. The preparation method according to claim 14, characterized in that, The method of forming an electrode layer connected to the doped layer on at least one side of the epitaxial layer away from the silicon waveguide layer and on at least one side of the germanium waveguide layer along the second direction includes: The first region is subjected to a second doping on the side of the first region away from the silicon waveguide layer in the first direction and on the side of the third region away from the silicon waveguide layer in the first direction and on the side of the third region away from the germanium waveguide layer in the second direction, to form an electrode layer embedded in the first region and / or the third region, wherein the electrode layer is connected to the doped layer.

16. The preparation method according to claim 14, characterized in that, The method of forming an electrode layer connected to the doped layer on at least one side of the epitaxial layer away from the silicon waveguide layer and on at least one side of the germanium waveguide layer along the second direction includes: Conductive material is deposited in the first region on one side away from the silicon waveguide layer along the first direction and on the side away from the germanium waveguide layer in the second direction, and / or in the third region on one side away from the silicon waveguide layer along the first direction and on the side away from the germanium waveguide layer in the second direction, to form an electrode layer protruding from the surface of the first region and / or the third region, wherein the electrode layer is connected to the doped layer.

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