Thin film transistor of heterogeneous double-channel layer and preparation method of thin film transistor
By employing a heterogeneous dual-channel layer structure and optimizing the fabrication process in thin-film transistors, the problems of high off-state current and low threshold voltage in InSnO channel layer thin-film transistors have been solved, enabling the fabrication of thin-film transistors with high mobility and low power consumption, thus meeting the application requirements of high performance and low power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-12
- Publication Date
- 2026-04-07
AI Technical Summary
Existing thin-film transistors based on InSnO channel layers suffer from high off-state current and low threshold voltage, resulting in high energy consumption and making it difficult to meet the application requirements of high performance and low energy consumption.
A heterogeneous dual-channel layer structure was adopted to fabricate thin-film transistors by combining magnetron sputtering and solution methods. A heterogeneous dual-channel layer was formed by amorphous TaLaO thin film and amorphous InSnO thin film. By designing the electrode structure and improving the film deposition process conditions, thin-film transistors with high mobility and low power consumption were fabricated.
It achieves high mobility (over 60 cm²/Vs) and low power consumption (off-state current <10⁻¹⁰A, threshold voltage in the range of 0V to 1V), reducing device power consumption and improving performance.
Smart Images
Figure CN121815876A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of thin-film transistor technology, specifically to a heterogeneous dual-channel thin-film transistor and its fabrication method. Background Technology
[0002] Thin-film transistors (TFTs) based on amorphous oxide semiconductor (AOS) channel layers have become the most promising next-generation technology to replace traditional silicon-based semiconductor (amorphous silicon or low-temperature polycrystalline silicon) channel layer TFTs due to their high mobility, good electrical uniformity, and low-temperature fabrication capability (<150℃). They are expected to be applied in next-generation display fields such as ultra-large screen displays and flexible displays. Indium tin oxide (InSnO), a typical representative of the AOS material system, has been explored by researchers as a channel layer for TFT development due to its high carrier mobility. However, studies have shown that InSnO naturally contains defects such as oxygen vacancies and metal ion gaps, resulting in excessively high electron carrier concentration. This leads to high off-state currents in InSnO-based TFT devices, and the devices often operate in depletion mode (i.e., a negative threshold voltage), resulting in high energy consumption during operation. It is well known that high performance (e.g., high mobility >30 cm⁻¹) is crucial for TFTs. 2 / Vs) and low energy consumption (e.g., having a low off-state current <10 -10 A, and the threshold voltage (which is close to zero and positive) are key factors that directly determine whether AOS TFTs can be practically applied.
[0003] To address this, some research groups have attempted to introduce low-electro-positive elements (such as Al and Ga) into the InSnO channel layer or to reduce the carrier concentration of the InSnO channel layer by optimizing the InSnO material composition, effectively optimizing the threshold voltage and off-state current of InSnO-based TFT devices.
[0004] In fact, the synergistic advantages of combining the development of new electrode materials, the design of channel layer structures, and the optimization of device structures may also effectively regulate the key energy consumption parameters (such as threshold voltage and off-state current) of InSnO-based TFT devices and further promote the improvement of key electrical performance indicators (such as mobility).
[0005] Therefore, new approaches to fabricating thin-film transistors with both high performance and low energy consumption based on traditional low-cost processes (magnetron sputtering and solution methods) remain a key research focus. Summary of the Invention
[0006] To address the aforementioned technical problems in the prior art, this invention provides a method for fabricating thin-film transistors with both high performance (such as high mobility) and low power consumption using traditional low-cost processes (magnetron sputtering and solution methods).
[0007] A method for fabricating a thin-film transistor with a heterogeneous dual-channel layer includes the following steps: (1) On a glass substrate, amorphous InSnO thin films and amorphous TaLaO thin films were prepared sequentially at room temperature by radio frequency magnetron sputtering and DC magnetron sputtering, respectively, to form a channel layer with an “amorphous TaLaO thin film / amorphous InSnO thin film” structure. (2) On the above-mentioned channel layer, combined with a mask, Al thin film and Ti thin film are sequentially prepared at room temperature by DC magnetron sputtering to form source / drain electrodes with a "Ti thin film / Al thin film" structure; (3) Based on the dip-coating process, a dielectric layer of PVP film is prepared on the above-mentioned channel layer and source / drain electrodes using a sol solution of polytetravinylphenol; (4) On the above PVP dielectric layer, combined with a mask, Al thin film and Ti thin film are prepared sequentially at room temperature by DC magnetron sputtering to form a gate electrode with a "Ti thin film / Al thin film" structure, thus obtaining the desired device.
[0008] Furthermore, in step (1), when preparing a heterogeneous bilayer film with an "amorphous TaLaO thin film / amorphous InSnO thin film" structure as the channel layer using radio frequency magnetron sputtering and DC magnetron sputtering at room temperature, firstly, an indium tin oxide target (4N purity) is used to prepare an amorphous InSnO thin film under the conditions of an argon working gas pressure of 0.6–0.8 Pa, an oxygen partial pressure (O2 / (Ar+O2)) of 15%, a sputtering power of 75–90 W, and a sputtering time of 6–9 min; subsequently, a tantalum target (4N purity) and a lanthanum target (4N purity) are selected, and the sputtering is carried out under the conditions of an argon working gas pressure of 0.6 Pa, an oxygen partial pressure (O2 / (Ar+O2)) of 15%, and a sputtering time of 6–9 min. With an O2 content of 25%, DC sputtering powers of 46.8 W and 28.7 W for tantalum and lanthanum targets, respectively, and a sputtering time of 1 min, an amorphous TaLaO film was deposited on an amorphous InSnO film, ultimately obtaining a channel layer with an "amorphous TaLaO film / amorphous InSnO film" structure.
[0009] Furthermore, the indium tin oxide target has an indium-tin molar ratio of In:Sn=7:3.
[0010] Furthermore, in step (2), when preparing the bilayer film of the "Ti thin film / Al thin film" structure as the source / drain electrode at room temperature using DC magnetron sputtering, firstly, an aluminum target (4N purity) is selected. Under the conditions of argon working pressure of 0.5-0.7 Pa, DC sputtering power of the aluminum target of 38-55 W, and sputtering time of 5-9 min, an Al thin film is deposited using a mask. Subsequently, a titanium target (4N purity) is selected. Under the conditions of argon working pressure of 0.5-0.7 Pa, DC sputtering power of the titanium target of 12-20 W, and sputtering time of 2-3 min, a Ti thin film is deposited on the Al thin film using a mask, and finally the source / drain electrode of the "Ti thin film / Al thin film" structure is obtained.
[0011] Furthermore, in step (3), the concentration of the polytetraethylene phenol sol solution is 25 mg / mL, the organic solvent is anhydrous ethanol, the dipping and pulling process for preparing PVP film has a pulling speed of (1.0~1.5) mm / s, the number of pulling times is (7~9), and after pulling, it is baked at 80℃ for 100~120 min to finally obtain the PVP medium layer.
[0012] Furthermore, in step (4), when preparing the bilayer thin film with the structure of "Ti thin film / Al thin film" as the gate electrode at room temperature using DC magnetron sputtering, firstly, an aluminum target (purity 4N) is selected. Under the conditions of argon working pressure of 0.5-0.7 Pa, DC sputtering power of the aluminum target of 12-35 W, and sputtering time of 3-9 min, an Al thin film is deposited using a mask. Subsequently, a titanium target (purity 4N) is selected. Under the conditions of argon working pressure of 0.5-0.7 Pa, DC sputtering power of the titanium target of 9-12 W, and sputtering time of 2-3 min, a Ti thin film is deposited on the Al thin film using a mask, and finally, the gate electrode with the structure of "Ti thin film / Al thin film" is obtained.
[0013] Furthermore, the purity of the various target materials is 4N.
[0014] A heterogeneous dual-channel thin-film transistor comprises a substrate, a channel layer, a dielectric layer, a gate electrode, and source / drain electrodes. The substrate is a glass substrate. The channel layer is a heterogeneous bilayer film (amorphous TaLaO / amorphous InSnO film) composed of an amorphous TaLaO film and an amorphous InSnO film. The dielectric layer is a polytetravinylphenol (PVP) film. The source / drain electrodes and the gate electrode are bilayer films (Ti / Al film) composed of a Ti film and an Al film. The transistor is prepared using the method described above.
[0015] Compared with the prior art, the technical effects of this invention are reflected in: Considering that the high off-state current of TFT devices based on InSnO channel layers is mainly due to the excessively high electron carrier concentration of the InSnO channel layer itself, this invention proposes to form a heterogeneous bilayer channel layer by combining an amorphous tantalum lanthanum oxide (TaLaO) film with insulating properties with an amorphous InSnO film with a high electron carrier concentration. The strong bonding between tantalum and lanthanum with oxygen compared to the bonding between indium and tin with oxygen is utilized to suppress the generation of oxygen vacancy defects in the channel layer between the source and drain electrodes when the TFT device is in the off state, thereby enabling the device to have a lower off-state current. Simultaneously, the presence of the high electron carrier concentration InSnO film in the heterogeneous bilayer channel layer ensures that the conductive channel formed in the semiconductor channel layer between the source and drain electrodes has a high electron carrier concentration when the device is in the on state, thus enabling the device to have a higher on-state current. Furthermore, this invention patent also leverages the synergistic advantages of designing electrode structures (aluminum / titanium thin films) and improving the film deposition process conditions of each thin film layer constituting the device, ultimately providing new ideas and solutions for fabricating thin film transistors with both high performance and low energy consumption based on traditional low-cost processes (magnetron sputtering and solution methods).
[0016] Currently reported top-gate structure devices (which exhibit good environmental stability and share the same structure as this invention) aim to achieve high mobility (over 30 cm). 2 / Vs) often require sacrificing process costs; for example, the dielectric layer is often prepared using methods such as pulse-enhanced chemical vapor deposition (PECVD). However, this invention achieves a depth exceeding 60 cm² entirely based on low-cost processes (magnetron sputtering for channel layer preparation; low-temperature solution-based dielectric layer preparation). 2 Development of high mobility devices with a mobility of / Vs. Attached Figure Description
[0017] Figure 1 This is a schematic cross-sectional view of the thin-film transistor in this invention. Detailed Implementation
[0018] The technical solution of the present invention will be further defined below with reference to specific embodiments, but the scope of protection is not limited to the description.
[0019] Example 1 Using a glass substrate, a TFT with a top-gate coplanar structure is fabricated using a bilayer film with an amorphous TaLaO thin film / amorphous InSnO thin film structure as the channel layer, a PVP thin film as the dielectric layer, and a bilayer film with a Ti thin film / Al thin film structure as the source / drain electrode and gate electrode. The structure of the TFT is as follows. Figure 1 As shown, the specific steps are as follows: First, a bilayer film with an “amorphous TaLaO thin film / amorphous InSnO thin film” structure was prepared as the channel layer. Specifically, the following steps were taken: (1) An indium tin oxide target (purity 4N, indium-tin molar ratio In:Sn=7:3) was used to prepare an amorphous InSnO thin film under the conditions of argon working pressure of 0.6pa, oxygen partial pressure (O2 / (Ar+ O2)) of 15%, sputtering power of 75W, and sputtering time of 6min; (2) A tantalum target (purity 4N) and a lanthanum target (purity 4N) were selected to deposit an amorphous TaLaO thin film on the amorphous InSnO thin film under the conditions of argon working pressure of 0.6pa, oxygen partial pressure (O2 / (Ar+ O2)) of 25%, DC sputtering power of tantalum target and lanthanum target of 46.8W and 28.7W respectively, and sputtering time of 1min. Based on implementation steps (1)-(2), the channel layer with the structure of “amorphous TaLaO thin film / amorphous InSnO thin film” is finally obtained; Subsequently, a bilayer film of "Ti / Al" structure was prepared on the channel layer of "amorphous TaLaO film / amorphous InSnO film" structure as the source / drain electrode. The specific implementation was as follows: (1) Using an aluminum target (purity 4N), under the conditions of argon working pressure of 0.5pa, DC sputtering power of aluminum target of 38W, and sputtering time of 5min, an Al film was deposited using a mask; (2) Using a titanium target (purity 4N), under the conditions of argon working pressure of 0.5pa, DC sputtering power of titanium target of 12W, and sputtering time of 2min, a Ti film was deposited on the Al film using a mask. Based on the implementation steps (1)-(2), the source / drain electrode of "Ti / Al" structure was finally obtained; Then, a PVP dielectric layer was prepared on the aforementioned channel layer and source / drain electrodes. Specifically, the substrate containing the channel layer with an amorphous TaLaO thin film / amorphous InSnO thin film structure and the source / drain electrode with a Ti thin film / Al thin film structure was immersed in a sol of polytetravinylphenol in anhydrous ethanol at a concentration of 25 mg / mL. After being pulled at a speed of 1.0 mm / s, it was baked in an oven at 80°C for 100 minutes to solidify, thereby obtaining a PVP film. The entire pulling and annealing process was repeated 7 times to finally obtain the PVP dielectric layer.
[0020] Finally, a bilayer film with a "Ti thin film / Al thin film" structure was prepared as the gate electrode. Specifically, the process was as follows: (1) Using an aluminum target (4N purity), an Al thin film was deposited using a mask under the conditions of an argon working pressure of 0.5 Pa, a DC sputtering power of 38 W for the aluminum target, and a sputtering time of 5 min; (2) Using a titanium target (4N purity), a Ti thin film was deposited on the Al thin film using a mask under the conditions of an argon working pressure of 0.5 Pa, a DC sputtering power of 12 W for the titanium target, and a sputtering time of 2 min. Based on steps (1)-(2), a gate electrode with a "Ti thin film / Al thin film" structure was finally obtained. In this example, the TFT exhibits a high saturation mobility (60.1 cm⁻¹). 2 / Vs), a small threshold voltage (0.87 V), and a low off-state current (<10 Vs). -10 A).
[0021] Example 2 Using a glass substrate, a TFT with a top-gate coplanar structure is fabricated using a bilayer film with an amorphous TaLaO thin film / amorphous InSnO thin film structure as the channel layer, a PVP thin film as the dielectric layer, and a bilayer film with a Ti thin film / Al thin film structure as the source / drain electrode and gate electrode. The structure of the TFT is as follows. Figure 1 As shown, the specific steps are as follows: First, a bilayer film with an “amorphous TaLaO thin film / amorphous InSnO thin film” structure was prepared as the channel layer. Specifically, the implementation was as follows: (1) An indium tin oxide target (purity 4N, indium-tin molar ratio In:Sn=7:3) was used to prepare an amorphous InSnO thin film under the conditions of argon working pressure of 0.8pa, oxygen partial pressure (O2 / (Ar+ O2)) of 15%, sputtering power of 90W, and sputtering time of 9min; (2) A tantalum target (purity 4N) and a lanthanum target (purity 4N) were selected to deposit an amorphous TaLaO thin film on the amorphous InSnO thin film under the conditions of argon working pressure of 0.6pa, oxygen partial pressure (O2 / (Ar+ O2)) of 25%, DC sputtering power of tantalum target and lanthanum target of 46.8W and 28.7W respectively, and sputtering time of 1min. Based on implementation steps (1)-(2), the channel layer with the structure of “amorphous TaLaO thin film / amorphous InSnO thin film” is finally obtained; Subsequently, a bilayer film of "Ti / Al" structure was prepared on the channel layer of the "amorphous TaLaO film / amorphous InSnO film" structure as the source / drain electrode. The specific implementation was as follows: (1) Using an aluminum target (purity 4N), under the conditions of argon working pressure of 0.7pa, DC sputtering power of aluminum target of 55W, and sputtering time of 9min, an Al film was deposited using a mask; (2) Using a titanium target (purity 4N), under the conditions of argon working pressure of 0.7pa, DC sputtering power of titanium target of 20W, and sputtering time of 3min, a Ti film was deposited on the Al film using a mask. Based on the implementation steps (1)-(2), the source / drain electrode of the "Ti / Al" structure was finally obtained; Then, a PVP dielectric layer was prepared on the aforementioned channel layer and source / drain electrodes. Specifically, the substrate containing the channel layer with an amorphous TaLaO thin film / amorphous InSnO thin film structure and the source / drain electrode with a Ti thin film / Al thin film structure was immersed in a sol of polytetravinylphenol in anhydrous ethanol at a concentration of 25 mg / mL. After being pulled at a speed of 1.5 mm / s, it was baked in an oven at 80°C for 120 minutes to solidify, thereby obtaining a PVP film. The entire pulling and annealing process was repeated 9 times to finally obtain the PVP dielectric layer.
[0022] Finally, a bilayer film with a "Ti thin film / Al thin film" structure was prepared as the gate electrode. Specifically, the process was as follows: (1) Using an aluminum target (4N purity), an Al thin film was deposited using a mask under the conditions of an argon working pressure of 0.7 Pa, a DC sputtering power of 55 W for the aluminum target, and a sputtering time of 9 min; (2) Using a titanium target (4N purity), a Ti thin film was deposited on the Al thin film using a mask under the conditions of an argon working pressure of 0.7 Pa, a DC sputtering power of 20 W for the titanium target, and a sputtering time of 3 min. Based on steps (1)-(2), a gate electrode with a "Ti thin film / Al thin film" structure was finally obtained. In this example, the TFT exhibits a high saturation mobility (70.5 cm⁻¹). 2 / Vs), a small threshold voltage (0.40 V), and a low off-state current (<10 Vs). -10 A).
[0023] Example 3 Using a glass substrate, a TFT with a top-gate coplanar structure is fabricated using a bilayer film with an amorphous TaLaO thin film / amorphous InSnO thin film structure as the channel layer, a PVP thin film as the dielectric layer, and a bilayer film with a Ti thin film / Al thin film structure as the source / drain electrode and gate electrode. The structure of the TFT is as follows. Figure 1 As shown, the specific steps are as follows: First, a bilayer film with an "amorphous TaLaO thin film / amorphous InSnO thin film" structure was prepared as the channel layer. Specifically, the following steps were taken: (1) An indium tin oxide target (purity 4N, indium-tin molar ratio In:Sn=7:3) was used to prepare an amorphous InSnO thin film under the conditions of argon working pressure of 0.7pa, oxygen partial pressure (O2 / (Ar+ O2)) of 15%, sputtering power of 85W, and sputtering time of 8min; (2) A tantalum target (purity 4N) and a lanthanum target (purity 4N) were selected to deposit an amorphous TaLaO thin film on the amorphous InSnO thin film under the conditions of argon working pressure of 0.6pa, oxygen partial pressure (O2 / (Ar+ O2)) of 25%, DC sputtering power of tantalum target and lanthanum target of 46.8W and 28.7W respectively, and sputtering time of 1min. Based on implementation steps (1)-(2), the channel layer with the structure of “amorphous TaLaO thin film / amorphous InSnO thin film” is finally obtained; Subsequently, a bilayer film of "Ti / Al" structure was prepared on the channel layer of the "amorphous TaLaO film / amorphous InSnO film" structure as the source / drain electrode. The specific implementation was as follows: (1) Using an aluminum target (purity 4N), under the conditions of argon working pressure of 0.6pa, DC sputtering power of aluminum target of 45W, and sputtering time of 6min, an Al film was deposited using a mask; (2) Using a titanium target (purity 4N), under the conditions of argon working pressure of 0.6pa, DC sputtering power of titanium target of 16W, and sputtering time of 2min, a Ti film was deposited on the Al film using a mask. Based on the implementation steps (1)-(2), the source / drain electrode of the "Ti / Al" structure was finally obtained; Then, a PVP dielectric layer was prepared on the aforementioned channel layer and source / drain electrodes. Specifically, the substrate containing the channel layer with an amorphous TaLaO thin film / amorphous InSnO thin film structure and the source / drain electrode with a Ti thin film / Al thin film structure was immersed in a sol of polytetravinylphenol in anhydrous ethanol at a concentration of 25 mg / mL. After being pulled at a speed of 1.3 mm / s, it was baked in an oven at 80°C for 110 minutes to solidify, thereby obtaining a PVP film. The entire pulling and annealing process was repeated 8 times to finally obtain the PVP dielectric layer.
[0024] Finally, a bilayer film with a "Ti thin film / Al thin film" structure was prepared as the gate electrode. Specifically, the process was as follows: (1) Using an aluminum target (4N purity), an Al thin film was deposited using a mask under the conditions of an argon working pressure of 0.6 Pa, a DC sputtering power of 45 W for the aluminum target, and a sputtering time of 6 min; (2) Using a titanium target (4N purity), a Ti thin film was deposited on the Al thin film using a mask under the conditions of an argon working pressure of 0.6 Pa, a DC sputtering power of 16 W for the titanium target, and a sputtering time of 2 min. Based on steps (1)-(2), a gate electrode with a "Ti thin film / Al thin film" structure was finally obtained. In this example, the TFT exhibits a high saturation mobility (64.7 cm⁻¹). 2 / Vs), a small threshold voltage (0.53 V) and a low off-state current (<10 Vs). -10 A).
[0025] Example 4 Using a glass substrate, a TFT with a top-gate coplanar structure is fabricated using a bilayer film with an amorphous TaLaO thin film / amorphous InSnO thin film structure as the channel layer, a PVP thin film as the dielectric layer, and a bilayer film with a Ti thin film / Al thin film structure as the source / drain electrode and gate electrode. The structure of the TFT is as follows. Figure 1 As shown, the specific steps are as follows: First, a bilayer film with an “amorphous TaLaO thin film / amorphous InSnO thin film” structure was prepared as the channel layer. Specifically, the implementation was as follows: (1) An indium tin oxide target (purity 4N, indium-tin molar ratio In:Sn=7:3) was used to prepare an amorphous InSnO thin film under the conditions of argon working pressure of 0.6pa, oxygen partial pressure (O2 / (Ar+ O2)) of 15%, sputtering power of 81W, and sputtering time of 9min; (2) A tantalum target (purity 4N) and a lanthanum target (purity 4N) were selected to deposit an amorphous TaLaO thin film on the amorphous InSnO thin film under the conditions of argon working pressure of 0.6pa, oxygen partial pressure (O2 / (Ar+ O2)) of 25%, DC sputtering power of tantalum target and lanthanum target of 46.8W and 28.7W respectively, and sputtering time of 1min. Based on implementation steps (1)-(2), the channel layer with the structure of “amorphous TaLaO thin film / amorphous InSnO thin film” is finally obtained; Subsequently, a bilayer film of "Ti / Al" structure was prepared on the channel layer of the "amorphous TaLaO film / amorphous InSnO film" structure as the source / drain electrode. The specific implementation was as follows: (1) Using an aluminum target (purity 4N), under the conditions of argon working pressure of 0.7pa, DC sputtering power of aluminum target of 52W, and sputtering time of 8min, an Al film was deposited using a mask; (2) Using a titanium target (purity 4N), under the conditions of argon working pressure of 0.6pa, DC sputtering power of titanium target of 19W, and sputtering time of 3min, a Ti film was deposited on the Al film using a mask. Based on the implementation steps (1)-(2), the source / drain electrode of the "Ti / Al" structure was finally obtained; Then, a PVP dielectric layer was prepared on the aforementioned channel layer and source / drain electrodes. Specifically, the substrate containing the channel layer with an amorphous TaLaO thin film / amorphous InSnO thin film structure and the source / drain electrode with a Ti thin film / Al thin film structure was immersed in a sol of polytetravinylphenol in anhydrous ethanol at a concentration of 25 mg / mL. After being pulled at a speed of 1.3 mm / s, it was baked in an oven at 80°C for 115 minutes to solidify, thereby obtaining a PVP film. The entire pulling and annealing process was repeated 9 times to finally obtain the PVP dielectric layer.
[0026] Finally, a bilayer film with a "Ti thin film / Al thin film" structure was prepared as the gate electrode. Specifically, the following steps were taken: (1) Using an aluminum target (4N purity), an Al thin film was deposited using a mask under the conditions of an argon working pressure of 0.7 Pa, a DC sputtering power of 52 W for the aluminum target, and a sputtering time of 8 min; (2) Using a titanium target (4N purity), a Ti thin film was deposited on the Al thin film using a mask under the conditions of an argon working pressure of 0.6 Pa, a DC sputtering power of 19 W for the titanium target, and a sputtering time of 3 min. Based on steps (1)-(2), a gate electrode with a "Ti thin film / Al thin film" structure was finally obtained. In this example, the TFT exhibits a high saturation mobility (63.0 cm⁻¹). 2 / Vs), a small threshold voltage (0.62 V), and a low off-state current (<10 Vs). -10 A).
[0027] The saturation mobility, threshold voltage, and off-state current of the thin-film transistors obtained in Examples 1-4 are compared as follows:
[0028] The above data demonstrates that this invention provides a method for preparing films with high mobility (>60 cm⁻¹) based on traditional film-forming processes (magnetron sputtering and solution methods). 2 / Vs) Low energy consumption (e.g., off-state current <10) -10A feasible solution is provided for thin-film transistors (0V < threshold voltage < 1V).
[0029] Current technologies, while introducing low-electron-weight elements (such as Al and Ga) into the InSnO channel layer or optimizing the InSnO material composition to reduce the carrier concentration of the InSnO channel layer, have effectively optimized the threshold voltage and off-state current of InSnO-based TFT devices. However, the final device mobility has not reached the 60 cm⁻¹ mobility described in this patented technology. 2 High mobility / Vs. For example, one report states that optimizing the InSnO material composition (by adjusting the In content) ultimately achieved a device mobility of 3.0 cm⁻¹. 2 / Vs and 8.94cm 2 / Vs; After optimizing the Al content by introducing Al into the InSnO channel layer, the optimal device mobility achieved was 13.3 cm⁻¹. 2 / Vs; The optimal device mobility achieved by introducing Ga elements into the InSnO channel layer and through synergistic device structure design is 41.9–54.5 cm⁻¹. 2 / V s (and this work is based on PEALD technology for film formation, directly sacrificing process cost).
[0030] Finally, it should be noted that the above embodiments are merely representative examples of the present invention. Obviously, the technical solution of the present invention is not limited to the above embodiments, and many variations are possible. All variations that can be directly derived or conceived by those skilled in the art from the content disclosed in this invention should be considered within the scope of protection of this invention.
Claims
1. A method for fabricating a thin-film transistor with a heterogeneous dual-channel layer, characterized in that, Includes the following steps: (1) On a glass substrate, amorphous InSnO thin films and amorphous TaLaO thin films were prepared sequentially at room temperature using radio frequency magnetron sputtering and DC magnetron sputtering, respectively, to form a channel layer with an "amorphous TaLaO thin film / amorphous InSnO thin film" structure; (2) On the above-mentioned channel layer, Al thin film and Ti thin film are prepared sequentially at room temperature by DC magnetron sputtering in combination with a mask to form source / drain electrode with "Ti thin film / Al thin film" structure; (3) Based on the dip-coating process, a dielectric layer of PVP film is prepared on the above-mentioned channel layer and source / drain electrodes using a sol solution of polytetravinylphenol; (4) On the above PVP dielectric layer, combined with a mask, Al thin film and Ti thin film are prepared sequentially at room temperature by DC magnetron sputtering to form a gate electrode with a "Ti thin film / Al thin film" structure, thus obtaining the desired device.
2. The method for fabricating a thin-film transistor with a heterogeneous dual-channel layer according to claim 1, characterized in that, In step (1), when preparing a heterogeneous bilayer film with an "amorphous TaLaO thin film / amorphous InSnO thin film" structure as the channel layer using radio frequency magnetron sputtering and DC magnetron sputtering at room temperature, an indium tin oxide target is first used to prepare an amorphous InSnO thin film under the conditions of an argon working gas pressure of 0.6-0.8 Pa, an oxygen partial pressure (O2 / (Ar+O2)) of 15%, a sputtering power of 75-90 W, and a sputtering time of 6-9 min. Subsequently, tantalum and lanthanum targets are selected to deposit an amorphous TaLaO thin film on the amorphous InSnO thin film under the conditions of an argon working gas pressure of 0.6 Pa, an oxygen partial pressure (O2 / (Ar+O2)) of 25%, DC sputtering powers of tantalum and lanthanum targets of 46.8 W and 28.7 W respectively, and a sputtering time of 1 min, thus finally obtaining a channel layer with an "amorphous TaLaO thin film / amorphous InSnO thin film" structure.
3. The method for fabricating a thin-film transistor with a heterogeneous dual-channel layer according to claim 1, characterized in that, The indium tin oxide target has an indium-tin molar ratio of In:Sn=7:
3.
4. The method for fabricating a thin-film transistor with a heterogeneous dual-channel layer according to claim 1, characterized in that, In step (2), when preparing a bilayer film with a "Ti thin film / Al thin film" structure as a source / drain electrode at room temperature using DC magnetron sputtering, an aluminum target is first selected. Under the conditions of an argon working pressure of 0.5-0.7 Pa, a DC sputtering power of 38-55 W for the aluminum target, and a sputtering time of 5-9 min, an Al thin film is deposited using a mask. Subsequently, a titanium target is selected. Under the conditions of an argon working pressure of 0.5-0.7 Pa, a DC sputtering power of 12-20 W for the titanium target, and a sputtering time of 2-3 min, a Ti thin film is deposited on the Al thin film using a mask, and finally, a source / drain electrode with a "Ti thin film / Al thin film" structure is obtained.
5. The method for fabricating a thin-film transistor with a heterogeneous dual-channel layer according to claim 1, characterized in that, The polytetravinylphenol sol solution in step (3) has a concentration of 25 mg / mL and anhydrous ethanol as the organic solvent. The dipping and pulling process for preparing PVP film has a pulling speed of (1.0~1.5) mm / s and a pulling number of (7~9) times. After pulling, the film is baked at 80°C for 100~120 min to finally obtain the PVP medium layer.
6. The method for fabricating a thin-film transistor with a heterogeneous dual-channel layer according to claim 1, characterized in that, In step (4), when preparing a bilayer thin film with a "Ti thin film / Al thin film" structure as a gate electrode at room temperature using DC magnetron sputtering, an aluminum target is first selected. Under the conditions of an argon working pressure of 0.5-0.7 Pa, a DC sputtering power of 12-35 W for the aluminum target, and a sputtering time of 3-9 min, an Al thin film is deposited using a mask. Subsequently, a titanium target is selected. Under the conditions of an argon working pressure of 0.5-0.7 Pa, a DC sputtering power of 9-12 W for the titanium target, and a sputtering time of 2-3 min, a Ti thin film is deposited on the Al thin film using a mask, and finally, a gate electrode with a "Ti thin film / Al thin film" structure is obtained.
7. The method for fabricating a thin-film transistor with a heterogeneous dual-channel layer according to claim 1, characterized in that, The purity of all types of target materials is 4N.
8. A thin-film transistor with a heterogeneous dual-channel layer, characterized in that, It consists of a substrate, a channel layer, a dielectric layer, a gate electrode, and source / drain electrodes; the substrate is a glass substrate; the channel layer is a heterogeneous bilayer film (amorphous TaLaO thin film / amorphous InSnO thin film) composed of an amorphous TaLaO thin film and an amorphous InSnO thin film; the dielectric layer is a polytetravinylphenol (PVP) thin film; the source / drain electrodes and the gate electrode are bilayer films (Ti thin film / Al thin film) composed of a Ti thin film and an Al thin film.
9. The thin-film transistor with a heterogeneous dual-channel layer according to claim 8, characterized in that, It is prepared by the preparation method according to any one of claims 1-7.