Display device

Abstract

A display device according to an embodiment of the present invention is provided with: a substrate having a display region in which a plurality of sub-pixels are arranged; a rib layer having a pixel opening in each of the plurality of sub-pixels; a partition wall surrounding each of the plurality of sub-pixels, the partition wall including a conductive lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion; a plurality of display elements disposed in the plurality of sub-pixels, respectively, and including an organic layer emitting light according to application of a voltage; a plurality of first sealing layers formed of an inorganic insulating material and respectively covering the plurality of display elements; and a second sealing layer formed of an inorganic insulating material and covering the plurality of first sealing layers. Further, the partition walls are divided into a plurality of segments by slits, and the second sealing layer is in contact with the rib layer in the slits.

Description

Cross Reference to Related Applications

[0001] This application claims priority based on Japanese Patent Application No. 2024-175794 filed on October 7, 2024, and incorporates by reference the entire disclosure of the Japanese Patent Application. TECHNICAL FIELD

[0002] Embodiments of the present application relate to a display device. BACKGROUND

[0003] In recent years, a display device using an organic light emitting diode (OLED) as a display element has been put into practical use. In such a display device, a technique for improving yield is required. SUMMARY

[0004] According to an embodiment, a display device includes a substrate having a display region in which a plurality of sub-pixels are arranged; a rib layer having a pixel opening in each of the plurality of sub-pixels; a partition wall surrounding each of the plurality of sub-pixels, the partition wall including a lower portion that is conductive and is arranged above the rib layer, and an upper portion having an end portion that protrudes from a side surface of the lower portion; a plurality of display elements arranged in the plurality of sub-pixels, respectively, and including an organic layer that emits light in accordance with a voltage application; a plurality of first sealing layers formed of an inorganic insulating material and covering the plurality of display elements, respectively; and a second sealing layer formed of an inorganic insulating material and covering the plurality of first sealing layers. Further, the partition wall is divided into a plurality of segments by a slit, and the second sealing layer is in contact with the rib layer in the slit.

[0005] According to another aspect, end portions of adjacent first sealing layers are separated from each other above at least a portion of the partition wall, and the second sealing layer is in contact with the upper portion in a region between the end portions.

[0006] According to another viewpoint, the display device comprises: a substrate having a display area with a plurality of sub-pixels and a peripheral area surrounding the display area; a rib layer formed in the display area and the peripheral area, and having a pixel opening in each of the plurality of sub-pixels; a first partition surrounding each of the plurality of sub-pixels, comprising a conductive lower portion disposed above the rib layer and an upper portion having an end portion protruding from the side of the lower portion; a plurality of display elements respectively disposed in the plurality of sub-pixels and including an organic layer that emits light upon voltage application; a plurality of first sealing layers formed of an inorganic insulating material and respectively covering the plurality of display elements; a second sealing layer formed of an inorganic insulating material and covering the plurality of first sealing layers; and a dam portion disposed in the peripheral area and surrounding the display area. Further, at least a portion of the rib layer in the region between the end of the substrate and the dam portion is removed.

[0007] Additionally, according to an embodiment, a method for manufacturing a display device includes: forming a rib layer above a substrate; forming a first partition surrounding each of a plurality of sub-pixels, the first partition including a conductive lower portion located above the rib layer and an upper portion having an end portion protruding from the side of the lower portion; forming a plurality of display elements including an organic layer that emits light according to voltage application for each of the plurality of sub-pixels, and a plurality of first sealing layers made of inorganic insulating material covering each of the display elements; forming a second sealing layer made of inorganic insulating material covering the plurality of first sealing layers; and forming a resin layer covering a portion of the second sealing layer.

[0008] Based on the structure and manufacturing methods of these display devices, the yield rate of display devices can be improved. Attached Figure Description

[0009] Figure 1 This is a diagram showing a structural example of the display device according to the first embodiment.

[0010] Figure 2 This is a schematic top view showing an example of the layout of subpixels.

[0011] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device along line III-III.

[0012] Figure 4 It is a top view showing a portion of the elements of the display device.

[0013] Figure 5 It is along Figure 2 A schematic cross-sectional view of the VV line display device.

[0014] Figure 6 It is alongFigure 2 A schematic cross-sectional view of the display device with the VI-VI line.

[0015] Figure 7 yes Figure 4 A rough top view of the area circled by box VII.

[0016] Figure 8 It is along Figure 7 A schematic cross-sectional view of the display device for lines VIII-VIII.

[0017] Figure 9 It is along Figure 7 A schematic cross-sectional view of the display device for the IX-IX line.

[0018] Figure 10 This is a schematic top view of the mother substrate of the first embodiment.

[0019] Figure 11 This is a schematic top view of the panel section in the first embodiment.

[0020] Figure 12 This is a flowchart illustrating an example of a method for manufacturing a display device according to the first embodiment.

[0021] Figure 13A It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0022] Figure 13B It means succession Figure 13A A rough cross-sectional view of the subsequent processes.

[0023] Figure 13C It means succession Figure 13B A rough cross-sectional view of the subsequent processes.

[0024] Figure 13D It means succession Figure 13C A rough cross-sectional view of the subsequent processes.

[0025] Figure 13E It means succession Figure 13D A rough cross-sectional view of the subsequent processes.

[0026] Figure 13F It means succession Figure 13E A rough cross-sectional view of the subsequent processes.

[0027] Figure 13G It means succession Figure 13F A rough cross-sectional view of the subsequent processes.

[0028] Figure 13H It means succession Figure 13G A rough cross-sectional view of the subsequent processes.

[0029] Figure 14 is a schematic plan view of the area encircled with a frame XIV in Figure 11

[0030] Figure 15 is a schematic sectional view of the panel portion along the line XV-XV in Figure 14

[0031] Figure 16A is a sectional view showing a comparative example.

[0032] Figure 16B is another sectional view showing a comparative example.

[0033] Figure 16C is still another sectional view showing a comparative example.

[0034] Figure 17A is a sectional view showing an effect of the first embodiment.

[0035] Figure 17B is another sectional view showing an effect of the first embodiment.

[0036] Figure 17C is still another sectional view showing an effect of the first embodiment.

[0037] Figure 18 is a schematic sectional view of the panel portion of the second embodiment.

[0038] Figure 19 is a schematic sectional view of the panel portion of the third embodiment.

[0039] Figure 20 is a schematic sectional view of the panel portion of the fourth embodiment.

[0040] Figure 21 is a schematic sectional view of the panel portion of the fifth embodiment.

[0041] Figure 22 is a schematic sectional view of the panel portion of the sixth embodiment.

[0042] Figure 23 is a schematic sectional view of the panel portion of the seventh embodiment. DETAILED DESCRIPTION

[0043] Some embodiments will be described with reference to the drawings.

[0044] ​​The disclosure is nothing more than an example, and appropriate modifications that a person skilled in the art can easily think of while maintaining the gist of the application are of course included in the scope of the application. In addition, with regard to the drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically shown compared to the actual form, but this is nothing more than an example and does not limit the explanation of the application. In addition, in the present specification and the drawings, the same reference numerals are attached to the components that have the same or similar functions as those described in the drawings that have appeared, and sometimes the repeated detailed description is appropriately omitted.

[0045] Note that, in the drawings, an X-axis, a Y-axis, and a Z-axis orthogonal to each other are shown as needed and for the convenience of understanding. The direction along the X-axis is referred to as the X direction, the direction along the Y-axis is referred to as the Y direction, and the direction along the Z-axis is referred to as the Z direction. The Z direction is the normal direction of the plane including the X direction and the Y direction. In addition, the case where various elements are observed in parallel with the Z direction is referred to as plan view.

[0046] The display device of each embodiment is an organic electroluminescent display device provided with an organic light emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0047] [1st Embodiment]

[0048] Figure 1 is a view showing a structural example of a display device DSP of the 1st embodiment. The display device DSP is provided with an insulating substrate 10. The substrate 10 has a display region DA in which an image is displayed, and a surrounding region SA around the display region DA. The substrate 10 can be glass or a resin film having flexibility.

[0049] In the present embodiment, the shape of the substrate 10 and the display region DA in plan view is circular. However, the shape of the substrate 10 and the display region DA in plan view is not limited to circular, and can be other shapes such as rectangular, square, or elliptical.

[0050] The display region DA is provided with a plurality of pixels PX arranged in a matrix shape in the X direction and the Y direction. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, a case is assumed in which the pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. The pixel PX can also include a sub-pixel SP of another color such as white in addition to or instead of any one of the sub-pixels SP1, SP2, SP3.

[0051] The display device DSP also has a terminal portion T disposed in the peripheral area SA. A flexible circuit board that supplies a voltage or a signal for driving the display device DSP is connected to the terminal portion T, for example.

[0052] The sub-pixel SP has a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 has a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by thin film transistors, for example.

[0053] In the display area DA, a plurality of scan lines G that supply a scan signal to the pixel circuit 1 of each sub-pixel SP, a plurality of signal lines S that supply an image signal to the pixel circuit 1 of each sub-pixel SP, and a plurality of power lines PL are disposed. In the example shown in FIG. 1, the scan lines G and the power lines PL extend in the X direction, and the signal lines S extend in the Y direction, but the example is not limited thereto. Figure 1

[0054] The gate of the pixel switch 2 is connected to the scan line G. One of the source and the drain of the pixel switch 2 is connected to the signal line S, and the other is connected to the gate of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source and the drain is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0055] Note that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 can have more thin film transistors and capacitors.

[0056] Figure 2 is a schematic plan view showing an example of the layout of the sub-pixels SP1, SP2, SP3 that constitute one pixel PX. In the example shown in FIG. 2, the sub-pixels SP1, SP3 are arranged in the Y direction. In addition, the sub-pixels SP1, SP3 are arranged in the X direction with the sub-pixel SP2 therebetween. Figure 2

[0057] In the case where the sub-pixels SP1, SP2, SP3 are arranged in this way, columns in which the sub-pixels SP1, SP3 are alternately arranged in the Y direction and columns in which a plurality of sub-pixels SP2 are repeatedly arranged in the Y direction are formed in the display area DA. These columns are alternately arranged in the X direction. Note that the layout of the sub-pixels SP1, SP2, SP3 is not limited to the example shown in FIG. 3. Figure 2

[0058] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, AP3 over the sub-pixels SP1, SP2, SP3, respectively. In the example shown in FIG. 4, the pixel openings AP1, AP2, AP3 are arranged in the Y direction. Figure 2 ​​​In the example of FIG. 1, the pixel openings AP1, AP2, and AP3 are each rectangular. The area of the pixel opening AP1 is larger than that of the pixel opening AP3. In addition, the area of the pixel opening AP2 is larger than that of the pixel opening AP1. However, the shapes of the pixel openings AP1, AP2, and AP3 are not limited to this example.

[0059] The sub-pixel SP1 includes the lower electrode LE1, the upper electrode UE1, and the organic layer OR1, which overlap the pixel opening AP1. The sub-pixel SP2 includes the lower electrode LE2, the upper electrode UE2, and the organic layer OR2, which overlap the pixel opening AP2. The sub-pixel SP3 includes the lower electrode LE3, the upper electrode UE3, and the organic layer OR3, which overlap the pixel opening AP3.

[0060] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 constitute a display element DE1 of the sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 constitute a display element DE2 of the sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 constitute a display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 can further include a cover layer described later. The rib layer 5 surrounds each of the display elements DE1, DE2, and DE3.

[0061] A conductive barrier wall 6A (first barrier wall) is disposed above the rib layer 5. The barrier wall 6A functions as a wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The barrier wall 6A overlaps the rib layer 5 as a whole and has the same planar shape as the rib layer 5. The barrier wall 6A surrounds the sub-pixels SP1, SP2, and SP3.

[0062] The barrier wall 6A has a plurality of slits SL extending in the Y direction. In the example of FIG. 1, the barrier wall 6A has a plurality of slits SL extending in the Y direction. Figure 2 In the example of FIG. 1, the sub-pixels SP1, SP2, and SP3 constituting one pixel PX are disposed between two slits SL in the X direction. Further, the barrier wall 6A has a connection portion CT connecting portions (segments SG described later) separated by the slits SL. Note that the configuration of the slits SL and the connection portion CT is not limited to the example of FIG. 1. For example, there can be a continuous slit SL between the two ends in the Y direction of the display region DA. Figure 2

[0063] The barrier wall 6A has a plurality of slits SL extending in the Y direction. In the example of FIG. 1, the barrier wall 6A has a plurality of slits SL extending in the Y direction.

[0064] The barrier wall 6A has a plurality of slits SL extending in the Y direction. In the example of FIG. 1, the barrier wall 6A has a plurality of slits SL extending in the Y direction. Figure 2 ​In the example, sealing layers SE11, SE12, and SE13 do not overlap with slit SL. As another example, at least one of the sealing layers SE11, SE12, and SE13 may overlap with slit SL.

[0065] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP along line III-III. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes... Figure 1 The diagram shows various circuits and wiring, including pixel circuit 1, scan line G, signal line S, and power line PL. Circuit layer 11 is covered by organic insulating layer 12. Organic insulating layer 12 functions as a planarization film to flatten the unevenness generated by circuit layer 11.

[0066] Lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. Rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The periphery of the lower electrodes LE1, LE2, and LE3 is covered by rib layer 5. Although not on... Figure 3 As shown in the cross-section, the lower electrodes LE1, LE2, and LE3 are connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided on the organic insulating layer 12.

[0067] The partition 6A includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a wider width than the lower portion 61. That is, the partition 6A is an overhanging shape in which the two ends of the upper portion 62 protrude beyond the sides of the lower portion 61.

[0068] exist Figure 3 In this example, the lower portion 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Figure 3 In the example, the two ends of the bottom layer 63 protrude from the sides of the shaft layer 64.

[0069] In addition, Figure 3 In this example, the upper part 62 has a first top layer 65 and a second top layer 66 disposed on the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. It is not limited to this, the first top layer 65 and the second top layer 66 can also have the same width.

[0070] Organic layer OR1 covers lower electrode LE1 through pixel opening AP1. Upper electrode UE1 covers organic layer OR1 and is opposite to lower electrode LE1. Organic layer OR2 covers lower electrode LE2 through pixel opening AP2. Upper electrode UE2 covers organic layer OR2 and is opposite to lower electrode LE2. Organic layer OR3 covers lower electrode LE3 through pixel opening AP3. Upper electrode UE3 covers organic layer OR3 and is opposite to lower electrode LE3. Upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of partition 6A.

[0071] Display element DE1 includes a capping layer CP1 covering the upper electrode UE1. Display element DE2 includes a capping layer CP2 covering the upper electrode UE2. Display element DE3 includes a capping layer CP3 covering the upper electrode UE3. The capping layers CP1, CP2, and CP3 respectively serve as optical adjustment layers for improving the light acquisition efficiency emitted by the organic layers OR1, OR2, and OR3.

[0072] In the following description, the multilayer comprising organic layer OR1, upper electrode UE1 and capping layer CP1 is referred to as laminated film FL1, the multilayer comprising organic layer OR2, upper electrode UE2 and capping layer CP2 is referred to as laminated film FL2, and the multilayer comprising organic layer OR3, upper electrode UE3 and capping layer CP3 is referred to as laminated film FL3.

[0073] Sealing layers SE11, SE12, and SE13 (first sealing layers) are respectively disposed on sub-pixels SP1, SP2, and SP3. Sealing layer SE11 continuously covers the laminated film FL1 and the surrounding partition wall 6A. Sealing layer SE12 continuously covers the laminated film FL2 and the surrounding partition wall 6A. Sealing layer SE13 continuously covers the laminated film FL3 and the surrounding partition wall 6A.

[0074] exist Figure 3 In the example, the sealing layer SE11 on the partition 6A between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition 6A. Additionally, the sealing layer SE11 on the partition 6A between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition 6A. However, any two of the sealing layers SE11, SE12, and SE13 can also be in contact above the partition 6A.

[0075] Sealing layers SE11, SE12, and SE13 are covered by sealing layer SE2 (the second sealing layer). See reference. Figure 5 and Figure 6 The details of the sealing layer SE2 will be described later.

[0076] The sealing layer SE2 is covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE3 (3rd sealing layer). The sealing layer SE3 is covered with a resin layer RS2. The resin layers RS1, RS2 and the sealing layer SE3 are provided at least continuously over the entire display region DA, and a part thereof also extends to the surrounding region SA.

[0077] In Figure 3 In the example, a touch panel electrode TP for detecting a touch operation of a user is provided on the sealing layer SE3. The touch panel electrode TP is formed of, for example, a metal material, and has the same shape as the barrier rib 6A in plan view.

[0078] A cover member such as a polarizing plate, a protective film or a glass cover can be further provided above the resin layer RS2. Such a cover member can be adhered to the resin layer RS2, for example, by an adhesive layer such as an OCA (Optical Clear Adhesive).

[0079] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2, SE3 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx) or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2, SE3 are formed of silicon nitride. The resin layers RS1, RS2 are formed of, for example, a resin material (organic insulating material) such as an epoxy resin or an acrylic resin.

[0080] The lower electrodes LE1, LE2, LE3 are formed of, for example, a reflective layer formed of silver, and a pair of conductive oxide layers covering the upper surface and the lower surface of the reflective layer, respectively. Each conductive oxide layer can be formed of, for example, a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide) or IGZO (Indium Gallium Zinc Oxide).

[0081] The upper electrodes UE1, UE2, UE3 are formed of, for example, a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0082] The organic layers OR1, OR2, OR3 are composed of a plurality of thin films including a light-emitting layer. In one example, the organic layers OR1, OR2, OR3 have a structure in which a hole-injection layer, a hole-transport layer, an electron-blocking layer, a light-emitting layer, a hole-blocking layer, an electron-transport layer, and an electron-injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, OR3 can have other structures such as a so-called tandem structure including a plurality of light-emitting layers.

[0083] The cover layers CP1, CP2, CP3 have, for example, a stacked structure in which a plurality of transparent layers are stacked. These transparent layers can include layers formed of inorganic materials and layers formed of organic materials. In addition, these transparent layers have different refractive indexes from each other. For example, the refractive indexes of these transparent layers are different from the refractive indexes of the upper electrodes UE1, UE2, UE3 and the refractive indexes of the sealing layers SE11, SE12, SE13. Note that at least one of the cover layers CP1, CP2, CP3 can be omitted.

[0084] The bottom layer 63 and the shaft layer 64 of the partition wall 6A are formed of a metal material. As the metal material of the bottom layer 63, for example, molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), or a molybdenum-niobium alloy (MoNb) can be used. As the metal material of the shaft layer 64, for example, aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), or an aluminum-silicon alloy (AlSi) can be used. Note that the shaft layer 64 can also be formed of an insulating material.

[0085] The first top layer 65 of the partition wall 6A is formed of, for example, a metal material. In addition, the second top layer 66 of the partition wall 6A is formed of, for example, a conductive oxide. As the metal material of the first top layer 65, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used. As the conductive oxide of the second top layer 66, for example, ITO or IZO can be used. Note that the upper portion 62 can have three or more layers, and can also be formed of a single layer. Further, the upper portion 62 can include a layer formed of an insulating material.

[0086] A common voltage is supplied to the partition wall 6A. The common voltage is supplied to the upper electrodes UE1, UE2, UE3 which are in contact with the lower portion 61. A pixel voltage corresponding to an image signal of the signal line S is supplied to the lower electrodes LE1, LE2, LE3 through the pixel circuit 1 of the sub-pixel SP1, SP2, SP3, respectively.

[0087] The organic layers OR1, OR2, OR3 emit light according to the voltage application. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0088] As other examples, the light-emitting layers of the organic layers OR1, OR2, OR3 can also emit light in the same color (e.g., white). In this case, the display device DSP can also be provided with a color filter that converts the light emitted by the light-emitting layers into light in the colors corresponding to the sub-pixels SP1, SP2, SP3. In addition, the display device DSP can also be provided with a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light in the colors corresponding to the sub-pixels SP1, SP2, SP3.

[0089] Figure 4 is a schematic plan view showing part of the elements of the display device DSP. The partition wall 6A is formed by Figure 2 The plurality of slits SL also shown are partitioned into a plurality of segments SG. Note that, in Figure 4 , the slits SL and the segments SG are schematically shown. For example, as Figure 2 indicated, in the case where the slits SL are located on both sides of the pixel PX in the X direction, more slits SL are formed in the display region DA.

[0090] As indicated in Figure 2 , at least part of the plurality of segments SG are connected by a connection portion CT that crosses the slits SL. On the other hand, among the plurality of slits SL, there can also be slits that are not provided with a connection portion CT.

[0091] One end of each segment SG in the extension direction of the slit SL (the Y direction in this embodiment) is connected to a power supply line PW provided in the surrounding region SA. The power supply line PW is connected to the terminal portion T. A common voltage is applied from the terminal portion T to each segment SG via the power supply line PW. In Figure 4 the example shown, the other end of each segment SG is separated by the slit SL and is not connected by a conductive member like the power supply line PW.

[0092] Figure 5 is a schematic cross-sectional view of the display device DSP along the V-V line in Figure 2 , showing part of the sub-pixels SP1, SP2 adjacent across the slit SL and the partition wall 6A therebetween. The side portion of the partition wall 6A facing the slit SL is overhanging in that the upper portion 62 protrudes from the side surface of the shaft layer 64. In the slit SL, the rib layer 5 is not opened.

[0093] In Figure 5 the example, the end portion E11 of the sealing layer SE11 and the end portion E12 of the sealing layer SE12 are both located above the partition wall 6A. That is, the sealing layers SE11, SE12 do not overlap the slit SL. As another example, the end portions E11, E12 can also be located in the slit SL. In this case, a portion of the slit SL overlaps the sealing layers SE11, SE12.

[0094] Gaps G1, G2 (spaces) are respectively formed between the upper portion 62 of the partition wall 6A and the sealing layers SE11, SE12 above it. The slit SL is filled with the resin layer RS1. The gaps G1, G2 can be filled with the resin layer RS1, or at least a portion of them can be hollow. In addition, the laminated films FL1, FL2 can be respectively arranged in at least a portion of the gaps G1, G2.

[0095] The sealing layer SE2 has a first portion P1 that covers the sealing layers SE11, SE12, and a second portion P2 that is located in the slit SL. The first portion P1 covers not only the upper surfaces of the sealing layers SE11, SE12, but also the end portions E11, E12. Further, in Figure 5 the example, the first portion P1 also covers the vicinity of the entrances of the gaps G1, G2 (a portion of the top surfaces of the gaps G1, G2).

[0096] The second portion P2 contacts the rib layer 5 in the slit SL and is covered with the resin layer RS1. Further, the second portion P2 covers the bottom layer 63, the shaft layer 64, the first top layer 65, and the second top layer 66 of the partition wall 6A that are exposed from the sealing layers SE11, SE12. More specifically, the second portion P2 directly contacts the bottom layer 63, the shaft layer 64, the first top layer 65, and the second top layer 66 of the partition wall 6A that are exposed from the sealing layers SE11, SE12. In Figure 5 the example, the first portion P1 is separated from the second portion P2. As another example, the first portion P1 can be connected to the second portion P2.

[0097] Figure 6 is a schematic cross-sectional view of the display device DSP along the VI-VI line in Figure 2 , showing a portion of the sub-pixels SP1, SP2 and the partition wall 6A therebetween. In Figure 6 the example, the end portion E11 of the sealing layer SE11 and the end portion E12 of the sealing layer SE12 are both located above the partition wall 6A and are separated in the X direction. In addition, gaps G1, G2 are respectively formed between the upper portion 62 of the partition wall 6A and the sealing layers SE11, SE12 above it.

[0098] The space between the end portions E11, E12 is filled with the resin layer RS1. The gaps G1, G2 can be filled with the resin layer RS1 as described above, or at least a part thereof can be hollow.

[0099] In Figure 6 a cross section, the first portion P1 of the sealing layer SE2 also covers the end portions E11, E12. Further, the sealing layer SE2 has a third portion P3 on the partition wall 6A. The third portion P3 contacts the upper portion 62 (the second top layer 66) in the region between the end portions E11, E12, and is covered with the resin layer RS1. In Figure 6 In the example of Figure 6 , the first portion P1 is separated from the third portion P3. As another example, the first portion P1 can be connected to the third portion P3.

[0100] The sealing layer SE11 has a thickness T1. The sealing layer SE2 has a thickness T2 smaller than the thickness T1 (T1 > T2). In one example, the thickness T2 is 1 / 2 or less of the thickness T1. If specific numerical values applicable to this case are cited, the thickness T1 is 2.0 μm or more, and the thickness T2 is 500 nm to 1.0 μm. Note that the thickness of the sealing layers SE12, SE13 is, for example, the same as the thickness T1 of the sealing layer SE11.

[0101] In Figure 5 and Figure 6 , the vicinity of the boundary of the sub-pixels SP1, SP2 is focused on, but the same structure can be applied to the vicinity of the boundary of the sub-pixels SP1, SP3 and the vicinity of the boundary of the sub-pixels SP2, SP3. The first portion P1 of the sealing layer SE2 also covers the upper surface and the end portions of the sealing layer SE13.

[0102] Figure 7 is Figure 4 a schematic plan view of the area encircled with the frame VII in

[0103] The partition wall 6B is provided in the peripheral region SA. Although simplified in Figure 7 , the partition wall 6B has a plurality of openings. The partition wall 6B is connected to the partition wall 6A provided in the display region DA.

[0104] The dam portions DM1, DM2, DM3, DM4, DM5 are provided between the partition wall 6B and the end portion E10. The dam portions DM1, DM2, DM3 are annular and surround the display region DA and the partition wall 6B. However, the dam portion DM3 is interrupted in the vicinity of the terminal portion T.

[0105] The dam portions DM4, DM5 are located between the terminal portion T and the dam portion DM2. The dam portion DM4 branches into the dam portions DM41, DM42 in the vicinity of the end portion E10.

[0106] The terminal portion T has a plurality of pads PD. These pads PD have a shape longer in the Y direction, and are arranged in the X direction between the dam portion DM5 and the end portion E10. A plurality of partition walls 6C (2nd partition walls) are arranged near the end portion E10. These partition walls 6C are arranged at a prescribed interval along the end portion E10, for example.

[0107] Figure 8 is a cross-sectional view of the display device DSP along the VIII-VIII line in Figure 7 . The partition walls 6B, 6C have the same configuration as the partition wall 6A. That is, the partition walls 6B, 6C include the lower portion 61 and the upper portion 62. In addition, the lower portion 61 includes the bottom layer 63 and the shaft layer 64, and the upper portion 62 includes the 1st top layer 65 and the 2nd top layer 66. At the end portion of the partition walls 6B, 6C, the upper portion 62 protrudes more than the side surface of the lower portion 61.

[0108] Figure 3 The circuit layer 11 shown in FIG. 8 includes inorganic insulating layers 31, 32, 33 formed of inorganic insulating materials, an organic insulating layer 34 formed of an organic insulating material, and metal layers 41, 42, 43. The inorganic insulating layer 31 covers the upper surface of the substrate 10. The metal layer 41 is arranged on the inorganic insulating layer 31. The inorganic insulating layer 32 covers the metal layer 41. The metal layer 42 is arranged on the inorganic insulating layer 32. The inorganic insulating layer 33 covers the metal layer 42. The organic insulating layer 34 covers the inorganic insulating layer 33. The metal layer 43 is arranged on the organic insulating layer 34, and is covered by the organic insulating layer 12.

[0109] The dam portions DM1, DM2, DM3 each protrude upward of the substrate 10. In the example of FIG. 8, the dam portion DM1 is formed of the organic insulating layers 12, 34. The dam portions DM2, DM3 are also similarly formed of the organic insulating layers 12, 34. That is, in the present embodiment, the dam portions DM1, DM2, DM3 are formed of the same material as the organic insulating layers 12, 34 on the same layer as the organic insulating layers 12, 34. Figure 8

[0110] A power supply line PW that applies a common voltage is arranged below the dam portions DM1, DM2. The power supply line PW has a 1st wiring W1 formed of the metal layer 42, and a 2nd wiring W2 formed of the metal layer 43.

[0111] In the example of FIG. 8, the 1st wiring W1 and the 2nd wiring W2 contact at a contact portion CN0 located between the dam portions DM1, DM2. A portion of the 2nd wiring W2 is located between the organic insulating layers 12, 34, respectively, at the dam portions DM1, DM2. Figure 8

[0112] ​​In the peripheral area SA, a conductive relay layer RLO connecting the barrier wall 6B and the power supply line PW, and the rib layer 5 are also provided. The relay layer RLO is formed of the same material as the above-mentioned lower electrodes LE1, LE2, LE3 by the same process, for example.

[0113] The relay layer RLO is located on the display area DA side (left side in the figure) compared with the dam portions DM1, and is covered with the organic insulating layer 12. The rib layer 5 continuously covers the relay layer RLO and the dam portions DM1, DM2, DM3.

[0114] The barrier walls 6B, 6C are provided on the rib layer 5. The barrier wall 6B contacts the relay layer RLO at the contact portion CN1. Specifically, the rib layer 5 is opened at the contact portion CN1, and the lower portion 61 (specifically, the bottom layer 63) of the barrier wall 6B contacts the relay layer RLO through the opening. The contact portion CN1 is located above the organic insulating layer 12.

[0115] The relay layer RLO contacts the 2nd wiring W2 of the power supply line PW at the contact portion CN2. The contact portion CN2 is located between the end portion E0 of the organic insulating layer 12 and the dam portion DM1 in plan view.

[0116] The laminated film FLx is provided on the barrier wall 6B. The barrier wall 6B and the laminated film FLx are covered with the sealing layer SE1x. The laminated film FLx is formed of the same process and the same material as any one of the laminated films FL1, FL2, FL3 shown in Figure 3 The sealing layer SE1x is formed of the same process and the same material as any one of the sealing layers SE11, SE12, SE13 shown in Figure 3 In the present embodiment, a case where the laminated film FLx and the sealing layer SE1x are formed of the same process and the same material as the laminated film FL3 and the sealing layer SE13, respectively, is assumed. That is, the laminated film FLx includes the upper electrode UE3, the organic layer OR3, and the cap layer CP3. The end portion Es1 of the sealing layer SE1x is located between the barrier wall 6B and the dam portion DM1, for example.

[0117] The sealing layer SE2 is also provided in the peripheral area SA. The sealing layer SE2 covers the sealing layer SE1x, and covers the rib layer 5 in a region outside (end portion E10 side) of the end portion Es1 of the sealing layer SE1x. In addition, the sealing layer SE2 also covers the barrier wall 6C.

[0118] The resin layer RS1, the sealing layer SE3, and the resin layer RS2 shown in Figure 3 are provided above the sealing layer SE2. In addition, the touch panel wiring TPL connected to the touch panel electrode TP shown in Figure 3 is provided on the sealing layer SE3. The touch panel wiring TPL is formed of the same material as the touch panel electrode TP, for example.

[0119] The resin layer RS1 covers the sealing layer SE2. The dam portions DM1, DM2, DM3 function to block the resin layer RS1 before curing at the time of manufacturing the display device DSP. In Figure 8 In the example, the end portion Er1 of the resin layer RS1 is located above the dam portion DM2. That is, the resin layer RS1 covers the dam portion DM1, and a part of the dam portion DM2. However, the position of the end portion Er1 is not limited to this example.

[0120] The sealing layer SE3 covers the end portion Er1 of the resin layer RS1. The sealing layer SE3 is in contact with the sealing layer SE2 at a region outside (right side in the drawing) of the end portion Er1. In Figure 8 In the example, a removal region RA1 in which the sealing layers SE2, SE3 are removed is formed in the vicinity of the dam portion DM3. By providing the removal region RA1, even in the case where a crack is generated in the sealing layers SE2, SE3, the growth of the crack to the display region DA side is suppressed.

[0121] Figure 9 is a schematic cross-sectional view of the display device DSP along the IX-IX line in Figure 7 The dam portions DM4, DM5 are formed of the organic insulating layers 12, 34 like the dam portions DM1, DM2, DM3.

[0122] In the example, the end portion Es2 of the sealing layer SE2 and the end portion Es3 of the sealing layer SE3 are aligned. These end portions Es2, Es3 are located above the dam portion DM4, for example, and are covered by the resin layer RS2. However, the positions of the end portions Es2, Es3 are not limited to this example. Figure 9 The end portion Er2 of the resin layer RS2 is located above the dam portion DM5, for example. The rib layer 5 is also formed at a region outside (end portion E10 side) of the end portion Er2. The pad PD of the terminal portion T is located between the end portion Er2 and the end portion E10.

[0123] The pad PD is formed of the same material as the touch panel electrode TP, the touch panel wiring TPL, for example. The pad PD is connected to the relay layer RL1. Further, the relay layer RL1 is connected to the relay layer RL2, and the relay layer RL2 is connected to the wiring LL. The relay layer RL1 is formed of the metal layer 43 of the circuit layer 11, the relay layer RL2 is formed of the metal layer 42 of the circuit layer 11, and the wiring LL is formed of the metal layer 41 of the circuit layer 11, for example.

[0124] Next, an example of a manufacturing method of the display device DSP will be described. At the time of manufacturing the display device DSP, a large-sized mother substrate in which a plurality of regions (panel portions) each including a part corresponding to the display device DSP are formed is prepared.

[0125]

[0126] ​Figure 10 is a schematic plan view of a mother substrate MB (mother substrate for display device) of the present embodiment. The mother substrate MB is, for example, rectangular as shown in the drawing, but can be circular or other shapes.

[0127] The mother substrate MB has a plurality of panel portions PP arranged in a matrix shape, and a blank area BA around the panel portions PP. In the present embodiment, the panel portions PP are arranged along the X direction and the Y direction with the blank area BA therebetween. However, the arrangement of the plurality of panel portions PP in the mother substrate MB is not limited to this example. As another example, some of the panel portions PP can be arranged without the blank area BA therebetween. Figure 10

[0128] Figure 11 is a schematic plan view of a panel portion PP. The outer shape of the panel portion PP corresponds to a cutting line CL1 for cutting out the panel portion PP from the mother substrate MB.

[0129] The panel portion PP has the display area DA and the surrounding area SA described above. The surrounding area SA in the panel portion PP corresponds to an area between the display area DA and the cutting line CL1.

[0130] The surrounding area SA also has a cutting line CL2 that becomes the outer shape of the substrate 10 of the display device DSP. When the display device DSP is manufactured, the panel portion PP is cut out from the mother substrate MB along the cutting line CL1. Further, the display device DSP is cut out from the panel portion PP along the cutting line CL2.

[0131] Figure 12 is a flowchart showing an example of a manufacturing method of the display device DSP. Figure 13A through Figure 13H is a schematic sectional view showing a manufacturing step of the display device DSP. In Figure 13A through Figure 13H , the display area DA is mainly focused on, and elements below the organic insulating layer 12 are omitted.

[0132] When the panel portion PP is formed, first, the circuit layer 11 including the inorganic insulating layers 31, 32, 33, the organic insulating layer 34, and the metal layers 41, 42, 43 described above, and the like is formed over the substrate 10 of the mother substrate MB (step PR1 of Figure 12 ). Further, the organic insulating layer 12 covering the circuit layer 11 is formed (step PR2 of Figure 12 ). At this time, the dam portions DM1, DM2, DM3, DM4 are also formed.

[0133] After the step PR2, as shown in Figure 13A , the lower electrodes LE1, LE2, LE3 are formed over the organic insulating layer 12 (step PR3 of Figure 12 ​Process PR3). Further, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed on the entire mother substrate MB. Figure 12 (Process PR4). At this point in time, pixel openings AP1, AP2, and AP3 are not provided on rib layer 5. Rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0134] After the formation of rib layer 5, as Figure 13B As shown, a partition wall 6A is formed on the rib layer 5. Figure 12 (Process PR5). The adjacent areas SA, 6B and 6C, are also formed together with adjacent area 6A.

[0135] Next, as Figure 13C As shown, pixel openings AP1, AP2, and AP3 are formed on rib layer 5. Figure 12 (Process PR6). It should be noted that pixel openings AP1, AP2, and AP3 can also be formed before adjacent openings 6A, 6B, and 6C.

[0136] After process PR6, a process for forming display element DE1 is performed. Figure 12 Process PR7). When forming the display element DE1, firstly, as... Figure 13D As shown, a laminated film FL1 and a sealing layer SE11 are formed. Figure 3 As shown, the laminated film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through a pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a capping layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the capping layer CP1 can be formed, for example, by vapor deposition. In addition, the sealing layer SE11 can be formed, for example, by CVD.

[0137] The laminate FL1 and the sealing layer SE11 are not only formed on the display area DA of each panel portion PP, but are formed on the entire mother substrate MB, including the peripheral area SA and the blank area BA. The laminate FL1 is separated by hanging partitions 6A, 6B, and 6C. The sealing layer SE11 continuously covers the separated portions of the laminate FL1 and the partitions 6A, 6B, and 6C.

[0138] Next, the laminated film FL1 and the sealing layer SE11 are patterned. In this patterning, as... Figure 13D As shown, resist RT is disposed on the sealing layer SE11. Resist RT covers a portion of sub-pixel SP1 and its surrounding partition 6A.

[0139] Next, an etching process is performed using photoresist RT as a mask. Thus, as... Figure 13EAs shown, the portions of the laminated film FL1 and the sealing layer SE11 exposed from the resist RT are removed. In other words, the portions of the laminated film FL1 and the sealing layer SE11 overlapping the lower electrode LE1 are left, and the other portions are removed. Thus, the display element DE1 is formed in the sub-pixel SP1. For example, the laminated film FL1 and the sealing layer SE11 are removed in the peripheral region SA and the blank region BA by this etching process. This etching process can include wet etching and dry etching performed on the sealing layer SE11, the cover layer CP1, the upper electrode UE1, and the organic layer OR1 in this order. After these etchings, the resist RT is removed (peeled off).

[0140] After the process PR7, a process for forming the display element DE2 is performed (process PR8). Figure 12 The display element DE2 can be formed in the same steps as the display element DE1. That is, when the display element DE2 is formed, the laminated film FL2 and the sealing layer SE12 are formed on the entire mother substrate MB. As shown, Figure 3 The laminated film FL2 includes the organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, the upper electrode UE2 covering the organic layer OR2, and the cover layer CP2 covering the upper electrode UE2.

[0141] The organic layer OR2, the upper electrode UE2, and the cover layer CP2 can be formed by evaporation, for example. In addition, the sealing layer SE12 can be formed by CVD, for example. By patterning such a laminated film FL2 and the sealing layer SE2, as shown, Figure 13F The display element DE2 is formed in the sub-pixel SP2. For example, in the peripheral region SA and the blank region BA, the laminated film FL2 and the sealing layer SE12 are removed by etching at the time of this patterning.

[0142] After the process PR8, a process for forming the display element DE3 is performed (process PR9). Figure 12 The display element DE3 can be formed in the same steps as the display elements DE1 and DE2. That is, when the display element DE3 is formed, the laminated film FL3 and the sealing layer SE13 are formed on the entire mother substrate MB. As shown, Figure 3 The laminated film FL3 includes the organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, the upper electrode UE3 covering the organic layer OR3, and the cover layer CP3 covering the upper electrode UE3.

[0143] The organic layer OR3, the upper electrode UE3, and the cover layer CP3 can be formed by evaporation, for example. In addition, the sealing layer SE13 can be formed by CVD, for example. By patterning such a laminated film FL3 and the sealing layer SE13, as shown, Figure 13G The display element DE3 is formed in the sub-pixel SP3.

[0144] For example, in most of the peripheral region SA and the blank region BA, the laminated film FL3 and the sealing layer SE13 are removed by etching at the time of the patterning. However, a portion of the laminated film FL3 and the sealing layer SE13 which covers the partition wall 6B remains. The portion thus remaining corresponds to the laminated film FLx and the sealing layer SE1x described above.

[0145] Note that the case where the display elements DE1, DE2, and DE3 are formed in this order is assumed here, but the display elements DE1, DE2, and DE3 can be formed in another order.

[0146] After the step PR9, a sealing layer SE2 covering the sealing layers SE11, SE12, and SE13 is formed, for example, by CVD (step PR10). The sealing layer SE2 is formed over the entire mother substrate MB including the panel portion PP and the blank region BA. Figure 13H

[0147] Next, a resin layer RS1 is formed (step PR11). The resin layer RS1 can be formed, for example, by an inkjet method. After the step PR11, a sealing layer SE3 is formed (step PR12) by CVD, for example. Figure 12 Figure 12

[0148] After the step PR12, etching for removing the rib layer 5, the sealing layer SE2, and the sealing layer SE3 which cover the terminal portion T is performed (step PR13). Further, etching for removing the sealing layers SE2 and SE3 in a larger region including the terminal portion T is performed (step PR14). In the step PR14, the rib layer 5 is not removed. These etchings are dry etchings, for example. Figure 12 Figure 12 Figure 8 The removal region RA1 illustrated in FIG. 8A is also formed by the etching of the step PR14.

[0149] After the step PR14, a touch panel electrode TP, a touch panel wiring TPL, and a pad PD are formed (step PR15). Further, a resin layer RS2 is formed (step PR16). The resin layer RS2 can be formed, for example, by an inkjet method. Figure 12 Figure 12

[0150] After the step PR16, the mother substrate MB is cut along the cutting line CL1 (step PR17). Further, the panel portion PP is cut along the cutting line CL2 (step PR18). The touch panel 1 is thus completed. Figure 12 Figure 12 ​​​​​​​​The display device DSP is completed. As to the cutting in the processes PR17, PR18, laser cutting in which infrared laser is irradiated along the cutting lines CL1, CL2 can be used, for example. However, the cutting in the processes PR17, PR18 can also be implemented by scribe cut or other methods.

[0151] Figure 14 is a schematic plan view of the area encircled with the frame XIV in Figure 11 , showing part of the elements with which the panel portion PP is provided before the cutting along the cutting line CL2 is implemented (process PR18).

[0152] The cutting line CL2 corresponds to the end portion E10 of the substrate 10 after the process PR18 is implemented. In Figure 14 , the structure inside the cutting line CL2 (upper left in the figure) is the same as that shown in Figure 7

[0153] The dam portions DM41, DM42, DM5 extend to the outside of the cutting line CL2, and enclose the substantially circular area enclosed by the cutting line CL2 (refer to Figure 11 ). In the example of Figure 14 , a plurality of the partition walls 6C are also arranged in the area between the cutting line CL2 and the dam portion DM41, the area between the dam portions DM41, DM42, and the area between the dam portions DM42, DM5. The partition walls 6C can also be further arranged in the area overlapping the dam portions DM41, DM42, DM5 or the area outside the dam portion DM5.

[0154] Figure 15 is a schematic sectional view of the panel portion PP along the XV-XV line in Figure 14 . The dam portions DM41, DM42, DM5 are formed of the organic insulating layers 12, 34 like the dam portions DM1, DM2, DM3.

[0155] The dam portions DM41, DM42, DM5 are covered by the rib layer 5, the sealing layer SE2, and the sealing layer SE3. The partition walls 6C outside the cutting line CL2 are located on the rib layer 5, and are covered by the sealing layer SE2.

[0156] In the example of Figure 15 , the cutting line CL2 overlaps the inorganic insulating layers 31 to 33, the rib layer 5, the sealing layer SE2, the sealing layer SE3, and the resin layer RS2. However, the cutting line CL2 does not overlap the partition walls 6C.

[0157] Here, the effects of the present embodiment are described.

[0158] Figure 16A through Figure 16C ​is a sectional view showing a comparative example of the present embodiment. Also, Figure 17A through Figure 17C is a sectional view showing an effect of the present embodiment. In these drawings, the structure around the slit SL is shown as well. Figure 5 The structure around the slit SL is shown as well. Note that the comparative example described above and the structure of the present embodiment differ in that the sealing layer SE2 is not provided.

[0159] When the resin layer RS1 is formed by the inkjet method, as shown in Figure 16A , droplets D of a resin material are ejected toward each panel portion PP. These droplets D mostly adhere to the sealing layers SE11, SE12, and SE13.

[0160] The droplets D adhering to the sealing layers SE11, SE12, and SE13 spread by wetting as shown in Figure 16B . The end portions E11 and E12 of the sealing layers SE11 and SE12 and the end portion of the sealing layer SE13 stand substantially vertically. Thus, as with the droplet D on the left side in the drawing, the droplet D can not flow into the slit SL due to the surface tension of these end portions.

[0161] Also, gaps G1 and G2 are formed between the upper portion 62 of the partition wall 6A and the sealing layers SE11 and SE12, and the same gaps are formed between the upper portion 62 and the sealing layer SE13. Thus, even if the droplets D spread by wetting into the slit SL, the droplets D can be blocked when bubbles of these gaps are discharged as shown by the arrow B. Further, the side portion of the partition wall 6A facing the slit SL is in a hanging shape, and bubbles generated through this portion can also block the droplets D.

[0162] If the droplets D are cured in the state of being blocked, as shown in Figure 16C , a shape defect of the resin layer RS1 can occur near the slit SL. Specifically, the resin layer RS1 does not sufficiently fill the slit SL, and a layer difference corresponding to the slit SL is generated. If the sealing layer SE3 is formed in this state, the sealing layer SE3 can be blocked to form a moisture penetration path. Further, the touch panel electrode TP formed on the sealing layer SE3 can also be broken.

[0163] To address this, in the present embodiment, as shown in Figure 17A , the sealing layer SE2 is provided which covers the entire display region DA including the sealing layers SE11, SE12, and SE13 and the slit SL. By covering the end portions E11 and E12 of the sealing layers SE11 and SE12 and the end portion of the sealing layer SE13 with this sealing layer SE2, the layer differences of these end portions become smooth. Thus, as shown in Figure 17B , the droplets D become easy to flow into the slit SL.

[0164] As shown in Figure 17C , the sealing layer SE2 is formed by the inkjet method.As shown, droplet D is not interrupted by slit SL but gradually smooths out. The result is, as... Figure 5 As shown, a resin layer RS1 with a flat upper surface can be formed. This can suppress the interruption of the sealing layer SE3 near the slit SL and the breakage of the touch panel electrode TP.

[0165] It should be noted that if the sealing layer SE2 is formed to be thicker, the entrances to the gaps G1 and G2 between the upper part 62 and the sealing layers SE11 and SE12, and the gap between the upper part 62 and the sealing layer SE13, will be blocked. Furthermore, the space below the upper part 62 of the partition wall 6A facing the slit SL will also be filled to some extent by the sealing layer SE2. In this case, the blocking of droplets D caused by bubbles can also be suppressed.

[0166] The above effects can be achieved not only near the slit SL, but also in Figure 6 The shown portion can also be obtained. That is, when the ends of the sealing layers SE11, SE12, and SE13 are separated above the partition wall 6A, although the resin layer RS1 may not flow into the space between these ends, this situation can be suppressed by providing the sealing layer SE2.

[0167] In addition, such as Figure 8 and Figure 9 As shown, the sealing layer SE2 is in contact with the sealing layer SE3 in the surrounding area SA. This allows the resin layer RS1 to be entirely surrounded by an inorganic insulating material, thus better suppressing the formation of moisture penetration pathways.

[0168] In addition to the description herein, various suitable effects can be obtained from this embodiment.

[0169] Hereinafter, embodiments 2 to 6 are disclosed. In these embodiments, consideration is given to... Figure 15 The same cross-section discloses other structures applicable to the peripheral region SA of the panel portion PP. Regarding structures of the panel portion PP not mentioned in each embodiment, the same structure as in the first embodiment can be applied. Furthermore, by cutting the panel portion PP disclosed in each embodiment along the cutting line CL2, a display device DSP having a structure in the panel portion PP that is closer to the cutting line CL2 can be obtained.

[0170] [Second Embodiment]

[0171] Figure 18 This is a schematic cross-sectional view of the panel portion PP according to the second embodiment. In this embodiment, the dam portion DM3 is not provided. Furthermore, a removal area RA2, where the rib layer 5 has been removed, is provided between the dam portions DM2 and DM41. The removal area RA2 can be, for example, formed in the process of forming pixel openings AP1, AP2, and AP3 on the rib layer 5 (…). Figure 12formed in the process PR6.

[0172] The removal region RA2 overlaps the cutting line CL2. The end portions of the rib layer 5 located at the edge of the removal region RA2 are covered by the sealing layers SE2, SE3. The partition walls 6C on both sides of the cutting line CL2 are located in the removal region RA2. These partition walls 6C are disposed on the inorganic insulating layer 33 and covered by the sealing layers SE2.

[0173] By omitting the dam portion DM3 as in this embodiment, the width of the surrounding region SA can be narrowed. In addition, since the rib layer 5 is removed on the cutting line CL2, the above-described cutting of the panel portion PP using laser cutting becomes easy.

[0174] Note that in the case of cutting the panel portion PP along the cutting line CL2 as illustrated in FIG. 2B, a portion of the display device DSP in which the rib layer 5 is removed is manufactured between the dam portion DM41 on the outermost periphery and the end portion E10 of the substrate 10. Figure 18 In the case of the panel portion PP illustrated in FIG. 2B, a portion of the display device DSP in which the rib layer 5 is removed is manufactured between the dam portion DM41 on the outermost periphery and the end portion E10 of the substrate 10.

[0175] [Embodiment 3]

[0176] Figure 19 is a schematic cross-sectional view of the panel portion PP of Embodiment 3. The structure illustrated in this figure is different from that of Embodiment 2 ( Figure 18 ) in that the width of the removal region RA2 is narrowed.

[0177] Specifically, the removal region RA2 is located between the partition walls 6C on both sides of the cutting line CL2. Thus, since these partition walls 6C are located on the rib layer 5, the partition walls 6C can be stably formed on the same base as the partition walls 6A or the like.

[0178] [Embodiment 4]

[0179] Figure 20 is a schematic cross-sectional view of the panel portion PP of Embodiment 4. The structure illustrated in this figure is different from that of Embodiment 3 ( Figure 19 ) in that the rib layer 5 is removed within the removal region RA1.

[0180] The removal region RA1 can be formed, for example, by etching in the process PR13. Figure 12 In this case, the end portions of the rib layer 5, the sealing layer SE2, and the sealing layer SE3 are aligned at the edge of the removal region RA1.

[0181] [Embodiment 5]

[0182] Figure 21 is a schematic cross-sectional view of the panel portion PP of Embodiment 5. The structure illustrated in this figure is different from that of Embodiment 2 ( Figure 18The difference from the structure of the display device of the fifth embodiment (FIG. 16) is that a removal region RA3 in which the sealing layers SE2, SE3 are removed is provided.

[0183] The removal region RA3 overlaps the cutting line CL2. More specifically, the removal region RA3 is located between the partition walls 6C on both sides of the cutting line CL2. The removal region RA3 can be formed by etching in the process PR14. Figure 12

[0184] In the case where the removal region RA3 is provided as in the present embodiment, the cutting of the panel portion PP by laser cutting becomes easier.

[0185] [Sixth Embodiment]

[0186] Figure 22 is a schematic cross-sectional view of the panel portion PP of the sixth embodiment. The structure shown in this figure corresponds to the structure of the third embodiment (FIG. 12) provided with the same removal region RA3 as the fifth embodiment (FIG. 16). If this structure, the same effects as the third and fifth embodiments are exerted. Figure 19 Figure 21

[0187] [Seventh Embodiment]

[0188] Figure 23 is a schematic cross-sectional view of the panel portion PP of the seventh embodiment. The structure shown in this figure corresponds to the structure of the fourth embodiment (FIG. 14) provided with the same removal region RA3 as the fifth embodiment (FIG. 16). If this structure, the same effects as the fourth and fifth embodiments are exerted. Figure 20 Figure 21

[0189] In each of the above embodiments, the term "partition wall" includes various configurations in a hanging shape. Even if a configuration in a hanging shape having a shape different from the partition wall disclosed in each of the embodiments, a portion extending to the side corresponds to the "upper portion", and a portion retreating below the portion corresponds to the "lower portion".

[0190] All display devices and manufacturing methods that can be implemented by a person skilled in the art by appropriately changing the design based on the display devices and manufacturing methods disclosed in each of the embodiments, as long as they include the gist of the present application, also belong to the scope of the present application.

[0191] Various modifications that can be conceived by a person skilled in the art within the scope of the idea of the present application can also be understood as belonging to the scope of the present application. For example, addition, deletion, or design change of a constituent element, or addition, omission, or condition change of a process that can be appropriately performed by a person skilled in the art on each of the above embodiments, as long as they include the gist of the present application, also belong to the scope of the present application. ​​​​​

[0192] In addition, other effects brought about by the solutions described in the above embodiments can of course be understood as effects brought about by the present application, from the effects known from the description of the present specification or effects that can be appropriately conceived by those skilled in the art.

Claims

1. A display device, characterized in that, have: A substrate having a display area configured with multiple sub-pixels; Rib layer, which has a pixel opening in each of the plurality of sub-pixels; The partition surrounding each of the plurality of sub-pixels includes a conductive lower portion disposed above the rib layer and an upper portion having an end portion protruding from the side of the lower portion; Multiple display elements are respectively disposed in the multiple sub-pixels and include an organic layer that emits light according to the application of voltage; Multiple first sealing layers, formed of inorganic insulating material, respectively cover the multiple display elements; and The second sealing layer, formed of an inorganic insulating material, covers the plurality of first sealing layers. The partition wall is divided into multiple segments by slits. The second sealing layer contacts the rib layer in the slit.

2. The display device according to claim 1, characterized in that, It also has a resin layer covering the second sealing layer. At least a portion of the slit is filled with the resin layer.

3. The display device according to claim 2, characterized in that, Above at least a portion of the partition wall, at least a portion of the space between the upper part of the partition wall and the first sealing layer is filled by the resin layer.

4. The display device according to claim 1, characterized in that, The ends of the plurality of first sealing layers are located above the partition wall. The second sealing layer covers the ends of the plurality of first sealing layers.

5. The display device according to claim 1, characterized in that, The second sealing layer has a first portion covering the plurality of first sealing layers and a second portion that contacts the rib layer in the slit. The first part is separated from the second part.

6. The display device according to claim 5, characterized in that, The second portion of the second sealing layer covers the lower portion and the upper portion of the partition wall.

7. The display device according to claim 5, characterized in that, The second portion of the second sealing layer is in direct contact with the lower portion and the upper portion of the partition wall.

8. The display device according to claim 1, characterized in that, The second sealing layer is thinner than the first sealing layer.

9. A display device, characterized in that, have: A substrate having a display area configured with multiple sub-pixels; Rib layer, which has a pixel opening in each of the plurality of sub-pixels; The partition surrounding each of the plurality of sub-pixels includes a conductive lower portion disposed above the rib layer and an upper portion having an end portion protruding from the side of the lower portion; Multiple display elements are respectively disposed in the multiple sub-pixels and include an organic layer that emits light according to the application of voltage; Multiple first sealing layers, formed of inorganic insulating material, respectively cover the multiple display elements; and The second sealing layer, formed of an inorganic insulating material, covers the plurality of first sealing layers. Above at least a portion of the partition wall, the ends of adjacent first sealing layers are separated from each other, and in the region between these ends, the second sealing layer contacts the upper portion.

10. The display device according to claim 9, characterized in that, It also has a resin layer covering the second sealing layer. Above at least a portion of the partition wall, the space between the ends of adjacent first sealing layers is filled with the resin layer.

11. The display device according to claim 10, characterized in that, Above at least a portion of the partition wall, at least a portion of the space between the upper part of the partition wall and the first sealing layer is filled by the resin layer.

12. The display device according to claim 9, characterized in that, The second sealing layer covers the ends of the plurality of first sealing layers.

13. The display device according to claim 9, characterized in that, The second sealing layer has a first portion covering the plurality of first sealing layers and a third portion in contact with the upper portion. The first part is separated from the third part.

14. The display device according to claim 9, characterized in that, The second sealing layer is thinner than the first sealing layer.

15. A display device, characterized in that, have: A substrate having a display area configured with a plurality of sub-pixels and a peripheral area surrounding the display area; Rib layers are formed in the display area and the surrounding area, and have pixel openings in each of the plurality of sub-pixels; The first partition surrounding each of the plurality of sub-pixels includes a conductive lower portion disposed above the rib layer and an upper portion having an end portion protruding from the side of the lower portion; Multiple display elements are respectively disposed in the multiple sub-pixels and include an organic layer that emits light according to the application of voltage; Multiple first sealing layers, formed of inorganic insulating material, respectively cover the multiple display elements; The second sealing layer is formed of an inorganic insulating material and covers the plurality of first sealing layers; and The dam section is located in the surrounding area and surrounds the display area. The rib layer is removed in at least a portion of the region between the end of the substrate and the dam portion.

16. The display device according to claim 15, characterized in that, The second sealing layer covers the end of the rib layer.

17. The display device according to claim 15, characterized in that, It also has: A resin layer that covers at least the second sealing layer in the display area; and The third sealing layer, formed of an inorganic insulating material, covers the resin layer. The third sealing layer covers the end of the rib layer.

18. The display device according to claim 17, characterized in that, The end of the second sealing layer is aligned with the end of the third sealing layer.

19. The display device according to claim 15, characterized in that, It also includes a second partition wall comprising a conductive lower portion disposed in the peripheral region in the area where the rib layer is removed, and an upper portion having an end portion protruding from the side of the lower portion.

20. The display device according to claim 19, characterized in that, The second sealing layer covers the second partition wall.

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