Display panel and display device

Abstract

The invention discloses a display panel and a display device, a storage capacitor comprises a first polar plate, a second polar plate and a third polar plate, the first polar plate and the second polar plate are overlapped to form a first capacitor, and the second polar plate and the third polar plate are overlapped to form a second capacitor; in the display panel in an overlooking view angle, a part of the first polar plate is overlapped with the first active part of the driving transistor, and the parts, located on the outer side of the first active part, of the first polar plate and the second polar plate are overlapped to form a first capacitor. According to the display panel and the display device provided by the embodiment of the invention, the first capacitor and the second capacitor which are connected in parallel and overlapped are arranged to form at least part of the storage capacitor, so that the capacitance of the storage capacitor is improved to improve the compensation capability for threshold voltage, and meanwhile, the risk that the layout area of the storage capacitor is too large is reduced to meet the requirement of high resolution.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and more particularly to a display panel and display device. Background Technology

[0002] In existing organic light-emitting diode (OLED) panels, pixel circuits are typically used to drive the light-emitting devices. During the compensation phase, the stronger the compensation capability for the threshold voltage of the driving transistor, the stronger the uniformity of the light-emitting device's brightness. The storage capacitor is a key factor affecting the compensation capability; the larger the storage capacitor, the stronger the compensation capability.

[0003] However, in OLED panels that require high resolution, the area of ​​the storage capacitor is limited, and the area of ​​the storage capacitor cannot be increased arbitrarily. Summary of the Invention

[0004] This application provides a display panel and a display device to at least partially solve the above-mentioned technical problems.

[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising: Substrate; A pixel circuit includes a driving transistor and a storage capacitor. The storage capacitor includes a first electrode plate, a second electrode plate, and a third electrode plate. The first electrode plate is connected to the third electrode plate. The first electrode plate and the second electrode plate at least partially overlap to form a first capacitor, and the second electrode plate and the third electrode plate at least partially overlap to form a second capacitor. In the thickness direction of the display panel, the first electrode plate is disposed on the substrate, the second electrode plate is disposed on the side of the first electrode plate away from the substrate, and the third electrode plate is disposed on the side of the second electrode plate away from the substrate. The first active portion of the driving transistor is disposed between the first electrode plate and the second electrode plate, and the first active portion includes a metal-oxide-semiconductor. In the display panel viewed from above, a portion of the first electrode plate overlaps with the first active portion of the driving transistor, and the portions of the first electrode plate and the second electrode plate located outside the first active portion overlap to form the first capacitor.

[0006] Optionally, in some embodiments of this application, the area of ​​the first capacitor is larger than the overlapping area of ​​the first electrode and the first active part.

[0007] Optionally, in some embodiments of this application, the pixel circuit includes a first node, which is disposed on the side of the third electrode plate away from the substrate, and the second electrode plate of the storage capacitor is connected to the first node; In the display panel viewed from above, the first node is spaced apart on one side of the first active part, and the first electrode plate and the second electrode plate extend from the first active part toward the first node and both partially overlap with the first node.

[0008] Optionally, in some embodiments of this application, in the direction from the first active portion to the first node, the distance from the edge of the first electrode plate near the first node to the edge of the first active portion near the first node is a first distance, and the distance from the edge of the second electrode plate near the first node to the edge of the first active portion near the first node is a second distance, and both the first distance and the second distance are greater than the width of the first active portion.

[0009] Optionally, in some embodiments of this application, in the display panel viewed from above, on the side of the first active portion near the first node, a portion of the first electrode plate and a portion of the second electrode plate overlap to form a first sub-capacitor of the first capacitor; on the side of the first active portion away from the first node, another portion of the first electrode plate and another portion of the second electrode plate overlap to form a second sub-capacitor of the first capacitor, wherein the capacitance of the first sub-capacitor is greater than the capacitance of the second sub-capacitor.

[0010] Optionally, in some embodiments of this application, the area of ​​the first sub-capacitor is larger than the area of ​​the second sub-capacitor.

[0011] Optionally, in some embodiments of this application, the first electrode plate includes a first part, a second part, and a third part, the second part and the first active part are overlapped, the first part is connected to the side of the second part near the first node, and the third part is connected to the side of the second part away from the first node. The second electrode plate includes a fourth part, a fifth part, and a sixth part. The fifth part is multiplexed as the gate of the driving transistor. The fourth part is connected to the side of the fifth part closer to the first node, and the sixth part is connected to the side of the fifth part away from the first node. In the display panel viewed from above, the first part and the fourth part overlap to form the first sub-capacitor, and the third part and the sixth part overlap to form the second sub-capacitor.

[0012] Optionally, in some embodiments of this application, the display panel includes a second active part disposed on the same layer as the first active part, the second active part being located on the side of the first active part closer to the first node, and the first node being connected to the second active part; In the display panel viewed from above, the portion of the first part located around the second electrode plate overlaps with a portion of the second active part to form the third capacitor of the storage capacitor.

[0013] Optionally, in some embodiments of this application, in the display panel viewed from above, the portion of the first part located outside the second electrode plate, the third electrode plate, and the second active part overlaps with a portion of the first node to form a fourth capacitor of the storage capacitor.

[0014] Optionally, in some embodiments of this application, in the display panel viewed from above, a portion of the third electrode plate overlaps with a portion of the first node to form the fifth capacitor of the storage capacitor.

[0015] Optionally, in some embodiments of this application, in the display panel viewed from above, a portion of the third electrode plate overlaps with a portion of the second active portion to form the sixth capacitor of the storage capacitor.

[0016] Optionally, in some embodiments of this application, the pixel circuit includes a transition portion connecting the output terminal of the driving transistor, the transition portion connecting the first electrode plate and the third electrode plate.

[0017] Optionally, in some embodiments of this application, the display panel includes a buffer layer, a first metal layer, a first insulating layer, a first active layer, a second insulating layer, a second metal layer, a third insulating layer, a third metal layer, a fourth insulating layer, a fourth metal layer, and a planarization layer sequentially disposed on the substrate. The pixel circuit includes a second node and a third node. A portion of the second node is multiplexed as the input terminal of the driving transistor, and the third node is the transition section. A portion of the third node is multiplexed as the output terminal of the driving transistor. The first metal layer includes the first electrode plate, the first active layer includes the first active part, the second metal layer includes the second electrode plate, the third metal layer includes the third electrode plate, and the fourth metal layer includes the first node, the second node, and the third node. The first node is connected to the second electrode plate through a first via, the third node is connected to the first electrode plate through a second via, the third node is connected to one end of the first active part through a third via, the third node is connected to the third electrode plate through a fourth via, and the second node is connected to the other end of the first active part through a fifth via.

[0018] Optionally, in some embodiments of this application, the pixel circuit further includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a sustaining capacitor; The gate of the driving transistor is connected to a first node, the input of the driving transistor is connected to a second node, and the output of the driving transistor is connected to a third node. One end of the storage capacitor is connected to the first node, and the other end of the storage capacitor is connected to the third node. The gate of the second transistor is connected to a second scan signal, the input of the second transistor is connected to a data signal, and the output of the second transistor is connected to the first node. The gate of the third transistor is connected to a first scan signal, the input of the third transistor is connected to a first reset signal, and the output of the third transistor is connected to the first node. The gate of the fourth transistor is connected to the third scan signal, the input of the fourth transistor is connected to the second reset signal, the output of the fourth transistor is connected to the fourth node, the anode of the light-emitting diode is connected to the fourth node, the cathode of the light-emitting diode is connected to the second power supply voltage signal, the gate of the fifth transistor is connected to the first light-emitting control signal, the input of the fifth transistor is connected to the first power supply voltage signal, and the output of the fifth transistor is connected to the second node. The gate of the sixth transistor is connected to the second light emission control signal, the input of the sixth transistor is connected to the third node, the output of the sixth transistor is connected to the fourth node, one end of the sustaining capacitor is connected to the third node, the other end of the sustaining capacitor is connected to the output of the seventh transistor, the gate of the seventh transistor is connected to the third scan signal, and the input of the seventh transistor is connected to the first power supply voltage signal.

[0019] According to a second aspect of this application, a display device is provided, which includes the display panel described in any of the above embodiments.

[0020] In the display panel and display device of this application embodiment, in the display panel viewed from above, a portion of the first electrode plate overlaps with the first active portion of the driving transistor, and the portions of the first electrode plate and the second electrode plate located outside the first active portion overlap to form the first capacitor, and the area of ​​the first capacitor is larger than the overlapping area of ​​the first electrode plate and the first active portion.

[0021] It is understood that the display panel and display device of the present application embodiment form at least part of the storage capacitor by setting a first capacitor and a second capacitor connected in parallel and overlapping, so as to improve the capacitance of the storage capacitor to improve the threshold voltage compensation capability, while reducing the risk of the storage capacitor layout area being too large, so as to meet the requirements of high resolution.

[0022] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0024] Figure 1 This is an equivalent circuit diagram of the pixel circuit in the display panel provided in the exemplary embodiments of this disclosure; Figure 2 This is a top view of the display panel provided in an exemplary embodiment of this disclosure; Figure 3 This is a partial cross-sectional view of the display panel provided in an exemplary embodiment of this disclosure; Figure 4 This is a top view of the first capacitor of the display panel provided in an exemplary embodiment of this disclosure; Figure 5 This is a top view of the second capacitor structure of the display panel provided in an exemplary embodiment of this disclosure; Figure 6 This is a top view of a portion of the display panel provided in an exemplary embodiment of this disclosure; Figure 7 This is a top view of another part of the display panel provided in an exemplary embodiment of this disclosure; Figure 8 This is a top view of the first metal layer of the display panel provided in an exemplary embodiment of this disclosure; Figure 9 This is a top view of the structure of the first active layer of the display panel provided in an exemplary embodiment of this disclosure; Figure 10 This is a top view of the second metal layer of the display panel provided in an exemplary embodiment of this disclosure; Figure 11 This is a top view of the third metal layer of the display panel provided in an exemplary embodiment of this disclosure; Figure 12 This is a top view of the fourth metal layer of the display panel provided in an exemplary embodiment of this disclosure; Figure 13 This is a schematic diagram of the structure of a display device provided in an exemplary embodiment of this disclosure.

[0025] Explanation of reference numerals in the attached figures: Display panel 100; Substrate 101; Pixel circuit p1; Light-emitting diode EL; Driving transistor T1; Storage capacitor Cst; Second transistor T2; Third transistor T3; Fourth transistor T4; Fifth transistor T5; Sixth transistor T6; Seventh transistor T7; Holding capacitor Cw; First node Q; Second node A; Third node B; Fourth node D; First scan signal Scan1; Second scan signal Scan2; Third scan signal Scan3; Data signal Data; First reset signal Vref; Second reset signal Vi; First power supply voltage signal VDD; Second power supply voltage signal VSS; First light emission control signal EM1; Second light emission control signal EM2; First electrode c1; Second electrode c2; Third electrode c3; First capacitor cst1; Second capacitor cst2; Third capacitor cst3; Fourth capacitor cst4; Fifth capacitor cst5; Sixth capacitor cst6; Active part yy1; Second active part yy2; First distance L1; Second distance L2; First sub-capacitor cs01; Second sub-capacitor cs02; First part c11; Second part c12; Third part c13; Fourth part c21; Fifth part c22; Sixth part c23; Second scan line s2; Adapter part Zj; Buffer layer 102; First metal layer 111; First insulating layer 103; First active layer 104; Second insulating layer 105; Second metal layer 11 2; Third insulating layer 106; Third metal layer 113; Fourth insulating layer 107; Fourth metal layer 114; Planarization layer 108; Anode layer 115; Pixel definition layer 109; Fifth insulating layer 1010; Sixth insulating layer 1011; First connecting part c14; Second connecting part c31; Clearance hole kb1; First via k1; Second via k2; Third via k3; Fourth via k4; Fifth via k5; Sixth via k6; Display device 1000. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0027] This application provides a display panel 100; please refer to [link / reference]. Figures 1 to 3 , Figure 1 This is an equivalent circuit diagram of the pixel circuit p1 in the display panel 100 provided in the exemplary embodiment of this disclosure; Figure 2 This is a top view of the display panel 100 provided in an exemplary embodiment of this disclosure; Figure 3This is a partial cross-sectional view of the display panel 100 provided in an exemplary embodiment of this disclosure.

[0028] This application provides a display panel 100, which can be an electroluminescent panel, such as a quantum dot light-emitting diode display panel and an organic light-emitting diode display panel. The following description will take an organic light-emitting diode display panel as an example.

[0029] The display panel 100 includes a substrate 101 and a pixel circuit p1, wherein the pixel circuit p1 is disposed on the substrate 101.

[0030] Among them, pixel circuit p1 is used to control the organic light-emitting diode EL to emit light.

[0031] The pixel circuit p1 includes at least a driving transistor T1 and a storage capacitor Cst. The gate of the driving transistor T1 and one plate of the storage capacitor Cst are connected to the first node Q.

[0032] The compensation capability of pixel circuit p1 for the threshold voltage of driving transistor T1 depends on: R = Cst / (Cst + C Q Where Cst is the storage capacitor, C Q Let Q be the parasitic capacitance of the first node.

[0033] The closer R is to 1, the stronger its ability to compensate for the threshold voltage of the driving transistor T1. As can be seen from the formula, methods to increase R include increasing the capacitance of the storage capacitor Cst and reducing the parasitic capacitance C of the first node Q. Q The electrical capacity.

[0034] It should be noted that in the display panel 100 of this application embodiment, as long as the pixel circuit p1 can control the organic light-emitting diode EL to emit light, and includes at least a driving transistor T1 and a storage capacitor Cst, and the gate of the driving transistor T1 and one plate of the storage capacitor Cst are connected to the first node Q, it is sufficient. However, when the driving transistor T1 is a metal-oxide transistor, due to the low mobility of metal oxide, the compensation capability for the threshold voltage is relatively weak.

[0035] The following explanation uses the 7T2C architecture of the pixel circuit p1 as an example, but it is not limited to this, such as 5T1C, 6T1C, etc.

[0036] Alternatively, please refer to Figure 1 In some embodiments of this application, the pixel circuit p1 further includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a sustaining capacitor Cw.

[0037] The gate of driving transistor T1 is connected to the first node Q, the input of driving transistor T1 is connected to the second node A, and the output of driving transistor T1 is connected to the third node B. One end of storage capacitor Cst is connected to the first node Q, and the other end of storage capacitor Cst is connected to the third node B.

[0038] The gate of the second transistor T2 is connected to the second scan signal Scan2, the input of the second transistor T2 is connected to the data signal Data, and the output of the second transistor T2 is connected to the first node Q. The gate of the third transistor T3 is connected to the first scan signal Scan1, the input of the third transistor T3 is connected to the first reset signal Vref, and the output of the third transistor T3 is connected to the first node Q.

[0039] The gate of the fourth transistor T4 is connected to the third scan signal Scan3, the input of the fourth transistor T4 is connected to the second reset signal Vi, and the output of the fourth transistor T4 is connected to the fourth node D. The anode of the light-emitting diode EL is connected to the fourth node D, and the cathode of the light-emitting diode EL is connected to the second power supply voltage signal VSS. The gate of the fifth transistor T5 is connected to the first light-emitting control signal EM1, the input of the fifth transistor T5 is connected to the first power supply voltage signal VDD, and the output of the fifth transistor T5 is connected to the second node A.

[0040] The gate of the sixth transistor T6 is connected to the second light-emitting control signal EM2, the input of the sixth transistor T6 is connected to the third node B, and the output of the sixth transistor T6 is connected to the fourth node D. One end of the holding capacitor Cw is connected to the third node B, and the other end of the holding capacitor Cw is connected to the output of the seventh transistor T7. The gate of the seventh transistor T7 is connected to the third scan signal Scan3, and the input of the seventh transistor T7 is connected to the first power supply voltage signal VDD.

[0041] In the first stage, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned on, resetting the third node B and the first node Q, respectively.

[0042] In the second stage, the driving transistors T1, T3, T4, T5, and T7 are turned on to charge the third node B. When the potential of the third node B reaches the required level, they are turned off, thus completing the compensation of the threshold voltage of the driving transistor T1.

[0043] In the third stage, transistors T2, T4, and T7 are turned on, while transistors T3, T5, and T6 are turned off. The data signal Data is written to the first node Q.

[0044] In the fourth stage, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned on, and the second reset signal Vi resets the third node B.

[0045] In the fifth stage, the driving transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned on, and the light-emitting diode EL emits light.

[0046] Optionally, in some embodiments of this application, each of the driving transistors T1 to T7 can be a P-type transistor or an N-type transistor. For example, all of the driving transistors T1 to T7 may be N-type transistors or P-type transistors. Or, for example, only the fifth transistor T5 and the sixth transistor T6 may be P-type transistors, while the other transistors may be N-type transistors.

[0047] Optionally, in some embodiments of this application, the driving transistor T1 is a metal-oxide-semiconductor transistor, and each of the second transistor T2 to the seventh transistor T7 can be a silicon-based semiconductor transistor or a metal-oxide-semiconductor transistor. For example, all of the second transistor T2 to the seventh transistor T7 are metal-oxide-semiconductor transistors or silicon-based semiconductor transistors. Or, for example, only the fifth transistor T5 and the sixth transistor T6 are silicon-based semiconductor transistors, and the others are metal-oxide-semiconductor transistors.

[0048] Optionally, the silicon-based semiconductor can be polycrystalline silicon or monocrystalline silicon, such as low-temperature polycrystalline silicon. The metal-oxide semiconductor can be IGZO, IGZTO, or IGTO, etc.

[0049] Please refer to Figures 2 to 5 The storage capacitor Cst includes a first plate c1, a second plate c2 and a third plate c3. The first plate c1 is connected to the third plate c3. The first plate c1 and the second plate c2 overlap at least partially to form a first capacitor cst1. The second plate c2 and the third plate c3 overlap at least partially to form a second capacitor cst2.

[0050] In the thickness direction of the display panel 100, a first electrode c1 is disposed on the substrate 101, a second electrode c2 is disposed on the side of the first electrode c1 away from the substrate 101, and a third electrode c3 is disposed on the side of the second electrode c2 away from the substrate 101. A first active portion yy1 of the driving transistor T1 is disposed between the first electrode c1 and the second electrode c2. The first active portion yy1 comprises a metal-oxide-semiconductor.

[0051] In some embodiments of this application, in the display panel 100 viewed from above, a portion of the first electrode c1 overlaps with the first active portion yy1 of the driving transistor T1. The portions of the first electrode c1 and the second electrode c2 located outside the first active portion yy1 overlap to form a first capacitor cst1.

[0052] It is understood that the display panel 100 in this embodiment forms at least a portion of the storage capacitor Cst by setting parallel and overlapping first capacitor cst1 and second capacitor cst2, thereby increasing the capacitance of the storage capacitor Cst to improve its compensation capability for threshold voltage, while reducing the risk of excessively large layout area of ​​the storage capacitor Cst to meet the requirements of high resolution. Optionally, the area of ​​the first capacitor cst1 is larger than the overlapping area cd1 of the first electrode c1 and the first active part yy1.

[0053] It is understandable that, compared to the overlapping area of ​​the first active part yy1 and the first plate c1, the area of ​​the first capacitor cst1 is larger in order to increase the capacitance of the storage capacitor Cst, thereby improving the compensation capability for the threshold voltage of the driving transistor T1.

[0054] Optionally, in some embodiments of this application, the pixel circuit p1 includes a first node Q, which is disposed on the side of the third electrode c3 away from the substrate 101. The second electrode c2 of the storage capacitor Cst is connected to the first node Q.

[0055] In the display panel 100 viewed from above, the first node Q is spaced apart on one side of the first active part yy1, and the first electrode c1 and the second electrode c2 extend from the first active part yy1 toward the first node Q and both partially overlap with the first node Q.

[0056] Understandably, since the first node Q needs to connect to the second electrode c2, the second electrode c2 needs to extend towards the first node Q and partially overlap with it. This allows the first node Q to directly connect to the second electrode c2 through a via, thus saving wiring area. Based on this, since the second electrode c2 and the first electrode c1 are on different layers, and the first electrode c1 also extends towards the first node Q and partially overlaps with it, the planar layout area of ​​the entire storage capacitor Cst will not increase. Furthermore, the extended portion of the first electrode c1 overlaps with the extended portion of the second electrode c2, increasing the overlap area between the first electrode c1 and the second electrode c2, thereby increasing the capacitance of the first capacitor cst1 and ultimately increasing the capacitance of the storage capacitor Cst.

[0057] That is, in the embodiment of this application, the display panel 100 is provided with a first electrode plate c1 extending from the first active part yy1 toward the first node Q and partially overlapping with the first node Q. This not only does not increase the planar layout area of ​​the storage capacitor Cst, but also increases the capacitance of the storage capacitor Cst and improves the compensation capability for the threshold voltage.

[0058] Optionally, in some embodiments of this application, in the direction from the first active portion yy1 to the first node Q, the distance from the edge of the first electrode c1 near the first node Q to the edge of the first active portion yy1 near the first node Q is a first distance L1, and the distance from the edge of the second electrode c2 near the first node Q to the edge of the first active portion yy1 near the first node Q is a second distance L2. Both the first distance L1 and the second distance L2 are greater than the width v1 of the first active portion yy1.

[0059] It is understandable that the first distance L1 and the second distance L2 are both greater than the width v1 of the first active part yy1, that is, the first electrode c1 and the second electrode c2 extend a larger distance, so as to increase the overlap area of ​​the two and thus increase the capacitance of the first capacitor cst1.

[0060] Optionally, in some embodiments of this application, in the display panel 100 viewed from above, on the side of the first active portion yy1 near the first node Q, a portion of the first electrode c1 and a portion of the second electrode c2 overlap to form a first sub-capacitor CS01 of the first capacitor cst1. On the side of the first active portion yy1 away from the first node Q, another portion of the first electrode c1 and another portion of the second electrode c2 overlap to form a second sub-capacitor CS02 of the first capacitor cst1. The capacitance of the first sub-capacitor CS01 is greater than the capacitance of the second sub-capacitor CS02.

[0061] It is understandable that the first capacitor cst1 includes a first sub-capacitor cs01 and a second sub-capacitor cs02. The second sub-capacitor cs02 is formed by making full use of the area of ​​the first active part yy1 on the side away from the first node Q, so as to improve the capacitance of the first capacitor cst1.

[0062] Optionally, in some embodiments of this application, the area of ​​the first sub-capacitor CS01 is larger than the area of ​​the second sub-capacitor CS02.

[0063] It is understandable that, given that the layout area of ​​the second sub-capacitor CS02 is also relatively small, the capacitance of the storage capacitor Cst can be increased without increasing the overall layout area of ​​the pixel circuit P1. Secondly, the area of ​​the first sub-capacitor CS01 is relatively large, which can increase the capacitance of the first sub-capacitor CS01, thereby increasing the capacitance of the storage capacitor Cst.

[0064] Optionally, in some embodiments of this application, the first electrode plate c1 includes a first part c11, a second part c12 and a third part c13. The second part c12 and the first active part yy1 are overlapped. The first part c11 is connected to the side of the second part c12 that is close to the first node Q, and the third part c13 is connected to the side of the second part c12 that is away from the first node Q.

[0065] The second electrode plate c2 includes a fourth part c21, a fifth part c22 and a sixth part c23. The fifth part c22 is multiplexed as the gate of the driving transistor T1. The fourth part c21 is connected to the side of the fifth part c22 closer to the first node Q, and the sixth part c23 is connected to the side of the fifth part c22 away from the first node Q.

[0066] In the display panel 100 viewed from above, the first part c11 and the fourth part c21 at least partially overlap to form a first sub-capacitor cs01, and the third part c13 and the sixth part c23 at least partially overlap to form a second sub-capacitor cs02.

[0067] That is, Part 1 (c11) and Part 4 (c21) can completely overlap or partially overlap. Part 3 (c13) and Part 6 (c23) can completely overlap or partially overlap.

[0068] The overlap between the channel of the second part c12 and the channel of the first active part yy1 reduces the risk of the channel of the first active part yy1 being illuminated by backlight. The fifth part c22 is multiplexed as the gate of the driving transistor T1, avoiding the need to additionally set the gate of the driving transistor T1, saving layout area, and at the same time blocking the top of the first active part yy1, reducing the risk of ambient light illuminating the channel of the first active part yy1.

[0069] Please refer to Figure 6 Optionally, in some embodiments of this application, the display panel 100 includes a second active part yy2 disposed on the same layer as the first active part yy1. The second active part yy2 is located on the side of the first active part yy1 close to the first node Q, and the first node Q is connected to the second active part yy2.

[0070] In the display panel 100 viewed from above, the portion of the first part c11 located around the second electrode c2 overlaps with a portion of the second active part yy2 to form the third capacitor cst3 of the storage capacitor Cst.

[0071] It is understandable that, based on the connection between the first node Q and the second electrode c2, and the connection between the second active part yy2 and the first node Q, the first node Q and the second active part yy2 are equivalent to an extension of the second electrode c2. Therefore, the third capacitor cst3 formed by the overlap between the portion of the first part c11 of the first electrode c1 located on the periphery of the second electrode c2 and the portion of the second active part yy2 can constitute a part of the storage capacitor Cst, thereby increasing the capacitance of the storage capacitor Cst and improving the compensation capability for the threshold voltage.

[0072] Optionally, the second active portion yy2 is the active portion of the second transistor T2. It is understood that the first plate c1 extends below the second transistor T2 and overlaps with the output electrode of the second active portion yy2, which not only eliminates the need to increase the layout area of ​​the pixel circuit p1, but also increases the capacitance of the storage capacitor Cst.

[0073] Optionally, in some embodiments of this application, in the display panel 100 from a top-down view, the portion of the first part c11 located outside the second electrode c2, the third electrode c3, and the second active part yy2 overlaps with a portion of the first node Q to form a fourth capacitor cst4 of the storage capacitor Cst.

[0074] It is understandable that, based on the connection between the first node Q and the second plate c2, the first node Q is equivalent to an extension of the second plate c2. Therefore, the fourth capacitor cst4 formed by the overlapping of the portion of the first part c11 of the first plate c1 with the portion surrounding the second plate c2 and the second active part yy2 and the portion of the first node Q can constitute part of the storage capacitor Cst, thereby increasing the capacitance of the storage capacitor Cst and improving the compensation capability for the threshold voltage.

[0075] Since the fourth capacitor cst4 is located on the side of the third capacitor cst3 away from the second active part yy2, and the part of the first node Q that forms the fourth capacitor cst4 is used to connect the output of the third transistor T3, the first plate c1 extends to the bottom of the output d2 of the third transistor T3 to form the fourth capacitor cst4. This not only eliminates the need to increase the layout area of ​​the pixel circuit p1, but also increases the capacitance of the storage capacitor Cst.

[0076] Optionally, in some embodiments, the display panel 100 further includes a second scan line s2, wherein the portion of the second scan line s2 that overlaps with the second active portion yy2 is multiplexed as the gate of the second transistor T2, and the width v2 of the portion of the second scan line s2 that overlaps with the second transistor T2 is greater than the width v3 of the portion of the second scan line s2 that overlaps with the first node Q.

[0077] Understandably, the width v3 of the portion of the second scan line s2 that overlaps with the first node Q is smaller to reduce the parasitic capacitance of the first node Q, thereby improving the compensation capability for the threshold voltage. Secondly, the width v2 of the portion of the second scan line s2 that is multiplexed as the gate of the second transistor T2 is larger to improve the power-on effect of the second transistor T2, thereby improving the ability of the data signal Data to pass through the second transistor T2, thus improving the charging capability of the first node Q.

[0078] Optionally, in some embodiments of this application, in the display panel 100 viewed from above, a portion of the third plate c3 overlaps with a portion of the first node Q to form the fifth capacitor cst5 of the storage capacitor Cst.

[0079] It is understandable that, since the first node Q is equivalent to an extension of the second plate c2, the fifth capacitor cst5 formed by the partial overlap of the third plate c3 and the first node Q can increase the capacitance of the storage capacitor Cst.

[0080] Optionally, in some embodiments of this application, in the display panel 100 viewed from above, a portion of the third electrode plate c3 overlaps with a portion of the second active portion yy2 to form the sixth capacitor cst6 of the storage capacitor Cst.

[0081] It is understandable that, since the output pole of the second active part yy2 is equivalent to an extension of the second plate c2, the sixth capacitor cst6 formed by the partial overlap of the third plate c3 and the second active part yy2 can increase the capacitance of the storage capacitor Cst.

[0082] Optionally, the portions of the third plate c3 used to form the fifth capacitor cst5 and the portions used to form the sixth capacitor cst6 share a common area. That is, dual capacitors are achieved by sharing the area of ​​the common portion, which not only saves layout area but also increases the capacitance of the storage capacitor Cst.

[0083] Optionally, in some embodiments, the pixel circuit p1 includes a transition section Zj that connects to the output terminal of the driving transistor T1. The transition section Zj connects the first electrode plate c1 and the third electrode plate c3.

[0084] It is understandable that using the adapter Zj to connect the output of the driving transistor T1, the first plate c1, and the third plate c3 can further save layout area and facilitate meeting the requirements of high resolution.

[0085] Optionally, the third node B is the transition part Zj.

[0086] Optionally, in some embodiments of this application, the display panel 100 includes a buffer layer 102, a first metal layer 111, a first insulating layer 103, a first active layer 104, a second insulating layer 105, a second metal layer 112, a third insulating layer 106, a third metal layer 113, a fourth insulating layer 107, a fourth metal layer 114, a planarization layer 108, an anode layer 115, and a pixel definition layer 109, which are sequentially disposed on a substrate 101.

[0087] Optionally, in some embodiments, the display panel 100 may further include a second active layer, a fifth insulating layer 1010, a fifth metal layer, and a sixth insulating layer 1011. The second active layer is disposed on the buffer layer 102, the fifth insulating layer 1010 covers the second active layer and the buffer layer 102, the fifth metal layer is disposed on the fifth insulating layer 1010, and the sixth insulating layer 1011 covers the fifth metal layer and the fifth insulating layer 1010. A first metal layer 111 is disposed on the sixth insulating layer 1011.

[0088] It should be noted that the film layer architecture of the pixel circuit p1 can be set according to actual needs. This application does not impose any restrictions, as long as it can achieve the control of the light-emitting diode EL to emit light.

[0089] Optionally, in some embodiments, the pixel circuit p1 includes a second node A and a third node B, wherein a portion of the second node A is multiplexed as the input terminal of the driving transistor T1, and a portion of the third node B is multiplexed as the output terminal of the driving transistor T1.

[0090] Optionally, please combine Figure 2 and Figure 8 The first metal layer 111 includes a first electrode plate c1. The first electrode plate c1 also includes a first connecting portion c14, which is connected to one side of the first portion c11. The first connecting portion c14 is used to connect with the third node B.

[0091] Optionally, please combine Figure 2 and Figure 9 The first active layer 104 includes a first active part yy1 and a second active part yy2.

[0092] Optionally, please combine Figure 2 and Figure 10 The second metal layer 112 includes a second electrode plate c2 and a second scan line s2. The first node Q is connected to the second electrode plate c2 through a first via k1.

[0093] Optionally, please combine Figure 2 and Figure 11 The third metal layer 113 includes a third electrode plate c3. The third electrode plate c3 has a clearance hole kb1 to avoid the first through hole k1. Furthermore, the third electrode plate c3 also includes a second connecting part c31, and a third node B connects to the second connecting part c31.

[0094] In addition, part of the third plate c3 is reused as one plate of the sustaining capacitor Cw.

[0095] Optionally, please combine Figure 2 and Figure 12The fourth metal layer 114 includes a first node Q, a second node A, and a third node B. The first node Q is connected to the second electrode plate c2 via a first via k1. The third node B is connected to the first connecting portion c14 of the first electrode plate c1 via a second via k2. The third node B is connected to one end of the first active portion yy1 via a third via k3. The third node B is connected to the second connecting portion c31 of the third electrode plate c3 via a fourth via k4. The second node A is connected to the other end of the first active portion yy1 via a fifth via k5. The first node Q is connected to the output terminal of the second active portion yy2 via a sixth via k6. The first node Q is also connected to the output terminal of the third transistor T3 via a seventh via k7.

[0096] Among them, the second via k2, the third via k3 and the fourth via k4 are arranged side by side, so that the third node B extends in the vertical direction to save layout area.

[0097] In addition, the fourth metal layer 114 also includes another electrode w1 for maintaining capacitor Cw. The other electrode w1 for maintaining capacitor Cw partially overlaps with the third electrode c3.

[0098] Please refer to Figure 13 , Figure 13 This is a schematic diagram of the structure of the display device 1000 provided in the embodiments of this application.

[0099] Optionally, in some embodiments, this application provides a display device 1000, which includes the display panel 100 described in any of the above embodiments.

[0100] It should be noted that the structure of the display panel 100 of the display device 1000 provided in this application embodiment is similar to or the same as the structure of the display panel 100 provided in the above embodiments. For details, please refer to... Figures 1 to 12 Therefore, the relevant explanations will not be repeated here.

[0101] Optionally, the display device 1000 can be at least one of the following: smartphone, tablet, mobile phone, video phone, e-book reader, desktop computer, laptop, netbook, workstation, server, personal digital assistant, portable media player, MP3 player, television, mobile medical device, camera, game console, digital camera, car navigation system, in-vehicle display, electronic billboard, ATM, or wearable device, VR device, AR device.

[0102] In the display device 1000 of this application embodiment, in the display panel 100 from a top-view perspective, a portion of the first electrode plate c1 overlaps with the first active portion yy1 of the driving transistor T1, and the portions of the first electrode plate c1 and the second electrode plate c2 located outside the first active portion yy1 overlap to form a first capacitor cst1, and the area of ​​the first capacitor cst1 is larger than the overlap area cd1 of the first electrode plate c1 and the first active portion yy1.

[0103] It is understood that the display device 1000 of this application embodiment forms at least a portion of the storage capacitor Cst by setting a first capacitor cst1 and a second capacitor cst2 connected in parallel and overlapping, so as to increase the capacitance of the storage capacitor Cst while reducing the risk of the storage capacitor Cst having an excessively large layout area, so as to meet the requirements of high resolution; secondly, compared with the overlapping area of ​​the first active part yy1 and the first plate c1, the area of ​​the first capacitor cst1 is larger to increase the capacitance of the storage capacitor Cst.

[0104] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0105] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0106] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0107] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, include: Substrate; A pixel circuit is disposed on the substrate. The pixel circuit includes a driving transistor and a storage capacitor. The storage capacitor includes a first electrode plate, a second electrode plate, and a third electrode plate. The first electrode plate is connected to the third electrode plate. The first electrode plate and the second electrode plate at least partially overlap to form a first capacitor. The second electrode plate and the third electrode plate at least partially overlap to form a second capacitor. In the thickness direction of the display panel, the first electrode plate is disposed on the substrate. The second electrode plate is disposed on the side of the first electrode plate away from the substrate. The third electrode plate is disposed on the side of the second electrode plate away from the substrate. The first active portion of the driving transistor is disposed between the first electrode plate and the second electrode plate. The first active portion includes a metal-oxide-semiconductor. In the display panel viewed from above, a portion of the first electrode plate overlaps with the first active portion of the driving transistor, and the portions of the first electrode plate and the second electrode plate located outside the first active portion overlap to form the first capacitor.

2. The display panel according to claim 1, characterized in that, The area of ​​the first capacitor is larger than the overlapping area of ​​the first electrode plate and the first active part.

3. The display panel according to claim 1, characterized in that, The pixel circuit includes a first node, which is disposed on the side of the third electrode plate away from the substrate, and the second electrode plate of the storage capacitor is connected to the first node; In the display panel viewed from above, the first node is spaced apart on one side of the first active part, and the first electrode plate and the second electrode plate extend from the first active part toward the first node and both partially overlap with the first node.

4. The display panel according to claim 3, characterized in that, In the direction from the first active part to the first node, the distance from the edge of the first electrode plate near the first node to the edge of the first active part near the first node is the first distance, and the distance from the edge of the second electrode plate near the first node to the edge of the first active part near the first node is the second distance. Both the first distance and the second distance are greater than the width of the first active part.

5. The display panel according to claim 4, characterized in that, In the display panel viewed from above, on the side of the first active portion near the first node, a portion of the first electrode plate and a portion of the second electrode plate overlap to form a first sub-capacitor of the first capacitor; on the side of the first active portion away from the first node, another portion of the first electrode plate and another portion of the second electrode plate overlap to form a second sub-capacitor of the first capacitor, wherein the capacitance of the first sub-capacitor is greater than the capacitance of the second sub-capacitor.

6. The display panel according to claim 5, characterized in that, The area of ​​the first sub-capacitor is larger than the area of ​​the second sub-capacitor.

7. The display panel according to claim 5, characterized in that, The first electrode plate includes a first part, a second part, and a third part. The second part and the first active part are overlapped. The first part is connected to the side of the second part closer to the first node, and the third part is connected to the side of the second part away from the first node. The second electrode plate includes a fourth part, a fifth part, and a sixth part. The fifth part is multiplexed as the gate of the driving transistor. The fourth part is connected to the side of the fifth part closer to the first node, and the sixth part is connected to the side of the fifth part away from the first node. In the display panel viewed from above, the first part and the fourth part at least partially overlap to form the first sub-capacitor, and the third part and the sixth part at least partially overlap to form the second sub-capacitor.

8. The display panel according to claim 7, characterized in that, The display panel includes a second active part disposed on the same layer as the first active part. The second active part is located on the side of the first active part closer to the first node, and the first node is connected to the second active part. In the display panel viewed from above, the portion of the first part located around the second electrode plate overlaps with a portion of the second active part to form the third capacitor of the storage capacitor.

9. The display panel according to claim 8, characterized in that, In the display panel viewed from above, the portion of the first part located outside the second electrode plate, the third electrode plate, and the second active part overlaps with a portion of the first node to form the fourth capacitor of the storage capacitor.

10. The display panel according to claim 8, characterized in that, In the display panel viewed from above, a portion of the third electrode plate overlaps with a portion of the first node to form the fifth capacitor of the storage capacitor.

11. The display panel according to claim 10, characterized in that, In the display panel viewed from above, a portion of the third electrode plate overlaps with a portion of the second active portion to form the sixth capacitor of the storage capacitor.

12. The display panel according to any one of claims 3-11, characterized in that, The pixel circuit includes a junction that connects to the output terminal of the driving transistor, and the junction connects the first electrode plate and the third electrode plate.

13. The display panel according to claim 12, characterized in that, The display panel includes a buffer layer, a first metal layer, a first insulating layer, a first active layer, a second insulating layer, a second metal layer, a third insulating layer, a third metal layer, a fourth insulating layer, a fourth metal layer, and a planarization layer, which are sequentially disposed on the substrate. The pixel circuit includes a second node and a third node. A portion of the second node is multiplexed as the input terminal of the driving transistor, and the third node is the transition section. A portion of the third node is multiplexed as the output terminal of the driving transistor. The first metal layer includes the first electrode plate, the first active layer includes the first active part, the second metal layer includes the second electrode plate, the third metal layer includes the third electrode plate, and the fourth metal layer includes the first node, the second node, and the third node. The first node is connected to the second electrode plate through a first via, the third node is connected to the first electrode plate through a second via, the third node is connected to one end of the first active part through a third via, the third node is connected to the third electrode plate through a fourth via, and the second node is connected to the other end of the first active part through a fifth via.

14. The display panel according to any one of claims 1-11, characterized in that, The pixel circuit also includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a sustaining capacitor; The gate of the driving transistor is connected to a first node, the input of the driving transistor is connected to a second node, and the output of the driving transistor is connected to a third node. One end of the storage capacitor is connected to the first node, and the other end of the storage capacitor is connected to the third node. The gate of the second transistor is connected to a second scan signal, the input of the second transistor is connected to a data signal, and the output of the second transistor is connected to the first node. The gate of the third transistor is connected to a first scan signal, the input of the third transistor is connected to a first reset signal, and the output of the third transistor is connected to the first node. The gate of the fourth transistor is connected to the third scan signal, the input of the fourth transistor is connected to the second reset signal, the output of the fourth transistor is connected to the fourth node, the anode of the light-emitting diode is connected to the fourth node, the cathode of the light-emitting diode is connected to the second power supply voltage signal, the gate of the fifth transistor is connected to the first light-emitting control signal, the input of the fifth transistor is connected to the first power supply voltage signal, and the output of the fifth transistor is connected to the second node. The gate of the sixth transistor is connected to the second light emission control signal, the input of the sixth transistor is connected to the third node, the output of the sixth transistor is connected to the fourth node, one end of the sustaining capacitor is connected to the third node, the other end of the sustaining capacitor is connected to the output of the seventh transistor, the gate of the seventh transistor is connected to the third scan signal, and the input of the seventh transistor is connected to the first power supply voltage signal.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1-14.

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