Manufacturing method of electromagnetic shielding structure packaged by board-level plastic package

Abstract

The invention discloses a manufacturing method of an electromagnetic shielding structure for board-level plastic package of a vertical structure chip and a flip chip, which comprises the following steps of: firstly, manufacturing a bottom interconnection line layer, a bottom bonding pad and an external grounding point at the bottom end of a partition box dam of a shielding cover structure according to design requirement parameters, and then manufacturing the partition box dam and a copper column for realizing vertical interconnection; after the plastic package chip is fixedly mounted, a vertical interconnection line and a top metal layer of a shielding cover structure are sequentially manufactured layer by layer; when the carrier is separated, a layer of copper foil is reserved for manufacturing an outer circuit layer and an outer bonding pad, and finally cutting is carried out to obtain a single packaged finished product; a top metal layer, a partition box dam, vertically interconnected copper columns, interconnection line layers at all levels, bonding pads and grounding points are directly processed and manufactured by using a substrate wet process such as laser drilling, copper deposition, electroplating and pattern transfer in the prior art, so that the space occupation area can be reduced, the process is simplified, the space utilization rate is improved, and the cost input is reduced; and the stability and reliability of the product are ensured.

Description

Technical Field

[0001] This invention belongs to the field of electronic equipment technology, and specifically discloses a method for manufacturing an electromagnetic shielding structure for vertical structure chips and flip chip board-level plastic encapsulation. Background Technology

[0002] Traditional electromagnetic interference (EMI) shielding solutions employ metal shielding grilles, which are space-consuming and inefficient. Existing technologies typically utilize conformal shielding and partitioned shielding. While conformal shielding maintains the same shape as the original package without increasing its size, it requires internal isolation structures to prevent interference between subsystems. Furthermore, large SiP (System-in-Package) structures are prone to internal resonance, leading to system malfunction. Partitioned shielding is a further improvement on conformal shielding, achieving both external shielding and internal separation between subsystem modules. However, this method requires laser penetration of the encapsulation to expose the grounding copper on the packaging substrate, into which conductive filler is poured to form a shielding wall. This method has the following drawbacks: 1. It requires the use of expensive materials such as silver paste; 2. It adds extra filling and baking operations, increasing both operating costs and production cycle; 3. It is difficult to control voids in the filling process; 4. Subsequent process stress increases the risk of adhesive cracking after curing; 5. Excessive laser grooving increases operating costs; 6. The laser groove has an excessively large depth-to-width ratio, resulting in poor grooving process stability and effectiveness. This leads to complex processes, expensive materials, high production costs, and poor product stability.

[0003] However, the interconnect lines of flip chips and vertical structure chips differ from those of horizontal structure chips. Therefore, there is a need to provide a method for manufacturing an electromagnetic shielding structure that can avoid the above-mentioned defects and is applicable to both flip chips and vertical structure chips. Summary of the Invention

[0004] To address the aforementioned problems in the existing technology, the present invention aims to provide a method for manufacturing an electromagnetic shielding structure for vertical structure chips and flip-chip board-level plastic encapsulation, which can reduce the space occupied, simplify the process, improve space utilization, reduce cost input, and ensure the stability and reliability of the product.

[0005] The technical solution adopted in this invention is as follows: The first technical solution provides a method for manufacturing an electromagnetic shielding structure for vertical structure chips and flip-chip board-level plastic encapsulation, comprising the following steps: Obtain all chip and interconnect design parameters, and preset the shielding structure graphic parameters; Create the bottom interconnect layer, bottom pads, and external grounding point at the bottom of the isolation dam; Fabricate the partition dam and the copper pillars for vertical interconnection of the chips; Securely mount all chips to the designed locations; The top metal layer of the vertical interconnect lines and shielding structure is fabricated layer by layer. Separate the carrier, remove the separation layer, and fabricate the outer circuit layer and outer pads; Cut to obtain single-packaged finished products.

[0006] Specifically, obtaining all chip and interconnect design parameters and preset shielding structure graphic parameters includes the following operations: Set the design location of all chips, interconnect parameters of each layer, copper pillar parameters of vertical interconnects, and location specifications of areas requiring electromagnetic shielding according to design requirements and chip parameters; The location and dimensions of the top metal layer of the shielding structure are preset, as are the location and height of the partition dam.

[0007] Specifically, the copper pillars of the partition dam and the vertical interconnection line are at the same height.

[0008] Specifically, the fabrication of the bottom interconnect layer, bottom pads, and external grounding point at the bottom of the isolation dam includes the following operations: Add a first layer of insulating medium to the carrier; Drilling holes to form the bottom interconnect vias of the chip and the external grounding vias at the bottom of the isolation dam; Fabricate the bottom interconnect layer, and fill the drilled holes with metal to form the bottom pads of the copper pillars of the chip and the vertical interconnect, as well as the external grounding point at the bottom of the partition dam. Both the bottom pad and the external grounding point at the bottom of the partition dam are electrically connected to the separation layer of the carrier.

[0009] Specifically, the process of fixing and mounting all chips to the designed location includes the following operations: All chips are fixedly mounted onto the underlying interconnect layer.

[0010] Furthermore, if the chip includes flip chips, the flip chips are fixedly mounted one by one onto the bottom pads of the bottom interconnect layer with the front pads facing down.

[0011] Specifically, the step-by-step fabrication of the interconnection layer and the top metal layer of the shielding structure includes the following operations: Add a second layer of insulating medium to encapsulate all chips, embed all the partition barriers and copper pillars for vertical interconnection of all chips; drilling; A first metal layer is added to create the vertical interconnect lines of the chip. At the same time, metal is filled into the drilled holes to form a conductive connection structure between the top metal layer of the partition dam and the shield structure. Add a third layer of insulating medium, drill a hole; A second metal layer is added to form the top metal layer of the shielding structure; at the same time, metal is filled into the drilled hole so that the top metal layer of the shielding structure is connected and conductive to the partition dam.

[0012] Furthermore, the step-by-step fabrication of the interconnection layer and the top metal layer of the shielding structure also includes the following operations: An outer plastic seal layer is also laminated onto the top metal layer of the shielding structure.

[0013] Specifically, the separation of the carrier, removal of the separation layer, and fabrication of the outer circuit layer and outer pads include the following operations: Separate the carrier, remove the first copper foil layer that is in close contact with the carrier in the separation layer, and retain the second copper foil layer that is far away from the carrier; The outer circuit layer and outer pads are fabricated using a second layer of copper foil.

[0014] The second technical solution provides another method for manufacturing an electromagnetic shielding structure for horizontal structure chip board-level plastic packaging, which includes the following steps: Obtain all chip and redistribution layer circuit design parameters, and preset shielding cover structure graphic parameters; The top metal layer of the prefabricated shielding structure and the partition dam are prefabricated on the carrier; Securely mount all chips to the designed locations; All chips are encapsulated in layers of plastic molding and all isolation barriers are embedded; each plastic molding layer is drilled to create an electrical interconnect redistribution layer, and metal is filled into the drilled holes to form chip pads and isolation barrier grounding points respectively. The carrier is separated, cut, and single-packaged finished products are obtained.

[0015] Finally, both the first and second technical solutions can have separation layers on both sides of the carrier, and the carrier board can be simultaneously encapsulated at the board level.

[0016] The beneficial effects of this invention are as follows: It provides a method for manufacturing an electromagnetic shielding structure for vertical structure chips and flip-chip board-level plastic encapsulation. According to the design requirements, the bottom interconnect layer, bottom pads, and the bottom grounding point of the shielding structure are first fabricated. Then, the isolation dam and copper pillars for vertical interconnection are fabricated. After the plastic-encapsulated chip is fixed and mounted, the top metal layer of the vertical interconnect and shielding structure is fabricated layer by layer. When separating the carrier, a layer of copper foil is reserved for fabricating the outer circuit layer and outer pads. Finally, the single packaged product is cut to obtain the final product. This method can reduce the space occupied, simplify the process, improve space utilization, reduce cost input, and ensure the stability and reliability of the product. It is compatible with existing board-level molding and packaging equipment, and can directly fabricate the top metal layer, partition barriers, vertical interconnect copper pillars, interconnect layers, pads, and grounding points using existing wet substrate processes such as laser drilling, copper plating, electroplating, and pattern transfer. This eliminates the need for complex processes like laser deep grooving and silver paste filling, avoiding the risk of adhesive cracking after curing due to subsequent process stress. This significantly shortens the production cycle and reduces operating and material costs. The layered drilling and metal filling process for pads, partition barriers, and grounding points avoids excessively large aspect ratios from laser grooving, resulting in good process stability and excellent performance. Furthermore, it is highly adaptable, capable of accommodating various structures with different packaging requirements, and has a wide range of applications. Attached Figure Description

[0017] Figure 1 The top-middle image is a schematic diagram of the structure of a metal shielding cover in conventional technology; the middle image is a schematic diagram of a conformal shielding structure in existing technology; and the bottom image is a schematic diagram of a partitioned shielding structure in existing technology. Figures 2-6 This is a schematic diagram of the manufacturing process of an electromagnetic shielding structure for vertical structure chip board-level plastic encapsulation according to Embodiment 1 of the present invention. Figure 7 Yes~ Figure 11 This is a schematic diagram of the manufacturing process of an electromagnetic shielding structure for flip-chip board-level plastic encapsulation according to Embodiment 2 of the present invention. Figures 12-16 This is a schematic diagram of the manufacturing process of the electromagnetic shielding structure for vertical structure chips and flip chip board-level plastic encapsulation according to Embodiment 3 of the present invention. Figures 17-21 This is a schematic diagram of the manufacturing process of an electromagnetic shielding structure for vertical structure chip board-level plastic encapsulation according to Embodiment 4 of the present invention. Figures 22-26 This is a schematic diagram illustrating the manufacturing process of an electromagnetic shielding structure for flip-chip board-level plastic encapsulation according to Embodiment 5 of the present invention. Detailed Implementation

[0018] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "vertical," "horizontal," "left," "right," "inner," "outer," and similar expressions used in this specification are for illustrative purposes only. In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of indicated technical features. Thus, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0019] Furthermore, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections via an intermediate medium, or internal communication between two components. All technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0020] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0021] Please refer to Figures 1 to 26 As shown, this invention provides a method for manufacturing a board-level plastic encapsulation electromagnetic shielding structure for vertical structure chips and flip chips. The analysis of existing technical solutions is as follows: Shielding in electronic systems serves two main purposes: compliance with EMC standards and prevention of interference. Electromagnetic shielding requirements in chip packaging primarily arise in scenarios with extremely high demands for signal integrity, operational reliability, or safety. For example, in high-performance computing and communication, high-speed data exchange within and between CPU / GPU, RF chips, power amplifiers, baseband chips, and high-speed switching power supplies generates strong electromagnetic noise; high-power circuits are susceptible to interference; and high signal frequencies (moving towards GHz and THz) easily radiate interference. In high-density integrated and miniaturized devices, RF chips, digital chips, and analog chips, along with multiple functional chips (RF, digital, and analog), are integrated into extremely small spaces in system-in-package (SiP), making them highly susceptible to mutual interference ("neighborhood disputes"); the extremely limited physical space necessitates ultra-thin shielding layers. In automotive electronics and new energy vehicles, power modules such as SiC modules, radar chips, and smart cockpit main control chips operate in harsh automotive electronic environments (temperature variations, vibration); high-power devices (such as inverters) generate strong electromagnetic interference during switching, threatening low-voltage control circuits; and safety (ADAS) is involved, requiring extremely high reliability. In medical and precision instruments, the signals of high-precision analog chips, sensor signal processing chips, low-noise amplifiers, and other equipment are extremely weak and easily overwhelmed by external electromagnetic noise; therefore, shielding measures are required to protect themselves while preventing electromagnetic pollution from the outside world.

[0022] Traditional electromagnetic interference (EMI) shielding has been using metal shielding enclosures for over 30 years. These enclosures are mounted on SMT-finished PCBs to cover the components that need to be shielded. The enclosures occupy valuable PCB space horizontally and vertically within the equipment. Each section requires approximately 1mm of pad and keep-out zone space. They take up too much space and are inefficient, which is a major obstacle to equipment miniaturization.

[0023] As electronic devices evolve towards higher performance, higher integration, and miniaturization, electromagnetic interference (EMI) has become increasingly prominent, especially in the field of chip packaging. System-in-package (SiP) modules integrate hundreds or thousands of components, making it essential to avoid mutual interference between components within and outside the module. This prevents EMI generation between densely packed internal components and external signals, ensuring stable device performance. Electromagnetic shielding has become a key technology for ensuring device reliability and signal integrity. Due to the need for improved shielding effectiveness and miniaturization, metal shielding grids have been gradually phased out. Currently, the most common electromagnetic shielding methods in the industry are conformal shielding and compartment shielding.

[0024] Conformal shielding technology maintains the same shape as the original package, forming a uniform metallic shielding layer on the package surface through processes such as electroplating, spraying, and sputtering without increasing the package size. Conformal shielding is mainly used in SiP module packages such as PAs, WiFi / BT, and memory modules to isolate interference between the internal circuitry and external systems.

[0025] For complex SiP packages that integrate AP / BB, memory, WiFi / BT, FEM, etc., the various subsystems within the package can interfere with each other, requiring isolation within the package. Furthermore, for large-size SiP packages, the electromagnetic resonant frequency of the entire shielding structure is low, and combined with the wide noise bandwidth of the digital system itself, resonance can easily occur within the SiP, causing the system to malfunction.

[0026] Compartment shielding, besides being used for external shielding of packages, can also isolate subsystem modules within a package. It's an improvement on conformal shielding technology, using a laser to penetrate the plastic package, exposing the grounded copper on the package substrate. Conductive filler is then poured in to form a shielding wall, which, together with the conformal shielding layer on the package surface, completely isolates each subsystem. Furthermore, compartment shielding divides the shielding cavity into smaller cavities, reducing its size. These cavities have resonant frequencies much higher than the system noise frequency, avoiding electromagnetic resonance and thus making the system more stable. Additionally, compartment shielding allows for selective shielding, shielding only areas requiring shielding.

[0027] However, the current method of partitioned shielding by filling the groove with conductive silver paste and curing it, and then connecting the conductive paste to the ground on the substrate, presents several challenges in terms of processing difficulty and cost. The main difficulties of this method are: 1. Using expensive materials such as silver paste; 2. Adding extra filling and baking operations, which increases both operating costs and production cycle; 3. Difficulty in controlling voids in the filling; 4. High risk of adhesive cracking after curing due to stress from subsequent processes; 5. Excessive laser grooving, resulting in high operating costs; 6. Excessive aspect ratio of the laser groove, leading to poor stability and effectiveness of the grooving process.

[0028] Therefore, to solve the above-mentioned technical problems, the present invention conceived and planned the following technical solution in the early stage: It provides an electromagnetic shielding technology for board-level plastic packaging, mainly targeting board-level plastic packaging structures. It utilizes processes such as wet pattern electroplating and pattern etching on the substrate to create copper dams inside the plastic packaging layer according to design requirements, and connects them to the laser-etched vias for grounding. This effectively solves some of the defects of current partitioned shielding technologies that use laser grooving followed by filling with conductive adhesive. Furthermore, through precise and flexible shielding design, it effectively reduces mutual interference between components, improving product stability and reliability. Secondly, the developed board-level packaging shielding technology significantly reduces the space occupied, providing customers with the possibility of implementing more functions within a limited space, meeting customers' increasingly diversified product design needs, and further enhancing production competitiveness in chip module board-level packaging.

[0029] Based on the characteristics of various chip structures, corresponding technical solutions and process designs are developed. Specifically, based on the different structural characteristics of vertical structure chips, flip chips, and planar structure chips, as well as the usage requirements for shielding in different areas, corresponding technical solutions and process designs are developed.

[0030] The first technical solution provides a method for manufacturing an electromagnetic shielding structure for vertical structure chips and flip-chip board-level plastic encapsulation. The planned technical solution can be summarized as follows: obtain all chip and interconnect design parameters, and preset the shielding structure graphic parameters; fabricate the bottom interconnect layer, bottom pads, and external grounding points at the bottom of the isolation dam; fabricate the isolation dam and copper pillars for vertical interconnection of the chips; fix and mount all chips to the designed positions and encapsulate them; fabricate the top metal layer of the vertical interconnect and shielding structure layer by layer; separate the carrier, remove the separation layer, and fabricate the outer circuit layer and outer pads; cut to obtain a single packaged finished product.

[0031] The first technical solution is mainly applied to the shielding structure of vertical structure chips and flip chips. Specific operational details can be implemented based on the layout requirements of vertical structure chips and flip chips, as well as the shielding requirements for different areas. The process method adopted by the first technical solution is to first fabricate the bottom interconnect layer, bottom pads, and the grounding point at the bottom of the isolation dam of the shielding structure according to the design requirements. Then, the isolation dam and copper pillars for vertical interconnection are fabricated. After fixing the molded chip, the top metal layer of the vertical interconnect and shielding structure is fabricated layer by layer. When separating the carrier, a layer of copper foil is retained for fabricating the outer circuit layer and outer pads. Finally, the chip is cut to obtain a single packaged product. This method can reduce the space occupied, simplify the process, improve space utilization, reduce cost input, and ensure product stability and reliability. It is compatible with existing board-level molding and packaging equipment, and can directly fabricate the top metal layer, partition barriers, vertical interconnect copper pillars, interconnect layers, pads, and grounding points using existing wet substrate processes such as laser drilling, copper plating, electroplating, and pattern transfer. This eliminates the need for complex processes like laser deep grooving and silver paste filling, avoiding the risk of adhesive cracking after curing due to subsequent process stress. This significantly shortens the production cycle and reduces operating and material costs. The layered drilling and metal filling process for pads, partition barriers, and grounding points avoids excessively large aspect ratios from laser grooving, resulting in good process stability and excellent performance. Furthermore, it is highly adaptable, capable of accommodating various structures with different packaging requirements, and has a wide range of applications.

[0032] In other words, the first technical solution employs a different process than the existing method of first packaging the chip and then setting the shielding structure. Specifically, the bottom grounding point of the shielding structure's isolation barrier is fabricated simultaneously with the fabrication of the underlying interconnect lines. Then, the isolation barrier and copper pillars for vertical interconnection are fabricated. After fixing and mounting the molded chip, the vertical interconnect lines and the top metal layer of the shielding structure are fabricated layer by layer. When separating the carrier, a layer of copper foil is retained for fabricating the outer circuit layers and outer pads. Finally, the chip is cut to obtain a single packaged product. This solution abandons the high aspect ratio laser grooving process used in existing partitioned shielding technologies. The grooving process offers excellent stability and effectiveness, eliminating the need for difficult-to-control deep-hole filling operations, resulting in good product stability. Simultaneously filling the drilled holes with metal during the fabrication of each circuit layer creates the external connection points for the circuit pads and isolation barrier, eliminating the need for expensive materials like silver paste and additional filling and baking operations. This simplifies the process, shortens the production cycle, and reduces manufacturing costs.

[0033] The second technical solution provides another method for manufacturing an electromagnetic shielding structure for horizontal chip board-level plastic encapsulation, including the following steps: obtaining all chip and redistribution layer circuit design parameters, and pre-setting shielding structure graphic parameters; prefabricating the top metal layer and isolation dams of the shielding structure on the carrier; fixing and mounting all chips to the designed positions; layering and plastic encapsulating all chips and embedding all isolation dams; drilling holes in each plastic encapsulation layer to create electrical interconnection redistribution layers, and filling the drilled holes with metal to form chip pads and isolation dam grounding points respectively; separating the carrier, cutting, and obtaining a single packaged finished product.

[0034] The second technical solution is mainly applied to the shielding structure of planar chips. Specific operational details can be implemented based on whether heat dissipation is required and the shielding requirements for different areas. The second technical solution is similar in principle to the first. The process involves first prefabricating the top metal layer and isolation dam of the shielding structure. After fixing the chip to the designed position, it is then encapsulated layer by layer. Simultaneously, holes are drilled in each encapsulation layer to create electrical interconnection and redistribution layers, and metal is filled into the drilled holes to form chip pads and external grounding points for the isolation dam.

[0035] Furthermore, both the first and second technical solutions can have separation layers on both sides of the carrier, allowing for simultaneous board-level plastic encapsulation on both sides of the carrier. This further doubles production efficiency, shortens the production cycle, and reduces production costs.

[0036] Example 1: As Figures 2-6 As shown. Following the steps of the shielding structure manufacturing method in the board-level plastic encapsulation process for chip 102, where all chips are vertically structured, as described in the first technical solution above, a shielding metal cover needs to be set to ensure electromagnetic shielding covers all chip areas. In this example, all metal layers are copper. In actual production operations, other metal materials suitable for the chip industry can be flexibly selected, such as gold, silver, aluminum, tin, iron, etc.

[0037] First, the design parameters for all vertical structure chips 102 and vertical interconnect lines are set according to the design requirements. The shielding structure graphic parameters are preset, specifically the design positions of all vertical structure chips 102, the parameters of each interconnect line layer, the parameters of the copper pillars 52 of the vertical interconnect lines, and the position specifications of the areas requiring electromagnetic shielding. The position and size parameters of the top metal layer 2 of the shielding structure, as well as the position and height parameters of the partition dam 52 are preset.

[0038] In actual operation, the height of the isolation barrier 52 must be higher than the thickness of the vertical structure chip 102, that is, higher than the distance between the top surface of the vertical structure chip 102 and the bottom circuit layer, so as to ensure the isolation and shielding effect of the isolation barrier 52.

[0039] In Embodiment 1, the area requiring electromagnetic shielding needs to cover all the areas where the vertical structure chips 102 are located. Therefore, the coverage of the shielding metal cover needs to cover all the vertical structure chips 102. Thus, the location and size parameters of the partition dam of the shielding cover structure are set to surround all chip areas, and the partition dam 52 is designed to be set around each vertical structure chip 102.

[0040] Secondly, fabricate the bottom interconnect layer, the bottom pads, and the external grounding point at the bottom of the isolation dam.

[0041] The second step involves adding a first insulating dielectric layer 20 to the carrier 100 using a lamination process. The carrier 100 is made of materials such as double-sided copper-clad laminate or steel plate. The first insulating dielectric layer 20 is made of materials such as plastic sealing film or prepreg. To facilitate the subsequent separation of the carrier 100, an easily removable separation layer 40 can be provided between the carrier 100 and the first insulating dielectric layer 20. The material of the separation layer 40 can be copper foil. To further simplify the manufacturing process of the external circuit layer, the copper foil of the separation layer 40 can be further configured as a separable double-layer copper foil, consisting of a first copper foil 41 away from the carrier and a second copper foil 42 close to the carrier.

[0042] The third step involves drilling holes using laser drilling or developing patterns using a developable plastic sealant film to create external grounding vias 21 at the bottom of each partition dam, bottom interconnect vias 23 at the position of each vertical structure chip 102, and interconnect vias 24 at the bottom of each vertical interconnect line's copper pillar. All external grounding vias 21 at the bottom of the partition dam, bottom interconnect vias 23 at the chip, and interconnect vias 24 at the bottom of the vertical interconnect line's copper pillar are through holes, ensuring that the bottom ends of all external grounding vias 21 at the bottom of the partition dam 51, bottom interconnect vias 23 at the chip, and interconnect vias 24 at the bottom of the vertical interconnect line's copper pillar 52 are open and connected to the first layer of copper foil 41 of the carrier 100.

[0043] The fourth step involves fabricating the bottom interconnect layer. Simultaneously, metal is filled into the external grounding via 21 at the bottom of the isolation dam, the bottom interconnect via 23 of the chip, and the bottom interconnect via 24 of the copper pillars of the vertical interconnect. This prefabricates the bottom pads 33 of the vertical structure chip and the bottom pads 34 of the copper pillars of the vertical interconnect, as well as the external grounding point 31 at the bottom of the isolation dam 51. All bottom pads and all external grounding points at the bottom of the isolation dam are conductively connected to the carrier's separation layer. Specifically, conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, and pattern transfer can be used to fabricate this bottom interconnect layer, grounding point, and pads.

[0044] In actual operation, since all the external grounding vias 21 corresponding to the bottom position of the isolation dam, the bottom interconnect vias 23 corresponding to the chip position, and the interconnect vias 24 corresponding to the bottom position of the copper pillars of the vertical interconnect line are open and connected to the first layer copper foil 41 of the carrier 100 in the second step; and the separation layer 40 is a separable double layer copper foil, consisting of the first layer copper foil 41 away from the carrier and the second layer copper foil 42 close to the carrier; therefore, all the bottom pads 33 of the chip and the bottom pads 34 of the copper pillars of the vertical interconnect line, as well as the external grounding point 31 at the bottom of the isolation dam 52, are connected to the first layer copper foil 41, forming an electrical bottom interconnect structure.

[0045] The fifth step involves fabricating all the partition dams 51 and the copper pillars 52 used for vertical interconnection of the chips. Specifically, according to the design requirements, a wet pattern electroplating process is used to electroplat copper metal dams of the designed height around the electromagnetic shielding area, as well as single-column copper pillars, thereby forming the partition dams 51 and the copper pillars 52 used for vertical interconnection of the chips.

[0046] In actual operation, at the external grounding point 31 at the bottom of the corresponding isolation dam, a wet pattern electroplating process is used to electroplat copper metal around the electromagnetic shielding area, stacking it to a height that meets the design requirements, thus prefabricating the isolation dam 51, which forms the shielding cover structure; on the bottom pad 34 at the corresponding vertical interconnection line copper pillar position, a wet pattern electroplating process is used to electroplat copper metal single pillar around the electromagnetic shielding area, stacking it to a height that meets the design requirements, thus prefabricating the copper pillar 52, which forms the vertical interconnection line. For example... Figure 2 As shown.

[0047] Next, in step six, all chips are fixedly mounted to their designed positions. Since all chips are vertically oriented chips 102, they are directly fixed to the bottom pads 33 of the underlying interconnect layer using surface mount methods such as silver paste, SMT soldering, or DAF (Die Attach Film), thus enabling conductive connections to external electrical circuits through the bottom pads 33. For example... Figure 3 As shown.

[0048] Next, the top metal layer of the vertical interconnect lines and shielding structure is fabricated layer by layer.

[0049] Step 7: First, perform molding, adding a second insulating layer 60 to encapsulate all chips, embedding all isolation barriers 52 and all copper pillars 53 used to realize the vertical interconnection lines of the chips. Specifically, resin-based molding materials can be used, employing vacuum pressing or molding processes to form the second insulating layer 60, which encapsulates all vertically structured chips 102, while simultaneously embedding all isolation barriers 52 and all copper pillars 53 used to realize the vertical interconnection lines of the chips.

[0050] Step 8, drilling; using laser drilling, drill through-hole slots 61 at the top of all the isolation dams 52, through-holes 62 for all the chips, and through-holes 63 at the top of all the copper pillars 52 for all the vertical interconnect lines on the second insulating medium 60.

[0051] In the ninth step, conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, and pattern transfer are used to fabricate the vertical interconnect layer 70. Simultaneously, metal is filled into the via slots 61 at the top of all the isolation barriers 52, prefabricating an inner connection segment for interconnecting the top of the isolation barriers 52 with the top metal layer of the shielding structure. Metal is also filled into the interlayer interconnect vias 62 of all chips and the interconnect vias 63 at the top of the copper pillars 53 of all vertical interconnect lines, so that both ends of each vertical interconnect layer 70 are conductively connected to the vertical structure chip 102 and the copper pillar 52, respectively. That is, each vertical structure chip 102 is conductively connected to the corresponding copper pillar 52 through both ends of the vertical interconnect layer 70; thus, the upper and lower poles of each vertical structure chip 102 are connected to the bottom layer.

[0052] Step 10: Add a third layer of insulating medium 80 and drill holes. In actual operation, a third layer of insulating medium 80 is added on top of the carrier using a pressing process. The material of the third layer of insulating medium 80 can be a plastic sealing film or a prepreg, etc. Then, laser drilling is used to drill the inner conductive groove 81 at the top of the partition dam 52 on the third layer of insulating medium 80.

[0053] Step 11: Add a second metal layer to form the top metal layer of the shielding structure; simultaneously, fill the drilled holes with metal to connect the top metal layer of the shielding structure to the isolation dam. In actual operation, conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, and pattern transfer are used to fabricate the top metal layer 2 of the shielding metal cover, and the inner conductive slots 81 are metallized and filled to connect the top metal layer 2 of the shielding structure to the isolation dam 52. Figure 4 As shown. The top metal layer 2 of the shielding metal cover can also be selectively patterned by electroplating and etching, flexibly achieving selective area shielding.

[0054] After the top metal layer 2 of the shielding metal cover is manufactured, an outer plastic sealing layer 200 can be laminated on top of the top metal layer 2 according to design requirements. For example... Figure 5 As shown.

[0055] Next, separate the carrier, remove the separation layer, and fabricate the outer circuit layer and outer pads.

[0056] Step 12: Remove the separation layer from the carrier 100, and then fabricate the outer circuit layer and outer pads. In actual operation, because the separation layer 40 is a separable double-layer copper foil, consisting of a first copper foil 41 away from the carrier and a second copper foil 42 in close contact with the carrier, when separating the carrier 100, the second copper foil 42 in close contact with the carrier 100 is simultaneously removed, while the first copper foil 41 away from the carrier is retained. Figure 16 As shown. When fabricating the outer circuit layer and outer pads, the outer circuit layer and outer pads 411 are directly fabricated using a pattern etching process through the first copper foil 41, which is furthest from the carrier. For example... Figure 6 As shown.

[0057] Finally, in the thirteenth step, the product is cut to obtain several individually packaged finished products.

[0058] Example 2: Figures 7-11 As shown. According to the above-described first technical solution, the shielding structure manufacturing method in the board-level plastic encapsulation process for all chips being flip chips 101 requires the installation of a second shielding metal cover to ensure electromagnetic shielding covers all chip areas. Since flip chips do not require vertical interconnect lines like vertical structure chips, there is no need for vertical interconnect copper pillar structures. The specific operation is based on the above-described embodiment one, but the copper pillar-related process steps are omitted. Furthermore, corresponding operations need to be performed according to the flip chip mounting requirements in each step, especially in the chip mounting process.

[0059] First, the first step is to set the design parameters for all flip chips 101 and interconnect lines according to the design requirements and the flip-chip process. This involves pre-setting the graphic parameters of the second shielding structure, specifically the layout of all flip chips 101, setting the parameters for each interconnect layer, and defining the location and specifications of areas requiring electromagnetic shielding. The step also involves pre-setting the position and dimensions of the second top metal layer 220 of the second shielding structure, as well as the position and height of the second isolation barrier 521. Flip chips do not require vertical circuit interconnects or inter-layer interconnects, therefore, inter-layer interconnect circuits and copper pillars are unnecessary.

[0060] In actual operation, the height of the second isolation barrier 521 must be higher than the thickness of the flip chip 101, that is, higher than the distance between the top surface of the flip chip 101 and the bottom circuit layer, so as to ensure the isolation and shielding effect of the second isolation barrier 521.

[0061] In Embodiment 2, the area requiring electromagnetic shielding also covers the area where all flip chips 101 are located. Therefore, the shielding structure of Embodiment 2 is based on the same principle as the shielding structure of Embodiment 1. The coverage of the second shielding metal cover needs to cover all flip chips 101. Therefore, the position and size parameters of the second partition dam 521 of the second shielding cover structure are designed to surround all chip areas, and the second partition dam 52 is designed to surround each flip chip 101.

[0062] Secondly, the bottom interconnect layer, bottom pads, and external grounding point at the bottom of the isolation dam are fabricated. The second step in Example 2 also involves adding a first insulating dielectric layer 20 to the carrier 100 using a lamination process. The specific operation is the same as the second step in Example 1.

[0063] The third step involves drilling holes using laser drilling or developing patterns using a developable encapsulating film to create external grounding second via slots 221 at the bottom of each second partition dam and bottom interconnect second vias 22 at each flip chip location. All external grounding second via slots 21 and bottom interconnect second vias 22 at the bottom of the second partition dam are through-holes, ensuring that the bottom ends of all second via slots 21 and second vias 22 are open and connected to the first copper foil 41 of the carrier 100. Figure 18 As shown. Based on the characteristics of the flip-chip process, the position and number of the second via slot 221 are set according to the pin parameters of the flip-chip 101.

[0064] The fourth step involves fabricating the bottom interconnect layer. Simultaneously, metal is filled into the second via slot 221 and the second via 22 to prefabricate the second bottom pad 32 and the second external ground point 321 at the bottom of the second isolation dam 521, forming the second bottom pad 32 of the flip chip. All second bottom pads and all second external ground points are conductively connected to the carrier's separation layer. Specifically, conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, and pattern transfer can be used to fabricate this bottom interconnect layer, ground point, and pads.

[0065] In actual operation, since all the second through-hole slots 221 and second through-holes 22 in the second step are open at the bottom and connected to the first copper foil 41 of the carrier 100; and the separation layer 40 is a separable double copper foil, consisting of the first copper foil 41 away from the carrier and the second copper foil 42 close to the carrier; therefore, all the second bottom pads 32 and the second external ground point 321 are conductively connected to the first copper foil 41, forming an electrical bottom interconnection structure.

[0066] Next, in the fifth step, all the second partition dams 521 are fabricated. Specifically, according to the design requirements, a wet pattern electroplating process is used to electroplat copper metal dams of the designed height around the electromagnetic shielding area, thus forming the second partition dams 521.

[0067] In actual operation, at the second external grounding point 321 corresponding to the bottom of the second partition dam, a wet pattern electroplating process is used to electroplat a copper metal layer around the electromagnetic shielding area to a height that meets the design requirements, thus prefabricating the second partition dam 521, which constitutes the second shielding cover structure. For example... Figure 7 As shown.

[0068] Next, in the sixth step, all chips are fixedly mounted to their designed positions. Since all chips are flip chips 101, they are all mounted face down using methods such as silver paste, SMT soldering grounding, or DAF (Die Attach Film). The lead pads on the front of each flip chip 101 are directly and fixedly attached to the second bottom layer pad 32 of the underlying interconnect layer, thus enabling conductivity to external electrical circuits through the second bottom layer pad 32. For example... Figure 8 As shown.

[0069] Next, the second top metal layer of the interconnecting lines and the second shielding structure is fabricated layer by layer.

[0070] Step 7: First, perform plastic encapsulation, adding a second insulating layer 62 to encapsulate all flip chips and embed all second isolation barriers 521. Specifically, resin-based encapsulation materials are used, employing vacuum pressing or molding processes to form the second insulating layer 62, which encapsulates all flip chips 101 and simultaneously embeds all second isolation barriers 521.

[0071] Step 8, drilling; using laser drilling, drill the second through-hole grooves 621 on the top of all the second partition dams 521 using laser drilling.

[0072] Step 9: Using conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, pattern transfer, etc., fill the second through-hole grooves 621 at the top of all the second partition dams 521 with metal, and prefabricate the second inner connection section 721 for interconnecting and communicating the top of the second partition dam 521 with the second top metal layer of the second shield structure.

[0073] Step 10: Add a third layer of insulating medium 82 and drill holes. In actual operation, a pressing process is used to add a third layer of insulating medium 82 on top of the carrier. The material of the third layer of insulating medium 82 can be a plastic sealing film or a prepreg, etc.

[0074] And on the third layer of insulating medium 82, at the position corresponding to the second partition dam 521, the second inner layer conductive slot 821 at the top of the partition dam is drilled using laser drilling technology.

[0075] Step 11: Add a second metal layer to form the second top metal layer 220 of the second shielding structure; simultaneously, fill the drilled holes with metal, so that the second top metal layer 220 of the second shielding structure is connected and conductive to the second isolation dam 521. In actual operation, conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, and pattern transfer are used to fabricate the second top metal layer 220 of the shielding metal cover, and to metallize and fill the conductive slots 821 in the second inner layer, so that the second top metal layer 220 of the second shielding structure is connected and conductive to the second isolation dam 521. The second top metal layer 220 of the second shielding metal cover can also be selectively pattern transferred, electroplated, and etched to flexibly achieve selective area shielding. Figure 9 As shown.

[0076] After the second top metal layer 220 of the second shielding metal cover is manufactured, a second outer plastic sealing layer 202 can be laminated on top of the second top metal layer 220 according to design requirements. For example... Figure 10 As shown.

[0077] Next, separate the carrier, remove the separation layer, and fabricate the outer circuit layer and outer pads.

[0078] Step 12: Separate the carrier 100 by removing the separation layer, and then fabricate the outer circuit layer and outer pads. In actual operation, because the separation layer 40 is a separable double-layer copper foil, consisting of a first copper foil 41 far from the carrier and a second copper foil 42 close to the carrier, when separating the carrier 100, the second copper foil 42 close to the carrier 100 in the separation layer is removed simultaneously, while the first copper foil 41 far from the carrier is retained. When fabricating the outer circuit layer and outer pads, the second outer circuit layer and outer pads 412 are directly fabricated using a pattern etching process through the first copper foil 41 far from the carrier. Figure 11 As shown.

[0079] Finally, in the thirteenth step, the product is cut to obtain several individually packaged finished products.

[0080] Example 3: Figures 12-16As shown. According to the first technical solution described above, the shielding structure manufacturing method for the board-level plastic encapsulation process, which includes both flip chips 101 and vertical structure chips 102, requires the installation of a third shielding metal cover to ensure electromagnetic shielding covers all chip areas. In Embodiment Three, it is necessary to simultaneously accommodate the flip-chip process characteristics of flip chips and the vertical interconnect characteristics of vertical structure chips. Specifically, based on Embodiment One, it needs to incorporate the relevant operations of the vertical interconnect layer and copper pillars from Embodiment One, as well as the corresponding operations performed according to the flip-chip mounting requirements in Embodiment Two's flip-chip mounting process.

[0081] First, in the first step of Embodiment 3, according to the design requirements, the vertical interconnect lines and the chip flip-chip process requirements are used to set the design parameters of all flip-chip 101, and preset the graphic parameters of the third shielding cover structure. Specifically, the design positions of all flip-chip 101 and vertical structure chip 102 are laid out, and the parameters of each interconnect line layer, the parameters of the copper pillars 52 of the vertical interconnect lines, and the position and specification parameters of the areas requiring electromagnetic shielding are set. The position and specification dimensions of the third top metal layer 230 of the third shielding cover structure, as well as the position and height parameters of the third partition dam 531, are preset.

[0082] In actual operation, the height of the third isolation barrier 531 must be higher than the thickness of all flip chips 101 and vertical structure chips 102, that is, higher than the maximum distance between the top surface of the flip chips 101 and vertical structure chips 102 and the bottom circuit layer, so as to ensure the isolation and shielding effect of the second isolation barrier 521; the height of the second isolation barrier 521 must not be less than the thickness of the flip chips 101 and vertical structure chips 102.

[0083] In Embodiment 3, the area requiring electromagnetic shielding also covers the area where all flip chips 101 and vertical structure chips 102 are located. Therefore, the shielding structure in Embodiment 3 is based on the same principle as the shielding structure in Embodiment 1. The coverage of the third shielding metal cover needs to cover all flip chips 101 and vertical structure chips 102. Therefore, the position and size parameters of the third partition dam 531 of the third shielding cover structure are designed to surround all chip areas, and the third partition dam 531 is designed to surround each flip chip 101 and vertical structure chip 102.

[0084] Secondly, the bottom interconnect layer, bottom pads, and external grounding point at the bottom of the isolation dam are fabricated. The second step also involves adding a first insulating dielectric layer 20 to the carrier 100 using a lamination process. The specific operations are the same as the second step in Example 1.

[0085] The third step involves drilling holes using laser drilling or developing patterns using a developable encapsulating film to create external grounding third via slots 231 corresponding to the bottom position of each third partition dam, bottom interconnect second vias 22 corresponding to each flip chip position, external grounding third vias 23 corresponding to the bottom position of each vertical structure chip 102, and interconnect vias 24 corresponding to the bottom position of each vertical interconnect line's copper pillar. All third via slots 231, second vias 22, bottom interconnect vias 23, and interconnect vias 24 are through holes, with their bottom ends open and connected to the first layer of copper foil 41 of the carrier 100. Based on the characteristics of the flip chip process, the position and number of second via slots 221 are set according to the pin parameters of the flip chip 101.

[0086] The fourth step involves fabricating the bottom interconnect layer. Simultaneously, metal is filled into the third via slot 231, the second via 22, the bottom interconnect via 23, and the interconnect via 24. This prefabricates the third external grounding point 331 at the bottom of the third isolation dam 531, the second bottom pad 32 for the flip chip, the bottom pad 33 for the vertical structure chip, and the copper pillar bottom pad 34 for the vertical interconnect. All the third external grounding points 331, the second bottom pad 32, the bottom pad 33 for the vertical structure chip, and the copper pillar bottom pad 34 are electrically connected to the carrier's separation layer. Specifically, conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, and pattern transfer can be used to fabricate this bottom interconnect layer, grounding point, and pads.

[0087] In actual operation, since the bottom ends of all the third via slots 231, second vias 22, bottom interconnect vias 23 and interconnect vias 24 in the second step are open and connected to the first copper foil 41 of the carrier 100, and the separation layer 40 is a separable double copper foil, consisting of the first copper foil 41 away from the carrier and the second copper foil 42 close to the carrier; therefore, all the third external ground points 331, the second bottom pads 32, the vertical structure chip bottom pads 33 and the copper pillar bottom pads 34 are conductively connected to the first copper foil 41, forming an electrical bottom interconnect structure.

[0088] Step 5: Fabricate all the third isolation barriers 531 and the copper pillars 52 for the vertical interconnect lines. In actual operation, according to the design requirements, at the third external grounding point 331 at the bottom of the corresponding third isolation barrier, a wet pattern electroplating process is used to electroplat a copper metal ring around the electromagnetic shielding area, stacking it to the required height, thus prefabricating the third isolation barrier 531 that forms the third shielding structure. On the bottom pad 34 of the copper pillar at the corresponding vertical interconnect line copper pillar position, a wet pattern electroplating process is used to electroplat a copper metal single pillar around the electromagnetic shielding area, stacking it to the required height, thus prefabricating the copper pillar 52 that forms the vertical interconnect line. For example... Figure 12 As shown.

[0089] Next, in the sixth step, all chips are fixedly mounted in their designed positions.

[0090] Specifically, all flip chips 101 are mounted face down using methods such as silver paste, SMT soldering grounding, or DAF film (Die Attach Film), and the lead pads on the front of each flip chip 101 are directly and fixedly attached to the second bottom pad 32 of the underlying interconnect layer. All vertical structure chips 102 are directly and fixedly attached to the bottom pad 33 of the vertical structure chip using methods such as silver paste, SMT soldering grounding, or DAF film (Die Attach Film), thus enabling all chips to be electrically connected to external electrical circuits. For example... Figure 13 As shown.

[0091] Next, the interconnecting lines and the first top metal layer of the third shielding structure are fabricated layer by layer.

[0092] Step 7: First, perform molding, adding a second insulating layer 63 to encapsulate all flip chips 101, vertical structure chips 102, third isolation dam 531, and copper pillars 52 of vertical interconnect lines. Specifically, resin-based molding materials are used during molding, employing vacuum pressing or molding processes to form the second insulating layer 63 that acts as the molding layer.

[0093] Step 8, drilling; using laser drilling, drill the third through-hole groove 631 at the top of all the third partition dams 531, all the interlayer interconnection through-holes 632, and the interconnection through-holes 633 at the top of all the copper pillars 52 of the vertical interconnection lines on the second layer of insulating medium 63.

[0094] In the ninth step, conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, and pattern transfer are used to fabricate the third vertical interconnect layer 73. Simultaneously, metal is filled into the third via slots 631 at the top of all third partition dams 531, the interlayer interconnect vias 632, and the interconnect vias 633 at the top of all vertical interconnect copper pillars 52. This forms the third inner connection segment 731, which is used for interconnection between the top of the third partition dam 531 and the third shield structure. Metal is also filled into all interlayer interconnect vias 632 and the interconnect vias 633 at the top of all vertical interconnect copper pillars 52, so that both ends of each third vertical interconnect layer 73 are conductively connected to the vertical structure chip 102 and the copper pillar 52, respectively. In other words, each vertical structure chip 102 is conductively connected to the corresponding copper pillar 52 through both ends of the third vertical interconnect layer 73. This achieves that both the upper and lower poles of each vertical structure chip 102 are connected to the bottom layer.

[0095] Step 10: Add a third layer of insulating medium 83 and drill holes.

[0096] In actual operation, a third insulating medium 83 is added on top of the carrier using a pressing process. The material of the third insulating medium 83 can be a plastic sealing film or a prepreg, etc.

[0097] And a third inner layer conductive slot 831 is drilled on the third insulating medium 83 at the position corresponding to the third partition dam 531 at the top of the partition dam using laser drilling technology.

[0098] In the eleventh step, a second metal layer is added to form the third top metal layer 230 of the third shielding structure; at the same time, metal is filled into the borehole so that the third top metal layer 230 of the third shielding structure is connected to the third partition dam 531.

[0099] In actual operation, conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, and pattern transfer are used to fabricate the third top metal layer 230 of the shielding metal cover, and to metallize and fill the conductive slots 831 in the third inner layer, so that the third top metal layer 230 of the third shielding cover structure is connected and conductive to the third partition dam 531. Figure 14 As shown. The third top metal layer 230 of the third shielding metal cover can also be selectively patterned by electroplating and etching, flexibly achieving selective area shielding.

[0100] After the third top metal layer 230 of the third shielding metal cover is manufactured, a third outer plastic sealing layer 203 can be laminated on top of the third top metal layer 230 according to design requirements. For example... Figure 15 As shown.

[0101] Next, separate the carrier, remove the separation layer, and fabricate the outer circuit layer and outer pads.

[0102] Step 12: Separate the carrier 100 by removing the separation layer, and then fabricate the outer circuit layer and outer pads. In actual operation, because the separation layer 40 is a separable double-layer copper foil, consisting of a first copper foil 41 away from the carrier and a second copper foil 42 in close contact with the carrier, when separating the carrier 100, the second copper foil 42 in close contact with the carrier 100 is removed simultaneously, while the first copper foil 41 away from the carrier is retained. When fabricating the outer circuit layer and outer pads, the third outer circuit layer and outer pads 413 are fabricated directly through the first copper foil 41 away from the carrier using a pattern etching process. Figure 16 As shown Finally, in the thirteenth step, the product is cut to obtain several individually packaged finished products.

[0103] Example 4: Figures 17-21As shown. Following the steps of the shielding structure manufacturing method in the board-level plastic encapsulation process for chips 102, where all chips are vertical structures, according to the first technical solution described above, a shielding metal cover needs to be set to cover a portion of the chip area to achieve electromagnetic shielding. Selective pattern transfer plating and etching can flexibly achieve selective area shielding.

[0104] The operation steps of Example 4 are the same as those of Example 1, except that the parameters are adjusted according to the different parameters of the selective shielding area. Specifically, in the first step, the position and size parameters of the fourth top metal layer 240 of the fourth shielding cover structure, as well as the position and height parameters of the fourth partition dam 541, need to be preset according to the design requirements and the location specifications of the area requiring electromagnetic shielding. In Example 4, the area where electromagnetic shielding needs to be achieved covers the area where the vertical structure chip 102 is located. Therefore, the shielding structure of Example 4 sets the position and size parameters of the fourth partition dam 541 of the fourth shielding cover structure to surround the chip area that needs electromagnetic shielding, with the fourth partition dam 541 set around the corresponding vertical structure chip 102.

[0105] The second step is exactly the same as the second step in Example 1.

[0106] In the third step, laser drilling or developing a pattern of a developable encapsulating film is used to drill out the external grounding fourth via slot 241 corresponding to the bottom position of each fourth partition dam, the bottom interconnect via 23 corresponding to the position of each vertical structure chip 102, and the interconnect via 24 corresponding to the bottom position of the copper pillar of each vertical interconnect line; all fourth via slots 241, bottom interconnect vias 23, and interconnect vias 24 are through holes, and their bottom ends are open and connected to the first layer of copper foil 41 of the carrier 100. Figure 17 As shown.

[0107] The fourth step involves fabricating the bottom interconnect layer. Simultaneously, metal is filled into the fourth via slot 241, bottom interconnect via 23, and interconnect via 24 to prefabricate the fourth external grounding point 341, the bottom pad 33 of the vertical structure chip, and the copper pillar bottom pad 34 of the vertical interconnect. All fourth external grounding points 341, bottom pads 33, and copper pillar bottom pads 34 are also electrically connected to the first copper foil 41 in the carrier's separation layer. Specifically, conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, and pattern transfer can be used to fabricate this bottom interconnect layer, grounding points, and pads. Figure 17 As shown.

[0108] The fifth step involves using a wet patterned electroplating process to electroplat a copper metal ring around the electromagnetic shielding area, stacking it to a height that meets design requirements. This prefabricates the copper pillars 52 that form all the fourth partition dams 541 and the vertical interconnection lines. For example... Figure 17 As shown.

[0109] Step 6: Securely mount all vertical structure chips 102 to their designed positions. For example... Figure 18 As shown.

[0110] Step 7: Encapsulate the second layer of insulating medium 64, encapsulating all vertical structure chips 102, the fourth partition dam 541, and the copper pillars 52 of the vertical interconnect lines.

[0111] Step 8, drilling; using laser drilling, drill the fourth through-hole groove 641 at the top of all the fourth partition dams 541, all the interlayer interconnection through-holes 642, and the interconnection through-holes 643 at the top of all the copper pillars 52 of the vertical interconnection lines on the second layer of insulating medium 64.

[0112] Step 9: Using conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, pattern transfer, etc., fabricate the fourth vertical interconnect layer 74; at the same time, fill the third via slot 641 at the top of all the fourth partition dams 541, the interlayer interconnect via 642, and the interconnect via 643 at the top of all the copper pillars 52 of the vertical interconnect with metal.

[0113] Step 10: Add a third layer of insulating medium 84 and drill a groove 841.

[0114] Step 11: Add a second metal layer to form the fourth top metal layer 240 of the fourth shielding structure; thus, the fourth top metal layer 240 of the fourth shielding structure is connected and conductive to the fourth partition dam 541. For example... Figure 19 As shown.

[0115] After the fourth top metal layer 240 of the fourth shielding metal cover is manufactured, a fourth outer plastic sealing layer 204 can be laminated on top of the fourth top metal layer 240 according to design requirements. For example... Figure 20 As shown.

[0116] Step 12: Separate the carrier 100, simultaneously remove the second copper foil 42 that is in close contact with the carrier 100 in the separation layer, retaining the first copper foil 41 that is far from the carrier, and use a pattern etching process to fabricate the fourth outer circuit layer and outer pad 414 through the first copper foil 41 that is far from the carrier. Figure 21 As shown Finally, in the thirteenth step, the product is cut to obtain several individually packaged finished products.

[0117] Example 5: Figures 22-26As shown. Following the steps of the shielding structure manufacturing method in the board-level plastic encapsulation process for all chips (101) using the first technical solution described above, a shielding metal cover needs to be set to cover a portion of the chip area to achieve electromagnetic shielding. Selective pattern transfer plating and etching can flexibly achieve selective area shielding.

[0118] The operation steps of Example 5 are the same as those of Example 1, except that the parameters are adjusted according to the different parameters of the selective shielding area. Specifically, in the first step, the position and size parameters of the fifth top metal layer 250 of the fifth shielding cover structure, as well as the position and height parameters of the fifth partition dam 551, need to be preset according to the design requirements and the location specifications of the area requiring electromagnetic shielding. In Example 5, the area where electromagnetic shielding needs to be achieved covers the area where the flip chip 101 is located. Therefore, the shielding structure of Example 5 sets the position and size parameters of the fifth partition dam 551 of the fifth shielding cover structure to surround the chip area that needs electromagnetic shielding, with the fifth partition dam 551 set around the corresponding flip chip 101.

[0119] The second step is exactly the same as the second step in Example 1.

[0120] In the third step, laser drilling or developing a pattern of a developable plastic sealant film is used to drill out the external grounding fifth via slot 251 corresponding to the bottom position of each fifth partition dam and the bottom interconnect second via 22 corresponding to the position of each flip chip 101.

[0121] The fourth step is to fabricate the bottom interconnect layer, and at the same time fill the fifth via slot 251 and the second via 22 with metal to prefabricate the second bottom pad 32 of the flip chip and the fifth external ground point 351 at the bottom of the fifth isolation dam 551.

[0122] The fifth step involves using a wet patterned electroplating process to electroplat and stack copper metal around the electromagnetic shielding area to a height that meets design requirements, prefabricating all the fifth partition dams 551. For example... Figure 22 As shown.

[0123] Step 6: Securely mount all flip chips 101 to their designed locations. For example... Figure 23 As shown.

[0124] Step 7: Plastic encapsulate the second layer of insulating medium 65, encapsulating all flip chips 101 and the fifth partition dam 551.

[0125] Step 8: Drilling; using laser drilling, drill the fifth through-hole grooves 651 on the top of all the fifth partition dams 551 using the second insulating medium 65. Step 9: Using conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, pattern transfer, etc., fill the fifth through-hole grooves 651 on the top of all the fifth partition dams 551 with metal, prefabricating the fifth inner connection section 751 for interconnecting and conducting between the top of the fifth partition dam 551 and the fifth top metal layer of the fifth shield structure. Step 10: Add a third layer of insulating medium 85 and drill a groove 851.

[0126] Step 11: Add a second metal layer to form the fourth top metal layer 250 of the fifth shielding structure; thus connecting the fifth top metal layer 250 of the fifth shielding structure to the fifth partition dam 551. Figure 24 As shown.

[0127] After the fifth top metal layer 250 of the fifth shielding metal cover is manufactured, a fifth outer plastic sealing layer 205 can be laminated on top of the fifth top metal layer 250 according to design requirements. For example... Figure 25 As shown.

[0128] Step 12: Separate the carrier 100, and simultaneously remove the second copper foil 42 that is in close contact with the carrier 100 in the separation layer, retaining the first copper foil 41 that is away from the carrier. The fifth outer circuit layer and outer pad 415 are fabricated using a pattern etching process on the first copper foil 41 that is away from the carrier. (Example...) Figure 26 As shown Finally, in the thirteenth step, the product is cut to obtain several individually packaged finished products.

[0129] This invention provides a method for manufacturing an electromagnetic shielding structure for vertical structure chips and flip-chip board-level plastic encapsulation. According to design requirements, the method first fabricates the bottom interconnect layer, bottom pads, and the bottom grounding point of the shielding structure's isolation dam. Then, it fabricates the isolation dam and copper pillars for vertical interconnection. After fixing and mounting the plastic-encapsulated chip, it sequentially fabricates the top metal layer of the vertical interconnect and shielding structure. When separating the carrier, a layer of copper foil is retained for fabricating the outer circuit layer and outer pads. Finally, the chip is cut to obtain a single packaged product. This method reduces space occupation, simplifies the process, improves space utilization, reduces cost, and ensures product stability and reliability. It is compatible with existing board-level molding and packaging equipment, and can directly fabricate the top metal layer, partition barriers, vertical interconnect copper pillars, interconnect layers, pads, and grounding points using existing wet substrate processes such as laser drilling, copper plating, electroplating, and pattern transfer. This eliminates the need for complex processes like laser deep grooving and silver paste filling, avoiding the risk of adhesive cracking after curing due to subsequent process stress. This significantly shortens the production cycle and reduces operating and material costs. The layered drilling and metal filling process for pads, partition barriers, and grounding points avoids excessively large aspect ratios from laser grooving, resulting in good process stability and excellent performance. Furthermore, it is highly adaptable, capable of accommodating various structures with different packaging requirements, and has a wide range of applications.

[0130] Specifically, it achieves the following advantages: 1. High capacity and low cost: It matches existing board-level plastic packaging equipment and utilizes wet substrate processes such as laser drilling, copper plating, electroplating, and pattern transfer, eliminating laser grooving and silver paste filling processes, significantly improving the production cycle and reducing operating and material costs; 2. High reliability: It uses electroplated copper dams instead of silver paste filling, shortening the production cycle and stabilizing the yield, avoiding shielding and grounding abnormalities caused by large voids in the filling, glue cracking, poor silver paste contact or aging, etc. The integrated copper metal shielding cover has higher reliability; 3. High applicability: The structural design is more flexible for different packaging requirements and has a wide range of applications.

[0131] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Under the concept of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the present invention as described above. For the sake of brevity, they are not provided in detail. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing an electromagnetic shielding structure for vertical chip and flip chip board-level plastic encapsulation, characterized in that: The following steps are included: Obtain all chip and interconnect design parameters, and preset the shielding structure graphic parameters; Create the bottom interconnect layer, bottom pads, and external grounding point at the bottom of the isolation dam; Fabricate the partition dam and the copper pillars for vertical interconnection of the chips; Securely mount all chips to the designed locations; The top metal layer of the vertical interconnect lines and shielding structure is fabricated layer by layer. Separate the carrier, remove the separation layer, and fabricate the outer circuit layer and outer pads; Cut to obtain single-packaged finished products.

2. The method for manufacturing an electromagnetic shielding structure for vertical chip and flip-chip board-level plastic encapsulation according to claim 1, characterized in that: The process of obtaining all chip and interconnect design parameters and preset shielding structure graphic parameters includes the following operations: Set the design location of all chips, interconnect parameters of each layer, copper pillar parameters of vertical interconnects, and location specifications of areas requiring electromagnetic shielding according to design requirements and chip parameters; The location and dimensions of the top metal layer of the shielding structure are preset, as are the location and height of the partition dam.

3. The method for manufacturing an electromagnetic shielding structure for vertical chip and flip-chip board-level plastic encapsulation according to claim 1, characterized in that: The copper pillars of the isolation dam and the vertical interconnection line are at the same height.

4. The method for manufacturing an electromagnetic shielding structure for vertical chip and flip-chip board-level plastic encapsulation according to claim 1, characterized in that: The fabrication of the bottom interconnect layer, bottom pads, and external grounding point at the bottom of the isolation dam includes the following operations: Add a first layer of insulating medium to the carrier; Drilling holes to form the bottom interconnect vias of the chip and the external grounding vias at the bottom of the isolation dam; Fabricate the bottom interconnect layer, and fill the drilled holes with metal to form the bottom pads of the copper pillars of the chip and the vertical interconnect, as well as the external grounding point at the bottom of the partition dam. Both the bottom pad and the external grounding point at the bottom of the partition dam are electrically connected to the separation layer of the carrier.

5. The method for manufacturing an electromagnetic shielding structure for vertical chip and flip-chip board-level plastic encapsulation according to claim 1, characterized in that: The process of fixing and mounting all chips to the designed location includes the following operations: All chips are fixedly mounted on the bottom interconnect layer.

6. The method for manufacturing an electromagnetic shielding structure for vertical chip and flip-chip board-level plastic encapsulation according to claim 5, characterized in that: If the chip includes flip chips, the flip chips are fixedly mounted one by one onto the bottom pads of the bottom interconnect layer with the front pads facing down.

7. The method for manufacturing an electromagnetic shielding structure for vertical chip and flip-chip board-level plastic encapsulation according to claim 1, characterized in that: The process of sequentially fabricating the interconnection layer and the top metal layer of the shielding structure includes the following operations: Add a second layer of insulating medium to encapsulate all chips, embed all the partition barriers and copper pillars for vertical interconnection of all chips; drilling; A first metal layer is added to create the vertical interconnect lines of the chip. At the same time, metal is filled into the drilled holes to form a conductive connection structure between the top metal layer of the partition dam and the shield structure. Add a third layer of insulating medium, drill a hole; A second metal layer is added to form the top metal layer of the shielding structure; at the same time, metal is filled into the drilled hole so that the top metal layer of the shielding structure is connected and conductive to the partition dam.

8. The method for manufacturing an electromagnetic shielding structure for vertical chip and flip-chip board-level plastic encapsulation according to claim 7, characterized in that: It also includes the following operations: An outer plastic seal layer is also laminated onto the top metal layer of the shielding structure.

9. The method for manufacturing an electromagnetic shielding structure for vertical chip and flip-chip board-level plastic encapsulation according to claim 1, characterized in that: The separation carrier, removal of the separation layer, and fabrication of the outer circuit layer and outer pads include the following operations: Separate the carrier, remove the first copper foil layer that is in close contact with the carrier in the separation layer, and retain the second copper foil layer that is far away from the carrier; The outer circuit layer and outer pads are fabricated using a second layer of copper foil.

10. The method for manufacturing an electromagnetic shielding structure for vertical chip and flip-chip board-level plastic encapsulation according to claim 1, characterized in that: Separation layers are provided on both sides of the carrier, and board-level plastic encapsulation is performed simultaneously on both sides of the carrier plate.

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