A packaging method of a high power density SiC power module

Abstract

The application discloses a packaging method of a high-power-density SiC power module, and relates to the field of semiconductor processing.The packaging method of the high-power-density SiC power module provides key components such as a power chip, a first substrate, a second substrate, a plurality of conductive columns and a heat dissipation shell, and realizes the assembly and packaging of the module through specific process steps.The packaging method of the high-power-density SiC power module constructs a three-dimensional power circuit with low parasitic inductance, overcomes the defects of large area and high parasitic parameters of a traditional planar bonding line packaging circuit, simultaneously expands a heat dissipation path, reduces the thermal resistance of the module, enhances insulation and protection, and overall synergistically reduces the parasitic inductance, improves heat dissipation and improves structural compactness in a single process framework, thereby providing a reliable packaging solution for the high-power-density and high-performance SiC power module.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processing technology, specifically to a packaging method for a high power density SiC power module. Background Technology

[0002] Silicon carbide (SiC) power modules, thanks to the excellent properties of the material itself, have become key components of next-generation high-efficiency, high-frequency power electronic systems. Currently, most mainstream commercial SiC power modules inherit and adopt mature planar packaging technology designed for silicon-based IGBTs. This technology typically uses a direct-bonded copper (DBC) substrate as the carrier, soldering the power chip to the substrate surface, and using metal bonding wires (such as aluminum or copper wires) to achieve electrical interconnection between the chip's surface electrodes and the substrate or other conductive parts. Heat is typically conducted downwards through the DBC substrate at the bottom of the chip to a heat sink. This architecture, after long-term development, has advantages such as mature technology and relatively controllable cost.

[0003] However, with the rapid increase in the switching speed of SiC devices and their use in high-temperature operating scenarios, the traditional packaging mode based on bonding wires and planar layout has problems in use. First, the power loop path of the planar layout is long and the surrounding area is large. Combined with the parasitic inductance introduced by the bonding wires themselves, the overall parasitic inductance parameter of the module is high. In high-frequency and high-speed switching, it is easy to cause voltage overshoot and electromagnetic oscillation, which not only increases switching losses but also limits the optimal switching frequency of SiC devices. At the same time, the thermal resistance of the single-sided heat dissipation path is large, and the heat dissipation capability and long-term reliability of the module are unstable. This makes it impossible to fully utilize the performance of SiC chips in high-temperature scenarios. Moreover, the two-dimensional extended layout occupies a lot of substrate area, which is not conducive to further improving the power density of the module and makes it difficult to meet the increasingly stringent requirements for system miniaturization and lightweighting. In order to address the shortcomings of the existing technology, this invention provides a packaging method for high power density SiC power modules to solve the above problems. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a packaging method for high-power-density SiC power modules. By employing conductive pillars to achieve vertical interconnection between a first and second substrate, and cooperating with conductive clamps, a three-dimensional power loop with low parasitic inductance is constructed. This effectively overcomes the drawbacks of traditional planar bonded wire packaging, such as large loop area and high parasitic parameters. Furthermore, this method configures a heat dissipation shell to form a double-sided heat dissipation structure through thermal contact with the outer sides of both the first and second substrates, expanding the heat dissipation path and reducing the module's thermal resistance. Through a step-by-step process, this method achieves potting and filling of the module's internal space, enhancing insulation and protection. Overall, within a single process framework, it synergistically reduces parasitic inductance, improves heat dissipation, and enhances structural compactness, thus providing a reliable packaging solution for achieving high-power-density, high-performance SiC power modules.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a packaging method for a high power density SiC power module, the method comprising the following steps:

[0006] Step S1: Provide a power chip, a first substrate, a second substrate, multiple conductive pillars, and a heat dissipation shell;

[0007] Step S2: A high thermal conductivity connection layer is formed on the first substrate, and the power chip is fixed to the first substrate through the high thermal conductivity connection layer;

[0008] Step S3: Use a conductive clamp to electrically connect the upper surface electrode of the power chip to the second substrate;

[0009] Step S4: Vertically interconnect the second substrate and the first substrate through the plurality of conductive pillars to construct a three-dimensional power circuit;

[0010] Step S5: Configure the heat dissipation shell to make thermal contact with the outer sides of the first substrate and the second substrate respectively, so as to form a double-sided heat dissipation structure;

[0011] Step S6: Fill the internal space formed by the first substrate, the second substrate, the heat dissipation shell and the power chip with potting compound.

[0012] Preferably, in step S1, both the first substrate and the second substrate are direct-bonded copper substrates; the power chip is a SiC chip.

[0013] Preferably, in step S2, the high thermal conductivity bonding layer is a nano-silver sintered layer; the step of forming the nano-silver sintered layer and fixing the power chip to the first substrate includes:

[0014] Nano-silver paste is coated at predetermined locations on the first substrate;

[0015] The back electrode of the power chip is aligned and placed on the nano silver paste;

[0016] Sintering is carried out under preset temperature and pressure conditions to form mechanical connections and electrical conduction.

[0017] Preferably, in step S3, the conductive clamp is a pre-formed copper clip; the step of making an electrical connection using the copper clip includes:

[0018] Align one end of the copper clip with the upper surface electrode of the power chip and press or weld it;

[0019] Align and solder the other end of the copper clip with the corresponding pad on the lower surface of the second substrate.

[0020] Preferably, in step S4, the plurality of conductive pillars are arranged in an array in a predetermined interconnection area between the first substrate and the second substrate; the step of performing vertical interconnection includes:

[0021] The two ends of the conductive pillar are fixedly connected to the corresponding through holes or pads on the first substrate and the second substrate by welding or sintering to form a vertical current path.

[0022] The arrangement, quantity, and cross-sectional dimensions of the conductive pillars are optimized based on the parasitic inductance, current capacity, and heat dissipation requirements of the three-dimensional power circuit, so that the total parasitic inductance of the module is less than 1nH.

[0023] Preferably, in step S5, the step of forming the double-sided heat dissipation structure includes:

[0024] Thermally conductive interface material is coated on the side of the first substrate away from the power chip and the side of the second substrate away from the copper clip, respectively.

[0025] The lower half of the heat dissipation shell is tightly bonded to the first substrate through the thermally conductive interface material, and the upper half of the heat dissipation shell is tightly bonded to the second substrate through the thermally conductive interface material.

[0026] The upper and lower heat dissipation shells are locked in place by mechanical fasteners to ensure stable thermal contact.

[0027] Preferably, before step S6, a step of integrating a signal adapter board is further included:

[0028] Provides a signal adapter board that integrates drive circuitry and sensing circuitry;

[0029] The signal adapter board is mounted on the side region of the first substrate or the second substrate;

[0030] The control signal output terminal of the signal adapter board is connected to the control electrode of the power chip using a short-wire connection.

[0031] Preferably, the signal adapter board includes a temperature sensor and / or a current sensor; the sensing circuit is configured as follows:

[0032] The temperature sensor's sensing point is placed close to the packaging area of ​​the power chip.

[0033] The detection terminal of the current sensor is connected in series in the power circuit of the power chip, and the temperature sensor and the current sensor are used to monitor and control the module's operating status in real time.

[0034] Preferably, in step S6, the potting compound is a high-temperature silicone potting compound or epoxy resin; after filling the potting compound, a stepped temperature curing process is performed, with a peak curing temperature of not less than 150°C, to enhance the long-term stability and insulation strength of the material at high temperatures.

[0035] Preferably, in step S4, the material of the conductive pillar is copper or copper alloy; the diameter of the conductive pillar ranges from 0.5 mm to 2.0 mm, and the height ranges from 1.0 mm to 4.0 mm; the arrangement of the conductive pillar is configured based on electromagnetic field simulation and thermal simulation to minimize the inductance of the power loop and homogenize the heat flow path.

[0036] The technical effects and advantages of this invention are as follows:

[0037] 1. This high-power-density SiC power module packaging method utilizes conductive pillars to achieve vertical interconnection between the first and second substrates, and in conjunction with conductive fixtures, constructs a three-dimensional power loop with low parasitic inductance. This overcomes the shortcomings of traditional planar bonded wire packaging, which suffers from large loop area and high parasitic parameters. Furthermore, the method employs a heat dissipation shell that makes thermal contact with the outer surfaces of both the first and second substrates, forming a double-sided heat dissipation structure. This expands the heat dissipation path and reduces the module's thermal resistance. The method achieves potting and filling of the module's internal space through a step-by-step process, enhancing insulation and protection. Overall, within a single process framework, it synergistically reduces parasitic inductance, improves heat dissipation, and enhances structural compactness, thus providing a reliable packaging solution for achieving high-power-density, high-performance SiC power modules.

[0038] 2. The packaging method for this high power density SiC power module uses a nano-silver sintered layer as a high thermal conductivity connection layer to fix the power chip, and uses pre-formed copper clips as conductive fixtures for electrical connection on the upper surface. This method completely abandons the traditional bonding wire process, which not only significantly reduces the parasitic inductance and resistance of the interconnection part and improves the electrical performance, but also utilizes the high thermal conductivity of the nano-silver sintered layer and the excellent thermal conductivity of the copper clips, combined with the double-sided heat dissipation structure, to greatly enhance the heat dissipation efficiency and high-temperature reliability of the module, and solves the bottleneck problems of temperature resistance and heat dissipation capacity of traditional packaging materials.

[0039] 3. The packaging method of this high power density SiC power module integrates a signal adapter board for driving and sensing circuits during the packaging process and uses a short-wire connection to mount it close to the power chip. This design minimizes parasitic parameters such as common source inductance in the gate circuit, which is beneficial to improving the switching speed and dynamic stability of the SiC chip. It also enables real-time and local monitoring and control of the module's operating status, thereby improving the module's intelligent protection level and operational reliability. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the method flow of the present invention;

[0042] Figure 2 This is a schematic diagram of the core architecture of the SiC power module of the present invention;

[0043] Figure 3 This is a schematic diagram illustrating the formation of the nano-silver sintered layer in this invention;

[0044] Figure 4 This is a schematic diagram of the double-sided heat dissipation structure configuration of the present invention;

[0045] Figure 5 This is a schematic diagram of the sensing circuit configuration of the present invention;

[0046] Figure 6 This is a schematic diagram of the SiC power module structure of the present invention.

[0047] In the diagram: 1. Power chip; 2. First substrate; 21. High thermal conductivity connection layer; 3. Second substrate; 4. Conductive pillar; 5. Heat dissipation shell; 6. Copper clip; 7. Signal adapter board. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] This embodiment discloses a packaging method for a high power density SiC power module, according to the appendix. Figure 1 To be continued Figure 6 As shown, this packaging method employs a three-dimensional vertical interconnect and double-sided heat dissipation integrated structure. The aim is to reduce parasitic inductance in the power circuit, improve heat dissipation, increase power density, and enhance the reliability of the module under high temperature and high frequency conditions. It includes the following components and process steps:

[0050] It provides key components such as power chip 1, first substrate 2, second substrate 3, multiple conductive pillars 4 and heat dissipation shell 5, and realizes the assembly and packaging of the module through specific process steps.

[0051] Furthermore, the power chip 1 is preferably a silicon carbide (SiC) chip, which has the potential for high voltage resistance, high frequency switching and high temperature operation. The first substrate 2 and the second substrate 3 are both direct-bonded copper (DBC) substrates. Both the first substrate 2 and the second substrate 3 include a ceramic insulating layer and copper layers on both sides, which are used for electrical insulation, mechanical support and heat conduction, respectively. The ceramic layer can be made of alumina, aluminum nitride or silicon nitride to meet different insulation and heat conduction requirements.

[0052] Specifically disclosed, in step S2, a high thermal conductivity connection layer 21 is formed at a predetermined position on the first substrate 2, i.e., the lower DBC substrate. The high thermal conductivity connection layer 21 is preferably a nano-silver sintered layer. The specific formation process includes: firstly, uniformly coating a layer of nano-silver paste onto the copper surface of the first substrate 2 by screen printing or dispensing; then, precisely aligning and placing the back electrode of the SiC chip, usually the drain or collector, onto the paste; finally, sintering is performed under a certain temperature and pressure under a nitrogen atmosphere. Typical process parameters are: temperature 200℃–250℃, pressure 3–10MPa, and holding time 10–30 minutes. The nano-silver layer formed after sintering not only achieves mechanical fixation and electrical conduction between the chip and the substrate, but also has excellent thermal conductivity, reducing interfacial thermal resistance.

[0053] It is particularly important to emphasize that in step S3, a conductive clamp is used to achieve the electrical connection between the upper surface electrode of the chip and the second substrate 3. The conductive clamp is a pre-formed copper clip 6. The shape of the copper clip 6 can be optimized according to the chip electrode layout and current path, such as using a U-shaped, L-shaped or multi-branch structure. During connection, one end of the copper clip 6 is first reliably connected to the upper surface electrode of the chip by ultrasonic welding, thermocompression welding or low-temperature solder welding. Then, the other end of the copper clip 6 is welded to the corresponding copper pad on the lower surface of the second substrate 3, i.e., the upper DBC substrate. This copper clip 6 replaces the traditional aluminum bonding wire, which not only has a stronger current carrying capacity, but also significantly reduces the connection inductance and resistance due to its flat and short path characteristics.

[0054] Furthermore, in step S4, a vertical interconnection between the first substrate 2 and the second substrate 3 is achieved through multiple conductive pillars 4, thereby constructing a three-dimensional power loop. The conductive pillars 4 are preferably made of copper or copper alloy, with a diameter generally ranging from 0.5 mm to 2.0 mm and a height ranging from 1.0 mm to 4.0 mm. The conductive pillars 4 are arranged in an array around the substrate or on the critical current path. The specific position, number, and cross-sectional dimensions of the conductive pillars 4 need to be optimized based on electromagnetic field simulation and thermal simulation to ensure that the power loop inductance is minimized, the current distribution is uniform, and the heat flow path is reasonably distributed. During interconnection, the two ends of the conductive pillars 4 are fixed to the corresponding metallized vias or pads on the first substrate 2 and the second substrate 3 by reflow soldering, sintering, or laser soldering. This design allows the current to flow from the first substrate 2, with part flowing directly to the second substrate 3 through the conductive pillars 4, and the other part flowing into the second substrate 3 through the chip and then through the copper clip 6, and finally flowing back to the output end of the first substrate 2 through the conductive pillars 4, forming a three-dimensional loop and reducing the parasitic inductance to below 1 nH.

[0055] Specifically disclosed, in step S5, a heat dissipation shell 5 is configured to form a double-sided heat dissipation structure. The heat dissipation shell 5 is usually made of aluminum or copper, and its surface can be processed into fins, microchannels, or vapor chamber structures to enhance heat dissipation. Before assembly, a thermal interface material needs to be applied to the back side of the first substrate 2 away from the chip and the back side of the second substrate 3 away from the copper clip 6. The thermal interface material can be such as thermal grease, thermal pad, or phase change material. Then, the lower half of the heat dissipation shell 5 is tightly attached to the first substrate 2, and the upper half is tightly attached to the second substrate 3. They are then locked by mechanical fastening methods such as screws, clips, or welding to ensure that the interface thermal resistance is minimized. This double-sided heat dissipation design allows the chip heat to be transferred in both upward and downward directions at the same time. The overall thermal resistance of the module is reduced by about 40% compared with the traditional single-sided heat dissipation, improving the continuous current capability and power density.

[0056] It is particularly important to emphasize that before filling the potting compound in step S6, a signal adapter board 7 should be integrated as needed. The signal adapter board 7 integrates a gate drive circuit, a temperature sensor, and a current sensor. The preferred mounting position of the signal adapter board 7 is in the side area of ​​the first substrate 2 or the second substrate 3, connecting to the chip control electrode via the shortest path. The signal adapter board 7 is connected to the chip via a flexible circuit board or metal wires. This design can minimize the common source inductance and parasitic capacitance in the control loop, and improve the switching speed and stability. At the same time, the temperature sensor's sensing point should be close to the chip packaging area, and the current sensor can be connected in series in the power loop to realize real-time monitoring of the operating status and overheat and overcurrent protection.

[0057] Furthermore, in step S6, a high-temperature potting compound is filled into the internal space of the module. The potting compound can be a high-temperature silicone gel or epoxy resin material. The potting compound has high insulation strength, high thermal conductivity and good high-temperature stability. Vacuum potting process can be used during filling to ensure that there are no air bubbles inside. After filling, a stepped temperature curing process is performed. For example, pre-curing at 80℃ for 1 hour, then curing at 120℃ for 2 hours, and finally post-curing at 150℃–180℃ for 1–2 hours. This process can enhance the mechanical strength and insulation performance of the potting compound at high temperature, ensuring that no partial discharge or insulation degradation occurs inside the module during long-term high-temperature operation.

[0058] Example 1: This example uses a 1200V / 100A half-bridge SiC power module as an example, combined with the attached... Figure 1 To be continued Figure 4 The packaging process is explained in detail below, and the workflow is as follows:

[0059] Materials required: Two aluminum nitride DBC substrates, namely the first substrate 2 and the second substrate 3, with a size of 30mm×20mm; two SiC chips with a chip size of 5mm×5mm; four copper conductive pillars 4 with a diameter of 1.0mm and a height of 2.0mm; pre-formed copper clips 6; nano silver paste; aluminum heat sink shell 5; and high-temperature silicone potting compound.

[0060] Chip sintering: Nano silver paste is screen-printed in the central area of ​​the first substrate 2, the back electrode of the SiC chip is aligned and placed, and then sent into a sintering furnace. It is sintered at 220°C and 5MPa pressure for 20 minutes to form a nano silver sintered layer.

[0061] Copper clip 6 welding: Using a precision fixture, one end of the copper clip 6 is ultrasonically welded to the source pad on the upper surface of the chip, and the other end is reflow soldered to the corresponding copper layer on the lower surface of the second substrate 3 using SnAgCu solder.

[0062] Interconnection of conductive posts 4: At the four corners, conductive posts 4 are inserted into the corresponding through holes of the first substrate 2 and the second substrate 3, and vacuum reflow soldering is used to achieve simultaneous welding at 250°C to form a vertical conductive path.

[0063] Assembly of heat dissipation shell 5: Thermally conductive phase change material is coated on the back of the first substrate 2 and the second substrate 3. The upper and lower heat dissipation shells 5 are aligned and attached, and then tightened with four stainless steel screws to the specified torque.

[0064] Signal adapter board 7 integration: A ceramic adapter board integrating a driver IC and an NTC temperature sensor is bonded to the side of the first substrate 2 with silver paste and connected to the chip gate and Kelvin source with aluminum wire bonding.

[0065] Encapsulation and curing: Place the module in a vacuum chamber, inject silicone potting compound, evacuate to ≤100Pa and maintain for 10 minutes, then cure according to the step curing curves of 80℃ for 1h, 120℃ for 2h and 150℃ for 1.5h.

[0066] Testing and Verification: Electrical tests were conducted after packaging. The parasitic inductance of the power circuit was measured to be 0.8nH, the thermal resistance to be 0.25K / W, and the power density of the module reached 4.5kW / in³, which is about 2.3 times higher than that of traditional planar packaging.

[0067] Example 2: This example uses a full-bridge SiC power module integrating current detection and temperature protection as an example, combined with the attached... Figure 1 Appendix Figure 5 With appendix Figure 6 The workflow is explained in detail below:

[0068] Structural layout: Four SiC chips are arranged on the first substrate 2 to form a full-bridge topology. Each chip is fixed by sintering with nano-silver. The second substrate 3 is designed as a multi-layer copper structure containing positive and negative buses and AC output terminals. It is connected to the corresponding nodes of the first substrate 2 through multiple conductive pillars 4.

[0069] 3D interconnection optimization: Based on electromagnetic simulation software, the layout of conductive pillar 4 is optimized. The 12 conductive pillars 4 are arranged at key nodes for current inflow and outflow, so that the conductive pillars 4 form a symmetrical three-dimensional loop. The simulation shows that the loop inductance is only 0.7nH.

[0070] Double-sided heat dissipation enhancement: The heat dissipation shell 5 adopts a copper-based heat dissipation plate structure, which is filled with working fluid. During assembly, a graphite thermal pad is inserted between the upper and lower base plates and the shell. After locking, the thermal interface contact pressure reaches more than 1MPa.

[0071] The intelligent signal adapter board integrates: In addition to the drive circuit, the adapter board also integrates a Hall current sensor and a digital temperature sensor. The current sensor is connected in series on the DC bus, and the temperature sensor is mounted on the substrate near the chip. The adapter board communicates with the external controller through a board-to-board connector.

[0072] Working process: After the module is powered on, the drive signal is sent through the adapter board and controls the switching of each SiC chip through an extremely short path. The current is input from the first substrate 2, flows through the three-dimensional path formed by the conductive pillar 4 and the chip, and is finally output from the second substrate 3. The heat generated by the chip is transferred to the upper and lower heat dissipation shells 5 at the same time. The heat dissipation shells 5 are connected to an external air cooling or liquid cooling system.

[0073] Protection mechanism: The adapter board collects the bus current and chip temperature in real time. When overcurrent or overtemperature is detected, the drive signal is immediately shut off and the fault is reported, achieving accurate real-time protection.

[0074] Reliability verification: After packaging, the module passed 1,000 thermal cycle tests without any connection failures; after continuous operation at 150℃ for 1,000 hours, the electrical parameter drift was <5%, demonstrating excellent long-term reliability.

[0075] Through the above implementation methods, this packaging method fully discloses a complete process flow and structural design for a SiC power module with high power density, low parasitic inductance, efficient heat dissipation, and high reliability, which can meet the needs of high-end power electronics applications such as electric vehicles and renewable energy converters.

[0076] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A packaging method for a high power density SiC power module, characterized in that, The method includes the following steps: Step S1: Provide a power chip (1), a first substrate (2), a second substrate (3), multiple conductive pillars (4), and a heat dissipation shell (5); Step S2: A high thermal conductivity connection layer (21) is formed on the first substrate (2), and the power chip (1) is fixed to the first substrate (2) through the high thermal conductivity connection layer (21). Step S3: Use a conductive clamp to electrically connect the upper surface electrode of the power chip (1) to the second substrate (3); Step S4: Vertically interconnect the second substrate (3) and the first substrate (2) through the plurality of conductive pillars (4) to construct a three-dimensional power circuit; Step S5: Configure the heat dissipation shell (5) to make thermal contact with the outer sides of the first substrate (2) and the second substrate (3) respectively, so as to form a double-sided heat dissipation structure; Step S6: Fill the internal space formed by the first substrate (2), the second substrate (3), the heat dissipation shell (5), and the power chip (1) with potting compound. Prior to step S6, the process also includes the step of integrating a signal adapter board (7): A signal adapter board (7) integrating drive circuitry and sensing circuitry is provided. The signal adapter board (7) is mounted on the side region of the first substrate (2) or the second substrate (3); The control signal output terminal of the signal adapter board (7) is connected to the control electrode of the power chip (1) using a short-wire connection method. The signal adapter board (7) includes a temperature sensor and / or a current sensor; the sensing circuit is configured as follows: Place the temperature sensing point of the temperature sensor close to the packaging area of ​​the power chip (1); The detection terminal of the current sensor is connected in series in the power circuit of the power chip (1), and the working status of the module is monitored and controlled in real time by the temperature sensor and the current sensor.

2. The packaging method for a high power density SiC power module according to claim 1, characterized in that, In step S1, the first substrate (2) and the second substrate (3) are both direct-bonded copper substrates; the power chip (1) is a SiC chip.

3. The packaging method for a high power density SiC power module according to claim 2, characterized in that, In step S2, the high thermal conductivity bonding layer (21) is a nano-silver sintered layer; the step of forming the nano-silver sintered layer and fixing the power chip (1) to the first substrate (2) includes: Nano silver paste is coated at a predetermined position on the first substrate (2); The back electrode of the power chip (1) is aligned and placed on the nano silver paste; Sintering is carried out under preset temperature and pressure conditions to form mechanical connections and electrical conduction.

4. The packaging method for a high power density SiC power module according to claim 3, characterized in that, In step S3, the conductive clamp is a pre-formed copper clip (6); the step of making an electrical connection using the copper clip (6) includes: Align one end of the copper clip (6) with the upper surface electrode of the power chip (1) and press or weld it; Align and solder the other end of the copper clip (6) with the corresponding pad on the lower surface of the second substrate (3).

5. The packaging method for a high power density SiC power module according to claim 4, characterized in that, In step S4, the plurality of conductive pillars (4) are arranged in an array in the predetermined interconnection area between the first substrate (2) and the second substrate (3); The steps for performing a vertical interconnect include: The two ends of the conductive post (4) are fixedly connected to the corresponding through holes or pads on the first substrate (2) and the second substrate (3) by welding or sintering to form a vertical current path; The arrangement, quantity, and cross-sectional dimensions of the conductive pillars (4) are optimized based on the parasitic inductance, current capacity, and heat dissipation requirements of the three-dimensional power circuit, so that the total parasitic inductance of the module is less than 1nH.

6. The packaging method for a high power density SiC power module according to claim 5, characterized in that, In step S5, the step of forming the double-sided heat dissipation structure includes: Thermal interface materials are coated on the side of the first substrate (2) away from the power chip (1) and the side of the second substrate (3) away from the copper clip (6), respectively. The lower half of the heat dissipation shell (5) is tightly bonded to the first substrate (2) through the thermal interface material, and the upper half of the heat dissipation shell (5) is tightly bonded to the second substrate (3) through the thermal interface material. The upper and lower heat dissipation shells (5) are locked together by mechanical fasteners.

7. The packaging method for a high power density SiC power module according to claim 1, characterized in that, In step S6, the potting compound is a high-temperature silicone potting compound or epoxy resin; after filling the potting compound, a stepped temperature curing process is performed.

8. The packaging method for a high power density SiC power module according to claim 1, characterized in that, In step S4, the material of the conductive pillar (4) is copper or copper alloy; the diameter of the conductive pillar (4) ranges from 0.5 mm to 2.0 mm, and the height ranges from 1.0 mm to 4.0 mm; the arrangement of the conductive pillar (4) is configured based on electromagnetic field simulation and thermal simulation.

Images