Display device

Abstract

An embodiment of the present invention discloses a display device including: data lines connected to pixels arranged in a display area and extending in a first direction; a shield line disposed over the data line in the display area, extending in the first direction, and overlapping the data line in a plan view; and a first voltage line connected to the pixel, extending in a second direction perpendicular to the first direction, disposed below the data line, and overlapping the data line in a plan view.

Description

Technical Field

[0001] One or more embodiments relate to pixels and display devices including pixels. Background Technology

[0002] Display devices have been used for a variety of purposes. Furthermore, as display devices have become thinner and lighter, their applications have become more widespread.

[0003] Because display devices are used in a variety of ways, various methods can be used to design the shape of display devices, and furthermore, more and more functions can be combined with or associated with display devices. Summary of the Invention

[0004] Technical issues

[0005] One or more embodiments include a display device with improved display quality. However, these problems are merely examples, and the scope of this disclosure is not limited thereto.

[0006] Solution to the problem

[0007] According to one or more embodiments, a display device includes: a data line connected to a pixel disposed in a display area, the data line extending in a first direction; a shielding line disposed above the data line in the display area, extending in the first direction and overlapping the data line in a plan view; and a first voltage line connected to the pixel, extending in a second direction perpendicular to the first direction, disposed below the data line and overlapping the data line in a plan view.

[0008] In an embodiment, a pixel may include: a first capacitor including a first electrode and a second electrode disposed on the first electrode and overlapping the first electrode in a plan view; a first transistor connected to a first voltage line and the second electrode of the first capacitor; and a second transistor connected to a data line and the gate electrode of the first transistor, wherein the data line may be arranged in the same layer as the second electrode of the first capacitor, and the semiconductor layer of the first transistor may be arranged in the same layer as the first electrode of the first capacitor.

[0009] In one embodiment, the voltage supplied to the shielding wire and the voltage supplied to the first electrode of the first capacitor may be different from each other.

[0010] In one embodiment, the voltage supplied to the shielding wire and the voltage supplied to the first electrode of the first capacitor can be the same as each other.

[0011] In an embodiment, the first capacitor may further include a third electrode disposed below the first electrode, overlapping the first electrode in a plan view, and connected to the second electrode.

[0012] In one embodiment, the first voltage line may be arranged in the same layer as the third electrode of the first capacitor and may be connected to the first electrode of the first capacitor.

[0013] In an embodiment, the display device may further include a vertical conductive line disposed in the same layer as the shielding line, overlapping the second electrode of the first capacitor in a plan view, and extending in a first direction.

[0014] In one embodiment, the vertical conductive line can be configured to supply a constant voltage to the pixel and can be connected to a horizontal conductive line extending in a second direction.

[0015] In one embodiment, the horizontal conductive line may include a first voltage line.

[0016] In an embodiment, the pixel may further include a second electrode connected to a first capacitor and a second capacitor for a light-emitting element, wherein the light-emitting element may include a first electrode connected to a first transistor and a second electrode facing the first electrode, and the second capacitor may be connected to the second electrode of the light-emitting element.

[0017] In an embodiment, the display device may further include a second voltage line extending in a second direction and connected to the first electrode of the first capacitor.

[0018] In an embodiment, the display device may further include a vertical conductive line disposed in the same layer as the shielding line, overlapping with the first electrode of the first capacitor in a plan view, and extending in a first direction.

[0019] In one embodiment, the vertical conductive line can be configured to supply a constant voltage to the pixel and can be connected to a horizontal conductive line extending in a second direction.

[0020] In one embodiment, the horizontal conductive line may include a second voltage line.

[0021] In an embodiment, the display device may further include a voltage supply line disposed in a non-display area outside the display area, connected to the shielding line, and configured to supply shielding voltage to the shielding line.

[0022] According to one or more embodiments, a display device includes: a first pixel circuit disposed in a first circuit region; and a second pixel circuit disposed in a second circuit region adjacent to the first circuit region in a first direction, wherein each of the first pixel circuit and the second pixel circuit is connected to a light-emitting diode, and each of the first pixel circuit and the second pixel circuit includes: a data line extending in a second direction perpendicular to the first direction; a shielding line disposed above the data line, extending in the second direction and overlapping the data line in a plan view; a first voltage line extending in the first direction, disposed below the data line and partially overlapping the data line in a plan view; a capacitor including a first electrode and a second electrode disposed above the first electrode and overlapping the first electrode in a plan view; a first transistor connected to the first voltage line and the second electrode of the capacitor; a second transistor connected to the data line and the gate electrode of the first transistor; a third transistor connected to the gate electrode of the first transistor and the second voltage line extending in the first direction; a fourth transistor connected to the first electrode of the light-emitting diode and the third voltage line extending in the first direction; and a conductive line disposed in the same layer as the shielding line, overlapping the second electrode of the capacitor in a plan view and extending in the second direction. The light-emitting diode connected to the first pixel circuit emits light of a first color, and the light-emitting diode connected to the second pixel circuit emits light of a second color. The conductive line of the first pixel circuit is connected to one of the first voltage line, the second voltage line, the third voltage line, and the fourth voltage line connected to the second electrode of the light-emitting diode. The conductive line of the second pixel circuit is connected to one of the second voltage line, the third voltage line, and the fourth voltage line, excluding the first voltage line.

[0023] In an embodiment, the voltage supplied to the shielding wire and the voltage supplied to the first electrode of the capacitor may be different from each other.

[0024] In an embodiment, the voltage supplied to the shielding wire and the voltage supplied to the first electrode of the capacitor can be the same as each other.

[0025] In an embodiment, the capacitor may further include a third electrode disposed below the first electrode, overlapping the first electrode in a plan view, and connected to the second electrode.

[0026] In one embodiment, the first voltage line may be arranged in the same layer as the third electrode of the capacitor and may be connected to the first electrode of the capacitor.

[0027] In one embodiment, the second voltage line may be arranged in the same layer as the third electrode of the capacitor and may be connected to the first electrode of the capacitor.

[0028] Beneficial effects of the present invention

[0029] According to embodiments, a display device with improved display quality can be provided. However, the scope of this disclosure is not limited to these effects. Attached Figure Description

[0030] Figure 1a , Figure 1b and Figure 2 This is a schematic diagram illustrating a display device according to an embodiment.

[0031] Figure 3 This is an equivalent circuit diagram of the pixels according to the embodiment.

[0032] Figures 4a to 4c This is a schematic diagram illustrating the shielding of the data line according to an embodiment.

[0033] Figures 5a to 5d This is a schematic diagram illustrating the shielding wires according to an embodiment.

[0034] Figure 6 It is shown schematically. Figure 3 The diagram shows the layout of the positions of the transistors and capacitors of the pixels.

[0035] Figures 7 to 16 It is shown schematically layer by layer. Figure 3 The layout diagram of the pixel components.

[0036] Figure 17 It is along Figure 6 A cross-sectional view of pixels intercepted by line I-I'.

[0037] Figure 18 It is along Figure 6 A cross-sectional view of the pixels captured by line II-II'.

[0038] Figure 19 This is a diagram showing the arrangement of data lines and signal lines according to a comparison example.

[0039] Figure 20 This is a schematic diagram illustrating the arrangement of vertical conductive lines according to an embodiment.

[0040] Figure 21 An example of a cross-section of the second pixel according to an embodiment is shown.

[0041] Figures 22 to 26 The equivalent circuit of a pixel according to an embodiment is shown.

[0042] Figures 27 to 32 This is an equivalent circuit diagram of the pixels according to the embodiment.

[0043] Figure 33 This is an equivalent circuit diagram of the pixels according to the embodiment.

[0044] Figure 34 It is shown schematically. Figure 33 The diagram shows the layout of the positions of the transistors and capacitors of the pixels.

[0045] Figures 35 to 41 It is shown schematically layer by layer. Figure 33 The layout diagram of the pixel components.

[0046] Figure 42 It is along Figure 34 A cross-sectional view of the pixels intercepted by line III-III'.

[0047] Figure 43 This is a diagram showing the arrangement of data lines and signal lines according to a comparison example.

[0048] Figures 44 to 49 The equivalent circuit of a pixel according to an embodiment is shown.

[0049] Figures 50a to 51b This is a cross-sectional view showing the structure of a display element according to an embodiment.

[0050] Figure 52 This is a cross-sectional view showing the structure of the pixels of a display device according to an embodiment. Detailed Implementation

[0051] According to one or more embodiments, a display device includes: a data line connected to a pixel disposed in a display area, the data line extending in a first direction; a shielding line disposed above the data line in the display area, extending in the first direction and overlapping the data line in a plan view; and a first voltage line connected to the pixel, extending in a second direction perpendicular to the first direction, disposed below the data line and overlapping the data line in a plan view.

[0052] The method of the present invention

[0053] This disclosure may include various embodiments and modifications, and specific embodiments of this disclosure are shown in the accompanying drawings and will be described in detail herein. The effects and features of this disclosure and its implementation methods will become apparent from the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below and may be embodied in various ways.

[0054] It will be understood that although terms such as “first” and “second” may be used in this document to describe various elements, these elements should not be limited by these terms, and these terms are only used to distinguish one element from another.

[0055] As used herein, the singular forms “a” and “the (said)” are intended to include the plural forms as well, unless the context explicitly indicates otherwise.

[0056] Furthermore, it will be understood that the terms “comprising,” “including,” “containing,” and “having” as used herein indicate the presence of the stated feature or element, but do not exclude the presence or addition of one or more other features or elements.

[0057] As used herein, "A and / or B" means A, B, or A and B. Furthermore, "at least one of A and B" means A, B, or A and B.

[0058] In the following embodiments, when X and Y are connected to each other, X and Y can be functionally connected, electrically connected, or physically connected. Furthermore, when X and Y are connected to each other, X and Y can be directly connected or indirectly connected, with one or more other elements between X and Y. Here, X and Y can be elements (e.g., devices, apparatuses, circuits, lines, electrodes, terminals, films, layers, or regions). For example, when X and Y are electrically connected to each other, X and Y can be directly electrically connected or indirectly electrically connected, with one or more other elements between X and Y. When X and Y are indirectly electrically connected, one or more devices (e.g., switches, transistors, capacitors, inductors, resistors, or diodes) that enable the electrical connection between X and Y can be connected between X and Y. Therefore, this disclosure is not limited to specific connection relationships (e.g., those indicated in the drawings or detailed description) and may also include any relationships other than those indicated in the drawings or detailed description.

[0059] In the following embodiments, "on" in conjunction with device states can refer to the active state of the device, and "off" can refer to the deactivated state of the device. "On" in conjunction with signals received by the device can refer to signals that activate the device, and "off" can refer to signals that deactivate the device. The device can be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) can be activated by a low-level voltage, and an N-channel transistor (N-type transistor) can be activated by a high-level voltage. Therefore, it should be understood that the "on" voltages of P-type and N-type transistors have opposite (low to high) voltage levels.

[0060] Furthermore, in this paper, the x, y, and z directions are not limited to directions along the three axes of a Cartesian coordinate system, and can be interpreted in a broader sense. For example, the x, y, and z directions can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0061] The display device according to the embodiments can be a device for displaying moving or still images, and can be used as a display screen for various products such as televisions, laptop computers, monitors, billboards, and Internet of Things (“IoT”) devices and portable electronic devices (e.g., mobile phones, smartphones, tablet PCs (“PCs”), mobile communication terminals, e-notebooks, e-readers, portable multimedia players (“PMPs”), navigation devices, and ultra-mobile PCs (“UMPCs”). Furthermore, the display device according to the embodiments can be used in wearable devices such as smartwatches, watch phones, glasses-type displays, and head-mounted displays (“HMDs”). Additionally, the display device according to the embodiments can be used as a central information display (“CID”) arranged on the dashboard or center console or instrument panel of a vehicle, an interior mirror display replacing the side mirrors of a vehicle, or a display arranged behind the front seats of a vehicle as an entertainment system for the rear seats. Furthermore, the display device can be a flexible device.

[0062] Figure 1a , Figure 1b and Figure 2 This is a schematic diagram illustrating a display device according to an embodiment.

[0063] refer to Figure 1a and Figure 1b The display device 10 may include a display area DA for displaying an image and a peripheral area PA outside the display area DA. The display area DA may be completely surrounded by the peripheral area PA.

[0064] In a plan view, the display area DA can be rectangular. In other embodiments, the display area DA can be polygonal (e.g., triangular, pentagonal, or hexagonal), circular, elliptical, or irregular in shape. The corners of the edges of the display area DA can be curved. In embodiments, such as... Figure 1a As shown, the display device 10 may include a display area DA having a shape in which the length in the x-direction is greater than the length in the y-direction. In another embodiment, as... Figure 1b As shown, the display device 10 may include a display area DA having a shape in which the length in the y direction is greater than the length in the x direction.

[0065] refer to Figure 2 The display device 1 according to the embodiment may include a pixel area 11, a gate driving circuit 13, a data driving circuit 15, a power supply circuit 17, and a controller 19.

[0066] Pixel area 11 can be provided in display area DA. Various conductive lines for transmitting electrical signals to be applied to display area DA, external circuitry electrically connected to pixel circuitry, and / or pads to which printed circuit boards or driver IC chips are attached can be located in peripheral area PA. For example, gate drive circuitry 13, data drive circuitry 15, power supply circuitry 17, and controller 19 can be provided in peripheral area PA.

[0067] like Figure 2 As shown, multiple gate lines GL, multiple data lines DL, and multiple pixels PX connected to them can be arranged in the display area DA. The multiple pixels PX can be arranged in various forms, such as stripe arrangement, pentile arrangement, diamond arrangement, and mosaic arrangement, to realize an image. Each pixel PX can include an organic light-emitting diode (OLED) as a display element (referred to as a "light-emitting element"), and the OLED can be connected to the pixel circuitry. The pixel PX can emit light from the OLED, such as red, green, blue, or white light. Each pixel PX can be connected to at least one corresponding gate line among the multiple gate lines GL and a corresponding data line among the multiple data lines DL.

[0068] Each of the gate lines GL can extend in the x-direction (row direction) to connect to a pixel PX located in the same row. The gate line GL can be configured to transmit a gate signal to the pixel PX in the same row. Each of the data lines DL can extend in the y-direction (column direction) to connect to a pixel PX located in the same column. Each of the data lines DL can be configured to transmit a data signal DATA to each pixel PX in the same column in synchronization with the gate signal.

[0069] In one embodiment, the peripheral region PA can be a non-display area in which no pixels PX are arranged. In another embodiment, a plurality of pixels PX can be arranged in at least one corner of the peripheral region PA to overlap with the gate drive circuit 13 in a plan view. Accordingly, dead zones can be reduced and the display area DA can be expanded.

[0070] The gate drive circuit 13 can be connected to multiple gate lines GL, can generate gate signals in response to a drive control signal GCS from the controller 19, and can sequentially supply the gate signals to the gate lines GL. The gate lines GL can be connected to the gates of transistors included in the pixel PX. The gate signal GS can be a gate control signal used to control the on and off states of transistors whose gates are connected to the gate lines GL. The gate signal GS can be a signal including a gate on voltage that can turn on the transistor and a gate off voltage that can turn off the transistor. In an embodiment, the gate on voltage can be a high-level voltage (first-level voltage) or a low-level voltage (second-level voltage).

[0071] Figure 1a, Figure 1b and Figure 2 The diagram shows a pixel PX connected to a gate line GL; however, this is merely an example, and the pixel PX can be connected to two or more gate lines, and the gate drive circuit 13 can supply two or more gate signals with different timings to the two or more gate lines when an on-state voltage is applied.

[0072] The data driving circuit 15 can be connected to multiple data lines DL and can supply data signals DATA to the data lines DL in response to the drive control signal DCS from the controller 19. The data signal DATA supplied to the data lines DL can be supplied to the pixel PX of the supplied gate signal GS. The data driving circuit 15 can convert grayscale input image data from the controller 19 into a data signal DATA in the form of voltage or current.

[0073] Power supply circuit 17 can generate signals (voltage and current) for driving pixel PX in response to drive control signal PCS from controller 19. Power supply circuit 17 can generate a first driving voltage ELVDD and a second driving voltage ELVSS, and can supply the first driving voltage ELVDD and the second driving voltage ELVSS to pixel PX. The first driving voltage ELVDD can be a high-level voltage supplied to a first terminal of the driving transistor included in pixel PX that is connected to a first electrode (pixel electrode or anode) of the display element. The second driving voltage ELVSS can be a low-level voltage supplied to a second electrode (counter electrode or cathode) of the display element included in pixel PX. Power supply circuit 17 can generate a high-level high voltage VGH and a low-level low voltage VGL, and can supply the high-level high voltage VGH and the low-level low voltage VGL to gate drive circuit 13.

[0074] The controller 19 can generate drive control signals GCS, DCS, and PCS based on signals input from an external source, and can supply these signals to the gate drive circuit 13, the data drive circuit 15, and the power supply circuit 17. The drive control signal GCS output to the gate drive circuit 13 may include a gate start signal and multiple clock signals. The drive control signal DCS output to the data drive circuit 15 may include a source start signal and multiple clock signals.

[0075] The display device 10 may include a display panel, and the display panel may include a substrate. Pixels PX may be arranged in the display area DA of the substrate. Part or all of the gate driving circuit 13 may be formed directly in the peripheral area PA of the substrate in the process of forming the transistors constituting the pixel circuits in the display area DA of the substrate. Each of the data driving circuit 15, the power supply circuit 17, and the controller 19 may be formed as a separate integrated circuit chip or a single integrated circuit chip, and may be disposed on a flexible printed circuit board (“FPCB”) electrically connected to pads disposed on one side of the substrate. In other embodiments, the data driving circuit 15, the power supply circuit 17, and the controller 19 may be disposed directly on the substrate using a chip-on-glass (“COG”) or chip-on-plastic (“COP”) method.

[0076] Figure 3 This is an equivalent circuit diagram of the pixels according to the embodiment.

[0077] refer to Figure 3 A pixel PX may include a pixel circuit PC and an organic light-emitting diode (OLED) connected to the pixel circuit PC as a display element.

[0078] Pixel PX can be connected to a first gate line GWL configured to transmit a first gate signal GW, a second gate line GIL configured to transmit a second gate signal GI, a third gate line GRL configured to transmit a third gate signal GR, a fourth gate line EML configured to transmit a fourth gate signal EM, a fifth gate line EMBL configured to transmit a fifth gate signal EMB, and a data line DL configured to transmit a data signal DATA. Because the emission of pixel PX is controlled by the fourth gate signal EM and the fifth gate signal EMB, the fourth gate signal EM and the fifth gate signal EMB can be referred to as emission control signals, and the fourth gate line EML and the fifth gate line EMBL can be referred to as emission control lines. Furthermore, pixel PX can be connected to a drive voltage line PL configured to transmit a first drive voltage ELVDD, a reference voltage line VRL configured to transmit a reference voltage Vref, and an initialization voltage line VL configured to transmit an initialization voltage Vint.

[0079] In embodiments, the plurality of transistors included in the pixel circuit PC may be N-type oxide thin-film transistors. Oxide thin-film transistors may include a semiconductor layer comprising an amorphous or crystalline oxide semiconductor. The oxide semiconductor may include zinc oxide-based materials such as zinc oxide, indium zinc oxide, or gallium indium zinc oxide. In some embodiments, the oxide semiconductor may be an In-Ga-Zn-O (“IGZO”) semiconductor. In some embodiments, the oxide semiconductor may be an In-Sn-Ga-Zn-O (“ITGZO”) semiconductor. In embodiments, the oxide thin-film transistor may be a low-temperature polycrystalline oxide (“LTPO”) thin-film transistor. However, this is merely an example, and N-type transistors are not limited thereto. For example, the semiconductor layer included in an N-type transistor may include inorganic semiconductors (e.g., amorphous silicon or polycrystalline silicon) or organic semiconductors.

[0080] The pixel circuit PC may include first transistors T1 through T6, a first capacitor C1, and a second capacitor C2. First transistor T1 may be a drive transistor for outputting a drive current corresponding to the data signal DATA, and second transistors T2 through T6 may be switching transistors configured to transmit signals. The first terminal (first electrode) and second terminal (second electrode) of each of the first transistors T1 through T6 may be source or drain depending on the voltage between the first and second terminals. For example, depending on the voltage between the first and second terminals, the first terminal may be drain and the second terminal may be source, or vice versa. In the following, the node to which the first gate of the first transistor T1 is connected may be defined as first node N1, and the node to which the second terminal of the first transistor T1 is connected may be defined as second node N2.

[0081] The first transistor T1 can be connected to the driving voltage line PL and the organic light-emitting diode (OLED). The first transistor T1 can be connected between the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may include a gate, a first terminal, and a second terminal connected to the second node N2. The first transistor T1 can be a dual-gate transistor. The first transistor T1 may include a first gate connected to the first node N1. The first transistor T1 may further include a second gate connected to its second terminal. The first gate and the second gate of the first transistor T1 can be arranged on different layers facing each other. For example, the first gate and the second gate of the first transistor T1 can be positioned facing each other, with a semiconductor layer between the first gate and the second gate of the first transistor T1. Hereinafter, the gate (or gate electrode) of the first transistor T1 may refer to the first gate used to receive the data signal DATA as a gate signal.

[0082] The first gate of the first transistor T1 can be connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the first capacitor C1. The second gate of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first terminal of the first transistor T1 can be connected to the driving voltage line PL via the fifth transistor T5, and the second terminal of the first transistor T1 can be connected to the pixel electrode of the organic light-emitting diode (OLED) via the sixth transistor T6. The first terminal of the first transistor T1 can be connected to the second terminal of the fifth transistor T5. The second terminal of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first transistor T1 can receive the data signal DATA according to the switching operation of the second transistor T2, and can output a driving current corresponding to the data signal DATA.

[0083] The second transistor T2 can be connected to the data line DL and the first gate of the first transistor T1. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second terminal of the second transistor T2 can be connected to the first gate of the first transistor T1, the first terminal of the third transistor T3, and the first capacitor C1. The second transistor T2 can be turned on by a first gate signal GW received from the first gate line GWL to electrically connect the data line DL to the first node N1 and transmit the data signal DATA received through the data line DL to the first node N1.

[0084] A third transistor T3 can be connected to the first gate of the first transistor T1 and the reference voltage line VRL. The third transistor T3 may include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3 can be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first capacitor C1. The third transistor T3 can be turned on by a third gate signal GR received from the third gate line GRL to transmit the reference voltage Vref received through the reference voltage line VRL to the first node N1.

[0085] The fourth transistor T4 can be connected to the sixth transistor T6 and the initialization voltage line VL. The fourth transistor T4 can be connected between the organic light-emitting diode (OLED) and the initialization voltage line VL. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the third node N3, and a second terminal connected to the initialization voltage line VL. The first terminal of the fourth transistor T4 can be connected to the second terminal of the sixth transistor T6 and the pixel electrode of the OLED. The fourth transistor T4 can be turned on by a second gate signal GI received from the second gate line GIL to transmit the initialization voltage Vint received through the initialization voltage line VL to the third node N3.

[0086] The fifth transistor T5 can be connected to the drive voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate connected to the fourth gate line EML, a first terminal connected to the drive voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 can be turned on or off according to the fourth gate signal EM received from the fourth gate line EML.

[0087] The sixth transistor T6 can be connected to the first transistor T1 and the organic light-emitting diode (OLED). The sixth transistor T6 can be connected between the second node N2 and the third node N3. The sixth transistor T6 may include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first terminal of the sixth transistor T6 can be connected to the second terminal of the first transistor T1, the first capacitor C1, and the second capacitor C2. The second terminal of the sixth transistor T6 can be connected to the first terminal of the fourth transistor T4 and the pixel electrode of the OLED. The sixth transistor T6 can be turned on or off according to the fifth gate signal EMB received from the fifth gate line EMBL.

[0088] A first capacitor C1 can be connected between the first gate and the second terminal of the first transistor T1. The first electrode of the first capacitor C1 can be connected to the first node N1, and the second electrode of the first capacitor C1 can be connected to the second node N2. The first electrode of the first capacitor C1 can be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the first capacitor C1 can be connected to the second terminal and the second gate of the first transistor T1, the second electrode of the second capacitor C2, and the first terminal of the sixth transistor T6. The first capacitor C1 can be a storage capacitor, and can store the threshold voltage of the first transistor T1 and the voltage corresponding to the data signal DATA.

[0089] When the third transistor T3 and the fifth transistor T5 are turned on together, the first transistor T1 can be turned on. When the voltage at the second terminal of the first transistor T1 reaches the difference (Vref-Vth) between the reference voltage Vref and the threshold voltage (Vth) of the first transistor T1, the first transistor T1 can be turned off, and the voltage corresponding to the threshold voltage (Vth) of the first transistor T1 can be stored in the first capacitor C1, thus compensating for the threshold voltage (Vth) of the first transistor T1.

[0090] The second capacitor C2 can be connected between the drive voltage line PL and the second node N2. The first electrode of the second capacitor C2 can be connected to the drive voltage line PL. The second electrode of the second capacitor C2 can be connected to the second terminal and second gate of the first transistor T1, the second electrode of the first capacitor C1, and the first terminal of the sixth transistor T6. The second capacitor C2 can be configured to maintain the voltage stored in the first capacitor C1.

[0091] The capacitance of each of the first capacitor C1 and the second capacitor C2 can vary depending on the color of the light emitted by the pixel PX.

[0092] An organic light-emitting diode (OLED) can be connected to a first transistor T1 via a sixth transistor T6. The OLED may include a pixel electrode (anode) connected to a third node N3 and a counter electrode (cathode) facing the pixel electrode, and the counter electrode may receive a second driving voltage (common voltage) ELVSS. The counter electrode may be a common electrode shared by multiple pixels PX. Due to the conduction of the fifth transistor T5 and the sixth transistor T6, the driving current output from the first transistor T1 can flow through the OLED, and the OLED can emit light with a brightness corresponding to the driving current.

[0093] Figures 4a to 4c This is a schematic diagram illustrating the shielding of the data line according to an embodiment. Figures 5a to 5d This is a schematic diagram illustrating the shielding wires according to an embodiment.

[0094] In an embodiment, a shield line VEL overlapping the data line DL in a plan view can be provided above and / or below the data line DL. At least one insulating layer IL can be disposed between the data line DL and the shield line VEL. Accordingly, the effect of the coupling between the data line DL and at least one signal line caused by changes in the data signal DATA on the gate-source voltage change of the first transistor T1, which serves as the driving transistor, can be minimized.

[0095] In an embodiment, such as Figure 4aAs shown in the diagram, the shield line VEL, which overlaps with the data line DL in the plan view, can be positioned above the data line DL. In an embodiment, as... Figure 4b As shown in the diagram, the shield line VEL, which overlaps with the data line DL in the plan view, can be positioned below the data line DL. In an embodiment, as... Figure 4c As shown, the shield line VEL may include a first shield line VEL1 and a second shield line VEL2. The first shield line VEL1 may be disposed above the data line DL to overlap with the data line DL in the plan view, and the second shield line VEL2 may be disposed below the data line DL to overlap with the data line DL in the plan view.

[0096] like Figures 5a to 5d As shown, the shielding line VEL can extend in the y-direction within the display area DA of the substrate and can be a straight line with a stripe shape. In an embodiment, each shielding line VEL in each pixel column of the display area DA can be arranged to overlap with the data line DL in a planar view. In an embodiment, in some pixel columns of the display area DA, the shielding lines VEL can be arranged at specific intervals to overlap with the data line DL in a planar view. The shielding line VEL can be a conductive line that is not electrically connected to the pixel PX in the display area DA.

[0097] In the peripheral region PA of the substrate, the shielding line VEL can be electrically connected to the shielding voltage supply line PVEL arranged in the peripheral region PA to receive a shielding voltage VES, which is a constant voltage, from the shielding voltage supply line PVEL.

[0098] In an embodiment, such as Figure 5a As shown, the shielded voltage supply line PVEL can be arranged to extend in the x direction on the upper side of the display area DA, and can be electrically connected to one end of each of the multiple shielded lines VEL extending from the display area DA.

[0099] In an embodiment, such as Figure 5b As shown, the shielded voltage supply line PVEL can be arranged to extend in the x direction below the display area DA, and can be electrically connected to one end of each of the multiple shielded lines VEL extending from the display area DA.

[0100] In an embodiment, such as Figure 5c As shown, the shielded voltage supply line PVEL may include a first voltage supply line PVEL1 extending in the x-direction above the display area DA and a second voltage supply line PVEL2 extending in the x-direction below the display area DA. One end of each of the plurality of shielded lines VEL may be electrically connected to the first voltage supply line PVEL1, and the other end of each of the plurality of shielded lines VEL may be electrically connected to the second voltage supply line PVEL2.

[0101] In an embodiment, the shielding voltage VES supplied by the shielding voltage supply line PVEL can be a separate voltage that is different from the multiple voltages supplied to the pixel PX (e.g., the first driving voltage ELVDD, the reference voltage Vref, and the initialization voltage Vint).

[0102] In an embodiment, the shielding voltage VES supplied by the shielding voltage supply line PVEL can be one of several voltages supplied to the pixel PX (e.g., a first driving voltage ELVDD, a reference voltage Vref, and an initialization voltage Vint). The shielding line VEL may not be electrically connected to the driving voltage line PL, the reference voltage line VRL, and the initialization voltage line VL, which are arranged in the display area DA and electrically connected to the pixel PX. For example, as... Figure 5d As shown, the shield voltage supply line PVEL can be configured to supply a first driving voltage ELVDD to the shield line VEL, and the driving voltage supply line PPL can be configured to supply the first driving voltage ELVDD to the driving voltage line PL. The driving voltage line PL can be electrically connected to the pixel PX arranged in the display area DA. The shield line VEL can be arranged in the display area DA, but may not be electrically connected to the pixel PX arranged in the display area DA.

[0103] In an embodiment, the shield line VEL may receive one of a constant voltage (e.g., a high voltage VGH, a low voltage VGL, and a ground voltage) supplied to the peripheral circuitry (e.g., a gate drive circuit) that supplies electrical signals to the pixel PX.

[0104] Even when a change in the data signal DATA causes a change in the voltage of the shield line VEL due to the coupling of the capacitor formed between the data line DL and the shield line VEL, the voltage change at the terminals of other devices of the pixel PX can be prevented (minimized) because the shield line VEL is not electrically connected to the pixel PX.

[0105] Figure 6 It is shown schematically. Figure 3 The diagram shows the layout of the positions of the transistors and capacitors of the pixels. Figures 7 to 16 It is shown schematically layer by layer. Figure 3 The layout diagram of the pixel components. Figures 13 to 15 This is a schematic diagram illustrating the arrangement of vertical conductive lines according to an embodiment. Figure 17 It is along Figure 6 A cross-sectional view of pixels intercepted by line I-I'. Figure 18 It is along Figure 6 A cross-sectional view of the pixels captured by line II-II'. Figure 19 This is a diagram showing the arrangement of data lines and signal lines according to a comparison example. Figure 20 This is a schematic diagram illustrating the arrangement of vertical conductive lines according to an embodiment. Figure 21An example of a cross-section of the second pixel according to an embodiment is shown.

[0106] The plurality of pixels PX arranged in the display area DA may include a first pixel PX1 emitting light of a first color, a second pixel PX2 emitting light of a second color, and a third pixel PX3 emitting light of a third color. For example, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be arranged in a repeating pattern in the x and y directions according to a specific pattern. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include pixel circuitry and an organic light-emitting diode (OLED) electrically connected to the pixel circuitry as a display element.

[0107] The display area DA defined in the substrate 100 may include a plurality of circuit areas in which rows (pixel rows) and columns (pixel columns) intersect each other and pixel circuits are arranged. In an embodiment, a unit circuit area comprising two or more circuit areas adjacent to each other in the x-direction may be defined, and a unit pixel may be defined by pixels arranged in the circuit area constituting the unit circuit area. For example, a unit circuit area PCAu may include three circuit areas (i.e., a first circuit area PCA1, a second circuit area PCA2, and a third circuit area PCA3 adjacent in the x-direction), and a unit pixel may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first circuit area PCA1 may be the area in which the pixel circuit of the first pixel PX1 is arranged. The second circuit area PCA2 may be the area in which the pixel circuit of the second pixel PX2 is arranged. The third circuit area PCA3 may be the area in which the pixel circuit of the third pixel PX3 is arranged.

[0108] exist Figure 6 In the process, each pixel circuit in the pixel circuits arranged in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3 can be connected to... Figure 3 The pixel circuit PC corresponding to the pixel shown in the figure.

[0109] In this embodiment, by considering the light-emitting characteristics of the first pixel PX1, the second pixel PX2, and the third pixel PX3, different initialization voltages Vint can be supplied to the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, the pixel circuit PC of the first pixel PX1 can be connected to the first-1 initialization voltage line VL11, the pixel circuit PC of the second pixel PX2 can be connected to the first-2 initialization voltage line VL12, and the pixel circuit PC of the third pixel PX3 can be connected to the first-3 initialization voltage line VL13. The initialization voltage supplied to the first-1 initialization voltage line VL11, the initialization voltage supplied to the first-2 initialization voltage line VL12, and the initialization voltage supplied to the first-3 initialization voltage line VL13 can be different from each other.

[0110] The same components can be arranged in each layer of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. In the following description, for ease of illustration, reference numerals will be assigned to the components of the pixel circuit PC arranged in the first circuit region PCA1, and the first circuit region PCA1 will be described primarily; this can also be applied to the same components in the second circuit region PCA2 and the third circuit region PCA3. Referring together below... Figures 7 to 18 A description is provided. In the following text, the connecting electrode can be an electrode used to transmit signals by electrically connecting conductive lines and electrodes (conductive patterns) arranged in different layers.

[0111] The first conductive layer can be disposed on the substrate 100. For example... Figure 7 As shown, the first conductive layer may include conductive lines 200, a first electrode 210, a lower first gate line GWLb, a reference voltage line VRL, first-second initialization voltage lines VL12, first-third initialization voltage lines VL13, and a repair line RL. In an embodiment, a barrier layer may be further disposed between the substrate 100 and the first conductive layer.

[0112] The first electrode 210 may be island-shaped and may be arranged in each of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The first electrode 210 may include the second gate electrode G12 of the first transistor T1 and the lower second electrode C12b of the first capacitor C1 (see [reference]). Figure 18 ) and the lower first electrode C21b of the second capacitor C2 (see Figure 18 ).

[0113] Conductive line 200 may extend in the x-direction and may be arranged across the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. Conductive line 200 may be a drive voltage line PL to which a first drive voltage ELVDD is applied. In the following, conductive line 200 and drive voltage line PL may be used interchangeably. Conductive line 200 may include a main line 200m extending in the x-direction in each circuit region and a protrusion 200p protruding from the main line 200m in the +y direction.

[0114] The first gate line GWLb, the reference voltage line VRL, the first-second initialization voltage line VL12 and the first-third initialization voltage line VL13 can extend in the x direction and can be arranged across the first circuit region PCA1, the second circuit region PCA2 and the third circuit region PCA3.

[0115] The repair line RL can extend in the x direction and can be arranged across the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3.

[0116] The first insulating layer 101 can be disposed on the substrate 100 to cover the first conductive layer, and as follows: Figure 8 As shown, a semiconductor layer ACT, including an oxide semiconductor, may be disposed on the first insulating layer 101. The semiconductor layer ACT may include a first semiconductor layer ACT1, a second semiconductor layer ACT2, a third semiconductor layer ACT3, and a fourth semiconductor layer ACT4. The semiconductor layer ACT may include a source region, a drain region, and a channel region between the source and drain regions in each of the first transistor T1 to the sixth transistor T6. In some cases, the source or drain region may be interpreted as the source electrode or drain electrode of the transistor.

[0117] Figure 11 This is a diagram showing the transistors and capacitors in the first circuit region PCA1. (Reference) Figure 11 The first semiconductor layer ACT1 may include the source region S1 and drain region D1 of the first transistor T1 and the source region S5 and drain region D5 of the fifth transistor T5. The second semiconductor layer ACT2 may include the source region S2 and drain region D2 of the second transistor T2 and the source region S3 and drain region D3 of the third transistor T3. The third semiconductor layer ACT3 may include the source region S4 and drain region D4 of the fourth transistor T4 and the source region S6 and drain region D6 of the sixth transistor T6. The fourth semiconductor layer ACT4 may include the second electrode C22 of the second capacitor C2 (see...). Figure 18 ).

[0118] The second insulating layer 102 can be disposed on the first insulating layer 101 to cover the semiconductor layer ACT, and the second conductive layer can be disposed on the second insulating layer 102. For example... Figure 9As shown, the second conductive layer may include a second electrode 220, a third electrode 230, an upper first gate line GWLt, a second gate line GIL, a third gate line GRL, a fourth gate line EML, a fifth gate line EMBL, and a first initialization voltage line VL11.

[0119] The second electrode 220 and the third electrode 230 can be provided in an island shape. The second electrode 220 and the third electrode 230 can be arranged in each of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. In the plan view, the opening GOP overlapping with the first electrode 210 can be defined in the second electrode 220.

[0120] The first gate line GWLt, the second gate line GIL, the third gate line GRL, the fourth gate line EML, the fifth gate line EMBL, and the first initialization voltage line VL11 can extend in the x direction and can be arranged across the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3.

[0121] The upper first gate line GWLt may substantially overlap with the lower first gate line GWLb in a plan view, and may include a recess HM corresponding to a portion of the lower first gate line GWLb. In an embodiment, the portion of the upper first gate line GWLt that passes through the third circuit region PCA3 may include a recess HM corresponding to a portion of the lower first gate line GWLb.

[0122] like Figure 11 As shown, the second conductive layer may include the gate electrodes G1 to G6 of the first transistor T1 to the sixth transistor T6. In the plan view, the gate electrodes G1 to G6 may overlap with the channel region of the semiconductor layer ACT.

[0123] refer to Figure 11 The second electrode 220 may include the first gate electrode G11 of the first transistor T1 and the first electrode C11 of the first capacitor C1 (see...). Figure 18 In the plan view, the first gate electrode G11 may overlap with the first semiconductor layer ACT1. The third electrode 230 may include the gate electrode G2 of the second transistor T2. In the plan view, the gate electrode G2 of the second transistor T2 may overlap with the second semiconductor layer ACT2. The gate electrode G3 of the third transistor T3 may be the portion of the third gate line GRL that overlaps with the second semiconductor layer ACT2 in the plan view. The gate electrode G4 of the fourth transistor T4 may be the portion of the second gate line GIL that overlaps with the third semiconductor layer ACT3 in the plan view. The gate electrode G5 of the fifth transistor T5 may be the portion of the fourth gate line EML that overlaps with the first semiconductor layer ACT1 in the plan view. The gate electrode G6 of the sixth transistor T6 may be the portion of the fifth gate line EML that overlaps with the third semiconductor layer ACT3 in the plan view.

[0124] The third insulating layer 103 can be disposed on top of the second insulating layer 102 to cover the second conductive layer, and the third conductive layer can be disposed on top of the third insulating layer 103. For example... Figure 10 As shown, the third conductive layer may include a data line DL and connecting electrodes 270, 271, 272, 273, 274, 275, 276, 277a, 277b and 277c.

[0125] Data lines DL can be arranged in each circuit area to extend in the y-direction. Data lines DL can be connected to the drain region D2 of the second transistor T2 via contact holes 43 passing through the second insulating layer 102 and the third insulating layer 103. In a plan view, data lines DL can overlap with conductive lines 200.

[0126] The connecting electrode 270 may include a first region 270a overlapping the first electrode 210 and the second electrode 220 in the plan view, and a second region 270b protruding from the first region 270a in the -y direction. The connecting electrode 270 can connect the source region S1 of the first transistor T1 to the second gate electrode G12 of the first transistor T1 and the drain region D6 of the sixth transistor T6.

[0127] The first region 270a of the connecting electrode 270 can be connected to the source region S1 of the first transistor T1 through a contact hole 42 passing through the second insulating layer 102 and the third insulating layer 103. The connecting electrode 270 may include a source electrode connected to the source region S1 of the first transistor T1 and an upper second electrode C12t of the first capacitor C1 (see...). Figure 18 ) and the upper first electrode C21t of the second capacitor C2 (see Figure 18 The first region 270a of the connecting electrode 270 can be connected to the first electrode 210 through a contact hole 41 passing through the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. The first electrode 210 can be the second gate electrode G12 of the first transistor T1. Since the connecting electrode 270 is connected to the first electrode 210, the second gate electrode G12 of the first transistor T1 can be connected to the source region S1 of the first transistor T1.

[0128] The second region 270b of the connecting electrode 270 can be connected to the drain region D6 of the sixth transistor T6 through the contact hole 50 passing through the second insulating layer 102 and the third insulating layer 103.

[0129] Connection electrode 271 can be connected to the gate electrode G2 of the second transistor T2 through contact hole 45 passing through the third insulating layer 103. Connection electrode 271 can be connected to the upper first gate line GWLt through contact hole 44 passing through the third insulating layer 103. Connection electrode 272, arranged in at least one of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3, can be connected to the lower first gate line GWLb through contact hole 58 passing through the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. Contact hole 58 can be positioned to correspond to the groove of the upper first gate line GWLt.

[0130] The connecting electrode 272 can be connected to the drain region D3 of the third transistor T3 through the contact hole 46 passing through the second insulating layer 102 and the third insulating layer 103, and can be connected to the reference voltage line VRL through the contact hole 47 passing through the first insulating layer 101, the second insulating layer 102 and the third insulating layer 103.

[0131] The connecting electrode 273 can be connected to the source region S2 of the second transistor T2 and the source region S3 of the third transistor T3 through contact holes 48 passing through the second insulating layer 102 and the third insulating layer 103. The connecting electrode 273 can be connected to the second electrode 220 through contact holes 49 passing through the third insulating layer 103 to connect to the first gate electrode G11 of the first transistor T1. The connecting electrode 273 can be... Figure 3 The node electrode corresponding to the first node N1. The connecting electrode 273 can be a bridge electrode that connects at least two transistors. For example, the connecting electrode 273 can be a bridge electrode that connects the first gate electrode G11 of the first transistor T1, the source region S2 of the second transistor T2, and the source region S3 of the third transistor T3.

[0132] The connecting electrode 274 can be connected to the conductive line 200 through contact holes 51 passing through the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. The connecting electrode 274 can be connected to the drain region D5 of the fifth transistor T5 through contact holes 52 passing through the second insulating layer 102 and the third insulating layer 103. Accordingly, the drain region D5 of the fifth transistor T5 can be connected to the conductive line 200.

[0133] The connecting electrode 275 can be connected to the fourth semiconductor layer ACT4 through contact holes 53 passing through the second insulating layer 102 and the third insulating layer 103. The connecting electrode 275 can be connected to the conductive line 200 through contact holes 54 passing through the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. Accordingly, the first driving voltage ELVDD can be supplied to the fourth semiconductor layer ACT4, which includes the second electrode C22 of the second capacitor C2.

[0134] The connecting electrode 276 can be connected to the source region S6 of the sixth transistor T6 and the drain region D4 of the fourth transistor T4 through contact holes 55 passing through the second insulating layer 102 and the third insulating layer 103. In a plan view, the connecting electrode 276 may overlap with a portion of the repair line RL. The connecting electrode 276 may be insulated from the repair line RL and may be connected to the repair line RL later in case of defects in the pixel circuitry arranged in the circuit area.

[0135] In the first circuit region PCA1, the connection electrode 277a can be connected to the source region S4 of the fourth transistor T4 through the contact hole 56 passing through the second insulating layer 102 and the third insulating layer 103. The connection electrode 277a can be connected to the first initialization voltage line VL11 through the contact hole 57a passing through the third insulating layer 103.

[0136] In the second circuit region PCA2, the connection electrode 277b can be connected to the source region S4 of the fourth transistor T4 through the contact hole 56 passing through the second insulating layer 102 and the third insulating layer 103. The connection electrode 277b can be connected to the first-second initialization voltage line VL12 through the contact hole 57b passing through the first insulating layer 101, the second insulating layer 102 and the third insulating layer 103.

[0137] In the third circuit region PCA3, the connection electrode 277c can be connected to the source region S4 of the fourth transistor T4 through the contact hole 56 passing through the second insulating layer 102 and the third insulating layer 103. The connection electrode 277c can be connected to the first-third initialization voltage line VL13 through the contact hole 57c passing through the first insulating layer 101, the second insulating layer 102 and the third insulating layer 103.

[0138] A fourth insulating layer 104 may be disposed on top of the third insulating layer 103 to cover the third conductive layer, and a fourth conductive layer may be disposed on top of the fourth insulating layer 104. For example... Figures 12 to 15 As shown, the fourth conductive layer may include multiple vertical conductive lines VVL and connecting electrodes 281 and 283.

[0139] The connecting electrode 281 can be connected to the connecting electrode 270 through the contact hole 61 passing through the fourth insulating layer 104. The connecting electrode 281 can be arranged to cover and overlap the connecting electrode 273, which is a node electrode, in a plan view. The first electrode 210 can be disposed below the connecting electrode 273, and the connecting electrode 281 can be disposed above the connecting electrode 273. The connecting electrode 281 can substantially completely cover the connecting electrode 273, and the first electrode 210 can substantially completely cover the connecting electrode 273. The connecting electrode 281 can serve as an upper shielding layer for the connecting electrode 273, and the first electrode 210 can serve as a lower shielding layer for the connecting electrode 273.

[0140] The connecting electrode 283 can be connected to the connecting electrode 276 through the contact hole 62 through the fourth insulating layer 104 to connect to the source region S6 of the sixth transistor T6.

[0141] refer to Figure 13 The vertical conductive line VVL may include a shield line VEL, a first vertical conductive line VVL1 arranged in the first circuit region PCA1, a second vertical conductive line VVL2 arranged in the second circuit region PCA2, and a third vertical conductive line VVL3 arranged in the third circuit region PCA3.

[0142] In each of the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3, the shield line VEL may overlap with the data line DL in the plan view. Figure 4a The shielding line VEL shown corresponds to this. The shielding line VEL may not be connected to pixels PX in each of the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3. For example... Figures 5a to 5d As shown, the shielding line VEL can be connected to the shielding voltage supply line PVEL arranged in the peripheral area PA to receive a shielding voltage VES, which is a constant voltage, from the shielding voltage supply line PVEL.

[0143] In one embodiment, the shielding line VEL can receive a separate constant voltage from the shielding voltage supply line PVEL, which is different from the plurality of voltages (e.g., the first drive voltage ELVDD, the reference voltage Vref, and the initialization voltage Vint) supplied to the pixel PX. In another embodiment, the shielding line VEL can receive one of the plurality of voltages (e.g., the first drive voltage ELVDD, the reference voltage Vref, and the initialization voltage Vint) supplied to the pixel PX from the shielding voltage supply line PVEL. In yet another embodiment, the shielding line VEL can receive one of the constant voltages (e.g., the high voltage VGH, the low voltage VGL, and the ground voltage) supplied to the gate drive circuitry that supplies electrical signals to the pixel PX from the shielding voltage supply line PVEL.

[0144] The first vertical conductive line VVL1, the second vertical conductive line VVL2, and the third vertical conductive line VVL3 can be one of the following: the vertical drive voltage line PLv, the first vertical initialization voltage line VL11v, the second vertical initialization voltage line VL12v, the third vertical initialization voltage line VL13v, the vertical reference voltage line VRLv, and the vertical common voltage line EOL. Two of the first vertical conductive lines VVL1, the second vertical conductive line VVL2, and the third vertical conductive line VVL3 can be the same vertical conductive line VVL. The vertical drive voltage line PLv, the first vertical initialization voltage line VL11v, the second vertical initialization voltage line VL12v, the third vertical initialization voltage line VL13v, the vertical reference voltage line VRLv, and the vertical common voltage line EOL can be arranged alternately in the x-direction according to specific rules.

[0145] refer to Figure 14 and Figure 15 The vertical conductive line VVL can be electrically connected to the horizontal conductive line VHL extending in the x-direction. The horizontal conductive line VHL may include a drive voltage line PL (conductor line 200), a first-first initialization voltage line VL11, a first-second initialization voltage line VL12, a first-third initialization voltage line VL13, and a reference voltage line VRL. The drive voltage line PL can be electrically connected to the vertical drive voltage line PLv to have a grid structure in the display area DA. The first-first initialization voltage line VL11 can be electrically connected to the first vertical initialization voltage line VL11v to have a grid structure in the display area DA. The first-second initialization voltage line VL12 can be electrically connected to the second vertical initialization voltage line VL12v to have a grid structure in the display area DA. The first-third initialization voltage line VL13 can be electrically connected to the third vertical initialization voltage line VL13v to have a grid structure in the display area DA. The reference voltage line VRL can be electrically connected to the vertical reference voltage line VRLv to have a grid structure in the display area DA. The shield line VEL and the vertical common voltage line EOL may not have a grid structure and may be straight lines with stripes extending in the y direction.

[0146] In an embodiment, such as Figure 14 As shown, in the four unit circuit regions PCAu, the first vertical conductive line VVL1 can be the vertical drive voltage line PLv, and as the second vertical conductive line VVL2 and the third vertical conductive line VVL3, the first vertical initialization voltage VL11v / vertical reference voltage line VRLv, the second vertical initialization voltage line VL12v / vertical reference voltage line VRLv, the vertical reference voltage line VRLv / third vertical initialization voltage line VL13v and the vertical common voltage line EOL / vertical reference voltage line VRLv can be arranged alternately.

[0147] In an embodiment, such as Figure 15As shown, in the four unit circuit regions PCAu, the first vertical initialization voltage VL11v / a pair of vertical reference voltage lines VRLv, the second vertical initialization voltage line VL12v / vertical drive voltage line PLv / vertical reference voltage line VRLv, the third vertical initialization voltage line VL13v / a pair of vertical reference voltage lines VRLv, and the vertical drive voltage line PLv / vertical common voltage line EOL / vertical reference voltage line VRLv can be arranged alternately as the first vertical conductive line VVL1, the second vertical conductive line VVL2, and the third vertical conductive line VVL3.

[0148] Figure 12 An example is shown in which the first vertical conductive line VVL1 is the vertical drive voltage line PLv, the second vertical conductive line VVL2 is the second vertical initialization voltage line VL12v, and the third vertical conductive line VVL3 is the vertical reference voltage line VRLv.

[0149] The vertical drive voltage line PLv can be connected to the connection electrode 274 arranged in the first circuit region PCA1 through the contact hole 63 passing through the fourth insulating layer 104. Because the connection electrode 274 is connected to the conductive line 200, the vertical drive voltage line PLv can be electrically connected to the drive voltage line PL.

[0150] The second vertical initialization voltage line VL12v can be connected to the connection electrode 277b arranged in the second circuit area PCA2 through the contact hole 64 passing through the fourth insulating layer 104. Because the connection electrode 277b is connected to the first-second initialization voltage line VL12, the second vertical initialization voltage line VL12v can be electrically connected to the first-second initialization voltage line VL12.

[0151] The vertical reference voltage line VRLv can be connected to the connection electrode 272 arranged in the third circuit region PCA3 through the contact hole 65 passing through the fourth insulating layer 104. Because the connection electrode 272 is connected to the reference voltage line VRL, the vertical reference voltage line VRLv can be electrically connected to the reference voltage line VRL.

[0152] Although not shown, voltage supply lines electrically connected to the horizontal conductor VHL and / or the vertical conductor VVL can be further arranged in the peripheral area PA. The voltage supply lines can be arranged at least one of the upper, lower, left, and right sides of the display area DA.

[0153] The fifth insulating layer 105 may be disposed on the fourth insulating layer 104 to cover the fourth conductive layer, and the organic light-emitting diode (OLED) may be disposed as a display element on the fifth insulating layer 105. The OLED may include a pixel electrode 311, a counter electrode 315, and an intermediate layer between the pixel electrode 311 and the counter electrode 315.

[0154] Pixel electrode 311 can be connected to the first transistor T1 via contact hole 71 in the fifth insulating layer 105 to connection electrode 283 of the lower conductive pattern. For example... Figure 16 As shown, the pixel electrode 311a connected to the pixel circuit of the first pixel PX1 can be connected to the first transistor T1 by connecting to the connection electrode 283 arranged in the first circuit region PCA1. The pixel electrode 311b connected to the pixel circuit of the second pixel PX2 can be connected to the first transistor T1 by connecting to the connection electrode 283 arranged in the second circuit region PCA2. The pixel electrode 311c connected to the pixel circuit of the third pixel PX3 can be connected to the first transistor T1 by connecting to the connection electrode 283 arranged in the third circuit region PCA3. The pixel electrode 311c can have a square-shaped first region 311c1, a second region 311c2, and a third region 311c3 connecting the first region 311c1 and the second region 311c2. Shape. The auxiliary electrode AE ​​may be further arranged in the same layer as the pixel electrode 311. The auxiliary electrode AE ​​may be arranged between the pixel electrodes 311c of the third pixel PX3. The auxiliary electrode AE ​​may contact the counter electrode 315 in the display area DA. In an embodiment, the auxiliary electrode AE ​​may be electrically connected to the vertical common voltage line EOL in the display area DA.

[0155] like Figure 17 and Figure 18 As shown, a sixth insulating layer 106 of the pixel defining layer can be disposed above the pixel electrode 311 to cover the edge of the pixel electrode 311. An opening 106OP can be defined in the sixth insulating layer 106 to expose a portion of the pixel electrode 311 and define an emission region. The sixth insulating layer 106 may include a single layer or multiple layers comprising organic insulating layers and / or inorganic insulating layers.

[0156] The intermediate layer may include an emitter layer 313, a first functional layer below the emitter layer 313, and / or a second functional layer above the emitter layer 313. The first functional layer may include a hole transport layer (“HTL”). Alternatively, the first functional layer may include a hole injection layer (“HIL”) and an HTL. The second functional layer may include an electron transport layer (“ETL”) and / or an electron injection layer (“EIL”). The first and second functional layers may be integrally formed to correspond to a plurality of organic light-emitting diodes (OLEDs) included in the display area DA. Either the first or second functional layer may be omitted. Figure 17 and Figure 18 An organic light-emitting diode OLEDa is shown that is electrically connected to a pixel circuit arranged in the first circuit region PCA1.

[0157] The counter electrode 315 can be integrally formed to correspond to multiple organic light-emitting diodes (OLEDs) arranged in the display area DA.

[0158] Figure 19 This is a diagram illustrating the arrangement of data lines and signal lines according to a comparative example. In the comparative example, the conductive line 200 of the drive voltage line PL can be positioned below the data line DL to overlap with the data line DL in the plan view, the vertical drive voltage line PLv can be positioned above the data line DL to overlap with the data line DL in the plan view, and the vertical drive voltage line PLv can be positioned above the connection electrode 270 to overlap with the connection electrode 270 in the plan view.

[0159] In the comparative example, capacitor C' may be formed between data line DL and drive voltage line PL (conductor line 200) supplied with the first drive voltage ELVDD, and between data line DL and vertical drive voltage line PLv supplied with the first drive voltage ELVDD. When the data signal DATA changes, the first drive voltage ELVDD supplied to drive voltage line PL may change instantaneously (rise or fall) due to the coupling of capacitor C'. Due to the change in the first drive voltage ELVDD, the voltage at the second terminal of the first transistor T1 (i.e., the voltage at the second node N2) may change due to the coupling of the second capacitor C2 connected to drive voltage line PL, which may cause a change in the gate-source voltage of the first transistor T1. Accordingly, pixel PX may emit light with a brightness different from the given brightness, and multiline horizontal crosstalk of spots in the image may occur.

[0160] On the other hand, Figure 18 In the embodiment shown, the shield line VEL can be disposed above the data line DL. Because the shield line VEL is not electrically connected to the pixel PX, even when the data signal DATA changes, the voltage change of the shield line VEL will not affect the voltage change of the second terminal of the first transistor T1, and therefore the gate-source voltage change of the first transistor T1 can be minimized.

[0161] In a pixel circuit where the vertical drive voltage line PLv in the vertical conductive line VVL overlaps with the connection electrode 270 of the source region S1 including the first transistor T1 in a plan view, a capacitor may be formed due to the vertical drive voltage line PLv and the connection electrode 270, and therefore the capacitance of the second capacitor C2 may increase. When the data signal DATA changes due to the increase in the capacitance of the second capacitor C2, multi-line horizontal crosstalk caused by the coupling of the second capacitor C2 may increase. In an embodiment, the vertical drive voltage line PLv may not be disposed above the connection electrode 270 in the circuit region of at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 constituting the unit pixel. The vertical drive voltage line PLv may not be arranged in the second circuit region PCA2 in which the pixel with a large brightness contribution (e.g., the second pixel PX2, which is a green pixel) in the unit pixel is arranged.

[0162] In an embodiment, the second vertical conductive line VVL2 arranged in the second circuit region PCA2 can be one of the first vertical initialization voltage line VL11v, the second vertical initialization voltage line VL12v, the third vertical initialization voltage line VL13v, the vertical reference voltage line VRLv, and the vertical common voltage line EOL (excluding the vertical drive voltage line PLv). Figure 20 As shown, for example, Figure 15 In the second unit circuit area PCAu, the vertical drive voltage line PLv and the vertical reference voltage line VRLv of the second vertical conductive line VVL2 and the third vertical conductive line VVL3 can be replaced by the vertical reference voltage line VRLv and the vertical drive voltage line PLv. Figure 21 This is a cross-sectional view of an example in which the vertical reference voltage line VRLv is arranged as the second vertical conductive line VVL2 in the second circuit region PCA2.

[0163] The pixel circuitry of the pixel according to the embodiment is not limited to... Figure 3 The pixel circuit is shown in the figure. In other embodiments, this disclosure can be applied to various pixel circuits including a first capacitor C1 and a second capacitor C2 connected to the second terminal (source) of the first transistor T1.

[0164] Figures 22 to 26 The equivalent circuit of a pixel according to an embodiment is shown.

[0165] Figure 22 The pixel circuit of PX and PC Figure 3 The difference in the pixel circuit PC lies in that the fourth transistor T4 is connected to the second node N2 and the initialization voltage line VL. The fourth transistor T4 can be turned on by the second gate signal GI received from the second gate line GIL to transmit the initialization voltage Vint received from the initialization voltage line VL to the second node N2.

[0166] Figure 23 The pixel circuit of PX and PC Figure 22 The pixel circuit PC differs in that the seventh transistor T7 is additionally connected to the third node N3 and the second initialization voltage line VL2. The second initialization voltage line VL2 can be provided separately from the initialization voltage line VL and can be configured to supply a second initialization voltage Vaint that is different from the initialization voltage Vint. In an embodiment, the second initialization voltage Vaint can have a higher voltage level than the initialization voltage Vint.

[0167] The seventh transistor T7 can be turned on by the second gate signal GI received via the second gate line GIL to transmit the second initialization voltage Vaint received via the second initialization voltage line VL2 to the third node N3. The second node N2 and the third node N3 can be initialized to different voltages by the fourth transistor T4 and the seventh transistor T7, respectively.

[0168] Figure 24 The pixel circuit of PX and PC Figure 23 The difference in the pixel circuit PC lies in that the gate of the seventh transistor T7 is connected to the sixth gate line GBL to receive the sixth gate signal GB. The fourth transistor T4 and the seventh transistor T7 can be connected to different gate lines and controlled by different gate signals to independently control the initialization timing of the second node N2 and the third node N3.

[0169] Figure 25 The pixel circuit of PX and PC Figure 24 The difference in the pixel circuit PC lies in that the seventh transistor T7 is connected to the second node N2 and the second initialization voltage line VL2. The fourth transistor T4 and the seventh transistor T7 can be connected to different gate lines and controlled by different gate signals to precisely control the initialization of the second node N2.

[0170] Figure 26 The pixel circuit of PX and PC Figure 25 The difference between the pixel circuit PC of pixel PX and pixel PX is that the sixth transistor T6 is omitted.

[0171] picture Figure 3 As shown in the pixel PX, in Figures 22 to 26In the pixel PX shown, the shielding line can be positioned above the data line DL to overlap with the data line DL in the plan view, and may not be connected to the pixel PX. The shielding voltage supplied to the shielding line can be a separate voltage different from the first driving voltage ELVDD, the reference voltage Vref, the initialization voltage Vint, and the second initialization voltage Vaint, or it can be one of the first driving voltage ELVDD, the reference voltage Vref, the initialization voltage Vint, the second initialization voltage Vaint, the high voltage VGH, the low voltage VGL, and the ground voltage. Furthermore, the second vertical conductive line VVL2 arranged in the second circuit area PCA2 of the pixel circuit in which the second pixel PX2 is arranged can be one of the vertical conductive lines other than the vertical driving voltage line PLv.

[0172] Figures 27 to 32 This is an equivalent circuit diagram of the pixels according to the embodiment.

[0173] Figure 27 The pixel circuit of PX and PC Figure 3 The difference in the pixel circuit PC lies in the addition of a third capacitor C3. The third capacitor C3 can be connected between the second node N2 and the common voltage line CEL.

[0174] Figure 28 The pixel circuit of PX and PC Figure 20 The difference in the pixel circuit PC lies in the addition of a third capacitor C3. The third capacitor C3 can be connected between the second node N2 and the common voltage line CEL.

[0175] Figure 29 The pixel circuit of PX and PC Figure 21 The difference in the pixel circuit PC lies in the addition of a third capacitor C3. The third capacitor C3 can be connected between the second node N2 and the common voltage line CEL.

[0176] Figure 30 The pixel circuit of PX and PC Figure 22 The difference in the pixel circuit PC lies in the addition of a third capacitor C3. The third capacitor C3 can be connected between the second node N2 and the common voltage line CEL.

[0177] Figure 31 The pixel circuit of PX and PC Figure 23 The difference in the pixel circuit PC lies in the addition of a third capacitor C3. The third capacitor C3 can be connected between the second node N2 and the common voltage line CEL.

[0178] Figure 32 The pixel circuit of PX and PC Figure 24The difference in the pixel circuit PC lies in the addition of a third capacitor C3. The third capacitor C3 can be connected between the second node N2 and the common voltage line CEL.

[0179] exist Figures 27 to 32 In the embodiment shown, the common voltage line CEL can extend in the x-direction and can span the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The common voltage line CEL can be electrically connected to the vertical common voltage line EOL. In this embodiment, the common voltage line CEL can be disposed in the same layer as the first conductive layer.

[0180] Like the implementation Figure 3 Implementation examples Figure 11 Just like in the middle, also in Figures 27 to 32 In the pixel PX shown, the shielding line can overlap with the data line DL in the planar view, and the shielding line can overlap with the conductive line 200 in the planar view. Figures 27 to 32 The pixel PX shown may further include a third capacitor C3, thereby further minimizing voltage changes in the drive voltage line PL due to changes in the data signal DATA. Furthermore, the second vertical conductive line VVL2 in the second circuit region PCA2, in which the pixel circuit of the second pixel PX2 is arranged, may be one of the vertical conductive lines other than the vertical drive voltage line PLv.

[0181] Figure 33 This is an equivalent circuit diagram of the pixels according to the embodiment.

[0182] Figure 33 The pixel circuit of PX and PC Figure 3 The difference in the pixel circuit PC is that the second capacitor C2 is connected between the reference voltage line VRL and the second node N2. Figure 33 The pixel circuitry of the PX pixel PC can be configured with other features. Figure 3 The pixel circuit PC shown in the figure has the same configuration, and therefore, for the sake of brevity, its redundant description will be omitted.

[0183] Figure 34 It is shown schematically. Figure 33 The diagram shows the layout of the positions of the transistors and capacitors of the pixels. Figures 35 to 41 It is shown schematically layer by layer. Figure 33 The layout diagram of the pixel components. Figure 39 This is a diagram showing the transistors and capacitors in the first circuit region PCA1. Figure 42 It is along Figure 34 A cross-sectional view of the pixels intercepted by line III-III'. Figure 43This is a diagram illustrating the arrangement of data lines and signal lines according to a comparative example. In the following text, the same reference numerals will be assigned to... Figures 6 to 18 For components that are identical to those described in the previous section, redundant descriptions will be omitted, and the differences between them will be described primarily.

[0184] refer to Figure 35 The first conductive layer may be disposed on the substrate 100. The first conductive layer may include a conductive line 200 as a driving voltage line PL, a first electrode 210, a lower first gate line GWLb, a reference voltage line VRL, a first-second initialization voltage line VL12, a first-third initialization voltage line VL13, and a repair line RL.

[0185] refer to Figure 36 The first insulating layer 101 may be disposed on the substrate 100 to cover the first conductive layer, and the semiconductor layer ACT including oxide semiconductor may be disposed on the first insulating layer 101.

[0186] refer to Figure 37 The second insulating layer 102 can be disposed on the first insulating layer 101 to cover the semiconductor layer ACT, and the second conductive layer can be disposed on the second insulating layer 102. The second conductive layer may include a second electrode 220, a third electrode 230, an upper first gate line GWLt, a second gate line GIL, a third gate line GRL, a fourth gate line EML, a fifth gate line EMBL, and a first-1 initialization voltage line VL11.

[0187] refer to Figure 38 The third insulating layer 103 may be disposed on the second insulating layer 102 to cover the second conductive layer, and the third conductive layer may be disposed on the third insulating layer 103. The third conductive layer may include a data line DL and connecting electrodes 270, 271, 272, 273, 274, 275, 276, 277a, 277b, 277c and 278.

[0188] The connection electrode 272 can be connected to the drain region D3 of the third transistor T3 through contact holes 46 passing through the second insulating layer 102 and the third insulating layer 103, and can be connected to the reference voltage line VRL through contact holes 47 passing through the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. The connection electrode 272 can be connected to the fourth semiconductor layer ACT4 through contact holes 59 passing through the second insulating layer 102 and the third insulating layer 103. Accordingly, the reference voltage Vref can be supplied to the fourth semiconductor layer ACT4.

[0189] The connecting electrode 278 can be connected to the source region S4 of the fourth transistor T4 through the contact hole 60 passing through the second insulating layer 102 and the third insulating layer 103.

[0190] refer to Figure 40 The fourth insulating layer 104 may be disposed above the third insulating layer 103 to cover the third conductive layer, and the fourth conductive layer may be disposed above the fourth insulating layer 104. The fourth conductive layer may include multiple vertical conductive lines VVL (see...). Figures 13 to 15 ) and connecting electrodes 281 and 283. Figure 40 An example is shown in which the first vertical conductor VVL1 is the second vertical initialization voltage line VL12v, the second vertical conductor VVL2 is the vertical reference voltage line VRLv, and the third vertical conductor VVL3 is the vertical drive voltage line PLv.

[0191] The second vertical initialization voltage line VL12v can be connected to the connection electrode 278 arranged in the first circuit region PCA1 through the contact hole 67 passing through the fourth insulating layer 104. Because the connection electrode 278 is connected to the source region S4 of the fourth transistor T4 and the source region S4 of the fourth transistor T4 is connected to the first-second initialization voltage line VL12, the second vertical initialization voltage line VL12v can be electrically connected to the first-second initialization voltage line VL12.

[0192] The vertical reference voltage line VRLv can be connected to the connection electrode 272 arranged in the second circuit area PCA2 through the contact hole 68 passing through the fourth insulating layer 104. Because the connection electrode 272 is connected to the reference voltage line VRL, the vertical reference voltage line VRLv can be electrically connected to the reference voltage line VRL.

[0193] The vertical drive voltage line PLv can be connected to the connection electrode 274 arranged in the third circuit region PCA3 through the contact hole 69 passing through the fourth insulating layer 104. Because the connection electrode 274 is connected to the conductive line 200, the vertical drive voltage line PLv can be electrically connected to the drive voltage line PL.

[0194] refer to Figure 41 The fifth insulating layer 105 can be disposed on the fourth insulating layer 104 to cover the fourth conductive layer, and the organic light-emitting diode (OLED) can be disposed as a display element on the fifth insulating layer 105. The OLED may include a pixel electrode 311, a counter electrode 315, and an intermediate layer between the pixel electrode 311 and the counter electrode 315.

[0195] Figure 43This is a diagram illustrating the arrangement of data lines and signal lines according to a comparative example. In the comparative example, the conductive line 200 of the drive voltage line PL can be positioned below the data line DL to overlap with the data line DL in the plan view, the shield line VEL can be positioned above the data line DL to overlap with the data line DL in the plan view, and the vertical drive voltage line PLv can be positioned above the connecting electrode 270 to overlap with the connecting electrode 270 in the plan view.

[0196] In the comparative example, capacitor C' may be formed between the data line DL and the drive voltage line PL (conductor line 200) supplied with the first drive voltage ELVDD. When the data signal DATA changes, the first drive voltage ELVDD supplied to the drive voltage line PL may change instantaneously (rise or fall) due to the coupling of capacitor C'. Due to the change in the first drive voltage ELVDD, the voltage at the second terminal of the first transistor T1 (i.e., the voltage at the second node N2) may change due to the coupling of the capacitor formed between the vertical drive voltage line PLv and the connecting electrode 270, which may cause a change in the gate-source voltage of the first transistor T1.

[0197] In an embodiment, the vertical driving voltage line PLv may not be disposed above the connecting electrode 270 in the circuit region of at least one of the first pixel PX1, second pixel PX2, and third pixel PX3 in which the unit pixel is arranged. In an embodiment, the vertical driving voltage line PLv may not be disposed in the second circuit region PCA2 of the pixel with a large brightness contribution (e.g., the second pixel PX2, which is a green pixel) in which the unit pixel is arranged, thereby minimizing the capacitance of the capacitor formed between the vertical driving voltage line PLv and the connecting electrode 270.

[0198] The pixel circuitry of the pixel according to the embodiment is not limited to... Figure 33 The pixel circuit is shown in the figure. In other embodiments, this disclosure can be applied to various pixel circuits including a first capacitor C1 and a second capacitor C2 connected to the second terminal (source) of the first transistor T1.

[0199] Figures 44 to 49 The equivalent circuit of a pixel according to an embodiment is shown.

[0200] Figure 44 The pixel circuit of PX and PC Figure 33The pixel circuit PC differs in that a fourth transistor T4 is connected to the second node N2 and the initialization voltage line VL, and a seventh transistor T7 is additionally connected to the third node N3 and the second initialization voltage line VL2. The fourth transistor T4 can be turned on by a second gate signal GI received from the second gate line GIL to transmit the initialization voltage Vint received from the initialization voltage line VL to the second node N2. The second initialization voltage line VL2 can be provided separately from the initialization voltage line VL and can be configured to supply a second initialization voltage Vaint different from the initialization voltage Vint. In an embodiment, the second initialization voltage Vaint can have a higher voltage level than the initialization voltage Vint. The seventh transistor T7 can be turned on by the second gate signal GI received via the second gate line GIL to transmit the second initialization voltage Vaint received through the second initialization voltage line VL2 to the third node N3. The second node N2 and the third node N3 can be initialized to different voltages by the fourth transistor T4 and the seventh transistor T7, respectively.

[0201] In an embodiment, such as Figure 47 As shown, the third capacitor C3 can be increased to Figure 44 The pixel circuit PC of pixel PX is shown in the diagram. The third capacitor C3 can be connected between the second node N2 and the common voltage line CEL.

[0202] Figure 45 The pixel circuit of PX and PC Figure 44 The difference in the pixel circuit PC lies in that the gate of the seventh transistor T7 is connected to the sixth gate line GBL to receive the sixth gate signal GB. The fourth transistor T4 and the seventh transistor T7 can be connected to different gate lines and controlled by different gate signals to independently control the initialization timing of the second node N2 and the third node N3.

[0203] In an embodiment, such as Figure 48 As shown, the third capacitor C3 can be increased to Figure 45 The pixel circuit PC of pixel PX is shown in the diagram. The third capacitor C3 can be connected between the second node N2 and the common voltage line CEL.

[0204] Figure 46 The pixel circuit of PX and PC Figure 33 The difference between the pixel circuit PC of pixel PX and pixel PX is that the sixth transistor T6 is omitted.

[0205] In an embodiment, such as Figure 49 As shown, the third capacitor C3 can be increased to Figure 46The pixel circuit PC of pixel PX is shown in the diagram. The third capacitor C3 can be connected between the second node N2 and the common voltage line CEL.

[0206] In the above embodiments, the pixel circuit PC may include N-type transistors; however, the embodiments are not limited thereto. For example, according to various embodiments, the plurality of transistors in the pixel circuit PC may be P-type transistors, or some transistors may be P-type transistors and the others may be N-type transistors. In embodiments, the driving transistor among the plurality of transistors in the pixel circuit PC may be an N-type transistor, and at least one of the other transistors may be a P-type transistor. The P-type transistor may be a low-temperature polycrystalline silicon (“LTPS”) thin-film transistor comprising a semiconductor layer containing polycrystalline silicon.

[0207] According to an embodiment, in a pixel where a capacitor is connected between an electrode (e.g., the source) of a driving transistor and a signal line (e.g., a driving voltage line PL or a reference voltage line VRL) configured to supply a constant voltage to the pixel, a shielding line may be disposed above and / or below the data line DL. Accordingly, by minimizing (e.g., preventing) the formation of a capacitor between the data line DL and the signal line, when the data signal DATA changes, the gate-source voltage of the driving transistor T1 may not change due to the coupling of the capacitor formed between the data line DL and the signal line. Because the shielding line is not electrically connected to the pixel, the shielding voltage supplied to the shielding line can be one of a constant voltage supplied to the pixel and a constant voltage not supplied to the pixel.

[0208] Furthermore, according to an embodiment, the signal line supplied with the first driving voltage may not be arranged above the electrode (e.g., source) of the driving transistor in at least one of the sub-pixels (e.g., red, green, and blue pixels) of the unit pixel. Accordingly, when the data signal changes, the gate-source voltage of the driving transistor may not change due to the coupling of the capacitor formed between the electrode (e.g., source) of the driving transistor and the signal line supplied with the driving voltage.

[0209] Figures 50a to 51b This is a cross-sectional view showing the structure of a display element according to an embodiment.

[0210] According to an embodiment, an organic light-emitting diode (OLED) as a display element may include a pixel electrode 311, a counter electrode 315, and an intermediate layer 313m between the pixel electrode 311 (first electrode or anode) and the counter electrode 315 (second electrode or cathode).

[0211] Pixel electrode 311 may include a transparent conductive oxide such as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (“IGO”), or aluminum zinc oxide (“AZO”). Pixel electrode 311 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any compound thereof. For example, pixel electrode 311 may have a three-layer structure of ITO / Ag / ITO.

[0212] The counter electrode 315 may be disposed above the intermediate layer 313m. The counter electrode 315 may comprise a metal, alloy, conductive compound, or any combination thereof having a low work function. For example, the counter electrode 315 may comprise lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), lithium aluminum (Al-Li), calcium (Ca), magnesium indium (Mg-In), magnesium silver (Mg-Ag), ytterbium (Yb), silver ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The counter electrode 315 may be a transparent electrode, a translucent electrode, or a reflective electrode.

[0213] The intermediate layer 313m may include high-molecular-weight or low-molecular-weight organic materials for emitting light of a specific color. In addition to various organic materials, the intermediate layer 313m may further include metal-containing compounds such as organometallic compounds or inorganic materials such as quantum dots.

[0214] In an embodiment, the intermediate layer 313m may include an emitter layer and a first functional layer and a second functional layer located below and above the emitter layer, respectively. For example, the first functional layer may include a hole transport layer (HTL), or may include an HTL and a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first or second functional layer may be omitted. The first and second functional layers may be integrally formed to correspond to a plurality of organic light-emitting diodes (OLEDs) included in the display area DA.

[0215] In an embodiment, the intermediate layer 313m may include two or more emission units sequentially stacked between the pixel electrode 311 and the counter electrode 315, and a charge generation layer CGL disposed between the two emission units. When the intermediate layer 313m includes emission units and a charge generation layer, the organic light-emitting diode (OLED) can be a tandem light-emitting device. Because the organic light-emitting diode (OLED) has a stacked structure of multiple emission units, its color purity and luminous efficiency can be improved.

[0216] An emitting unit may include an emitting layer and a first functional layer and a second functional layer located below and above the emitting layer, respectively. The charge generation layer (CGL) may include a negative charge generation layer and a positive charge generation layer. The luminous efficiency of an organic light-emitting diode (OLED), a tandem light-emitting device comprising multiple emitting layers, can be further improved through the negative and positive charge generation layers.

[0217] The negative charge generation layer can be an n-type charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer can include a host material and a dopant. The host material can include an organic material. The dopant material can include a metallic material. The positive charge generation layer can be a p-type charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer can include a host material and a dopant. The host material can include an organic material. The dopant material can include a metallic material.

[0218] In an embodiment, such as Figure 50a As shown, an organic light-emitting diode (OLED) may include a first emitting unit EU1 comprising a first emitting layer EML1 and a second emitting unit EU2 comprising a second emitting layer EML2, which are sequentially stacked. A charge-generating layer CGL may be provided between the first emitting unit EU1 and the second emitting unit EU2. For example, an OLED may include a pixel electrode 311, a first emitting layer EML1, a charge-generating layer CGL, a second emitting layer EML2, and a counter electrode 315, which are sequentially stacked. A first functional layer and a second functional layer may be included below and above the first emitting layer EML1, respectively. The first functional layer and the second functional layer may be included below and above the second emitting layer EML2, respectively. The first emitting layer EML1 may be a blue emitting layer, and the second emitting layer EML2 may be a yellow emitting layer.

[0219] In an embodiment, such as Figure 50bAs shown, an organic light-emitting diode (OLED) may include a first emitting unit EU1 and a third emitting unit EU3, each containing a first emitting layer EML1, and a second emitting unit EU2 containing a second emitting layer EML2. A first charge-generating layer CGL1 may be provided between the first emitting unit EU1 and the second emitting unit EU2, and a second charge-generating layer CGL2 may be provided between the second emitting unit EU2 and the third emitting unit EU3. For example, an OLED may include a pixel electrode 311, a first emitting layer EML1, a first charge-generating layer CGL1, a second emitting layer EML2, a second charge-generating layer CGL2, a first emitting layer EML1, and a counter electrode 315, stacked sequentially. A first functional layer and a second functional layer may be included below and above the first emitting layer EML1, respectively. The first functional layer and the second functional layer may be included below and above the second emitting layer EML2, respectively. The first emitting layer EML1 may be a blue emitting layer, and the second emitting layer EML2 may be a yellow emitting layer.

[0220] In an embodiment, in an organic light-emitting diode (OLED), in addition to the second emitting layer EML2, the second emitting unit EU2 may further include a third emitting layer EML3 and / or a fourth emitting layer EML4 that are directly contacted below and / or above the second emitting layer EML2. Here, "direct contact" can mean that no other layers are arranged between the second emitting layer EML2 and the third emitting layer EML3 and / or between the second emitting layer EML2 and the fourth emitting layer EML4. The third emitting layer EML3 may be a red emitting layer, and the fourth emitting layer EML4 may be a green emitting layer.

[0221] For example, such as Figure 50c As shown, an organic light-emitting diode (OLED) may include a pixel electrode 311, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a second charge generation layer CGL2, a first emission layer EML1, and a counter electrode 315, which are sequentially stacked. Alternatively, as Figure 50d As shown, an organic light-emitting diode (OLED) may include a pixel electrode 311, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a fourth emission layer EML4, a second charge generation layer CGL2, a first emission layer EML1, and a counter electrode 315, which are stacked sequentially.

[0222] Figure 51a It is shown Figure 50c A cross-sectional view of an example organic light-emitting diode, and Figure 51b It is shown Figure 50d A cross-sectional view of an example organic light-emitting diode.

[0223] refer to Figure 51a An organic light-emitting diode (OLED) may include a first emitting unit EU1, a second emitting unit EU2, and a third emitting unit EU3 stacked sequentially. A first charge-generating layer CGL1 may be provided between the first emitting unit EU1 and the second emitting unit EU2, and a second charge-generating layer CGL2 may be provided between the second emitting unit EU2 and the third emitting unit EU3. Each of the first charge-generating layer CGL1 and the second charge-generating layer CGL2 may include a negative charge-generating layer nCGL and a positive charge-generating layer pCGL.

[0224] The first emitting unit EU1 may include a blue emitting layer BEML. The first emitting unit EU1 may further include a hole injection layer HIL and a hole transport layer HTL between the pixel electrode 311 and the blue emitting layer BEML. In an embodiment, a p-doped layer may be further included between the hole injection layer HIL and the hole transport layer HTL. The p-doped layer can be formed by doping the hole injection layer HIL with a p-type dopant. In an embodiment, at least one of a blue light assist layer, an electron blocking layer, and a buffer layer may be further included between the blue emitting layer BEML and the hole transport layer HTL. The blue light assist layer can improve the light output efficiency of the blue emitting layer BEML. The blue light assist layer can adjust the hole charge balance to improve the light output efficiency of the blue emitting layer BEML. The electron blocking layer can prevent electrons from being injected into the hole transport layer HTL. The buffer layer can compensate for the resonant distance depending on the wavelength of the light emitted from the emitting layer.

[0225] The second emitting unit EU2 may include a yellow emitting layer YEML and a red emitting layer REML directly contacting the yellow emitting layer YEML below it. The second emitting unit EU2 may further include a hole transport layer HTL between the red emitting layer REML and the positive charge generation layer pCGL of the first charge generation layer CGL1, and may further include an electron transport layer ETL between the yellow emitting layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0226] The third emitting unit EU3 may include a blue emitting layer BEML. The third emitting unit EU3 may further include a hole transport layer HTL between the blue emitting layer BEML and the positive charge generation layer pCGL of the second charge generation layer CGL2. The third emitting unit EU3 may further include an electron transport layer ETL and an electron injection layer EIL between the blue emitting layer BEML and the counter electrode 315. The electron transport layer ETL may include a single layer or multiple layers. In an embodiment, at least one of a blue light assist layer, an electron blocking layer, and a buffer layer may be further included between the blue emitting layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may be further included between the blue emitting layer BEML and the electron transport layer ETL. The hole blocking layer prevents holes from being injected into the electron transport layer ETL.

[0227] Figure 51b The organic light-emitting diode OLED shown can be compared with the stacked structure of the second emitting unit EU2 in terms of... Figure 51a The organic light-emitting diode (OLED) shown is different, and Figure 51b Other configurations of the organic light-emitting diode OLED shown can be combined with... Figure 51a The configuration shown is the same. (See reference) Figure 51b The second emitting unit EU2 may include a yellow emitting layer YEML, a red emitting layer REML directly contacting the yellow emitting layer YEML below it, and a green emitting layer GEML directly contacting the yellow emitting layer YEML above it. The second emitting unit EU2 may further include a hole transport layer HTL between the red emitting layer REML and the positive charge generation layer pCGL of the first charge generation layer CGL1, and may further include an electron transport layer ETL between the green emitting layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0228] Figure 52 This is a cross-sectional view showing the structure of the pixels of a display device according to an embodiment.

[0229] refer to Figure 52 The display device may include multiple pixels. The multiple pixels may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a pixel electrode 311, a counter electrode 315, and an intermediate layer 313m. In an embodiment, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. Here, each pixel may include an organic light-emitting diode (OLED) as a display element, and the OLED of each pixel may be electrically connected to the pixel circuitry.

[0230] Pixel electrode 311 can be independently provided in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0231] The intermediate layer 313m of the organic light-emitting diode (OLED) for each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first emitting unit EU1 and a second emitting unit EU2 stacked sequentially, and a charge generation layer CGL between the first emitting unit EU1 and the second emitting unit EU2. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0232] The first emitter unit EU1 of the first pixel PX1 may include a hole injection layer HIL, a hole transport layer HTL, a red emitter layer REML, and an electron transport layer ETL sequentially stacked on the pixel electrode 3111. The first emitter unit EU1 of the second pixel PX2 may include a hole injection layer HIL, a hole transport layer HTL, a green emitter layer GEML, and an electron transport layer ETL sequentially stacked on the pixel electrode 311. The first emitter unit EU1 of the third pixel PX3 may include a hole injection layer HIL, a hole transport layer HTL, a blue emitter layer BEML, and an electron transport layer ETL sequentially stacked on the pixel electrode 311. Each of the hole injection layer HIL, the hole transport layer HTL, and the electron transport layer ETL of the first emitter unit EU1 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0233] The second emitter unit EU2 of the first pixel PX1 may include a hole transport layer HTL, an auxiliary layer AXL, a red emitter layer REML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second emitter unit EU2 of the second pixel PX2 may include a hole transport layer HTL, a green emitter layer GEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second emitter unit EU2 of the third pixel PX3 may include a hole transport layer HTL, a blue emitter layer BEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. Each of the hole transport layer HTL and the electron transport layer ETL of the second emitter unit EU2 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3. In an embodiment, at least one of a hole blocking layer and a buffer layer may be further included between the emitter layer and the electron transport layer ETL in the second emitter unit EU2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0234] The thicknesses H1 of the red emitter layer REML, H2 of the green emitter layer GEML, and H3 of the blue emitter layer BEML can be determined based on the resonant distance. The auxiliary layer AXL can be a layer added to adjust the resonant distance and can include a resonant auxiliary material. For example, the auxiliary layer AXL can include the same material as the hole transport layer HTL.

[0235] exist Figure 52 In this embodiment, the auxiliary layer AXL is only included in the first pixel PX1; however, the embodiment is not limited to this. For example, the auxiliary layer AXL may be included in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 to adjust the resonant distance of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0236] The display device may further include a capping layer 317 disposed outside the counter electrode 315. According to the principle of constructive interference, the capping layer 317 can improve luminous efficiency. Accordingly, the light extraction efficiency of the organic light-emitting diode (OLED) can be improved, and therefore, the luminous efficiency of the OLED can be increased.

[0237] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and are not intended to be limiting. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the following claims.

Claims

1. A display device, comprising: A data cable is connected to pixels arranged in the display area, wherein the data cable extends in a first direction; A shielding line, disposed above the data line in the display area, extending in the first direction and overlapping the data line in a plan view; and A first voltage line, connected to the pixel, extends in a second direction perpendicular to the first direction, is disposed below the data line, and overlaps with the data line in the plan view.

2. The display device according to claim 1, wherein, The pixels include: A first capacitor includes a first electrode and a second electrode disposed on the first electrode and overlapping the first electrode in the plan view; A first transistor is connected to the first voltage line and the second electrode of the first capacitor; and The second transistor is connected to the data line and the gate electrode of the first transistor; The data line and the second electrode of the first capacitor are arranged in the same layer, and The semiconductor layer of the first transistor and the first electrode of the first capacitor are arranged in the same layer.

3. The display device according to claim 2, wherein, The voltage supplied to the shielding wire and the voltage supplied to the first electrode of the first capacitor are different from each other.

4. The display device according to claim 2, wherein, The voltage supplied to the shielding wire and the voltage supplied to the first electrode of the first capacitor are the same.

5. The display device according to claim 2, wherein, The first capacitor further includes a third electrode disposed below the first electrode, overlapping the first electrode in the plan view, and connected to the second electrode.

6. The display device according to claim 5, wherein, The first voltage line is arranged in the same layer as the third electrode of the first capacitor and is connected to the first electrode of the first capacitor.

7. The display device according to claim 6, further comprising: A vertical conductive line, arranged in the same layer as the shielding line, overlaps with the second electrode of the first capacitor in the plan view and extends in the first direction.

8. The display device according to claim 7, wherein, The vertical conductive line is configured to supply a constant voltage to the pixel and is connected to a horizontal conductive line extending in the second direction.

9. The display device according to claim 8, wherein, The horizontal conductive line includes the first voltage line.

10. The display device according to claim 5, wherein, The pixel further includes a second electrode connected to the first capacitor and a second capacitor connected to the light-emitting element. The light-emitting element includes a first electrode connected to the first transistor and a second electrode facing the first electrode. The second capacitor is connected to the second electrode of the light-emitting element.

11. The display device according to claim 5, further comprising: A second voltage line extends in the second direction and is connected to the first electrode of the first capacitor.

12. The display device according to claim 11, further comprising: A vertical conductive line, arranged in the same layer as the shielding line, overlaps with the first electrode of the first capacitor in the plan view and extends in the first direction.

13. The display device according to claim 12, wherein, The vertical conductive line is configured to supply a constant voltage to the pixel and is connected to a horizontal conductive line extending in the second direction.

14. The display device according to claim 13, wherein, The horizontal conductive line includes the second voltage line.

15. The display device according to claim 1, further comprising: A voltage supply line, located in a non-display area outside the display area, is connected to the shielding line and configured to supply shielding voltage to the shielding line.

16. A display device, comprising: The first pixel circuit is arranged in the first circuit area; as well as The second pixel circuit is arranged in a second circuit region adjacent to the first circuit region in the first direction. Each of the first pixel circuit and the second pixel circuit is connected to a light-emitting diode, and Each of the first pixel circuit and the second pixel circuit includes: The data cable extends in a second direction perpendicular to the first direction; A shielding line is disposed above the data line, extends in the second direction, and overlaps with the data line in a plan view; A first voltage line extends in the first direction, is disposed below the data line, and partially overlaps the data line in the plan view; A capacitor includes a first electrode and a second electrode disposed on the first electrode and overlapping the first electrode in the plan view; A first transistor is connected to the first voltage line and the second electrode of the capacitor; The second transistor is connected to the data line and the gate electrode of the first transistor; A third transistor is connected to the gate electrode of the first transistor and a second voltage line extending in the first direction; A fourth transistor is connected to the first electrode of the light-emitting diode and a third voltage line extending in the first direction; and The conductive wire, arranged in the same layer as the shielding wire, overlaps with the second electrode of the capacitor in the plan view and extends in the second direction. The light-emitting diode connected to the first pixel circuit emits light of a first color. The light-emitting diode connected to the second pixel circuit emits light of the second color. The conductive line of the first pixel circuit is connected to one of the first voltage line, the second voltage line, the third voltage line, and the fourth voltage line connected to the second electrode of the light-emitting diode. The conductive line of the second pixel circuit is connected to one of the second voltage line, the third voltage line, and the fourth voltage line, in addition to the first voltage line.

17. The display device according to claim 16, wherein, The voltage supplied to the shielding wire and the voltage supplied to the first electrode of the capacitor are different from each other.

18. The display device according to claim 16, wherein, The voltage supplied to the shielding wire and the voltage supplied to the first electrode of the capacitor are the same.

19. The display device according to claim 16, wherein, The capacitor further includes a third electrode disposed below the first electrode, overlapping the first electrode in the plan view, and connected to the second electrode.

20. The display device according to claim 19, wherein, The first voltage line is arranged in the same layer as the third electrode of the capacitor and is connected to the first electrode of the capacitor.

21. The display device according to claim 19, wherein, The second voltage line is arranged in the same layer as the third electrode of the capacitor and is connected to the first electrode of the capacitor.

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