Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of improving flexural resistance. The laminated ceramic capacitor (1) has an external electrode (40), the external electrode (40) has a base electrode layer (50), a conductive resin layer (60), and a plating layer (70), the film thickness of the conductive resin layer (60) on a ridge line portion (10a) of a laminated body (10) is 0.8 [mu] m or more and 8 [mu] m or less, and the conductive resin layer has a peeling region (P) that is peeled from the laminated body (10) in at least one extension portion (E). The peeling region (P) is disposed in a region from an end portion of the conductive resin layer (60) on the center side of the laminate in the longitudinal direction (L) to a region in front of an end portion of the base electrode layer (50) on the center side of the laminate in the longitudinal direction (L), and the dimension of the peeling region (P) in the longitudinal direction (L) is 5 [mu] m or more.

Description

Technical Field

[0001] This invention relates to multilayer ceramic capacitors. Background Technology

[0002] In recent years, multilayer ceramic capacitors have been required to withstand harsh environments such as flexural stress caused by thermal expansion. As a response, a technique using thermosetting conductive resin paste for the external electrodes of multilayer ceramic capacitors is known. Patent Document 1 illustrates this technique. Patent Document 1 describes a multilayer ceramic capacitor having an external electrode structure consisting of an electrode layer formed by impregnating and sintering a conductive paste, a conductive epoxy thermosetting resin layer, a nickel plating layer, and a tin-based layer, stacked sequentially.

[0003] Prior art literature

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 11-162771 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] However, when multilayer ceramic capacitors are mounted onto a substrate, the flexural stress generated on the external electrodes is transmitted to the laminate, raising concerns about the formation of cracks in the laminate, and efforts are being made to improve flexural toughness.

[0008] The purpose of this invention is to provide a multilayer ceramic capacitor that can improve flexural resilience.

[0009] Technical solutions for solving the problem

[0010] The multilayer ceramic capacitor of the present invention comprises: a multilayer body including a plurality of stacked dielectric layers, and having a first main surface and a second main surface opposite to each other in the height direction, a first side surface and a second side surface opposite to each other in the width direction orthogonal to the height direction, and a first end surface and a second end surface opposite to each other in the length direction orthogonal to the height direction and the width direction; a first inner electrode layer disposed on the plurality of dielectric layers and exposed on the first end surface; a second inner electrode layer disposed on the plurality of dielectric layers and exposed on the second end surface; a first outer electrode disposed on the first end surface; and a second outer electrode disposed on the second end surface, wherein the first outer electrode and the second outer electrode have a base electrode layer comprising a metal component, a conductive resin layer comprising filler powder and resin component disposed on the base electrode layer, and a plating layer disposed on the conductive resin layer ... base electrode layer comprising filler powder and resin component disposed on the base electrode layer, and a plating layer disposed on the conductive resin layer, wherein the first outer electrode and the base electrode layer comprising a metal component, the base electrode layer comprising a metal component, the first side surface and the second outer electrode have a base electrode layer comprising a metal component, a base electrode layer comprising filler powder and resin component disposed on the base electrode layer, and a plating layer comprising filler powder and resin component disposed on the conductive resin layer, wherein the first outer electrode and the base electrode layer comprising a metal component, the base electrode layer comprising a metal component, the first inner electrode layer and the second outer electrode have a base electrode layer comprising a metal component, a base electrode layer comprising a base electrode layer comprising a base electrode layer, a conductive resin layer comprising filler powder and resin component disposed on the base electrode layer, and a plating layer comprising filler powder and resin component disposed on the conductive resin layer, wherein the first outer electrode and the base electrode layer comprising a base electrode layer, the base electrode layer comprising The second external electrode has extensions that extend to a portion of the first main surface and a portion of the second main surface, respectively. The laminate has ridge portions at the portions where the first end face intersects with the first main surface, the portions where the first end face intersects with the second main surface, the portions where the second end face intersects with the first main surface, and the portions where the second end face intersects with the second main surface. A conductive resin layer is disposed on the ridge portions of the laminate. The thickness of the conductive resin layer on the ridge portions is 0.8 μm or more and 8 μm or less. The conductive resin layer has a peeling region in at least one of the extensions that is peeled off from the laminate. The peeling region is disposed in a region from the end of the conductive resin layer in the longitudinal direction of the laminate to the end of the substrate electrode layer in the longitudinal direction of the laminate in front of it. The dimension of the peeling region in the longitudinal direction is 5 μm or more.

[0011] Invention Effects

[0012] According to the present invention, a multilayer ceramic capacitor with improved flexural resilience can be provided. Attached Figure Description

[0013] Figure 1 This is a perspective view of the stacked ceramic capacitor of this embodiment.

[0014] Figure 2 yes Figure 1 The cross-sectional view of the multilayer ceramic capacitor shown is along line II-II.

[0015] Figure 3 yes Figure 2 The cross-sectional view of the multilayer ceramic capacitor shown is along line III-III.

[0016] Figure 4 yes Figure 2The cross-sectional view of the multilayer ceramic capacitor shown is along line IV-IV.

[0017] Figure 5 yes Figure 2 The enlarged view of the V portion of the multilayer ceramic capacitor shown is a schematic diagram used to explain in detail the structure of the edge portion of the multilayer ceramic capacitor.

[0018] Figure 6 This is a schematic diagram illustrating an example of the structure of a stacked ceramic capacitor with a dual-connection configuration.

[0019] Figure 7 This is a schematic diagram illustrating an example of the structure of a triplet-structured multilayer ceramic capacitor.

[0020] Figure 8 This is a schematic diagram illustrating an example of the structure of a quadruple-connected stacked ceramic capacitor. Detailed Implementation

[0021] <Implementation Method>

[0022] The following uses Figures 1-4 The multilayer ceramic capacitor 1, which is a multilayer ceramic electronic component according to one embodiment of the present disclosure, will be described. Figure 1 This is a perspective view of the stacked ceramic capacitor 1 of this embodiment. Figure 2 yes Figure 1 A cross-sectional view of the stacked ceramic capacitor 1 along line II-II. Figure 3 yes Figure 2 A cross-sectional view of the stacked ceramic capacitor 1 along line III-III. Figure 4 yes Figure 2 A cross-sectional view of the multilayer ceramic capacitor 1 along line IV-IV.

[0023] The multilayer ceramic capacitor 1 has a multilayer body 10 and an external electrode 40.

[0024] exist Figures 1-4 An XYZ orthogonal coordinate system is shown. The length direction L of the stacked ceramic capacitor 1 and the stacked body 10 corresponds to the X direction. The width direction W of the stacked ceramic capacitor 1 and the stacked body 10 corresponds to the Y direction. The stacking direction T, which is the height direction of the stacked ceramic capacitor 1 and the stacked body 10, corresponds to the Z direction. Here, Figure 2 The cross-section shown is also called the LT cross-section. Figure 3 The cross-section shown is also known as the WT cross-section. Figure 4 The cross-section shown is also called the LW cross-section.

[0025] like Figures 1-4As shown, the laminate 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in the lamination direction T, a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W orthogonal to the lamination direction T, and a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L orthogonal to the lamination direction T and the width direction W.

[0026] like Figure 1 As shown, the laminate 10 has a generally rectangular parallelepiped shape. Furthermore, the length L of the laminate 10 is not necessarily longer than its width W. It is preferable that the corners and edges of the laminate 10 have rounded corners. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Additionally, some or all of the surfaces constituting the laminate 10 may be formed with irregularities or depressions.

[0027] The dimensions of the laminate 10 are not particularly limited, but if the length direction L of the laminate 10 is defined as dimension L, then dimension L is preferably 0.2 mm or more and 10 mm or less. Furthermore, if the lamination direction T of the laminate 10 is defined as dimension T, then dimension T is preferably 0.1 mm or more and 10 mm or less. Furthermore, if the width direction W of the laminate 10 is defined as dimension W, then dimension W is preferably 0.1 mm or more and 10 mm or less.

[0028] like Figure 2 as well as Figure 3 As shown, the laminate 10 has an inner layer 11, and a first main surface side outer layer 12A, which is a first outer layer, and a second main surface side outer layer 12B, which is a second outer layer, sandwiched between the inner layer 11 in the lamination direction T.

[0029] The inner layer 11 includes multiple dielectric layers 20 that are multiple ceramic layers and multiple internal electrode layers 30 that are multiple internal conductor layers. The inner layer 11 includes internal electrode layers 30 extending from the side closest to the first main surface TS1 to the side closest to the second main surface TS2 in the stacking direction T. In the inner layer 11, the multiple internal electrode layers 30 are arranged opposite each other, separated by the dielectric layers 20. The inner layer 11 is the part that generates electrostatic capacitance and essentially functions as a capacitor.

[0030] Multiple dielectric layers 20 are composed of dielectric materials. For example, the dielectric material can be a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Alternatively, the dielectric material can also be a material in which secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds have been added to these main components.

[0031] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 30 μm or less. The number of stacked dielectric layers 20 is preferably 10 or more and 1500 or less. In addition, the number of dielectric layers 20 is the total number of dielectric layers in the inner layer 11 and the number of dielectric layers in the outer layer 12A on the first main surface side and the outer layer 12B on the second main surface side.

[0032] Multiple internal electrode layers 30 have first internal electrode layers 31 serving as multiple first internal conductor layers and second internal electrode layers 32 serving as multiple second internal conductor layers. Multiple first internal electrode layers 31 are disposed on multiple dielectric layers 20. Multiple second internal electrode layers 32 are disposed on multiple dielectric layers 20. The multiple first internal electrode layers 31 and multiple second internal electrode layers 32 are alternately disposed in the stacking direction T of the laminate 10, separated by dielectric layers 20. The first internal electrode layers 31 and second internal electrode layers 32 are configured to sandwich dielectric layers 20.

[0033] The first internal electrode layer 31 has a first opposing portion 31A opposite to the second internal electrode layer 32, and a first lead-out portion 31B extending from the first opposing portion 31A to the first end face LS1. The first lead-out portion 31B is exposed at the first end face LS1.

[0034] The second internal electrode layer 32 has a second opposing portion 32A opposite to the first internal electrode layer 31, and a second lead-out portion 32B extending from the second opposing portion 32A to the second end face LS2. The second lead-out portion 32B is exposed at the second end face LS2.

[0035] In this embodiment, the first opposing portion 31A and the second opposing portion 32A are opposed to each other through the dielectric layer 20, thereby forming a capacitor and exhibiting the characteristics of a capacitor.

[0036] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, and the corners of the rectangular shape may also be formed at an angle. The shapes of the first lead-out portion 31B and the second lead-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, and the corners of the rectangular shape may also be formed at an angle.

[0037] The width W of the first opposing portion 31A and the width W of the first lead-out portion 31B can be formed with the same size, or one of them can be formed with a smaller size. The width W of the second opposing portion 32A and the width W of the second lead-out portion 32B can be formed with the same size, or one of them can be formed with a smaller size.

[0038] The first internal electrode layer 31 and the second internal electrode layer 32 are made of suitable conductive materials, such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may also be made of, for example, an Ag-Pd alloy.

[0039] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 10 or more and 1500 or less.

[0040] The first main surface side outer layer 12A is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer 12A is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the inner electrode layer 30 closest to the first main surface TS1. The dielectric layer 20 used in the first main surface side outer layer 12A can be the same as the dielectric layer 20 used in the inner layer 11, or it can be a dielectric layer made of a different material.

[0041] The second main surface side outer layer 12B is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer 12B is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the inner electrode layer 30 closest to the second main surface TS2. The dielectric layer 20 used in the second main surface side outer layer 12B can be the same as the dielectric layer 20 used in the inner layer 11, or it can be a dielectric layer made of a different material.

[0042] Additionally, the laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion opposite to the first counter portion 31A of the first inner electrode layer 31 and the second counter portion 32A of the second inner electrode layer 32. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figure 4 The diagram shows the width W and length L of the counter electrode portion 11E. The counter electrode portion 11E is also referred to as the effective portion of the capacitor.

[0043] Additionally, the laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the counter electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the counter electrode portion 11E and the second side WS2. Figure 3 as well as Figure 4The diagram shows the width direction W of the first side outer layer WG1 and the second side outer layer WG2. The side outer layers are also referred to as W gaps or lateral gaps.

[0044] Additionally, the laminate 10 has an end-face side outer layer. The end-face side outer layer has a first end-face side outer layer LG1 and a second end-face side outer layer LG2. The first end-face side outer layer LG1 is a portion that includes a dielectric layer 20 located between the counter electrode portion 11E and the first end face LS1. The second end-face side outer layer LG2 is a portion that includes a dielectric layer 20 located between the counter electrode portion 11E and the second end face LS2. Figure 2 as well as Figure 4 The diagram shows the length direction L of the first end-face side outer layer LG1 and the second end-face side outer layer LG2. The end-face side outer layer is also referred to as the L-gap or end gap.

[0045] The external electrode 40 has a first external electrode 40A disposed on the first end face LS1 side and a second external electrode 40B disposed on the second end face LS2 side.

[0046] A first external electrode 40A is disposed on a first end face LS1. The first external electrode 40A is connected to a first internal electrode layer 31. The first external electrode 40A is disposed on a portion of a first main face TS1 and a portion of a second main face TS2. In this embodiment, the first external electrode 40A is formed by extending from the first end face LS1 to a portion of the first main face TS1, a portion of the second main face TS2, a portion of the first side face WS1, and a portion of the second side face WS2.

[0047] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B is disposed on a portion of the first main face TS1 and a portion of the second main face TS2. In this embodiment, the second external electrode 40B is formed by extending from the second end face LS2 to a portion of the first main face TS1 and a portion of the second main face TS2, and a portion of the first side face WS1 and a portion of the second side face WS2.

[0048] As previously described, within the laminate 10, the first opposing portion 31A of the first inner electrode layer 31 and the second opposing portion 32A of the second inner electrode layer 32 are opposed to each other across the dielectric layer 20, thereby forming a capacitor. Therefore, capacitor characteristics are exhibited between the first outer electrode 40A connected to the first inner electrode layer 31 and the second outer electrode 40B connected to the second inner electrode layer 32.

[0049] The first external electrode 40A has a first base electrode layer 50A containing a metallic component, a first conductive resin layer 60A disposed on the first base electrode layer 50A, and a first plating layer 70A disposed on the first conductive resin layer 60A. The first plating layer 70A has a first Ni plating layer 71A as a lower plating layer and a first Sn plating layer 72A as an upper plating layer.

[0050] The second external electrode 40B has a second base electrode layer 50B containing a metallic component, a second conductive resin layer 60B disposed on the second base electrode layer 50B, and a second plating layer 70B disposed on the second conductive resin layer 60B. The second plating layer 70B has a second Ni plating layer 71B as a lower plating layer and a second Sn plating layer 72B as an upper plating layer.

[0051] Here, the basic structures of each layer constituting the first external electrode 40A and the second external electrode 40B are the same. Furthermore, the first external electrode 40A and the second external electrode 40B are substantially symmetrical about the LW cross-section at the center of the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, without specifically distinguishing between the first external electrode 40A and the second external electrode 40B, they are sometimes collectively referred to as external electrode 40. Similarly, without specifically distinguishing between the first base electrode layer 50A and the second base electrode layer 50B, they are sometimes collectively referred to as base electrode layer 50. Furthermore, without specifically distinguishing between the first conductive resin layer 60A and the second conductive resin layer 60B, they are sometimes collectively referred to as conductive resin layer 60. Furthermore, unless it is necessary to specifically distinguish between the first plating layer 70A and the second plating layer 70B, the first plating layer 70A and the second plating layer 70B are sometimes collectively referred to as plating layer 70. Similarly, unless it is necessary to specifically distinguish between the first Ni plating layer 71A and the second Ni plating layer 71B, the first Ni plating layer 71A and the second Ni plating layer 71B are sometimes collectively referred to as Ni plating layer 71. Furthermore, unless it is necessary to specifically distinguish between the first Sn plating layer 72A and the second Sn plating layer 72B, the first Sn plating layer 72A and the second Sn plating layer 72B are sometimes collectively referred to as Sn plating layer 72. Finally, unless it is necessary to specifically distinguish between the first main surface TS1 and the second main surface TS2, the first main surface TS1 and the second main surface TS2 are sometimes collectively referred to as main surface TS. Furthermore, unless there is a specific distinction between the first side WS1 and the second side WS2, the first side WS1 and the second side WS2 are sometimes collectively referred to as side WS. Similarly, unless there is a specific distinction between the first end face LS1 and the second end face LS2, the first end face LS1 and the second end face LS2 are sometimes collectively referred to as end face LS.

[0052] The substrate electrode layer 50 has a first substrate electrode layer 50A and a second substrate electrode layer 50B.

[0053] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. In this embodiment, the first base electrode layer 50A is formed by extending from the first end face LS1 to a portion of the first main face TS1 and a portion of the second main face TS2, a portion of the first side face WS1 and a portion of the second side face WS2.

[0054] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. In this embodiment, the second base electrode layer 50B is formed by extending from the second end face LS2 to a portion of the first main face TS1 and a portion of the second main face TS2, and a portion of the first side face WS1 and a portion of the second side face WS2.

[0055] In this embodiment, the first base electrode layer 50A and the second base electrode layer 50B are sintered layers. The sintered layers preferably contain one or more of a metallic component, a glass component, or a ceramic component, or both. This improves the adhesion between the laminate 10 and the base electrode layer. The metallic component may contain at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloys, Au, etc. The glass component may contain at least one selected from B, Si, Ba, Mg, Al, Li, etc. The presence of a glass component aids in the sintering of the metallic component in the base electrode layer, promoting sintering. The ceramic component may be the same type of ceramic material as the dielectric layer 20, or a different type of ceramic material may be used. The ceramic component may contain at least one selected from BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, CaZrO3, etc.

[0056] The sintered layer is obtained, for example, by applying a conductive paste containing glass and metal to a laminate and then sintering it. The sintered layer can be obtained by simultaneously sintering a chip having internal electrodes and a dielectric layer and the conductive paste applied to the chip, or by sintering the chip having internal electrodes and a dielectric layer to obtain a laminate, then applying the conductive paste to the laminate and sintering it. Furthermore, when simultaneously sintering the chip having internal electrodes and a dielectric layer and the conductive paste applied to the chip, the sintered layer is preferably formed by sintering a conductive paste containing a ceramic material instead of glass. In this case, the same type of ceramic material as the dielectric layer 20 is particularly preferred as the added ceramic material. The sintered layer can also consist of multiple layers.

[0057] Regarding the thickness of the first base electrode layer 50A located on the first end face LS1 in the longitudinal direction, it is preferably 2 μm or more and 220 μm or less in the central part of the stacking direction T and the width direction W of the first base electrode layer 50A.

[0058] Regarding the thickness of the second base electrode layer 50B located on the second end face LS2 in the longitudinal direction, it is preferably 2 μm or more and 220 μm or less in the central part of the stacking direction T and the width direction W of the second base electrode layer 50B.

[0059] When the first base electrode layer 50A is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided on that portion in the stacking direction is preferably, for example, 4 μm or more and 40 μm or less at the central portion of the first base electrode layer 50A provided on that portion in the length direction L and the width direction W.

[0060] When a first base electrode layer 50A is also provided on a portion of at least one of the first side WS1 or the second side WS2, the thickness of the first base electrode layer 50A provided in the width direction of that portion is preferably, for example, 4 μm or more and 40 μm or less at the center of the first base electrode layer 50A provided in the length direction L and the stacking direction T of that portion.

[0061] When a second base electrode layer 50B is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided on that portion in the stacking direction is preferably, for example, 4 μm or more and 40 μm or less at the central portion of the second base electrode layer 50B provided on that portion in the length direction L and the width direction W.

[0062] When a second base electrode layer 50B is also provided on a portion of at least one of the first side WS1 or the second side WS2, the thickness of the second base electrode layer 50B provided in the width direction of that portion is preferably, for example, 4 μm or more and 40 μm or less at the center of the second base electrode layer 50B provided in the length direction L and the stacking direction T of that portion.

[0063] The external electrode 40 has a conductive resin layer 60 containing resin and metal components disposed on the base electrode layer 50.

[0064] The conductive resin layer 60 has a first conductive resin layer 60A and a second conductive resin layer 60B.

[0065] The first conductive resin layer 60A is configured to cover the first base electrode layer 50A. In this embodiment, the first conductive resin layer 60A is formed extending from the first end face LS1 to a portion of the first main face TS1, a portion of the second main face TS2, a portion of the first side face WS1, and a portion of the second side face WS2. The second conductive resin layer 60B is configured to cover the second base electrode layer 50B. In this embodiment, the second conductive resin layer 60B is formed extending from the second end face LS2 to a portion of the first main face TS1, a portion of the second main face TS2, a portion of the first side face WS1, and a portion of the second side face WS2. Here, the length direction L of the first conductive resin layer 60A on the first main face TS1 and the second main face TS2 is longer than the length direction L of the first base electrode layer 50A on the first main face TS1 and the second main face TS2. Furthermore, the dimension of the length direction L on the first main surface TS1 and the second main surface TS2 of the second conductive resin layer 60B is longer than the dimension of the length direction L on the first main surface TS1 and the second main surface TS2 of the second base electrode layer 50B.

[0066] Regarding the thickness of the first conductive resin layer 60A located on the first end face LS1 side in the longitudinal direction, it is preferably 5 μm or more and 200 μm or less in the central part of the stacking direction T and the width direction W of the first conductive resin layer 60A.

[0067] Regarding the thickness of the second conductive resin layer 60B located on the second end face LS2 side in the longitudinal direction, it is preferably 5 μm or more and 200 μm or less in the central part of the stacking direction T and the width direction W of the second conductive resin layer 60B.

[0068] When a first conductive resin layer 60A is also provided on a portion of the first main surface TS1 side and a portion of the second main surface TS2 side, the thickness of the first conductive resin layer 60A provided in the stacking direction of this portion is preferably, for example, 5 μm or more and 200 μm or less at the central portion of the first conductive resin layer 60A provided in the length direction L and width direction W of this portion.

[0069] When a first conductive resin layer 60A is also provided on a portion of the first side WS1 and a portion of the second side WS2, the thickness of the first conductive resin layer 60A provided in the width direction of this portion is preferably, for example, 5 μm or more and 200 μm or less at the center of the first conductive resin layer 60A provided in the length direction L and the stacking direction T of this portion.

[0070] When a second conductive resin layer 60B is also provided on a portion of the first main surface TS1 side and a portion of the second main surface TS2 side, the thickness of the second conductive resin layer 60B provided in the stacking direction of this portion is preferably, for example, 5 μm or more and 200 μm or less at the center of the length direction L and width direction W of the second conductive resin layer 60B provided in this portion.

[0071] When a second conductive resin layer 60B is also provided on a portion of the first side WS1 and a portion of the second side WS2, the thickness of the second conductive resin layer 60B provided in the width direction of this portion is preferably, for example, 5 μm or more and 200 μm or less at the center of the second conductive resin layer 60B provided in the length direction L and the stacking direction T of this portion.

[0072] A conductive resin layer 60 is disposed on the substrate electrode layer 50. Furthermore, a plating layer 70 is disposed to cover the conductive resin layer 60. The plating layer 70 has a Ni plating layer 71 and a Sn plating layer 72.

[0073] The conductive resin layer 60 has a resin portion as a resin component and a conductive filler as a filler powder dispersed within the resin portion.

[0074] The resin portion of the conductive resin layer 60 may, for example, contain at least one selected from various known thermosetting resins such as epoxy resin, phenoxy resin, phenolic resin, polyurethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, with its excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, the resin portion of the conductive resin layer 60 preferably contains a curing agent together with the thermosetting resin. When using epoxy resin as the base resin, the curing agent for the epoxy resin may also be various known compounds such as phenolic, amine, acid anhydride, imidazole, reactive ester, and amide-imide compounds.

[0075] Because the conductive resin layer 60 contains such a resin portion, it is more flexible than, for example, the base electrode layer 50, which is a plated film or a sintered product containing metal and glass components. Therefore, even when the multilayer ceramic capacitor 1 is subjected to a physical impact, such as an impact caused by thermal cycling, the conductive resin layer 60 functions as a buffer layer. Thus, the conductive resin layer 60 suppresses the formation of cracks in the multilayer ceramic capacitor 1.

[0076] The conductive filler is dispersed in a generally uniform distribution within the resin layer. The conductive filler primarily serves to conduct electricity through the conductive resin layer 60. Specifically, by having multiple conductive fillers in contact with each other, a current-carrying path is formed within the conductive resin layer 60, establishing a connection between the substrate electrode layer 50 and the plating layer 70.

[0077] The metal constituting the conductive filler can be either Ag monomer or an alloy containing Ag, or Ag-coated metal powder. Ag has the lowest resistivity among metals, making it suitable for electrode materials. Furthermore, Ag is a noble metal, thus it is not easily oxidized and has high weather resistance. Therefore, Ag metal powder is suitable as a conductive filler. Moreover, when using metal powder with Ag coating on its surface, Cu, Ni, Sn, Bi, or alloy powders containing them are preferred.

[0078] Furthermore, the conductive filler can also be a conductive filler that has undergone anti-oxidation treatment on Cu or Ni. Alternatively, the conductive filler can be metal powder coated with Sn, Ni, or Cu. When using metal powder coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of the above. The conductive filler is more preferably Cu particles having a core. Furthermore, it is more preferable that at least a portion of the surface of the Cu particles is coated with a Cu-Ag alloy of Cu and Ag. Alternatively, at least a portion of the surface of the Cu particles may be coated with Ag. This improves the affinity with Ni plating and enhances the electrical properties.

[0079] The shape of the conductive filler is not particularly limited. Spherical, flat, and other conductive fillers can be used. A mixture of spherical and flat metal powders is preferred. In other words, the conductive filler powder includes either flat or spherical powder.

[0080] The average particle size of the conductive filler can be, for example, greater than 0.3 μm and less than 10 μm.

[0081] Furthermore, the method for determining the average particle size of the conductive filler contained in the conductive resin layer 60 is independent of the shape of the conductive filler, and is calculated by laser diffraction particle size determination based on ISO 13320.

[0082] The plating layer 70 has a first plating layer 70A and a second plating layer 70B.

[0083] The first plating layer 70A is configured to cover the first conductive resin layer 60A. In this embodiment, the first plating layer 70A is configured to extend from the first end face LS1 to a portion of the first main face TS1 and a portion of the second main face TS2, and a portion of the first side face WS1 and a portion of the second side face WS2.

[0084] The second plating layer 70B is configured to cover the second conductive resin layer 60B. In this embodiment, the second plating layer 70B is configured to extend from the first end face LS1 to a portion of the first main face TS1 and a portion of the second main face TS2, and a portion of the first side face WS1 and a portion of the second side face WS2.

[0085] The plating layer 70 preferably has a two-layer structure consisting of a Ni plating layer 71 and a Sn plating layer 72. Preferably, a first Sn plating layer 72A is disposed on the first Ni plating layer 71A, and preferably a second Sn plating layer 72B is disposed on the second Ni plating layer 71B. The Ni plating layer 71 prevents the base electrode layer 50 and the conductive resin layer 60 from being eroded by solder during the mounting of the multilayer ceramic capacitor 1. The Sn plating layer 72 improves the wettability of the solder during the mounting of the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1.

[0086] The thickness of the first Ni plating layer 71A and the first Sn plating layer 72A is preferably 5 μm or more and 15 μm or less.

[0087] The thickness of the second Ni plating layer 71B and the second Sn plating layer 72B is preferably 5 μm or more and 15 μm or less.

[0088] Figure 5 yes Figure 2 The enlarged view of the V portion of the multilayer ceramic capacitor 1 shown is a schematic diagram for explaining in detail the structure of the ridge portion 10a, which will be described later in the multilayer ceramic capacitor 1.

[0089] Here, Figure 2 The four ridge portions 10a1 to 10a4 of the stacked body 10 shown have the same basic structure. Furthermore, the four extension portions E1 to E4 of the external electrode 40 have the same basic structure. Therefore, using... Figure 5 As a representative diagram, four regions are illustrated. Furthermore, as previously stated, the basic structures of the first external electrode 40A and the second external electrode 40B are identical; therefore, in Figure 5 They are also uniformly referred to as external electrodes 40. The same applies to other layers constituting the first external electrode 40A and the second external electrode 40B.

[0090] like Figure 5 As shown, the external electrode 40 has a base electrode layer 50, a conductive resin layer 60 disposed on the base electrode layer 50, and a plating layer 70 disposed on the conductive resin layer 60. The external electrode 40 has an extension E disposed extending to a portion of the main surface TS. The laminate 10 has a ridge portion 10a at the portion where the end face LS intersects with the main surface TS. The conductive resin layer 60 is disposed on the ridge portion 10a of the laminate 10.

[0091] The first external electrode 40A and the second external electrode 40B each have an extension E that extends to a portion of the first main surface TS1 and a portion of the second main surface TS2, respectively. In this embodiment, the first external electrode 40A and the second external electrode 40B also have an extension E that extends to a portion of the first side surface WS1 and a portion of the second side surface WS2, respectively.

[0092] For example, such as Figure 2 , 4 As shown in Figure 5, the extension E in this embodiment has a first extension E1, a second extension E2, a third extension E3, a fourth extension E4, a fifth extension E5, a sixth extension E6, a seventh extension E7, and an eighth extension E8.

[0093] like Figure 2 , 5 As shown, the first extension E1 is a portion of the first external electrode 40A that extends into a part of the first main surface TS1. Figure 2 , 5 As shown, the second extension E2 is a portion of the first external electrode 40A that extends into a part of the second main surface TS2.

[0094] like Figure 2 , 5 As shown, the third extension E3 is a portion of the second external electrode 40B that extends into a part of the first main surface TS1. Figure 2 , 5 As shown, the fourth extension E4 is a portion of the second external electrode 40B that extends into a part of the second main surface TS2.

[0095] like Figure 4 As shown, the fifth extension E5 is a portion of the first external electrode 40A that extends into a part of the first side WS1. Figure 4 As shown, the sixth extension E6 is a portion of the first external electrode 40A that extends to a part of the second side WS2.

[0096] like Figure 4 As shown, the 7th extension E7 is a portion of the 2nd external electrode 40B that extends into a part of the 1st side WS1. Figure 4 As shown, the 8th extension E8 is a portion of the 2nd external electrode 40B that extends to a part of the 2nd side WS2.

[0097] The structure of the extension E is not limited to this. For example, the extension E may be disposed on at least the first main surface TS1 and the second main surface TS2 in the first external electrode 40A and the second external electrode 40B.

[0098] The laminate 10 has ridge portions 10a at the portions where the first end face LS1 intersects with the first main face TS1, the portions where the first end face LS1 intersects with the second main face TS2, the portions where the second end face LS2 intersects with the first main face TS1, and the portions where the second end face LS2 intersects with the second main face TS2. In this embodiment, the laminate 10 also has ridge portions 10a at the portions where the first end face LS1 intersects with the first side face WS1, the portions where the first end face LS1 intersects with the second side face WS2, the portions where the second end face LS2 intersects with the first side face WS1, and the portions where the second end face LS2 intersects with the second side face WS2.

[0099] For example, the ridge portion 10a according to this embodiment has a first ridge portion 10a1, a second ridge portion 10a2, a third ridge portion 10a3, a fourth ridge portion 10a4, a fifth ridge portion 10a5, a sixth ridge portion 10a6, a seventh ridge portion 10a7, and an eighth ridge portion 10a8.

[0100] like Figure 2 , 5 As shown, the first ridge portion 10a1 is the part where the first end face LS1 and the first main face TS1 intersect. (As shown...) Figure 2 , 5 As shown, the second ridge portion 10a2 is the part where the first end face LS1 and the second main face TS2 intersect.

[0101] like Figure 2 , 5 As shown, the third ridge portion 10a3 is the part where the second end face LS2 and the first main face TS1 intersect. Figure 2 , 5 As shown, the fourth ridge 10a4 is the part where the second end face LS2 and the second main face TS2 intersect.

[0102] like Figure 4 As shown, the fifth ridge portion 10a5 is the part where the first end face LS1 and the first side face WS1 intersect. Figure 4 As shown, the sixth ridge 10a6 is the part where the first end face LS1 and the second side face WS2 intersect.

[0103] like Figure 4 As shown, the 7th ridge portion 10a7 is the part where the 2nd end face LS2 and the 1st side face WS1 intersect. Figure 4 As shown, the 8th ridge 10a8 is the part where the 2nd end face LS2 and the 2nd side face WS2 intersect.

[0104] A conductive resin layer 60 is disposed on the ridge portion 10a of the laminate 10, separated from the base electrode layer 50. That is, the conductive resin layer 60 is disposed on the ridge portion 10a of the laminate 10, such that it is sandwiched between the base electrode layer 50 and the plating layer 70. The thickness of the conductive resin layer 60 at the ridge portion 10a of the laminate 10 is thinner than the thickness of the conductive resin layer 60 at other portions, namely, the thickness of the conductive resin layer 60 at the end face LS of the laminate 10, the main face TS of the laminate 10, and the side face WS of the laminate 10. The film thickness t of the conductive resin layer 60 on the ridge portion 10a is preferably 0.8 μm or more and 8 μm or less.

[0105] When the plating layer 70 is disposed across the ridge portion 10a, the deflection generated on the main surface TS or side surface WS of the external electrode 40 may sometimes propagate to the end face LS of the laminate 10. However, if a conductive resin layer 60 is disposed on the ridge portion 10a, the flexibility of the conductive resin layer 60 can suppress the propagation of the deflection generated on the main surface TS or side surface WS of the external electrode 40 to the end face LS of the laminate 10.

[0106] like Figure 2 , 5 As shown, a first conductive resin layer 60A is disposed on the first ridge portion 10a1 of the laminate 10 according to this embodiment. Figure 2 , 5 As shown, a first conductive resin layer 60A is disposed on the second ridge portion 10a2 of the laminate 10 according to this embodiment. Figure 2 , 5 As shown, a second conductive resin layer 60B is disposed on the third ridge portion 10a3 of the laminate 10 according to this embodiment. Figure 2 , 5 As shown, a second conductive resin layer 60B is disposed on the fourth ridge portion 10a4 of the laminate 10 according to this embodiment.

[0107] like Figure 4 As shown, a first conductive resin layer 60A is disposed on the fifth ridge portion 10a5 of the laminate 10 according to this embodiment. Figure 4 As shown, a first conductive resin layer 60A is disposed on the sixth ridge portion 10a6 of the laminate 10 according to this embodiment. Figure 4 As shown, a second conductive resin layer 60B is disposed on the seventh ridge portion 10a7 of the laminate 10 according to this embodiment. Figure 4 As shown, a second conductive resin layer 60B is disposed on the eighth ridge portion 10a8 of the laminate 10 according to this embodiment.

[0108] The conductive resin layer 60 has a peeling region P in at least one extension E, which is peeled off from the laminate 10. The peeling region P is disposed in the region extending from the ends 60Aa and 60Ba on the central side of the laminate in the longitudinal direction L of the conductive resin layer 60 to the area in front of the ends 50Aa and 50Ba on the central side of the laminate in the longitudinal direction L of the substrate electrode layer 50. That is, the peeling region P does not reach the ends 50Aa and 50Ba on the central side of the laminate in the longitudinal direction L of the substrate electrode layer 50. The dimension of the peeling region P in the longitudinal direction L is preferably 5 μm or more. Furthermore, a particularly high efficiency can be obtained by disposing the peeling region P on the mounting surface side, but this is not a limitation.

[0109] At least one side of the first conductive resin layer 60A and the second conductive resin layer 60B has a peeling region P that is peeled off from the laminate 10 on either of the first main surface TS1 and the second main surface TS2 on the surface that is in contact with the ridge portion 10a.

[0110] For example, such as Figure 2 , 5 As shown, the first conductive resin layer 60A according to this embodiment has a first peeling region P1 on the first main surface TS1 that is in contact with the first ridge portion 10a1, which is peeled off from the laminate 10. Figure 2 , 5 As shown, the first conductive resin layer 60A according to this embodiment has a second peeling region P2 on the second main surface TS2 that is in contact with the second ridge portion 10a2, which is peeled off from the laminate 10.

[0111] like Figure 2 , 5 As shown, the second conductive resin layer 60B according to this embodiment has a third peeling region P3 on the first main surface TS1 that is in contact with the third ridge portion 10a3, which is peeled off from the laminate 10. Figure 2 , 5 As shown, the second conductive resin layer 60B according to this embodiment has a fourth peeling region P4 on the second main surface TS2 that is in contact with the fourth ridge portion 10a4, which is peeled off from the laminate 10.

[0112] For example, such as Figure 4 As shown, the first conductive resin layer 60A according to this embodiment has a fifth peeling region P5 on the first side surface WS1 that is in contact with the fifth ridge portion 10a5, which is peeled off from the laminate 10. Figure 4 As shown, the first conductive resin layer 60A according to this embodiment has a sixth peeling region P6 on the second side surface WS2 that is in contact with the sixth ridge portion 10a6, which is peeled off from the laminate 10.

[0113] like Figure 4As shown, the second conductive resin layer 60B according to this embodiment has a seventh peeling region P7 on the first main surface TS1 that is in contact with the seventh ridge portion 10a7, which is peeled off from the laminate 10. Figure 4 As shown, the second conductive resin layer 60B according to this embodiment has an eighth peeling region P8 on the second main surface TS2 that is in contact with the eighth ridge portion 10a8, which is peeled off from the laminate 10.

[0114] That is, the peeling region P involved in this embodiment has a first peeling region P1, a second peeling region P2, a third peeling region P3, a fourth peeling region P4, a fifth peeling region P5, a sixth peeling region P6, a seventh peeling region P7, and an eighth peeling region P8. The structure of the peeling region P is not limited to this. The peeling region P may not be disposed in all the extensions E of the first conductive resin layer 60A and the second conductive resin layer 60B extending to the main surface TS and the side surface WS. For example, the peeling region P may only be disposed in the extension E extending to the main surface TS.

[0115] For example, the stripping region P may also be an extension of at least one of the first extension E1 on the first main surface TS1 side of the first external electrode 40A and the second extension E2 on the second main surface TS2 side, and an extension of at least one of the third extension E3 on the first main surface TS1 side and the fourth extension E4 on the second main surface TS2 side of the second external electrode 40B.

[0116] In addition, the stripping region P can also be configured in the first extension E1 on the first main surface TS1 side of the first external electrode 40A and the third extension E3 on the first main surface TS1 side of the second external electrode 40B, or in the second extension E2 on the second main surface TS2 side of the first external electrode 40A and the fourth extension E4 on the second main surface TS2 side of the second external electrode 40B.

[0117] In addition, the stripping region P can also be configured in the first extension E1 on the first main surface TS1 side of the first external electrode 40A and the second extension E2 on the second main surface TS2 side, or in the third extension E3 on the first main surface TS1 side of the second external electrode 40B and the fourth extension E4 on the second main surface TS2 side.

[0118] In addition, the stripping region P can also be configured in the first extension E1 on the first main surface TS1 side of the first external electrode 40A and the second extension E2 on the second main surface TS2 side, and the third extension E3 on the first main surface TS1 side and the fourth extension E4 on the second main surface TS2 side of the second external electrode 40B.

[0119] The thickness of the conductive resin layer on the ridge portion 10a at the intersection of the main surface TS and the end surface LS of the laminate 10, which has an extension E with a peeling region P, is preferably 0.8 μm or more and 8 μm or less. In this embodiment, all extensions E have peeling regions P.

[0120] In this embodiment, the thickness of the first conductive resin layer 60A on the first ridge portion 10a1 is 0.8 μm or more and 8 μm or less. In this embodiment, the thickness of the first conductive resin layer 60A on the second ridge portion 10a2 is 0.8 μm or more and 8 μm or less.

[0121] In this embodiment, the thickness of the second conductive resin layer 60B on the third ridge portion 10a3 is 0.8 μm or more and 8 μm or less. In this embodiment, the thickness of the second conductive resin layer 60B on the fourth ridge portion 10a4 is 0.8 μm or more and 8 μm or less.

[0122] In this embodiment, the thickness of the first conductive resin layer 60A on the fifth ridge portion 10a5 is 0.8 μm or more and 8 μm or less. In this embodiment, the thickness of the first conductive resin layer 60A on the sixth ridge portion 10a6 is 0.8 μm or more and 8 μm or less.

[0123] In this embodiment, the thickness of the second conductive resin layer 60B on the 7th ridge portion 10a7 is 0.8 μm or more and 8 μm or less. In this embodiment, the thickness of the second conductive resin layer 60B on the 8th ridge portion 10a8 is 0.8 μm or more and 8 μm or less.

[0124] <Measurement of the film thickness of the conductive resin layer on the ridge>

[0125] The following uses Figure 5 The film thickness measurement of the conductive resin layer 60 on the ridge portion 10a will be explained. The film thickness measurement of the conductive resin layer 60 on the ridge portion 10a is based on observation using SEM (scanning electron microscope).

[0126] SEM observation for measuring the thickness of the conductive resin layer 60 on the ridge portion 10a was performed in an LT section that was almost parallel to the first side WS1 and the second side WS2 at a position approximately at the center of the width direction W of the laminate 10.

[0127] First, use pliers to break the laminate 10 at approximately the center of its width direction W, exposing the LT section of the laminate 10 of the ceramic capacitor 1.

[0128] Then, the fracture surface was heat-treated at 1000°C for 30 minutes, and a pretreatment was performed to facilitate observation of the conductive resin layer. After treatment using the aforementioned method, the measurement area was imaged at a high magnification of 20,000 using SEM. The outer edge of the conductive resin layer was delineated and its thickness measured using analysis software in the captured images.

[0129] like Figure 5 As shown, in measuring the thickness of the conductive resin layer 60 on the ridge portion 10a, a bisecting line is drawn such that the angle between the end face LS and the main face TS is bisected at an angle θ. In this embodiment, the angle between the end face LS and the main face TS is approximately 90°, therefore the bisecting line is drawn such that the angle θ = 45° is bisected. The thickness of the conductive resin layer 60 is measured in the direction of the drawn bisecting line.

[0130] The thickness of the conductive resin layer 60 on the ridge portion 10a is measured at four locations: the ridge portion 10a1 where the first end face LS1 and the first main face TS1 intersect, the ridge portion 10a2 where the first end face LS1 and the second main face TS2 intersect, the ridge portion 10a3 where the second end face LS2 and the first main face TS1 intersect, and the ridge portion 10a4 where the second end face LS2 and the second main face TS2 intersect. The average value of these measurements is taken as the film thickness t of the conductive resin layer 60 on the ridge portion 10a in this disclosure.

[0131] The stripping region P is disposed in the area from the end (60Aa, 60Ba) of the laminate in the longitudinal direction L of the conductive resin layer 60 to the end (50Aa, 50Ba) of the laminate in the longitudinal direction L of the substrate electrode layer 50. That is, the stripping region P does not reach the end (50Aa, 50Ba) of the laminate in the longitudinal direction L of the substrate electrode layer 50.

[0132] The first stripping region P1 in this embodiment is disposed in the length direction L between the end 60Aa of the laminate on the central side of the first conductive resin layer 60A in the length direction L and the end 50Aa of the laminate on the central side of the first base electrode layer 50A in the length direction L.

[0133] The second stripping region P2 in this embodiment is disposed in the length direction L between the end 60Aa of the laminate on the central side of the first conductive resin layer 60A in the length direction L and the end 50Aa of the laminate on the central side of the first base electrode layer 50A in the length direction L.

[0134] The third peeling region P3 in this embodiment is disposed in the length direction L between the end 60Ba on the central side of the laminate in the length direction L of the second conductive resin layer 60B and the end 50Ba on the central side of the laminate in the length direction L of the second base electrode layer 50B.

[0135] The fourth peeling region P4 in this embodiment is disposed in the length direction L between the end 60Ba on the central side of the laminate in the length direction L of the second conductive resin layer 60B and the end 50Ba on the central side of the laminate in the length direction L of the second base electrode layer 50B.

[0136] The fifth peeling region P5 in this embodiment is disposed in the length direction L between the end 60Aa of the laminate on the central side of the first conductive resin layer 60A in the length direction L and the end 50Aa of the laminate on the central side of the first base electrode layer 50A in the length direction L.

[0137] The sixth peeling region P6 in this embodiment is disposed in the length direction L between the end 60Aa of the laminate on the central side of the first conductive resin layer 60A in the length direction L and the end 50Aa of the laminate on the central side of the first base electrode layer 50A in the length direction L.

[0138] The seventh peeling region P7 in this embodiment is disposed in the length direction L between the end 60Ba on the central side of the laminate in the length direction L of the second conductive resin layer 60B and the end 50Ba on the central side of the laminate in the length direction L of the second base electrode layer 50B.

[0139] The eighth stripping region P8 in this embodiment is disposed in the length direction L between the end 60Ba on the central side of the laminate in the length direction L of the second conductive resin layer 60B and the end 50Ba on the central side of the laminate in the length direction L of the second base electrode layer 50B.

[0140] The end 50Aa of the first base electrode layer 50A on the inner side of the laminate 10 along the length direction L is positioned on the outer side of the laminate 10 along the length direction L, relative to any of the first peeling region P1, the second peeling region P2, the fifth peeling region P5, and the sixth peeling region P6. That is, none of the first peeling region P1, the second peeling region P2, the fifth peeling region P5, and the sixth peeling region P6 reaches the inner end of the first base electrode layer 50A in the laminate 10 along the length direction L.

[0141] The end 50Ba of the second base electrode layer 50B, located on the inner side of the laminate 10 along the length direction L, is positioned on the outer side of the laminate 10 along the length direction L, relative to any of the third peeling region P3, the fourth peeling region P4, the seventh peeling region P7, and the eighth peeling region P8. That is, none of the third peeling region P3, the fourth peeling region P4, the seventh peeling region P7, or the eighth peeling region P8 reaches the inner end of the second base electrode layer 50B in the laminate 10 along the length direction L.

[0142] The dimension d of the length direction L of the peeling region P is 5 μm or more. In this embodiment, the dimension d1 of the length direction L of the first peeling region P1 is 5 μm or more. In this embodiment, the dimension d2 of the length direction L of the second peeling region P2 is 5 μm or more.

[0143] In this embodiment, the dimension d3 of the length direction L of the third peeling region P3 is 5 μm or more. The dimension d4 of the length direction L of the fourth peeling region P4 in this embodiment is 5 μm or more.

[0144] In this embodiment, the dimension d5 of the length direction L of the fifth peeling region P5 is 5 μm or more. The dimension d6 of the length direction L of the sixth peeling region P6 in this embodiment is 5 μm or more.

[0145] In this embodiment, the length direction L dimension d7 of the 7th peeling region P7 is 5 μm or more. The length direction L dimension d8 of the 8th peeling region P8 in this embodiment is 5 μm or more.

[0146] <Determination of the length dimension of the peeled area>

[0147] The method for measuring the length L of the peeled region P in this embodiment will be described below. The measurement of the length L of the peeled region P is based on observation using SEM (scanning electron microscope).

[0148] SEM observations for determining the dimensions of the stripped region P along the length direction L were performed in an LT section that was almost parallel to the first side WS1 and the second side WS2, located approximately at the center of the width direction W of the laminate 10.

[0149] First, the section of the laminate 10 is ground at approximately the center position in the width direction W, so that the LT section of the laminate 10 of the ceramic capacitor 1 is exposed.

[0150] The target area was photographed using SEM at a high magnification of 20,000. Analysis software was used to delineate the extension E and the outer edge of the laminate 10 in the captured images and to determine the peeling region P. The dimension d of the longitudinal direction L of the determined peeling region P was measured.

[0151] The first Ni plating layer 71A is formed such that tensile stress is uniformly generated throughout in the direction intersecting the thickness direction of the first plating layer 70A. In other words, tensile stress remains as internal stress within the first Ni plating layer 71A. The portion of the first Ni plating layer 71A included in the extension E generates tensile stress in the direction intersecting the thickness direction of the first plating layer 70A, and therefore tends to contract in the direction intersecting the thickness direction of the plating layer 70A. The first conductive resin layer 60A, which is connected to and fixed to the portion of the first Ni plating layer 71A included in the extension E, is subjected to compressive stress in the contraction direction. Therefore, the first Ni plating layer 71A in the extension E and the first conductive resin layer 60A connected to and fixed to the first Ni plating layer 71A are subjected to compressive stress in the extension E portion of the first Ni plating layer 71A. Figure 5 In the extension E shown, the bending moment caused by the resultant force of these internal stresses, which causes warping towards the surface side of the first plating layer 70A, promotes peeling in the peeling region P of the extension E, and further improves the flexural resistance.

[0152] Furthermore, preferably, in the extension E of the peeling region P where the conductive resin layer 60 is peeled from the laminate 10, the ends of the Ni plating layer 71 and the Sn plating layer 72 are also peeled from the laminate 10, leaving tensile stress as internal stress within the Ni plating layer 71. This promotes peeling in the peeling region P of the extension E, further improving flexural strength.

[0153] Furthermore, if the length dimension of the multilayer ceramic capacitor 1, including the laminate 10 and the external electrode 40, is defined as dimension L, then dimension L is preferably 0.2 mm or more and 10 mm or less. Furthermore, if the dimension in the lamination direction of the multilayer ceramic capacitor 1 is defined as dimension T, then dimension T is preferably 0.1 mm or more and 10 mm or less. Furthermore, if the width dimension of the multilayer ceramic capacitor 1 is defined as dimension W, then dimension W is preferably 0.1 mm or more and 10 mm or less.

[0154] Next, the manufacturing method of the multilayer ceramic capacitor 1 according to this embodiment will be described. The manufacturing method of the multilayer ceramic capacitor 1 according to this embodiment is not limited as long as the above-described necessary conditions are met. However, a suitable manufacturing method includes the following steps. Details of each step will be described below.

[0155] Prepare a dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30. The conductive paste for the dielectric sheet and the internal electrode includes an adhesive and a solvent. The adhesive and solvent can be known adhesives and solvents.

[0156] Conductive paste for the inner electrode layer 30 is printed on the dielectric sheet in a given pattern, for example by screen printing, gravure printing, etc. Thus, a dielectric sheet having a pattern of the first inner electrode layer 31 and a dielectric sheet having a pattern of the second inner electrode layer 32 are prepared.

[0157] A portion forming the first main surface outer layer 12A on the first main surface TS1 side is formed by stacking a given number of dielectric sheets without printed internal electrode layer patterns. On this, dielectric sheets with printed first internal electrode layer 31 patterns and dielectric sheets with printed second internal electrode layer 32 patterns are sequentially stacked, thereby forming the inner layer 11. A given number of dielectric sheets without printed internal electrode layer patterns are stacked on this inner layer 11, thereby forming the second main surface outer layer 12B on the second main surface TS2 side. Thus, a laminated sheet is manufactured.

[0158] Laminated blocks are produced by pressing laminated sheets in the lamination direction using methods such as isostatic pressing.

[0159] By cutting the laminated blocks to a given size, small laminated pieces are cut out. At this time, the corners and edges of the small laminated pieces can also be rounded by methods such as tumbling.

[0160] The laminate 10 is fabricated by firing the stacked small pieces. Although the firing temperature also depends on the materials of the dielectric layer 20 and the internal electrode layer 30, it is preferably above 900°C and below 1400°C.

[0161] A conductive paste, forming a base electrode layer 50, is applied to both ends of the laminate 10. In this embodiment, the base electrode layer 50 is a sintered layer. The conductive paste, containing glass components and metal, is applied to the laminate 10, for example, by impregnation. Then, a sintering process is performed to form the base electrode layer 50. The sintering temperature is preferably 700°C or higher and 950°C or lower.

[0162] Next, a conductive resin layer 60 is formed. Alternatively, the conductive resin layer 60 can be formed on the surface of the substrate electrode layer 50 or directly on the laminate 10. In this embodiment, the conductive resin layer 60 is formed on the surface of the substrate electrode layer 50.

[0163] First, a conductive resin paste is prepared by dispersing a conductive filler in a thermosetting resin, which serves as the base resin. This conductive resin paste is generated by stirring and mixing the thermosetting resin and the conductive filler. Therefore, the conductive filler is uniformly dispersed within the conductive resin paste. Here, the thermosetting resin is, for example, an epoxy resin. The conductive filler is, for example, Ag metal powder.

[0164] Then, a conductive resin paste is applied to the substrate electrode layer 50 using an impregnation method, and heat-treated at a temperature of 200°C or higher and 550°C or lower. This heat-cures the resin, forming a conductive resin layer 60. The atmosphere during this heat treatment is preferably N2. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0165] The thickness of the conductive resin layer on the ridge portion can be controlled by adjusting the viscosity of the resin electrode and the coating conditions. The peeling area can be controlled by adjusting the thickness of the conductive resin layer, or by adjusting the thickness of the Ni plating with residual tensile stress (described later).

[0166] Then, a plating layer 70 is formed on the surface of the conductive resin layer 60. In this embodiment, a Ni plating layer 71 and a Sn plating layer 72 are formed on the conductive resin layer 60. The Ni plating layer 71 and the Sn plating layer 72 are formed sequentially using an electric field plating method. As a plating method, for example, roller plating is preferred.

[0167] The stress generated in the first Ni plating layer 71A and the second Ni plating layer 71B of the present invention can be controlled by the following method.

[0168] Furthermore, it is known that the stress generated during plating varies depending on the current density applied during film formation. The current density applied to the multilayer ceramic capacitor 1 is random. At the leading edge of the Ni plating layer located on the first main surface TS1, the second main surface TS2, the first side surface WS1, or the second side surface WS2, from the initial stage of Ni plating film formation until a thickness of, for example, 3 μm is reached, the average current density applied to each leading edge is the same on any surface of the leading edge of the Ni plating layer located on the first main surface TS1, the second main surface TS2, the first side surface WS1, or the second side surface WS2. Therefore, the same stress is applied to any surface of the Ni plating layer 71 on the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2.

[0169] The formation of the first Ni plating layer 71A and the second Ni plating layer 71B is achieved, for example, by treating the plating solution with an adjusted amount of stress-relieving agent, thereby forming a Ni plating layer with residual tensile stress as internal stress within the Ni plating layer. This residual stress acts as a bending moment, such as warping towards the surface of the plating layer 70, promoting peeling in the peeling region P of the extension E, and further improving flexural resistance.

[0170] In this embodiment, a Sn plating layer 72 is further formed on the Ni plating layer 71, a first Sn plating layer 72A is formed on the first Ni plating layer 71A, and a second Sn plating layer 72B is formed on the second Ni plating layer 71B. Electrolytic plating is used as the method for forming the Sn plating layer 72. Roller plating is preferably used as the plating process. Therefore, when mounting the multilayer ceramic capacitor 1, the wettability of the solder used for mounting can be improved, and mounting can be facilitated. The multilayer ceramic capacitor 1 is manufactured using the above manufacturing method.

[0171] The laminated ceramic capacitor 1 according to this embodiment achieves the following effects.

[0172] (1) The multilayer ceramic capacitor 1 according to this embodiment has: a multilayer body 10, comprising a plurality of multilayer dielectric layers 20, and having a first main surface TS1 and a second main surface TS2 opposite to each other in the height direction T, a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W orthogonal to the height direction T, and a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L orthogonal to the height direction T and the width direction W; a first internal electrode layer 31 disposed on the plurality of dielectric layers 20, The first internal electrode layer 32 is exposed on the first end face LS1; the second internal electrode layer 32 is disposed on a plurality of dielectric layers 20 and exposed on the second end face LS2; the first external electrode 40A is disposed on the first end face LS1; and the second external electrode 40B is disposed on the second end face LS2, wherein the first external electrode 40A and the second external electrode 40B have a base electrode layer 50 containing a metal component, a conductive resin layer 60 containing filler powder and resin component disposed on the base electrode layer 50, and a conductive resin layer 60 disposed on the conductive resin layer 60. The plating layer 70 on the 0, the first external electrode 40A and the second external electrode 40B respectively have extensions E that extend to a portion of the first main surface TS1 and a portion of the second main surface TS2, the laminate 10 has ridge portions 10a at the portions where the first end surface LS1 intersects with the first main surface TS1, the portions where the first end surface LS1 intersects with the second main surface TS2, the portions where the second end surface LS2 intersects with the first main surface TS1, and the portions where the second end surface LS2 intersects with the second main surface TS2, and the portions where the second end surface LS2 intersects with the second main surface TS2. A conductive resin layer 60 is disposed on the ridge portion 10a. The thickness of the conductive resin layer 60 on the ridge portion 10a is 0.8 μm or more and 8 μm or less. The conductive resin layer 60 has a peeling region P in at least one extension E that is peeled off from the laminate 10. The peeling region P is disposed in the region from the end of the laminate central side in the length direction L of the conductive resin layer 60 to the end of the laminate central side in the length direction of the substrate electrode layer 50. The dimension of the peeling region P in the length direction is 5 μm or more.

[0173] Therefore, by having a conductive resin layer 60 with a thickness of 0.8 μm or more and 8 μm or less at the ridge portion 10a of the laminate 10, flexural stress is not easily transmitted to the laminate 10 at this ridge portion 10a, thus improving flexural resistance. Furthermore, by having a peeling region P with a length direction L dimension of 5 μm or more that does not reach the substrate electrode layer 50, flexural stress is not easily transmitted to the laminate 10, thus improving flexural resistance.

[0174] (2) In the multilayer ceramic capacitor 1 of this embodiment, the conductive filler has Cu particles as the core, and at least a portion of the surface of the Cu particles is coated with a Cu-Ag alloy of Cu and Ag.

[0175] Therefore, the conductive resin layer 60 has good electrical properties, which can improve flexural strength while ensuring good affinity with Ni plating.

[0176] (3) The conductive filler includes flat powder or spherical powder.

[0177] Therefore, the conductive resin layer 60 has good electrical properties, which can improve flexural strength while ensuring good affinity with Ni plating.

[0178] (4) The plating layer 70 has a Ni plating layer 71 and a Sn plating layer 72 on the Ni plating layer 71, and tensile stress remains inside the Ni plating layer 71 as internal stress.

[0179] Therefore, by applying tensile stress to the conductive resin layer 60, peeling in the peeling region P is promoted, which can further improve flexural strength.

[0180] <Experimental Example>

[0181] Using the manufacturing method described in the above embodiments, samples were manufactured as experimental and comparative examples. Figures 1-5 A multilayer ceramic capacitor with a specific structure. Experimental and comparative examples were conducted to verify flexural resilience by varying the corner thickness while keeping the peel distance constant, and by varying the peel distance while keeping the corner thickness constant.

[0182] The peel distance is set as the distance from the front end of the central side of the laminate 10 along the longitudinal direction L of the external electrode 40. Specifically, experiments were conducted to change the corner thickness while keeping the peel distance fixed, as described in Table 1, under seven conditions where the corner thickness was varied while keeping the peel distance fixed at 5 μm. Experiments were also conducted to change the peel distance while keeping the corner thickness fixed, as described in Table 2, under seven conditions where the peel distance was varied while keeping the corner thickness fixed at 0.8 μm.

[0183] Regarding the number of evaluation samples, for each of the above conditions, 20 samples were randomly selected from the same batch, and the corner thickness and peel distance were determined using the above measurement methods, and their average values ​​were obtained. For the confirmation of flexural toughness, another 20 samples from the same batch as those used for the corner thickness and peel distance measurements were selected according to each of the above conditions, and the measurements were performed and crack evaluations were conducted.

[0184] Furthermore, regarding the samples, samples were manufactured by controlling the corner thickness and peeling distance using the methods described above, achieving the corner thickness and peeling distance conditions specified in Tables 1 and 2. The specifications of the multilayer ceramic capacitors are as follows.

[0185] • Dimensions of multilayer ceramic capacitors: 1.5mm (length L) × 0.5mm (width W) × 0.5mm (stack direction T)

[0186] Ceramic material: BaTiO3

[0187] • Static capacitance: 0.01μF

[0188] Rated voltage: 50V

[0189] Construction of external electrodes

[0190] (1) Substrate electrode layer: an electrode containing conductive metal (Cu) and glass components.

[0191] The thickness of the substrate electrode layer located at the center of the substrate electrode layer in the height direction on the first and second end faces is 20 μm.

[0192] The thickness of the base electrode layer located at the center of the base electrode layer along its length on the first and second main surfaces, the first side surface, and the second side surface is 4 μm.

[0193] (2) Conductive resin layer

[0194] Conductive resin layer: Conductive filler: Cu particles coated with Cu-Ag alloy

[0195] Resin: Thermosetting system

[0196] Thickness at the center of the first conductive resin layer on both the first and second end faces in the height direction: 20 μm

[0197] The thickness of the base electrode layer located at the center of the base electrode layer along its length on the first and second main surfaces, the first side surface, and the second side surface is 20 μm.

[0198] (3) Ni plating layer

[0199] Ni plating thickness: The thickness of the Ni plating layer at the center of the height direction on both the first and second end faces is 3.0 μm.

[0200] The thickness of the Ni plating layer located at the center of the length direction of the Ni plating layer on the first and second main surfaces, the first and second side surfaces: 4.0 μm

[0201] (4) Sn plating layer

[0202] Sn plating thickness: The Sn plating thickness at the center of the height direction of the Sn plating layer located on the first and second end faces is 4.0 μm.

[0203] The thickness of the Sn plating layer located at the center of the Sn plating layer along its length on the first and second main surfaces, the first side surface, and the second side surface is 4.0 μm.

[0204] Next, flexural tests were conducted on the experimental and comparative samples using the following method. For the prepared multilayer ceramic capacitors, flexural tests were performed according to JIS C 6484, and the presence or absence of cracks in the dielectric layer was evaluated with the flexural amount fixed at 5 mm. Cracks that appeared during the flexural test were marked as "×", and no cracks were marked as "〇". The results of the flexural tests are shown in Tables 1 and 2.

[0205] [Table 1]

[0206]

[0207] [Table 2]

[0208]

[0209] As shown in Table 1, no cracks were generated in the multilayer ceramic capacitor with a corner thickness of 0.8 μm, which was used as an experimental example. In contrast, cracks were generated in the multilayer ceramic capacitor with a corner thickness of 0.5 μm, which was used as a comparative example.

[0210] As shown in Table 1, no cracks were generated in the multilayer ceramic capacitor with a corner thickness of 8 μm, which was used as an experimental example. In contrast, cracks were generated in the multilayer ceramic capacitor with no conductive resin layer on the edge portion and the multilayer ceramic capacitor with a corner thickness of 10 μm, which were used as comparative examples.

[0211] When the corner thickness is thin, stress concentration can be considered to occur within the base electrode layer 50, resulting in cracks originating within the base electrode layer 50. When the corner thickness is thick, although stress concentration does not occur within the base electrode layer 50, stress is applied to the ends of the base electrode layer 50, leading to stress concentration and thus crack formation. Experimental results confirm that when the corner thickness is between 0.8 μm and 8 μm, the propagation of flexural stress to the laminate 10 can be suppressed, improving flexural resilience.

[0212] As shown in Table 2, no cracks were generated in the multilayer ceramic capacitor with a peeling distance of 5 μm, which was used as an experimental example. In contrast, cracks were generated in the multilayer ceramic capacitor with no peeling area and the multilayer ceramic capacitor with a corner thickness of 2 μm, which were used as comparative examples.

[0213] As shown in Table 2, no cracks were generated in the multilayer ceramic capacitor of the experimental example. In contrast, cracks were generated in the multilayer ceramic capacitor of the comparative example, where the stripping region reached the end of the substrate electrode layer.

[0214] When the peeling area at the end of the substrate electrode layer 50 is small, it can be assumed that the stress concentration at the end of the substrate electrode layer 50 cannot be mitigated, resulting in cracks originating from the end of the substrate electrode layer 50. When the peeling area reaches the substrate electrode layer 50, it can be assumed that stress concentration occurs at the end of the substrate electrode layer 50, thus resulting in cracks originating from the end of the substrate electrode layer 50. Experimental results confirm that when the peeling distance is greater than 5 μm and the peeling area does not reach the end of the substrate electrode, the propagation of flexural stress to the laminate 10 can be suppressed, and the flexural resistance is improved.

[0215] Furthermore, the structure of the multilayer ceramic capacitor 1 is not limited to Figures 1-4 The structure shown. For example, the multilayer ceramic capacitor 1 could also be... Figure 6 , Figure 7 , Figure 8 Multilayer ceramic capacitors with dual, triple, and quadruple configurations as shown.

[0216] Figure 6 The stacked ceramic capacitor 1 shown is a dual-structure stacked ceramic capacitor 1. As an internal electrode layer 30, in addition to the first internal electrode layer 33 and the second internal electrode layer 34, it also has a floating internal electrode layer 35 that is not led out to either the first end face LS1 or the second end face LS2. Figure 7 The stacked ceramic capacitor 1 shown is a stacked ceramic capacitor 1 with a triple structure having a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as floating internal electrode layers 35. Figure 8 The illustrated multilayer ceramic capacitor 1 is a quadruple structure comprising a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C, which serve as floating internal electrode layers 35. In this way, by providing the floating internal electrode layer 35 as the internal electrode layer 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portions are divided into multiple parts. Consequently, multiple capacitor components are formed between the opposing internal electrode layers 30, forming a structure in which these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component is lower, and a high withstand voltage can be achieved for the multilayer ceramic capacitor 1. Furthermore, it is self-evident that the multilayer ceramic capacitor 1 of this embodiment can also be a multi-unit structure with four or more parts.

[0217] In addition, the multilayer ceramic capacitor 1 can be either a two-terminal multilayer ceramic capacitor with two external electrodes or a multi-terminal multilayer ceramic capacitor with many external electrodes.

[0218] This invention is not limited to the structures described in the above embodiments, and can be applied with appropriate modifications without changing the spirit of the invention. Furthermore, structures obtained by combining two or more of the preferred structures described in the above embodiments are also still part of this invention.

[0219] <1>

[0220] A multilayer ceramic capacitor having:

[0221] A laminate comprising a plurality of stacked dielectric layers, and having a first main surface and a second main surface opposite each other in the height direction, a first side surface and a second side surface opposite each other in the width direction orthogonal to the height direction, and a first end surface and a second end surface opposite each other in the length direction orthogonal to the height direction and the width direction.

[0222] A first internal electrode layer is disposed on the plurality of dielectric layers and exposed at the first end face;

[0223] A second internal electrode layer is disposed on the plurality of dielectric layers and exposed at the second end face;

[0224] A first external electrode is disposed on the first end face; and

[0225] The second external electrode is disposed on the second end face.

[0226] in,

[0227] The first external electrode and the second external electrode have a base electrode layer containing a metal component, a conductive resin layer containing filler powder and resin component disposed on the base electrode layer, and a plating layer disposed on the conductive resin layer.

[0228] The first external electrode and the second external electrode each have extensions that extend to a portion of the first main surface and a portion of the second main surface, respectively.

[0229] The laminate has ridge portions at the portions where the first end face and the first main face intersect, the portions where the first end face and the second main face intersect, the portions where the second end face and the first main face intersect, and the portions where the second end face and the second main face intersect.

[0230] The conductive resin layer is disposed on the ridge portion of the laminate.

[0231] The thickness of the conductive resin layer on the ridge portion is 0.8 μm or more and 8 μm or less.

[0232] The conductive resin layer has a peeling region in at least one of the extensions that is peeled off from the laminate.

[0233] The stripping region is located in the area from the end of the laminate on the central side of the length direction of the conductive resin layer to the end of the laminate on the central side of the length direction of the substrate electrode layer.

[0234] The length dimension of the stripped area is greater than 5 μm.

[0235] <2>

[0236] According to the multilayer ceramic capacitor described in <1>, among which,

[0237] The filler powder has Cu particles as a core, and at least a portion of the surface of the Cu particles is coated with a Cu-Ag alloy of Cu and Ag.

[0238] <3>

[0239] According to the multilayer ceramic capacitor described in <1> or <2>, wherein,

[0240] The filler powder includes flat powder or spherical powder.

[0241] <4>

[0242] According to any one of <1> to <3>, the multilayer ceramic capacitor described therein,

[0243] The plating layer has a Ni plating layer and a Sn plating layer disposed on the Ni plating layer.

[0244] Tensile stress remains inside the Ni plating layer as internal stress.

[0245] Explanation of reference numerals in the attached figures

[0246] 1. Multilayer ceramic capacitor

[0247] 10-layer stack

[0248] 10a Ridge section

[0249] 20 Dielectric layer

[0250] 31 First Inner Electrode Layer

[0251] 32 Second inner electrode layer

[0252] 40A First External Electrode

[0253] 40Aa end

[0254] 40B Second External Electrode

[0255] 40Ba end

[0256] 50A First base electrode layer

[0257] 50Aa end

[0258] 50B Second Substrate Electrode Layer

[0259] 50Ba end

[0260] 60A First conductive resin layer

[0261] 60B Second Conductive Resin Layer

[0262] 70A First Coating Layer

[0263] 70B Second Plating Layer

[0264] d. Average dimension of the stripped area along its length.

[0265] P stripping area

[0266] t is the average film thickness.

[0267] T in the height direction

[0268] TS1 Main side 1

[0269] TS2 2nd Main Side

[0270] W width direction

[0271] WS1 First Side

[0272] WS2 Second Side

[0273] L (length direction)

[0274] LS1 First end face

[0275] LS2, second end face.

Claims

1. A multilayer ceramic capacitor, comprising: A laminate comprising a plurality of stacked dielectric layers, and having a first main surface and a second main surface opposite each other in the height direction, a first side surface and a second side surface opposite each other in the width direction orthogonal to the height direction, and a first end surface and a second end surface opposite each other in the length direction orthogonal to the height direction and the width direction. A first internal electrode layer is disposed on the plurality of dielectric layers and exposed at the first end face; A second internal electrode layer is disposed on the plurality of dielectric layers and exposed at the second end face; A first external electrode is disposed on the first end face; and The second external electrode is disposed on the second end face. in, The first external electrode and the second external electrode have a base electrode layer containing a metal component, a conductive resin layer containing filler powder and resin component disposed on the base electrode layer, and a plating layer disposed on the conductive resin layer. The first external electrode and the second external electrode each have extensions that extend to a portion of the first main surface and a portion of the second main surface, respectively. The laminate has ridge portions at the portions where the first end face and the first main face intersect, the portions where the first end face and the second main face intersect, the portions where the second end face and the first main face intersect, and the portions where the second end face and the second main face intersect. The conductive resin layer is disposed on the ridge portion of the laminate. The thickness of the conductive resin layer on the ridge portion is 0.8 μm or more and 8 μm or less. The conductive resin layer has a peeling region in at least one of the extensions that is peeled off from the laminate. The stripping region is located in the area from the end of the laminate on the central side of the length direction of the conductive resin layer to the end of the laminate on the central side of the length direction of the substrate electrode layer. The length dimension of the stripped area is greater than 5 μm.

2. The multilayer ceramic capacitor according to claim 1, wherein, The filler powder has Cu particles as a core, and at least a portion of the surface of the Cu particles is coated with a Cu-Ag alloy of Cu and Ag.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein, The filler powder includes flat powder or spherical powder.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein, The plating layer has a Ni plating layer and a Sn plating layer disposed on the Ni plating layer. Tensile stress remains inside the Ni plating layer as internal stress.

Images