Multilayer ceramic electronic component

Abstract

Provided is a multilayer ceramic electronic component with improved moisture resistance.　In a multilayer ceramic capacitor 1, a first lead-out portion 31B of a first internal electrode layer 31 has a first inclined portion 31Ba that is led out from a first facing portion 31A and is inclined inward in the lamination direction as the first inclined portion 31Ba extends from the first facing portion 31A side toward a first end surface LS1 side, and a second lead-out portion 32B of a second internal electrode layer 32 has a second inclined portion 32Ba that is led out from a second facing portion 32A and is inclined inward in the lamination direction as the second inclined portion 32Ba extends from the second facing portion 32A side toward a second end surface LS2 side. A first principal surface TS1 of a laminate 10 has a first raised portion 15 disposed in the vicinity of the first end surface LS1 and a second raised portion 16 disposed in the vicinity of the second end surface LS2. At least a top portion 15a of the first raised portion 15 is covered with a first external electrode 40A, and at least a top portion 16a of the second raised portion 16 is covered with a second external electrode 40B.

Description

Multilayer ceramic electronic components

[0001] This invention relates to multilayer ceramic electronic components.

[0002] Patent Document 1 discloses a multilayer ceramic capacitor as a multilayer ceramic electronic component. Such a multilayer ceramic capacitor comprises a laminate in which a plurality of dielectric layers and a plurality of internal electrode layers made of ceramic material are stacked, and an external electrode provided on the end face of the laminate.

[0003] Japanese Patent Publication No. 2016-76582

[0004] In such multilayer ceramic capacitors, moisture can sometimes penetrate the laminate from the edges of the external electrodes. If this moisture penetrates into the internal electrode layers of the laminate, the electrical characteristics of the capacitor will deteriorate.

[0005] The present invention aims to provide multilayer ceramic electronic components with improved moisture resistance.

[0006] The multilayer ceramic electronic component according to the present invention comprises a plurality of stacked ceramic layers and a plurality of internal conductor layers, and includes a laminate having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, a first external electrode disposed on the side of the first end surface, and a second external electrode disposed on the side of the second end surface, wherein the internal conductor layer has a first internal conductor layer connected to the first external electrode and a second internal conductor layer connected to the second external electrode, the first internal conductor layer has a first opposing portion facing an adjacent internal conductor layer in the stacking direction and a first leading portion drawn out from the first opposing portion and connected to the first external electrode, and the second internal conductor layer is The laminate has a second opposing portion facing an adjacent internal conductor layer in the stacking direction, and a second leading portion extending from the second opposing portion and connected to the second external electrode, wherein the first leading portion extends from the first opposing portion and has a first inclined portion that slopes inward in the stacking direction as it moves from the first opposing portion side toward the first end face side, the second leading portion extends from the second opposing portion and has a second inclined portion that slopes inward in the stacking direction as it moves from the second opposing portion side toward the second end face side, the first main surface of the laminate has a first raised portion located near the first end face, and a second raised portion located near the second end face, where at least the top of the first raised portion is covered by the first external electrode, and at least the top of the second raised portion is covered by the second external electrode.

[0007] According to the present invention, it is possible to provide multilayer ceramic electronic components with improved moisture resistance.

[0008] This is an external perspective view of a multilayer ceramic capacitor according to an embodiment. This is a cross-sectional view taken along line II-II in Figure 1. This is a cross-sectional view taken along line III-III in Figure 2. This is a cross-sectional view taken along line IVA-IVA in Figure 2. This is a cross-sectional view taken along line IVB-IVB in Figure 2. This is an enlarged view of section V in Figure 2. This is an enlarged view of section VI in Figure 2. This is a diagram showing a double-gang multilayer ceramic capacitor. This is a diagram showing a triple-gang multilayer ceramic capacitor. This is a diagram showing a quadruple-gang multilayer ceramic capacitor.

[0009] Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to the present disclosure will be described with reference to the drawings.

[0010] As shown in Figure 1, the multilayer ceramic capacitor 1 according to this embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 comprises a laminate 10 having a substantially rectangular parallelepiped shape, and a pair of external electrodes 40 arranged spaced apart from each other at both ends of the laminate 10.

[0011] In Figure 1, arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T is also the thickness direction and height direction of the multilayer ceramic capacitor 1 and the laminate 10. The direction of the stacking direction T that approaches the center of the laminate 10 is also called the "inside of the stacking direction T". The direction of the stacking direction T that moves away from the center of the laminate 10 (i.e., the opposite direction of the inside of the stacking direction T) is also called the "outside of the stacking direction T". In Figure 1, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, perpendicular to the stacking direction T. In Figure 1, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, perpendicular to the stacking direction T and the length direction L. A pair of external electrodes 40 are arranged at one end and the other end of the laminate 10 in the length direction L, respectively.

[0012] Figures 1 to 4B show the XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross-section shown in Figure 2 is also called the LT cross-section. The cross-section shown in Figure 3 is also called the WT cross-section. The cross-sections shown in Figures 4A and 4B are also called the LW cross-section.

[0013] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing the lamination direction T, a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the lamination direction T, and a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the lamination direction T and the length direction L.

[0014] The first main surface TS1 and the second main surface TS2 are collectively referred to as "main surface TS". The first end surface LS1 and the second end surface LS2 are collectively referred to as "end surface LS". The first side surface WS1 and the second side surface WS2 are collectively referred to as "side surface WS".

[0015] As shown in Figure 1, the laminate 10 has a substantially rectangular parallelepiped shape. The length L dimension of the laminate 10 is not necessarily longer than the width W dimension. It is preferable that the corners and edges of the laminate 10 are rounded. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Some or all of the surfaces constituting the laminate 10 may have irregularities or bumps formed on them.

[0016] The dimensions of the laminate 10 are not particularly limited, but if the length L of the laminate 10 is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 10 mm or less. If the dimension T of the laminate 10 is denoted as dimension T, then it is preferable that dimension T is 0.05 mm or more and 10 mm or less. If the width W of the laminate 10 is denoted as dimension W, then it is preferable that dimension W is 0.1 mm or more and 10 mm or less.

[0017] As shown in Figures 2 and 3, the laminate 10 has an inner layer 11 and a first main surface-side outer layer 12 and a second main surface-side outer layer 13 arranged to sandwich the inner layer 11 in the lamination direction T.

[0018] The inner layer 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers, which are alternately stacked in the stacking direction T. The inner layer 11 includes the internal electrode layer 30 located on the first main surface TS1 side to the internal electrode layer 30 located on the second main surface TS2 side in the stacking direction T. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor.

[0019] Multiple dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, BaTiO ３ CaTiO ３ SrTiO ３ , or CaZrO ３ The dielectric ceramic may contain components such as the above. Alternatively, the dielectric material may have minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds added to these main components. The dielectric material may have BaTiO as its main component. ３ It is particularly preferable that the material contains [a specific substance].

[0020] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 15 μm or less. The number of dielectric layers 20 to be stacked is preferably 10 or more and 1200 or less. This number of dielectric layers 20 is the sum of the number of dielectric layers 20 in the inner layer portion 11 and the number of dielectric layers 20 in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0021] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 as multiple first internal conductor layers and multiple second internal electrode layers 32 as multiple second internal conductor layers. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the stacking direction T with a dielectric layer 20 in between. The first internal electrode layers 31 are drawn out to the first end face LS1. The second internal electrode layers 32 are drawn out to the second end face LS2. In the following, when it is not necessary to explain the first internal electrode layers 31 and the second internal electrode layers 32 separately, the first internal electrode layers 31 and the second internal electrode layers 32 may be collectively referred to as the internal electrode layer 30. In Figures 3 and 4, some of the internal electrode layers 30 are omitted and represented in detail by dots.

[0022] As shown in Figure 4A, the first internal electrode layer 31 has a first opposing portion 31A and a first leading portion 31B. The first opposing portion 31A is a region that faces the second internal electrode layer 32 with the dielectric layer 20 in between, and is located inside the laminate 10. The first leading portion 31B is a portion that is drawn out from the first opposing portion 31A to the first end face LS1, and is exposed to the first end face LS1.

[0023] As shown in Figure 4B, the second internal electrode layer 32 has a second opposing portion 32A and a second leading portion 32B. The second opposing portion 32A is a region that faces the first internal electrode layer 31 with the dielectric layer 20 in between, and is located inside the laminate 10. The second leading portion 32B is a portion that is drawn out from the second opposing portion 32A to the second end face LS2, and is exposed to the second end face LS2.

[0024] In this embodiment, capacitance is formed when the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0025] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first drawer portion 31B and the second drawer portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0026] The widthwise dimension W of the first opposing portion 31A and the widthwise dimension W of the first drawer portion 31B may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion 32A and the widthwise dimension W of the second drawer portion 32B may be the same, or one of them may be narrower.

[0027] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0028] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 10 or more and 1000 or less.

[0029] As shown in Figures 2 and 3, the first main surface-side outer layer 12 is located on the first main surface TS1 side of the laminate 10. The first main surface-side outer layer 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface-side outer layer 13 is located on the second main surface TS2 side of the laminate 10. The second main surface-side outer layer 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface-side outer layer 12 and the second main surface-side outer layer 13 may be the same as the dielectric layers 20 used in the inner layer 11.

[0030] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figures 4A and 4B show the width W and length L ranges of the counter electrode portion 11E. The counter electrode portion 11E is also called the capacitor effective portion.

[0031] The laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figures 3, 4A, and 4B show the widthwise range W of the first side outer layer WG1 and the second side outer layer WG2. The side outer layer is also called a W gap or side gap.

[0032] The laminate 10 has an end-face side outer layer. The end-face side outer layer has a first end-face side outer layer LG1 and a second end-face side outer layer LG2. The first end-face side outer layer LG1 is a portion located between the opposing electrode portion 11E and the first end face LS1, and includes the dielectric layer 20 and the first lead portion 31B. That is, the first end-face side outer layer LG1 is an assembly of the portions of multiple dielectric layers 20 on the first end face LS1 side and multiple first lead portions 31B. The second end-face side outer layer LG2 is a portion located between the opposing electrode portion 11E and the second end face LS2, and includes the dielectric layer 20 and the second lead portion 32B. That is, the second end-face side outer layer LG2 is an assembly of the portions of multiple dielectric layers 20 on the second end face LS2 side and multiple second lead portions 32B. Figures 2, 4A, and 4B show the longitudinal range L of the first end-face outer layer LG1 and the second end-face outer layer LG2. The end-face outer layer is also called the L gap or end gap.

[0033] As shown in Figures 1 and 2, the external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side of the laminate 10, and a second external electrode 40B positioned on the second end face LS2 side of the laminate 10.

[0034] The basic configurations of the first external electrode 40A and the second external electrode 40B are the same. Furthermore, the first external electrode 40A and the second external electrode 40B have shapes that are generally symmetrical with respect to the WT cross-section at the center of the length L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to explain the first external electrode 40A and the second external electrode 40B separately, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrode 40.

[0035] The first external electrode 40A is positioned on the first end face LS1. The first external electrode 40A is in contact with the first lead-out portion 31B of each of the multiple first internal electrode layers 31 exposed on the first end face LS1. As a result, the first external electrode 40A is electrically connected to the multiple first internal electrode layers 31. The first external electrode 40A may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0036] The second external electrode 40B is positioned on the second end face LS2. The second external electrode 40B is in contact with the second lead portion 32B of each of the multiple second internal electrode layers 32 exposed on the second end face LS2. As a result, the second external electrode 40B is electrically connected to the multiple second internal electrode layers 32. The second external electrode 40B may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0037] As described above, within the laminate 10, capacitance is formed when the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other via the dielectric layer 20. Therefore, capacitor characteristics are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

[0038] As shown in FIGS. 2, 4A, and 4B, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. Further, the second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0039] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to each first lead-out portion 31B of the plurality of first internal electrode layers 31 exposed on the first end face LS1. In the present embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a part of the first main face TS1, a part of the second main face TS2, a part of the first side face WS1, and a part of the second side face WS2.

[0040] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is in contact with each second lead-out portion 32B of the plurality of second internal electrode layers 32 exposed on the second end face LS2. In the present embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a part of the first main face TS1, a part of the second main face TS2, a part of the first side face WS1, and a part of the second side face WS2.

[0041] The first base electrode layer 50A and the second base electrode layer 50B of the present embodiment are baking layers. The baking layer preferably contains either a metal component and a glass component or a ceramic component, or both. The metal component contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag - Pd alloy, Au, etc. The glass component contains at least one selected from, for example, B, Si, Ba, Mg, Al, Li, etc. The ceramic component may use the same type of ceramic material as the dielectric layer 20 or a different type of ceramic material. The ceramic component is, for example, BaTiO ３ 、CaTiO ３ 、(Ba, Ca)TiO ３ 、SrTiO ３ 、CaZrO ３It includes at least one selected from the like.

[0042] The baking layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate 10 and baking it. The baking layer can be formed by co-firing the pre-fired laminate chip, which is the material of the laminate 10 having a plurality of internal electrodes and dielectric layers, and the conductive paste applied to the laminate chip. Alternatively, after firing the laminate chip to obtain the laminate 10, it may also be formed by applying a conductive paste to the laminate 10 and baking it. In the case of the above co-fire, it is preferable to form the baking layer by baking a material in which a ceramic material is added instead of the glass component. In that case, it is particularly preferable to use the same kind of ceramic material as the dielectric layer 20 as the ceramic material to be added. Note that the baking layer may be a plurality of layers.

[0043] The thickness corresponding to the length direction L of the first base electrode layer 50A located on the first end face LS1 is preferably, for example, about 2 μm or more and 220 μm or less at the center in the stacking direction T and the width direction W of the first base electrode layer 50A.

[0044] The thickness corresponding to the length direction L of the second base electrode layer 50B located on the second end face LS2 is preferably, for example, 2 μm or more and 220 μm or less at the center in the stacking direction T and the width direction W of the second base electrode layer 50B.

[0045] When the first base electrode layer 50A is provided on at least a part of one of the first main surface TS1 or the second main surface TS2, the thickness corresponding to the stacking direction T of the first base electrode layer 50A provided in this part is, for example, preferably about 3 μm or more and 40 μm or less at the center in the length direction L and the width direction W of the first base electrode layer 50A provided in this part.

[0046] When the first base electrode layer 50A is also provided on a part of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 50A provided in this part, corresponding to the width direction W, is preferably, for example, 3 μm or more and 40 μm or less in the central part of the length direction L and the lamination direction T of the first base electrode layer 50A provided in this part.

[0047] When a second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided in this portion, corresponding to the lamination direction T, is preferably, for example, 3 μm to 40 μm, at the center of the second base electrode layer 50B in the length direction L and width direction W.

[0048] When a second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B provided in this portion, corresponding to the width direction W, is preferably, for example, 3 μm to 40 μm, at the center of the second base electrode layer 50B provided in this portion, in the length direction L and the lamination direction T.

[0049] The first plating layer 60A is positioned to cover the first underlay electrode layer 50A.

[0050] The second plating layer 60B is positioned to cover the second under electrode layer 50B.

[0051] The first plating layer 60A and the second plating layer 60B may each contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed by multiple layers. Preferably, the first plating layer 60A and the second plating layer 60B have a two-layer structure in which a Sn plating layer is formed on top of a Ni plating layer.

[0052] The first plating layer 60A is arranged to cover the first underlay electrode layer 50A. In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0053] The second plating layer 60B is arranged to cover the second under electrode layer 50B. In this embodiment, the second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0054] The Ni plating layer prevents the first and second base electrode layers 50A and 50B from being corroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B and the second Sn plating layer 62B is preferably between 2 μm and 15 μm.

[0055] The external electrode 40 in this embodiment may, for example, have a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be arranged to cover the baking layer. When the conductive resin layer is arranged to cover the baking layer, the conductive resin layer is placed between the baking layer and the plating layer (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the baking layer or cover a part of the baking layer.

[0056] A conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plated film or a fired conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer. Thus, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0057] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or alloys containing these. The conductive particles preferably contain Ag. The conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, since Ag is a noble metal, it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as conductive particles.

[0058] Furthermore, the conductive particles may be metal powders with an Ag coating on their surface. When using metal powders with an Ag coating on their surface, the metal powders are preferably Cu, Ni, Sn, Bi, or alloys thereof. It is preferable to use Ag-coated metal powders in order to maintain the properties of Ag while making the base metal less expensive.

[0059] Furthermore, the conductive particles may be Cu or Ni that have been treated to prevent oxidation. Alternatively, the conductive particles may be metal powder coated with Sn, Ni, or Cu on the surface of the metal powder. When using metal powder coated with Sn, Ni, or Cu on the surface, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of these.

[0060] The shape of the conductive particles is not particularly limited. Conductive particles can have shapes such as spherical or flattened, but it is preferable to use a mixture of spherical metal powder and flattened metal powder.

[0061] The conductive particles contained in the conductive resin layer primarily play a role in ensuring the conductivity of the conductive resin layer. Specifically, the contact between multiple conductive particles forms an electrical pathway within the conductive resin layer.

[0062] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin in the conductive resin layer includes a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0063] The conductive resin layer may be formed from multiple layers. Preferably, the thickness of the thickest part of the conductive resin layer is 10 μm or more and 150 μm or less.

[0064] The above describes the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the lengthwise dimension of the multilayer ceramic capacitor 1, including the laminate 10 and the external electrode 40, is denoted as dimension L, then it is preferable that dimension L is between 0.2 mm and 10 mm. Furthermore, if the dimension in the stacking direction of the multilayer ceramic capacitor 1 is denoted as dimension T, then it is preferable that dimension T is between 0.05 mm and 10 mm. Also, if the widthwise dimension of the multilayer ceramic capacitor 1 is denoted as dimension W, then it is preferable that dimension W is between 0.1 mm and 10 mm.

[0065] Here, as shown in Figure 5, in a cross section LT passing through the center of the width W of the multilayer ceramic capacitor 1, the first lead portion 31B is led out from the first opposing portion 31A and has a first inclined portion 31Ba that inclins inward in the stacking direction T as it moves from the first opposing portion 31A side toward the first end face LS1 side. The first main surface TS1 of the laminate 10 has a first raised portion 15 located near the first end face LS1. At least the top portion 15a of the first raised portion 15 is covered by the first external electrode 40A.

[0066] Furthermore, the end of the first opposing portion 31A on the first end face LS1 side may be inclined inward in the stacking direction T as it approaches the first end face LS1 side. The end of the second opposing portion 32A on the first end face LS1 side may also be inclined inward in the stacking direction T as it approaches the first end face LS1 side. In this case, the distance from the main surface TS to the effective part of the capacitor can be increased, thereby preventing cracks that occur near the main surface TS from reaching the effective part of the capacitor.

[0067] The first raised portion 15 has a convex shape that protrudes outward in the stacking direction T, and more specifically, it has an arc shape. The first raised portion 15 is continuous with, for example, the first end face LS1. The end of the first raised portion 15 on the second end face LS2 side is located on the first end face LS1 side of the center in the longitudinal direction L of the laminate 10. The end of the first raised portion 15 on the second end face LS2 side overlaps with, for example, the opposing electrode portion 11E in the stacking direction T. The top portion 15a of the first raised portion 15 overlaps with, for example, the opposing electrode portion 11E in the stacking direction T. The top portion 15a overlaps with, for example, the portion of the first internal electrode layer 31 that slopes inward in the stacking direction T as it approaches the first end face LS1 side.

[0068] The entire first raised portion 15 is preferably covered by the first external electrode 40A. The entire first raised portion 15 is, for example, covered by the first base electrode layer 50A. The entire first raised portion 15 is, for example, covered by the first plating layer 60A.

[0069] It is preferable that the distance a1 in the stacking direction T between the end of the first extraction portion 31B on the side of the first opposing portion 31A and the end of the first extraction portion 31B on the side of the first end face LS1 is greater than the thickness of the dielectric layer 20 arranged between the internal electrode layers 30 in the stacking direction T (referred to as "dielectric layer thickness tc"). Note that the dielectric layer thickness tc corresponds to the ceramic layer thickness.

[0070] The dielectric layer thickness tc is determined by measuring the thickness of the dielectric layer 20 in the stacking direction T at five locations arranged at equal intervals in the length direction L within the portion of the dielectric layer 20 sandwiched between the adjacent first opposing portion 31A and second opposing portion 32A, and taking the average of the obtained values.

[0071] When the dielectric layer thickness tc is measured in relation to a certain internal electrode layer 30, it is defined as the thickness in the stacking direction T of the dielectric layer 20 adjacent to the side of the laminate 10 of the internal electrode layer 30 that is close to the center in the stacking direction T.

[0072] Preferably, the distance a1 in the stacking direction T between the end of the first draw-out portion 31B on the side of the first opposing portion 31A and the end of the first draw-out portion 31B on the side of the first end face LS1 is greater than the sum Tt1 of the thickness of the first internal electrode layer 31 in the stacking direction T (referred to as "first internal electrode layer thickness te1") and the dielectric layer thickness tc.

[0073] The distance T in the stacking direction between the end of the first draw-out portion 31B on the side of the first opposing portion 31A and the end of the first draw-out portion 31B on the side of the first end face LS1 is more preferably three times or more the sum Tt1 of the first internal electrode layer thickness te1 and the dielectric layer thickness tc, and even more preferably five times or more the sum Tt1 of the first internal electrode layer thickness te1 and the dielectric layer thickness tc.

[0074] It is preferable that the distance a1 in the stacking direction T between the end of the first draw-out portion 31B on the side of the first opposing portion 31A and the end of the first draw-out portion 31B on the side of the first end face LS1 is 10 μm or more.

[0075] Preferably, the amount of protrusion b1 of the first raised portion 15 is greater than the thickness of the dielectric layer 20 arranged between the internal electrode layers 30 in the stacking direction T.

[0076] The amount of protrusion b1 of the first protrusion 15 is defined as the distance in the stacking direction T between the main surface TS on which the first protrusion 15 is formed and the top of the first protrusion 15, when the intersection point of the main surface TS on which the first protrusion 15 is formed and a virtual straight line extending parallel to the stacking direction T passing through the center of the length direction L of the laminate 10 is defined as the "main surface center point" and the virtual straight line extending parallel to the length direction L passing through the main surface center point is defined as the "main surface reference line".

[0077] Preferably, the amount of protrusion b1 of the first raised portion 15 is greater than the sum Tt1 of the first internal electrode layer thickness Te1 and the dielectric layer thickness tc.

[0078] The amount of protrusion b1 of the first raised portion 15 is more preferably three times or more the sum Tt1 of the first internal electrode layer thickness Te1 and the dielectric layer thickness tc, and even more preferably five times or more the sum Tt1 of the first internal electrode layer thickness Te1 and the dielectric layer thickness tc.

[0079] The amount of protrusion b1 of the first raised portion 15 is preferably 2 μm or more.

[0080] As shown in Figure 6, in a cross section LT passing through the center of the width W of the multilayer ceramic capacitor 1, the second lead portion 32B is led out from the second opposing portion 32A and has a second inclined portion 32Ba that slopes inward in the stacking direction T as it moves from the second opposing portion 32A side toward the second end face LS2 side. The first main surface TS1 of the laminate 10 has a second raised portion 16 located near the second end face LS2. At least the top portion 16a of the second raised portion 16 is covered by the second external electrode 40B.

[0081] Furthermore, the end of the second opposing portion 32A on the second end face LS2 side may be inclined inward in the stacking direction T as it approaches the second end face LS2 side. The end of the first opposing portion 31A on the second end face LS2 side may be inclined inward in the stacking direction T as it approaches the second end face LS2 side.

[0082] The second raised portion 16 has a convex shape that protrudes outward in the stacking direction T, and more specifically, it has an arc shape. The second raised portion 16 is continuous with, for example, the second end face LS2. The end of the second raised portion 16 on the first end face LS1 side is located on the second end face LS2 side of the center in the length direction L of the laminate 10. The end of the second raised portion 16 on the first end face LS1 side overlaps with, for example, the opposing electrode portion 11E in the stacking direction T. The top portion 16a of the second raised portion 16 overlaps with, for example, the opposing electrode portion 11E in the stacking direction T. The top portion 16a overlaps with, for example, the portion of the second internal electrode layer 32 that slopes inward in the stacking direction T as it approaches the second end face LS2 side.

[0083] Preferably, the entire second raised portion 16 is covered by the second external electrode. The entire second raised portion 16 is covered by, for example, the second base electrode layer 50B. The entire second raised portion 16 is covered by, for example, the second plating layer 60B.

[0084] It is preferable that the distance a2 in the stacking direction T between the end of the second draw-out portion 32B on the second opposing portion 32A side and the end of the second draw-out portion 32B on the second end face LS2 side is greater than the dielectric layer thickness tc.

[0085] Preferably, the distance a2 in the stacking direction T between the end of the second lead portion 32B on the second opposing portion 32A side and the end of the second lead portion 32B on the second end face LS2 side is greater than the sum Tt2 of the thickness of the second internal electrode layer 32 in the stacking direction T (referred to as "second internal electrode layer thickness te2") and the dielectric layer thickness tc.

[0086] The distance a2 in the stacking direction T between the end of the second draw-out portion 32B on the second opposing portion 32A side and the end of the second draw-out portion 32B on the second end face LS2 side is more preferably three times or more the sum Tt2 of the second internal electrode layer thickness Te2 and the dielectric layer thickness tc, and even more preferably five times or more the sum Tt2 of the second internal electrode layer thickness Te2 and the dielectric layer thickness tc.

[0087] It is preferable that the distance a2 in the stacking direction T between the end of the second draw-out portion 32B on the second opposing portion 32A side and the end of the second draw-out portion 32B on the second end face LS2 side is 10 μm or more.

[0088] Preferably, the amount of protrusion b2 of the second raised portion 16 is greater than the thickness tc of the dielectric layer 20.

[0089] The amount of protrusion b2 of the second protrusion 16 is the distance in the stacking direction T between the main surface reference line of the main surface on which the second protrusion 16 is formed and the top 16a of the second protrusion 16, in an LT cross-section passing through the center of the width direction W of the multilayer ceramic capacitor 1.

[0090] Preferably, the amount of protrusion b2 of the second raised portion 16 is greater than the sum Tt2 of the second internal electrode layer thickness te2 and the dielectric layer thickness tc.

[0091] The amount of protrusion b2 of the second raised portion 16 is more preferably three times or more the sum Tt2 of the second internal electrode layer thickness te2 and the dielectric layer thickness tc, and even more preferably five times or more the sum Tt2 of the second internal electrode layer thickness te2 and the dielectric layer thickness tc.

[0092] The amount of protrusion b2 of the second raised portion 16 is preferably 2 μm or more.

[0093] The various dimensions are measured by exposing the LT cross-section passing through the center of the width W of the multilayer ceramic capacitor 1 through polishing or other means, and then observing the exposed LT cross-section with a scanning electron microscope (SEM).

[0094] The second main surface TS2 may also have a raised portion.

[0095] That is, in a cross-section LT passing through the center of the width direction W of the multilayer ceramic capacitor 1, the second main surface TS2 of the laminate has a first raised portion 15 located near the first end face LS1 and a second raised portion 16 located near the second end face LS2, and at least the top portion 15a of the first raised portion 15 is covered by the first external electrode 40A, and at least the top portion 16a of the second raised portion 16 may be covered by the second external electrode 40B.

[0096] Preferably, the entire first raised portion 15 is covered by the first external electrode 40A, and the entire second raised portion 16 is covered by the second external electrode 40B.

[0097] Furthermore, on the second main surface TS2 side, the first pull-out portion 31B may have a first inclined portion 31Ba that is pulled out from the first opposing portion 31A and inclined inward in the stacking direction T as it moves from the first opposing portion 31A side toward the first end face LS1 side, and the second pull-out portion 32B may have a second inclined portion 32Ba that is pulled out from the second opposing portion 32A and inclined inward in the stacking direction T as it moves from the second opposing portion 32A side toward the second end face LS2 side.

[0098] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. The manufacturing method of the multilayer ceramic capacitor 1 of this embodiment is not limited as long as the above requirements are satisfied. However, a preferred manufacturing method comprises the following steps. The details of each step are described below.

[0099] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and solvent may be known substances.

[0100] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer 31 formed on it, and a dielectric sheet with the pattern for the second internal electrode layer 32 formed on it.

[0101] A predetermined number of dielectric sheets without the pattern of the internal electrode layer 30 printed on them are stacked to form the first main surface outer layer portion 12 on the first main surface TS1 side. On top of this, dielectric sheets with the pattern of the first internal electrode layer 31 printed on them and dielectric sheets with the pattern of the second internal electrode layer 32 printed on them are stacked alternately in sequence to form the inner layer portion 11. On top of this inner layer portion 11, a predetermined number of dielectric sheets without the pattern of the internal electrode layer 30 printed on them are stacked to form the second main surface outer layer portion 13 on the second main surface TS2 side. This results in a laminated sheet.

[0102] Here, dielectric paste, which will form the first raised portion 15 and the second raised portion 16, is printed on the first main surface TS1 side of the dielectric sheet. The composition of the dielectric paste is the same as that of the dielectric sheet. The dielectric paste is printed in a stripe pattern extending in the width direction W. The dielectric paste overlaps in the stacking direction T with the portion that will form the first inclined portion 31Ba and the portion that will form the second inclined portion 32Ba of the pattern of the internal electrode layer 30. Next, dielectric paste is printed in the same manner on the second main surface TS2 side of the dielectric sheet.

[0103] Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or other means to create a laminated block. The dielectric paste printed on the surface of the dielectric sheet is pushed inward into the dielectric sheet. The portion of the pattern of the internal electrode layer 30 that overlaps with the dielectric paste is bent inward in the lamination direction T of the dielectric sheet. As a result, a first inclined portion 31Ba and a second inclined portion 32Ba are formed in the pattern of the internal electrode layer 30. The surface of the dielectric paste is raised above the surface of the dielectric sheet. As a result, a first raised portion 15 and a second raised portion 16 are formed on the surface of the laminated block.

[0104] Laminated chips are cut out by cutting the laminated block to a predetermined size using a cutting blade or the like. If the cutting blade or the like is inserted into the laminated block relatively quickly, the longitudinal L-end of the internal electrode layer can be bent to follow the cutting blade or the like. If the cutting blade or the like is inserted into the laminated block even faster, the inclination of the internal electrode layer can be increased. The degree of inclination of the internal electrode layer can also be adjusted by adjusting the speed at which the cutting blade or the like is inserted into the laminated block.

[0105] The corners and edges of the laminated chip are rounded, for example, by barrel polishing. The shape and amount of the first raised portion 15 and the shape and amount of the second raised portion 16 are adjusted, for example, by polishing. Alternatively, when pressing the laminated sheet, a plate material having a curved portion may be pressed against the laminated sheet to adjust the shape and amount of the first raised portion 15 and the shape and amount of the second raised portion 16, respectively. Furthermore, the boundary between the end face LS and the main face TS is preferably rounded, and the radius R of the boundary between the end face LS and the main face TS is preferably gentler.

[0106] The laminated chips are fired to produce the laminated body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably between 900°C and 1400°C.

[0107] A conductive paste, which will serve as the base electrode layer, is applied to both end faces of the laminate 10. In this embodiment, the base electrode layer is a baked layer. A conductive paste containing glass components and metal is applied to the laminate 10 by a method such as dipping. The conductive paste that will become the first base electrode layer is applied, for example, so as to cover the entire first raised portion. The conductive paste that will become the second base electrode layer is applied, for example, so as to cover the entire first raised portion. After that, a baking process is performed to form the base electrode layers. The temperature of the baking process at this time is preferably 700°C to 900°C.

[0108] Furthermore, when firing the laminated chip before firing and the conductive paste applied to the laminated chip simultaneously, it is preferable to form the baked layer by baking a ceramic material added instead of the glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form a laminate 10 with a baked layer.

[0109] Subsequently, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Also, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with a catalyst or the like to improve the plating deposition rate. Therefore, it is generally preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0110] When a conductive resin layer is provided as the base electrode layer, the conductive resin layer may be arranged to cover the baking layer. When a conductive resin layer is provided, a conductive resin paste containing a thermosetting resin and metal components is applied to the baking layer, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to harden, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably 100 ppm or less.

[0111] Through the above manufacturing process, a multilayer ceramic capacitor 1 is manufactured.

[0112] Note that the configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 6. For example, the multilayer ceramic capacitor 1 may be a double-gang, triple-gang, or quadruple-gang multilayer ceramic capacitor as shown in Figures 7A, 7B, and 7C.

[0113] The multilayer ceramic capacitor 1 shown in Figure 7A is a double-gang multilayer ceramic capacitor 1, and as an internal electrode layer 30, it includes a first internal electrode layer 33 and a second internal electrode layer 34, as well as a floating internal electrode layer 35 that is not led out to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in Figure 7B is a triple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in Figure 7C is a quadruple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. In this way, by providing floating internal electrode layers 35 as internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and the voltage rating of the multilayer ceramic capacitor 1 can be increased. It goes without saying that the multilayer ceramic capacitor 1 in this embodiment may also have a multi-gang structure of four or more units.

[0114] The multilayer ceramic capacitor 1 may be a two-terminal type with two external electrodes, or a multi-terminal type with multiple external electrodes.

[0115] In the embodiments described above, a multilayer ceramic capacitor was used as an example of a multilayer ceramic electronic component in which a dielectric layer 20 made of dielectric ceramic is used as the ceramic layer. However, the multilayer ceramic electronic components of this disclosure are not limited to this. For example, the ceramic electronic components of this disclosure can also be applied to various multilayer ceramic electronic components such as piezoelectric components using piezoelectric ceramic as the ceramic layer, and thermistors using semiconductor ceramic as the ceramic layer. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, and examples of semiconductor ceramics include spinel ceramics.

[0116] The multilayer ceramic capacitor 1 according to the embodiment described above provides the following effects.

[0117] In the multilayer ceramic capacitor 1 according to this embodiment, the first lead portion 31B is led out from the first opposing portion 31A and has a first inclined portion 31Ba that inclins inward in the stacking direction T as it moves from the first opposing portion 31A side toward the first end face LS1 side. The first main surface TS1 of the laminate 10 has a first raised portion 15 located near the first end face LS1. At least the top portion 15a of the first raised portion 15 is covered by the first external electrode 40A.

[0118] The second extension portion 32B extends from the second opposing portion 32A and has a second inclined portion 32Ba that inclins inward in the stacking direction T as it moves from the second opposing portion 32A side toward the second end face LS2 side. The first main surface TS1 of the laminate 10 has a second raised portion 16 located near the second end face LS2. At least the top portion 16a of the second raised portion 16 is covered by the second external electrode 40B.

[0119] One possible path for moisture to penetrate into the laminate 10 is that moisture that has penetrated the boundary between the tip of the external electrode 40 and the main surface TS reaches the end surface LS along the interface between the external electrode 40 and the main surface TS, and further reaches the portion of the end surface LS where the internal electrode layer 30 is exposed.

[0120] However, with this configuration, the portion of each main surface TS near each end face is raised, which increases the distance from the tip of the external electrode 40 to the end face LS along the interface between the external electrode 40 and the main surface TS. Furthermore, the lengthwise end L of the internal electrode layer 30 is curved toward the center of the stacking direction T of the laminate 10, which increases the distance from the main surface TS to the portion of the internal electrode layer 30 exposed on the end face LS. As a result, the intrusion of moisture into the laminate 10 can be suppressed, and a multilayer ceramic capacitor 1 with improved moisture resistance can be provided.

[0121] Furthermore, the portion of the external electrode 40 located near the edge of the laminate 10 is likely to have the thinnest thickness. Therefore, one possible path for moisture to penetrate into the laminate 10 is that moisture permeates through the portion of the external electrode 40 located near the edge of the laminate 10 (i.e., the relatively thin portion of the external electrode 40), reaches the area near the edge of the laminate 10, and then reaches the portion of the internal electrode layer 30 on the end face LS that is exposed.

[0122] However, with this configuration, since the longitudinal end L of the internal electrode layer 30 is curved toward the center T of the lamination direction of the laminate 10, the distance from the main surface TS to the exposed portion of the internal electrode layer 30 on the end surface LS can be increased, thereby suppressing the intrusion of moisture into the laminate 10.

[0123] Furthermore, cracks are relatively prone to occur in the area where the external electrodes 40 are located on the laminate 10 due to the effects of substrate bending, temperature cycling, etc. However, the distance between the internal electrode layer 30 and the main surface TS can be increased because the portion of the main surface TS near the end face LS is raised, and the longitudinal end L of the internal electrode layer 30 is bent inward in the lamination direction T of the laminate 10. This prevents cracks that occur near the main surface TS from reaching the internal electrode layer 30 (especially the capacitor effective portion) and causing problems such as short circuits.

[0124] Furthermore, even if a crack occurs in the laminate 10, the raised main surface TS causes the crack to extend in a direction more aligned with the length L compared to the case where the main surface TS is flat. This suppresses the crack from extending toward the internal electrode layer 30, thus more effectively preventing a crack near the main surface TS of the laminate 10 from reaching the internal electrode layer 30 (especially the capacitor's effective portion).

[0125] Furthermore, in the laminate 10, chipping and cracking are prone to occur near the edges and corners. However, because the portion of the main surface TS near the end surface LS is raised, it is possible to make the radius (R) near the edge between the main surface TS and the end surface LS gentler. This suppresses the occurrence of chipping and cracking in the laminate 10. Also, even if chipping and cracking occur on the main surface TS near the edge, the distance between the main surface TS and the capacitor's effective portion is increased, which suppresses the crack from reaching the capacitor's effective portion. This suppresses the occurrence of short circuits in the capacitor's effective portion.

[0126] Furthermore, it is possible to make the radius of the ridge between the main surface TS and the end surface LS gentler, which improves the contact of the external electrode 40 with the vicinity of the ridge. This makes it easier to make the portion of the external electrode 40 that is positioned on the ridge thicker. As a result, the sealing performance of the external electrode 40 near the ridge between the main surface TS and the end surface LS can be improved, thereby suppressing the intrusion of moisture into the laminate 10.

[0127] In the multilayer ceramic capacitor 1 according to this embodiment, it is preferable that the entire first raised portion 15 is covered by the first external electrode 40A.

[0128] Preferably, the entire second raised portion 16 is covered by the second external electrode.

[0129] With this configuration, it is possible to more easily increase the distance on the main surface from the boundary between the tip of the external electrode 40 and the main surface TS to the end surface LS, thereby further improving moisture resistance.

[0130] Furthermore, it is believed that the larger the length L dimension of the portion of the external electrode 40 that is located on the main surface TS, the greater the stress generated in that portion. For this reason, cracks may easily occur in the portion of the laminate 10 near the main surface TS due to the stress transmitted from the external electrode 40. However, in the multilayer ceramic capacitor 1, the distance between the main surface TS and the internal electrode layer 30 is ensured by the raised main surface TS and the inclination of the length L end of the internal electrode layer 30. As a result, even if a crack occurs in the portion of the laminate 10 near the main surface TS, the crack's reach of the effective part of the capacitor is suppressed.

[0131] In the multilayer ceramic capacitor 1 according to the embodiment, it is preferable that the distance a1 in the stacking direction T between the end of the first lead portion 31B on the side of the first opposing portion 31A and the end of the first lead portion 31B on the side of the first end face LS1 is greater than the dielectric layer thickness tc.

[0132] It is preferable that the distance a2 in the stacking direction T between the end of the second draw-out portion 32B on the second opposing portion 32A side and the end of the second draw-out portion 32B on the second end face LS2 side is greater than the dielectric layer thickness tc.

[0133] With this configuration, the distance between the longitudinal end L of the internal electrode layer 30 and the main surface TS can be suitably secured, thereby suitably suppressing the arrival of moisture and cracks into the internal electrode layer 30.

[0134] In the multilayer ceramic capacitor 1 according to the embodiment, the distance a1 in the stacking direction T between the end of the first lead portion 31B on the side of the first opposing portion 31A and the end of the first lead portion 31B on the side of the first end face LS1 is preferably greater than the sum Tt1 of the first internal electrode layer thickness te1 and the dielectric layer thickness tc, more preferably three times or more the sum Tt1 of the first internal electrode layer thickness te1 and the dielectric layer thickness tc, and even more preferably five times or more the sum Tt1 of the first internal electrode layer thickness te1 and the dielectric layer thickness tc.

[0135] The distance a2 in the stacking direction T between the end of the second extraction portion 32B on the second opposing portion 32A side and the end of the second extraction portion 32B on the second end face LS2 side is preferably greater than the sum Tt2 of the second internal electrode layer thickness te2 and the dielectric layer thickness tc, more preferably the distance a2 in the stacking direction T between the end of the second extraction portion 32B on the second opposing portion 32A side and the end of the second extraction portion 32B on the second end face LS2 side is three times or more the sum Tt2 of the second internal electrode layer thickness Te2 and the dielectric layer thickness tc, and even more preferably five times or more the sum Tt2 of the second internal electrode layer thickness Te2 and the dielectric layer thickness tc.

[0136] With this configuration, the distance between the longitudinal end L of the internal electrode layer 30 and the main surface TS can be suitably secured, thereby suitably suppressing the arrival of moisture and cracks into the internal electrode layer 30.

[0137] In the multilayer ceramic capacitor 1 according to the embodiment, it is preferable that the distance a1 in the stacking direction T between the end of the first lead portion 31B on the side of the first opposing portion 31A and the end of the first lead portion 31B on the side of the first end face LS1 is 10 μm or more.

[0138] It is preferable that the distance a2 in the stacking direction T between the end of the second draw-out portion 32B on the second opposing portion 32A side and the end of the second draw-out portion 32B on the second end face LS2 side is 10 μm or more.

[0139] With this configuration, the distance between the longitudinal end L of the internal electrode layer 30 and the main surface TS can be suitably secured, thereby suitably suppressing the arrival of moisture and cracks into the internal electrode layer 30.

[0140] In the multilayer ceramic capacitor 1 according to this embodiment, it is preferable that the amount of protrusion b1 of the first protrusion 15 is greater than the thickness of the dielectric layer 20 arranged between the internal electrode layers 30 in the stacking direction T.

[0141] Preferably, the amount of protrusion b2 of the second raised portion 16 is greater than the thickness tc of the dielectric layer 20.

[0142] With this configuration, the main surface TS can be suitably raised, thereby ensuring a suitable distance between the longitudinal end L of the internal electrode layer 30 and the main surface TS. This effectively suppresses the arrival of moisture and cracks into the internal electrode layer 30. Furthermore, it is easier to create a gentle radius R at the ridge between the main surface TS and the end surface LS, thereby effectively suppressing chipping and cracking of the laminate 10, preventing cracks from extending toward the internal electrode layer 30, and facilitating close contact of the external electrode 40 with the ridge between the main surface TS and the end surface LS.

[0143] In the multilayer ceramic capacitor 1 according to the embodiment, the amount of protrusion b1 of the first protrusion 15 is preferably greater than the sum Tt1 of the first internal electrode layer thickness Te1 and the dielectric layer thickness tc, more preferably the amount of protrusion b1 of the first protrusion 15 is three times or more the sum Tt1 of the first internal electrode layer thickness Te1 and the dielectric layer thickness tc, and even more preferably five times or more the sum Tt1 of the first internal electrode layer thickness Te1 and the dielectric layer thickness tc.

[0144] The amount of protrusion b2 of the second protrusion 16 is preferably greater than the sum Tt2 of the second internal electrode layer thickness te2 and the dielectric layer thickness tc, more preferably three times or more the sum Tt2 of the second internal electrode layer thickness te2 and the dielectric layer thickness tc, and even more preferably five times or more the sum Tt2 of the second internal electrode layer thickness te2 and the dielectric layer thickness tc.

[0145] With this configuration, the main surface TS can be raised more effectively, and therefore the effects of raising the main surface TS can be obtained more effectively.

[0146] In the multilayer ceramic capacitor 1 according to this embodiment, it is preferable that the amount of protrusion b1 of the first raised portion 15 is 2 μm or more.

[0147] The amount of protrusion b2 of the second raised portion 16 is preferably 2 μm or more.

[0148] With this configuration, the main surface TS can be raised more effectively, and therefore the effects of raising the main surface TS can be obtained more effectively.

[0149] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the desirable configurations described in the above embodiments also constitutes the present invention.

[0150] 1 Multilayer ceramic capacitor (multilayer ceramic electronic component) 10 Laminate 15 First raised portion 15a Top portion 16 Second raised portion 16a Top portion 20 Dielectric layer (ceramic layer) 30 Internal electrode layer (internal conductor layer) 31 First internal electrode layer (first internal conductor layer) 31A First opposing portion 31B First lead portion 31Ba First inclined portion 32 Second internal electrode layer (second internal conductor layer) 32A Second opposing portion 32B Second lead portion 32Ba Second inclined portion 40A First external electrode 40B Second external electrode L Length direction T Lamination direction W Width direction LS1 First end face LS2 Second end face TS1 First main surface TS2 Second main surface WS1 First side surface WS2 Second side surface

Claims

1. A laminate comprising a plurality of stacked ceramic layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction; a first external electrode disposed on the side of the first end surface; and a second external electrode disposed on the side of the second end surface, wherein the internal conductor layer comprises a first internal conductor layer connected to the first external electrode and a second internal conductor layer connected to the second external electrode, and the first internal conductor layer comprises a first opposing portion facing an adjacent internal conductor layer in the stacking direction and a first leading portion drawn out from the first opposing portion and connected to the first external electrode. The second internal conductor layer has a second opposing portion facing an adjacent internal conductor layer in the stacking direction, and a second leading portion extending from the second opposing portion and connected to the second external electrode; the first leading portion extends from the first opposing portion and has a first inclined portion that slopes inward in the stacking direction as it moves from the first opposing portion side toward the first end face side; the second leading portion extends from the second opposing portion and has a second inclined portion that slopes inward in the stacking direction as it moves from the second opposing portion side toward the second end face side; the first main surface of the laminate has a first raised portion located near the first end face, and a second raised portion located near the second end face; at least the top of the first raised portion is covered by the first external electrode; and at least the top of the second raised portion is covered by the second external electrode; a multilayer ceramic electronic component.

2. The multilayer ceramic electronic component according to claim 1, wherein the entirety of the first raised portion is covered by the first external electrode, and the entirety of the second raised portion is covered by the second external electrode.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein the distance in the stacking direction between the first opposing end of the first lead portion and the first end face end of the first lead portion is greater than the thickness of the ceramic layer, which is the thickness of the ceramic layer in the stacking direction, disposed between the internal conductor layers, and the distance in the stacking direction between the second opposing end of the second lead portion and the second end face end of the second lead portion is greater than the thickness of the ceramic layer, which is the thickness of the ceramic layer in the stacking direction, disposed between the internal conductor layers.

4. The multilayer ceramic electronic component according to claim 3, wherein the distance in the stacking direction between the end of the first drawer on the side of the first opposing portion and the end of the first drawer on the side of the first end face is greater than the sum of the thickness of the internal conductor layer in the stacking direction and the thickness of the ceramic layer, and the distance in the stacking direction between the end of the second drawer on the side of the second opposing portion and the end of the second drawer on the side of the second end face is greater than the sum of the thickness of the internal conductor layer in the stacking direction and the thickness of the ceramic layer.

5. The multilayer ceramic electronic component according to claim 4, wherein the distance in the stacking direction between the end of the first drawer on the side of the first opposing part and the end of the first drawer on the side of the first end face is three times or more the sum of the thickness of the internal conductor layer in the stacking direction and the thickness of the ceramic layer, and the distance in the stacking direction between the end of the second drawer on the side of the second opposing part and the end of the second drawer on the side of the second end face is three times or more the sum of the thickness of the internal conductor layer in the stacking direction and the thickness of the ceramic layer.

6. The multilayer ceramic electronic component according to any one of claims 1 to 5, wherein the distance in the stacking direction between the end of the first drawer on the first opposing side and the end of the first drawer on the first end face side is 10 μm or more, and the distance in the stacking direction between the end of the second drawer on the second opposing side and the end of the second drawer on the second end face side is 10 μm or more.

7. The amount of the first raised portion is greater than the thickness of the ceramic layer arranged between the internal conductor layers in the lamination direction, and the amount of the second raised portion is greater than the thickness of the ceramic layer arranged between the internal conductor layers in the lamination direction, according to any one of claims 1 to 6.

8. The amount of the first raised portion is greater than the sum of the thickness of the internal conductor layer in the stacking direction and the thickness of the ceramic layer disposed between the internal conductor layers in the stacking direction, which is the ceramic layer thickness, and the amount of the second raised portion is greater than the sum of the thickness of the internal conductor layer in the stacking direction and the thickness of the ceramic layer disposed between the internal conductor layers in the stacking direction, which is the ceramic layer thickness, according to claim 7.

9. The amount of the first raised portion is three times or more the sum of the thickness of the internal conductor layer in the lamination direction and the thickness of the ceramic layer, and the amount of the second raised portion is three times or more the sum of the thickness of the internal conductor layer in the lamination direction and the thickness of the ceramic layer, according to claim 8.

10. The multilayer ceramic electronic component according to any one of claims 1 to 9, wherein the amount of protrusion of the first raised portion is 2 μm or more, and the amount of protrusion of the second raised portion is 2 μm or more.

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