Sensor

Abstract

The present disclosure relates to a sensor made of multiple layers on a semiconductor wafer, including a plurality of sensor elements arranged in a tile, the tile including a plurality of vertically arranged control lines extending from a bottom edge of the tile in an opposite top edge direction. One of the plurality of vertically arranged control lines terminates between the bottom edge and the top edge, and the other control lines extend from the bottom edge to the top edge and turn at one of the bottom edge or the top edge, so that the control line of the plurality of vertically arranged control lines of a first splicing block of the plurality of splicing blocks is connected with the staggered vertical lines of an adjacent second splicing block of the plurality of splicing blocks. The plurality of splicing blocks further comprise at least one vertically-arranged read-out line extending from the bottom edge to the top edge, and at least one vertically-arranged read-out line of a first splicing block in the plurality of splicing blocks is connected with at least one vertically-arranged read-out line of an adjacent second splicing block in the plurality of splicing blocks. The plurality of tiles further includes a plurality of horizontally arranged control lines extending from the right side to the opposite left side and connecting control lines of the plurality of vertically arranged control lines.

Description

[0001] Cross-references to related applications This application claims the benefit and priority of European Patent Application No. 24383097.3, filed on 8 October 2024. Technical Field

[0002] The present invention relates to a sensor having a plurality of sensor elements arranged in a modular fashion. Background Technology

[0003] Microelectronic circuits are typically fabricated using a process called photolithography or optical lithography, which patterns the various parts of a microelectronic circuit on a layer (e.g., a thin film) or surface of a semiconductor wafer (also called a substrate).

[0004] The process of using photolithography equipment is well known. This process uses light from a light source to project a geometric pattern from a photomask (also called a photomask or optical mask) onto a photosensitive chemical photoresist layer on the surface of a semiconductor wafer or a thin film (substrate) in one step. Exposure of the photoresist layer to light causes a chemical change in the exposed portions of the photoresist layer, allowing these exposed portions to be selectively removed, thereby forming a geometric pattern within the photoresist layer.

[0005] A series of chemical processes either etch the exposed portions that form the geometric pattern into the material or deposit new material (such as metal tracks or lines) on the exposed portions into the material beneath the photoresist layer in the desired geometric pattern. Subsequently, the photoresist layer is removed by chemically altering the remaining photoresist in the photoresist layer, so that the photoresist layer no longer adheres to the surface of the thin film or substrate.

[0006] Modern semiconductor wafers are large, making it impossible for optical masks or photomasks to simultaneously project geometric patterns onto the entire surface of the thin film or semiconductor wafer. As mentioned above, the geometric patterns to be projected onto the semiconductor wafer surface can be highly repetitive; therefore, a series of geometric patterns can be created in a photomask, which are selectively projected onto the surface of the thin film or semiconductor wafer. In this specification, these geometric patterns will be referred to as "blocks." The photomask is located in a stepper machine, which "steps" the photomask onto the surface of the thin film or semiconductor wafer in subsequent steps, thereby exposing selected areas of the photoresist layer. Light sources can be arranged such that only certain blocks at the desired locations on the surface of the semiconductor wafer or thin film are illuminated by the photomask. The projection and stepping steps continue until all geometric patterns are projected onto the surface of the thin film or semiconductor layer.

[0007] As mentioned above, in many applications, such as X-ray inspection, electronic inspection, industrial applications, machine vision, photogrammetry, or medium format photography, it is necessary to fabricate image sensors larger than the lithographic field (mask) on a semiconductor wafer. This lithographic field (mask) is generated by an optical mask and used to manufacture microelectronic devices. Because the edges of the mask need to support structures beyond the microelectronic circuit design, such as alignment marks or process control monitoring (PCM) structures, special techniques are required to fabricate large-area devices as image sensors. This technique is often referred to as "stitching" because a complete large-area device is formed by seamlessly "stitching" together several lithographic exposures.

[0008] The first splicing devices date back to the 1990s, when the fabrication of VLSI (Very Large Scale Integration) devices became more stable and yielded higher volumes. Although other applications were considered at the time, one of the earliest applications developed was in imaging. Examples of early imaging devices can be found in the following publication: PPSuni's publication "CCD wafer scale integration," which was published in the Proceedings of the IEEE International Conference on Wafer Scale Integration (ICWSI). doi:10.1109 / icwsi.1995.515446, and later PJ Pool, WAFFSuske, and JEU Ashton, “Design Aspect and Characterisation of EEV Large Area CCDs for Scientific & Medical Applications,” SPIE Vol. 1242, Charge-Coupled Devices and Solid-State Optical Sensors (1990), 17-25. All these examples refer to charge-coupled devices (CCDs), which were the dominant type of imaging device at the time.

[0009] After the invention of CMOS image sensors in the early 1990s, stitching technology was also applied to such devices. Reference patent US6194105B1 describes a method for fabricating stitched image sensors using CMOS technology, and this method is now used by most foundries to manufacture image sensors.

[0010] Unfortunately, some types of sensors, even those large enough to fill an entire wafer, are not large enough for certain applications, such as X-ray imaging. Therefore, sensors need to be "tiled" together to cover large areas, and the number of tiles required in one direction often exceeds two tiles. Consequently, sensors need to be manufactured with a minimum amount of "dead zone" on at least three sides so that the three sides can be matched together to form a larger area. In this case, the sensor is called "three-sided mating." In three-sided mating sensors, and even two-sided mating sensors, the "dead zone" (i.e., the area without an imaging element) on the mating surfaces should typically be less than half a pixel, so that when the sensors are mated together, at most one row—that is, one column or row—is lost.

[0011] Several methods exist for fabricating three-sided mating sensors. Korthout et al. described one method in their paper, *A wafer-scale CMOS APS imager for medical X-ray applications* (ISSW 2009, http: / / www.imagesensors.org / Past%20Workshops / 2009%20Workshop / 2009%20Papers / 070_paper_korthout_dalsa_wsc.pdf, downloaded February 18, 2020), in which certain columns of the image sensor carry shift registers for addressing. The presence of shift registers in the columns leads to a decrease in sensitivity of these columns of the image sensor, but this decrease in sensitivity can be corrected in the final image. This sensor is disclosed in a related patent, U.S. Patent No. 7,659,516, but that patent does not cover any details regarding the stitching or how to make the sensor three-sided mating possible. A method of introducing a logic circuit system within the pixel region is similar to that in U.S. Patent No. 7,009,646.

[0012] Other patents disclose similar methods. For example, in US7737390, selective exposure of a mask (in this case, a mask) is used to create blocks with slightly different designs, and then all control logic is moved to the bottom of the sensor, leaving no circuitry on three sides. US9247169 achieves the same result by using additional control lines and some circuitry directly integrated into the sensor's focal plane.

[0013] Similarly, UK patent application GB2504111 teaches an image sensor device comprising a pixel sensor array consisting of several mosaic blocks, each mosaic block containing pixel sensors arranged in at least one row group and having two sets of address lines, namely a first set of address lines and a second set of address lines. The arrangement of the pixel sensors and address lines is identical in each mosaic block. Row addressing circuitry is arranged along the outer edge of the array, parallel to the rows of pixel sensors, and coupled to the pixel sensors using the first set of address lines to perform row addressing. GB2504111 has a so-called "group addressing circuitry," which is also arranged along the same edge of the array and coupled to the pixel sensors using at least a portion of the second set of address lines to perform group addressing. The second set of address lines is L-shaped or stepped ("turn").

[0014] In GB2504111, each mosaic block combines row addressing with group addressing to select only one row from a group of rows within a mosaic block at a time. The first and second sets of addressing lines are connected to logic gates to address individual pixel sensors within the pixel sensor array. The interleaving or turning of the second set of addressing lines means that these (second set) addressing lines actually traverse the sensor array diagonally. The imaging sensor device has multiple readout lines arranged to provide signals from individual pixel sensors in each of the multiple rows of the pixel sensor array when selected by the first and second sets of addressing lines. These readout lines do not interleave (or turn).

[0015] European patent application EP3885832A1 describes a sensor fabricated on a semiconductor wafer in multiple layers, comprising multiple sensor elements arranged in blocks with multiple vertical readout lines. The multiple vertical readout lines extend from a bottom edge toward an opposite top edge, and multiple horizontal select / reset lines extend from a right edge to an opposite left edge. Multiple readout circuits are connected to the multiple vertical readout lines, wherein one of the multiple vertical readout lines has a bend at either the bottom edge or the top edge, such that a vertical readout line in a first block of the multiple blocks is connected to a staggered vertical readout line in an adjacent second block of the multiple blocks.

[0016] In the EP3885832A1, the number of pixel output lines must equal the number of tile blocks, which results in variations in the length and capacitance of the output lines due to the required wiring. These varying output line lengths and capacitances affect the low-pass filtering of the pixels, thus altering the noise characteristics depending on the tile block in which the pixel resides.

[0017] However, existing technologies do not disclose a sensor that does not require any logic within the pixel while maintaining a constant length and capacitance of the output line to reduce the impact on noise characteristics. Summary of the Invention

[0018] The purpose of this invention is to provide an enhanced sensor that overcomes the shortcomings of the prior art.

[0019] This document discloses a sensor fabricated from multiple layers on a semiconductor wafer. The sensor includes multiple sensor elements arranged in mosaic tiles. Each mosaic tile includes multiple vertically arranged control lines extending from a bottom edge of the tile to a top edge of the tile with opposite orientation. One of the vertically arranged control lines terminates between the bottom and top edges. Other control lines extend from the bottom edge to the top edge and have a bend at either the bottom or top edge, such that a control line in a first mosaic tile connects to a staggered vertical line in a adjacent second mosaic tile. The mosaic tiles also include at least one vertically arranged readout line extending from the bottom edge to the top edge. At least one vertically arranged readout line in the first mosaic tile connects to at least one vertically arranged readout line in an adjacent second mosaic tile. Multiple splicing blocks also include multiple horizontally arranged control lines that extend from the right edge to the opposite left edge and connect to the control lines in multiple vertically arranged control lines.

[0020] The term "sensor" refers to a device that detects and measures physical properties such as temperature, pressure, light, or motion. Sensors convert these physical quantities into electrical signals that can be read and interpreted by other devices or systems. Sensors are used in a wide range of applications, including automation, robotics, medical devices, and environmental monitoring. Sensors enable precise control and analysis by acquiring and feeding back data in real time.

[0021] The term "sensor element" refers to a unit, such as a pixel, in a digital image sensor that captures light and converts it into electrical signals. A pixel is composed of photosensitive elements (such as photodiodes) used to detect light intensity and color. Pixels are arranged on the sensor in a pattern such as a grid, with each pixel corresponding to a point in the captured image. The resolution of a sensor is determined by the number and distribution of pixels, which affects the detail and quality of the image. High-resolution sensors have more pixels, resulting in greater image sharpness and finer detail capture. Pixels in an image sensor are arranged in a grid-like matrix, forming rows and columns. Each pixel corresponds to a specific location in the captured image. Each intersection of a row and column represents a single pixel.

[0022] The term "stitching block" refers to modular design units used in the fabrication of integrated circuits, such as sensors. These blocks are designed to be repeated and seamlessly connected (or "stitched") on a substrate such as a silicon wafer to create larger, more complex circuits. Using stitching blocks enables the efficient production of large-scale devices by simplifying the design and manufacturing process. This modular approach enhances scalability, reduces design time, and improves yield. It is particularly useful in the production of image sensors, where the precise alignment and integration of multiple blocks is crucial for high-resolution performance.

[0023] The term "control line" refers to the control lines used to manage the operation of individual pixels within a sensor array. Control lines can include select lines and / or reset lines. Select lines and reset lines are the minimum set of lines required for an active pixel, but obviously, if a pixel requires different control lines, these different control lines can be implemented using the same scheme. Specifically, select lines are used to activate pixels in a specific row, thus enabling those pixels to be read out. On the other hand, reset lines are used to clear or reset the stored charge in a pixel, preparing the pixel for the next exposure. Select lines and reset lines work together for the sequential reading and refreshing of pixel data, ensuring accurate image capture and processing. Select lines and reset lines are indispensable to the timing and control circuitry of image sensors, contributing to the ordered operation and high-speed performance required for imaging applications. Row select lines activate pixels in a specific row, while column select lines enable the reading of individual pixels within that row.

[0024] The term "readout line" refers to the circuitry that facilitates the transfer of pixel data from the pixels of a sensor array to the output stage, where an image is created. When a specific pixel is selected using a select line, the readout line is enabled to access the pixel data from that pixel.

[0025] The term "swerve" refers to a change in direction, such as a sudden or abrupt change in direction, like a curve, a diagonal line, or a dogleg.

[0026] Using the sensor according to the first aspect, the length and capacitance of the readout lines can remain (substantially) constant, thereby reducing the impact on the sensor's noise characteristics. Furthermore, the response time of all pixel rows in the sensor is identical, thus avoiding potential image artifacts. The requirement in the prior art that the number of readout lines equals the number of vertically adjacent stitching blocks in the sensor is further eliminated, providing greater flexibility in the stitching scheme for manufacturing the sensor. This sensor can also implement a more traditional readout method, i.e., reading a group of rows at a time.

[0027] The term "offset vertical lines" refers to two vertical lines in two different splicing blocks. As mentioned above, several splicing blocks of a sensor are typically designed identically, with each block containing multiple vertically arranged control lines. Each control line in the vertically arranged control lines of a splicing block is arranged horizontally, that is, in a direction different from the direction in which the vertically arranged control lines extend, and is offset from the other vertically arranged control lines. For example, the first vertically arranged control line of a splicing block is offset or displaced horizontally relative to the second vertically arranged control line of the same splicing block. The term "offset vertical lines" now refers to the fact that, for example, it means the first vertically arranged control line of the first splicing block and the second vertically arranged control line of the second splicing block. If two splicing blocks are superimposed, then these two vertically arranged control lines (referred to as "displaced" relative to each other) will be offset from each other in the vertical direction.

[0028] The sensor element can be a 3-transistor pixel, a 4-transistor pixel, or a more transistor-type pixel. It should be understood that this does not limit the invention, and the sensor element can alternatively or additionally be any other type of pixel. It should also be noted that some pixels can "share" transistors, so the effective number of transistors per pixel can be fractional.

[0029] The term "3-transistor pixel" refers to a circuit that includes one photosensitive element (such as a photodiode) and three transistors (such as a metal-oxide-semiconductor field-effect transistor (MOSFET)).

[0030] The multiple horizontally arranged control lines may also include row select lines and row reset lines, and the sensor element is also connected to one of the row select lines and one of the row reset lines.

[0031] The row selection line that terminates in one of the splicing blocks can also be connected to a single selection line in a vertically arranged selection line.

[0032] The sensor may also include N splicing blocks and at least N vertically arranged control lines.

[0033] The turn can be a sharp turn.

[0034] The vertically arranged control lines can also be arranged into at least one group.

[0035] The vertically arranged control lines can also be arranged into at least two groups.

[0036] The at least two groups may also include one of a plurality of vertically arranged control lines terminating between the bottom edge and the top edge.

[0037] The sensor may also include M groups and at least M vertically arranged readout lines.

[0038] The sensor may also include M groups and at least M horizontally arranged control lines.

[0039] This application further discloses the use of the sensor according to the invention as an imaging sensor.

[0040] Advantageous aspects and / or embodiments of this disclosure are the subject of the dependent claims. Any and all combinations of at least two features disclosed in the specification, claims, and / or drawings fall within the scope of this disclosure. Specifically, linguistically common paraphrasing and / or similar substitutions of corresponding terms, particularly the use of synonyms supported by generally accepted linguistic literature, are of course included within the scope of this disclosure, without the need to explicitly mention all variations.

[0041] Those skilled in the art can combine all the aspects and / or embodiments described above according to their own circumstances. Other possible embodiments of the invention include any combination of features, aspects, and / or embodiments not explicitly mentioned in the foregoing or hereinafter described with respect to exemplary aspects and / or embodiments. For example, the invention can be applied to pixel architectures other than the 3T type pixels described herein, such as 4T or 5T pixels, thereby supporting correlated double sampling (CDS) and global shutter. In such cases, those skilled in the art can also add various aspects as improvements or supplements to the corresponding basic forms of the invention.

[0042] In this example, the word "one" should not be construed as limited to a single element. Instead, multiple elements may be provided, such as two, three, or more. Any other numbers used herein should also not be construed as limited to a precise number of the elements stated. Rather, unless otherwise stated, numerical deviations are possible. Attached Figure Description

[0043] Figure 1 The image shows a 3T-type pixel.

[0044] Figure 2 The image shows a 4T-type pixel.

[0045] Figure 3 The 3T pixel layout of a conventional sensor is shown.

[0046] Figure 4 This illustrates a 3T-type pixel layout that can be spliced ​​on three sides according to the present invention.

[0047] Figure 5 The layout of the topmost pixel of the splicing block according to the present invention is shown.

[0048] Figure 6 The layout of the splicing blocks according to the present invention is shown.

[0049] Figure 7 A mosaic block layout of a sensor according to the present invention is shown, wherein the pixel array consists of two repeating mosaic blocks in the horizontal and vertical directions. Detailed Implementation

[0050] The invention will now be described in conjunction with the accompanying drawings. It should be understood that the aspects and / or embodiments of the invention described herein are merely examples and do not limit the scope of the claims in any way. The invention is defined by the claims and their equivalents. It should be understood that a feature of one aspect and / or embodiment of the invention may be combined with features of one or more different aspects and / or embodiments of the invention.

[0051] Unless otherwise specified, identical or similar components in the figures will use the same reference numerals. It should also be noted that the illustrations in the figures are not necessarily drawn to scale.

[0052] It should be understood that terms such as “top,” “bottom,” “right,” “left,” “vertical,” “horizontal,” “row,” and “column” are used in this document only to distinguish various blocks, metal tracks, and circuits, and are not intended to have any meaning limited to a particular geometry.

[0053] Figure 1 The image shows a 3T type pixel. For simplicity, we will consider the 3T (3 transistors) type pixel as sensor element 700. Figure 1 A schematic diagram of the 3T-type pixel is shown. Figure 1 Three MOSFETs, 710, 720, and 730, are shown. Reset transistor 710 is connected to the reset RST line to reset sensor element 700. The gate of select transistor 730 is connected to the select SEL line to select sensor element 700 for readout via the output (OUT) line. The same or similar readout method can be applied to more complex sensor elements 700 or pixels.

[0054] Figure 2 This displays 4T-type pixels. 4T (4-transistor) type pixels are basically... Figure 1 The 3T type pixel shown has an additional transmission transistor 740 connected to the transmission line TX.

[0055] Figure 3The layout of a conventional 3T-type pixel is shown. For a layer of sensor element 700, the reset (RST) line and select (SEL) line are shown as horizontal tracks arranged in a row, and the OUT line is shown as vertical tracks arranged in a column. The layers are labeled M1, M2, M3, and M4, representing the metal tracks of different layers formed by the thin films of different layers of the sensor. V3_2 corresponds to a via created during the manufacturing process between the layers, connecting the metal track on layer M2 to the metal track on layer M3, commonly referred to as "via 2 to 3". The symbol M1_OUT is used as a shortcut to represent a combination of metal tracks and vias connecting a local output of sensor element 700 or a pixel on M1 to the output line on track M4. Of course, other combinations of metal layers are also possible.

[0056] These sensor elements 700 are read out using a so-called "rolling shutter" method. The basic idea of ​​"rolling readout" is that at any given time, one row in the sensor is selected for readout. In the sensor, the RST and SEL lines of all sensor elements 700 in the same row are connected together, and the OUT lines of all sensor elements 700 in the same column are connected together. In this way, the readout of a sensor element 700 is accomplished by generating a SEL signal for the row containing the sensor element 700. In this example, the SEL signal is connected to the gate of the selection transistor 730 in the sensor element 700, thereby activating all corresponding selection transistors 730 in the same row and connecting all sensor elements 700 in that row to their respective OUT lines. No other pixels in that column are connected to the OUT lines because the selection SEL value is low for all other rows; therefore, the voltage appearing on this OUT line depends only on the amount of charge in the photodiode of the connected sensor element 700 in the selected row. At the end of the readout, all sensor elements 700 in the selected row are reset by activating the RST transistor 710 in the sensor element 700 of that row. The pixels in that row can now begin integrating for the next frame, while control moves to the subsequent row and repeats the readout method until all rows have been read. In the subsequent row, the readout value on the corresponding OUT line corresponds to the amount of charge in the photodiode of the sensor element or pixel connected in that subsequent row.

[0057] This arrangement of horizontal control (RST and SEL) signals and vertical output lines in columns is standard practice in the art. In conventional (prior art) sensors, the row driver for applying RST and SEL signals to the sensor elements 700 in a row is located on the left and / or right side of the sensor element 700 array, while the output amplifier and related circuitry are located at the bottom of the sensor element 700 array. The row driver occupies some space on the semiconductor 5, which, although small, is typically equivalent to at least several pixels, even for sensors with larger pixels (e.g., >50μm). Therefore, sensors cannot be mated side-by-side, otherwise the gap between sensors would be too large.

[0058] One solution to address the issue of sensor docking on the left and right sides and at the top (even in traditional sensors, there is usually not much circuitry at the top) is to move the row-specific control circuitry to the bottom of the sensor. This changes the problem to how to address the horizontal row using the RST and / or SEL signals from the bottom of the sensor.

[0059] Figure 4 The layout of a 3T-type pixel with three mating sides according to the present invention is shown. To enable the sensor 1200 to be mating on three sides, the layout of each individual sensor element 900 has been modified, such as... Figure 4 As shown. Figure 4 The layout can be with Figure 3 Compared with existing technology layouts, it can be seen that vertical lines SEL / RES have been added to the exit OUT line. Vertical lines SEL / RES extend from the bottom edge 910 to the top edge 920 of the sensor element 900 array. The number of vertically arranged control lines 1205 has increased. The number of vertical control lines 1205 needs to be (at least) equal to the number of splicing blocks 1300 of the sensor 1200 in the vertical direction of the sensor 1200.

[0060] Figure 5 The layout of the topmost sensor element 1000 of the splicing block 1300 according to the present invention is shown. Figure 5 As shown, the layout of the topmost sensor element 1000 in each column of the splicing block 1300 of sensor 1200 will be modified at the top edge 1020. In this case, three of the four vertically arranged control lines 1205 will form a bend, such as a sharp bend 1030, just before the top edge 1020 of the topmost sensor element 1000. The sensor element 1000 will then be arranged in the splicing block 1300 as follows: Figure 6As shown. The sharp bend 1030 is created using a geometric pattern in the photomask of the mosaic block 1300 at the top sensor element 1000 of each column of sensor 1200. It can be understood that the design of the sharp bend 1030 is merely a non-limiting example of a "turn" or "deviation" from one vertically arranged select / readout line 1205 to another. This turn can also be achieved by a curve, arc, or diagonal. It is only required that the vertically arranged select / readout lines 1205 do not form a continuous column running through the mosaic blocks 1300, and that one end of a vertically arranged select / readout line 1205 in one mosaic block 1300 is located at the starting position of the other end of a vertically arranged select / readout line 1205 in a subsequent mosaic block 1300. It can be understood that the sharp bend design is most efficient in terms of space utilization.

[0061] Figure 6 The layout of the splicing block 1300 according to the invention is shown. Notably, the V3_2 via 1100 for connecting the vertical M3 line to the horizontal M2 line is placed in one and only one sensor element 700 in each column and each row. Thus, each vertically arranged control line 1205 has a unique correspondence with a horizontally arranged control line 1210, and in each splicing block 1300, the row can be uniquely addressed. If the number of rows is not equal to the number of columns, more or fewer vertically arranged control lines 1205 can be provided, and the vias 1100 placed accordingly. For simplicity, Figure 6 Only the case of square blocks is shown, but this is not a design limitation.

[0062] It can be seen that in each column, the leftmost vertically arranged control line 1205-1 does not reach the top column edge 1120 of the splicing block 1300.

[0063] Figure 7 The layout of the stitching blocks 1300 of the sensor 1200 according to the present invention is shown, wherein the pixel array is composed of stitching blocks 1300 repeated twice in the horizontal and vertical directions. The sensor 1200 or the pixel array is composed of 2x2 stitching blocks. The edges of the stitching blocks 1300 are marked with thick lines, but it should be understood that these thick lines are not physical lines, but are added only to facilitate the identification of individual stitching blocks 1300 within the stitching blocks 1300.

[0064] The leftmost vertically arranged selection line 1205-1 in each of the mosaic blocks 1300 terminates at position 1250 between the topmost horizontally arranged control line 1210 within the mosaic block 1300 and the top edge 1020 of the mosaic block 1200. This leftmost vertically arranged selection line 1205-1 enables the selection of all sensor elements 700 in the bottom row 1260 of the mosaic block 1300, which are addressed by the bottom horizontally arranged selection line 1210 in each of the mosaic blocks 1300. The sensor element 700 selected by the leftmost vertically arranged selection line 1205-1 can then be read out using the readout line 1230. The sensor element 700 in the left column 1270 of the lower left mosaic block 1300 will be connected to the readout line 1230, while the sensor element 700 in the left column 1270 of the upper left mosaic block will be connected to the readout line 1230 of the upper left mosaic block 1300, and the readout line 1230 of the upper left mosaic block 1300 will be connected to the readout line 1230 of the lower left mosaic block 1300.

[0065] The leftmost vertically arranged selection line 1205-1 of the top-left tile 1300 terminates at position 1250 within tile 1300, selecting all sensor elements 700 in the bottom row 1260 of the top-left tile 1300. These sensor elements are addressed by the bottom horizontally arranged selection line 1210 of the top-left tile, and then the sensor elements 700 are connected to the readout line 1230. The leftmost vertically arranged selection line 1205-1 of the top-left tile 1300 connects to the second left vertically arranged selection line 1205-2 of the bottom-left tile 1300. In this example, the leftmost vertically arranged selection line 1250-1 of the bottom-left tile 1300 selects a row in the bottom-left tile 1300, the second left vertically arranged selection line 1250-2 selects a row in the top-left tile 1300, and in this simplified example, the selected sensor elements 700 are read out on a common readout line 1230.

[0066] The number of rows that can be read simultaneously is independent of the splicing size N (vertical) x M (horizontal). The number of selection lines 1205-1 for each pixel is at least N vertical lines so that all rows can be addressed.

[0067] By avoiding physical connections between adjacent rows, this means that if one control line fails or is lost, multiple rows in adjacent rows will not be lost. The loss of multiple rows and / or columns almost certainly means the sensor will be considered inoperable. Since any faulty line is separated by a splice block, the defect will only be a single faulty line, which is generally acceptable. As long as the number of acceptable single faulty lines on the sensor is not too large and meets specifications, the sensor can improve manufacturing yield by selecting criteria. It is worth noting that this is also an improvement over non-spliced ​​sensors, in which multiple lines are adjacent whenever selected. Those skilled in the art will understand that the same techniques described herein can also be applied to non-spliced ​​sensors to improve the yield of fast sensors.

[0068] In the diagram, the horizontal lines in the rows of sensor 1200 are shown as complete and extend uninterruptedly from the right vertical edge of panel 1300 to the left vertical edge of panel 1300, so that the rows pass uninterruptedly across all panels 1300 on the entire sensor 1200. This is possible, but not necessary, as the horizontal lines could terminate before the right edge of panel 1300. No special technique is required to do this, as panel 1300 will remain identical. Whether it is better to break the horizontal lines at the edges of each panel 1300 depends on the design of the microelectronic circuitry.

[0069] Figure Labels 5 Semiconductor wafers / thin films 700 sensor element 710 reset transistor 720 transistors 730 Select Transistor 740 Transmission Transistor 900 sensor element 910 bottom edge 920 top edge 1000 sensor elements 1010 bottom edge 1020 top edge 1030 sharp bend 1100 via 1120 Top column edge 1200 pixel array 1205 vertically arranged control lines 1210 horizontally arranged control lines 1230 Readout Line 1240 top pixel 1250 position 1260 bottom row 1270 left column 1300 splicing blocks 1400 sets.

Claims

1. A sensor (1200) made of multiple layers on a semiconductor wafer (5) and comprising multiple sensor elements (700) arranged in multiple splicing blocks (1300), wherein, The plurality of splicing blocks (1300) include Multiple vertically arranged control lines (1205-1, 1205-2) extend from the bottom edge (1010) of the splicing block (1300) towards its opposite top edge (1020). One of the multiple vertically arranged control lines (1205-1) terminates between the bottom edge (1010) and the top edge (1020); and The other control lines (1205-2) of the plurality of vertically arranged control lines extend from the bottom edge (1010) to the top edge (1020) and have a turn (1030) at one of the bottom edge (1010) or the top edge (1020), such that the plurality of control lines (1205-2) of the plurality of vertically arranged control lines in the first splice block (1300-1) of the plurality of splice blocks (1300) are connected to the staggered vertical lines (1205-1) of the vertical lines in the adjacent second splice block (1300-2) of the plurality of splice blocks (1300). At least one vertically aligned readout line (1230) extending from the bottom edge (1010) to the top edge (1020), wherein the at least one vertically aligned readout line (1230) in the first splice block (1300-1) of the plurality of splice blocks (1300) is connected to the at least one vertically aligned readout line (1230) in the adjacent second splice block (1300-2) of the plurality of splice blocks (1300); and Multiple horizontally arranged control lines (1210) extend from the right edge to the opposite left edge and connect with multiple control lines among the multiple vertically arranged control lines (1210).

2. The sensor (1200) according to claim 1, wherein, The sensor element (700) is one of a 3-transistor pixel, a 4-transistor pixel, and a 5-transistor pixel.

3. The sensor (1200) according to claim 1 or 2, wherein, The plurality of horizontally arranged control lines (1210) include row selection lines and row reset lines, wherein the sensor element (700) is connected to one of the row selection lines and one of the row reset lines.

4. The sensor (1200) according to any one of the preceding claims, wherein, The row selection line (1205-1) terminating in one of the multiple splicing blocks (1300) is connected to a single selection line in the vertically arranged selection lines (1210).

5. The sensor (1200) according to any one of the preceding claims, wherein, There are N splicing blocks and at least N vertically arranged control lines (1205-1, 1205-2).

6. The sensor (1200) according to any one of the preceding claims, wherein, The turn is a sharp bend (1030).

7. The sensor (1200) according to any one of the preceding claims, wherein, The vertically arranged control lines (1205-1, 1205-2) are arranged into at least one group (1400-1).

8. The sensor (1200) according to any one of the preceding claims, wherein, The vertically arranged control lines (1205-1, 1205-2) are arranged into at least two groups (1400-1, 1400-2).

9. The sensor (1200) according to claim 8, wherein, The at least two sets (1400-1, 1400-2) include a control line (1205-1) among the plurality of vertically arranged control lines that terminates between the bottom edge (1010) and the top edge (1020).

10. The sensor (1200) according to any one of claims 7 to 9, wherein, There are M groups (1400) and at least M vertically arranged readout lines (1230).

11. The sensor (1200) according to any one of claims 7 to 10, wherein, There are M groups (1400) and at least M horizontally arranged control lines (1210).

12. Use of the sensor (1200) according to any one of claims 1 to 11 as an imaging sensor.

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