Epitaxial wafer and system for surface defect analysis and surface defect analysis method

Abstract

The invention discloses an epitaxial wafer and system for surface defect analysis and a surface defect analysis method. The epitaxial wafer for surface defect analysis comprises an epitaxial wafer which is set to be of a first conductive type and comprises a first surface; the electron transport layer is located on the first surface; the electric connection layer comprises a plurality of electrodes arranged in an array, and the electrodes are used for inputting or outputting electric signals; a defect to-be-detected area is formed between every two adjacent electrodes. According to the embodiment of the invention, the analysis cost of epitaxial wafer surface defects can be reduced, and the accuracy of surface defect analysis is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to an epitaxial wafer and system for surface defect analysis, and a surface defect analysis method. BACKGROUND

[0002] Semiconductor devices of third-generation wide-bandgap semiconductor materials such as silicon carbide or gallium nitride have become a research hotspot of power semiconductor devices due to their large critical breakdown field strength, high thermal conductivity, large bandgap, and high electron saturation drift speed.

[0003] Among them, there are various methods for analyzing the near-surface defects of the epitaxial wafer in the semiconductor device, involving multiple disciplines such as physics, chemistry, and electricity. These methods include optical methods, electron microscopy, atomic-level analysis, X-ray diffraction technology, and electrical analysis. In actual production and application, multiple analysis methods are usually combined to comprehensively evaluate the nature and distribution of defects. However, the existing technology relies on high-cost analysis equipment for defect identification, and the obtained defect information is limited. SUMMARY

[0004] The present application provides an epitaxial wafer and system for surface defect analysis, and a surface defect analysis method, to reduce the analysis cost of surface defects of the epitaxial wafer and improve the accuracy of surface defect analysis.

[0005] In a first aspect, an epitaxial wafer for surface defect analysis is provided, comprising: The epitaxial wafer is set to a first conductivity type and includes a first surface; An electron transport layer is located on the first surface; An electrical connection layer is located on the side of the electron transport layer away from the first surface and includes a plurality of electrodes arranged in an array, the electrodes being used for inputting or outputting electrical signals; a defect-to-be-tested region is formed between each adjacent two electrodes.

[0006] Optionally, the thickness of the electron transport layer ranges from 20 to 100 nm.

[0007] Optionally, the material of the electron transport layer includes any one of zinc oxide, titanium dioxide, or tin dioxide.

[0008] Optionally, the projection of the electrode on the first surface is a rectangle and extends along a first direction; In a second direction, the region between adjacent two electrodes is the defect-to-be-tested region; The first direction intersects the second direction.

[0009] Optionally, the material of the electrode includes aluminum metal.

[0010] In a second aspect, a surface defect analysis system is provided, comprising: a current detection device and an epitaxial wafer for surface defect analysis according to any embodiment of the first aspect.

[0011] In a third aspect, a method for surface defect analysis of an epitaxial wafer is provided, comprising: providing an epitaxial wafer; the epitaxial wafer is set to a first conductivity type and comprises a first surface; forming an electron transport layer on the first surface; forming an electrical connection layer on a side of the electron transport layer away from the first surface; the electrical connection layer comprises a plurality of electrodes arranged in an array, and a defect to be tested region is formed between each adjacent two electrodes; applying current to at least one group of adjacent two electrodes to perform current testing on the defect to be tested region to determine the type and location of defects present in the defect to be tested region.

[0012] Optionally, the forming of the electron transport layer on the first surface comprises: preparing a preset solution with a preset concentration; spin coating the preset solution on the first surface of the epitaxial wafer and performing high-temperature annealing to form the electron transport layer.

[0013] Optionally, the applying current to at least one group of adjacent two electrodes to perform current testing on the defect to be tested region to determine the type and location of defects present in the defect to be tested region comprises: collecting input end electrical signals and output end electrical signals of adjacent two electrodes during current testing, respectively; drawing a current density variation distribution map of the defect to be tested region according to the input end electrical signals and the output end electrical signals; determining the location and type of defects present in the defect to be tested region according to the current density variation distribution map.

[0014] Optionally, before forming the electron transport layer on the first surface, the method further comprises: performing surface defect characterization on the epitaxial wafer to determine a surface defect analysis result of the epitaxial wafer; after drawing the current density variation distribution map of the defect to be tested region according to the input end electrical signals and the output end electrical signals, the method further comprises: constructing an epitaxial wafer defect model according to the surface defect analysis result and the current density variation distribution map drawn during current testing; the epitaxial wafer defect model represents the mapping relationship between the surface defect type and the current density.

[0015] The epitaxial wafer for surface defect analysis provided by the embodiments of the present application is provided with an electron transmission layer on a first surface of the epitaxial wafer, and an electric connection layer is provided on a side of the electron transmission layer away from the first surface, the electric connection layer includes a plurality of electrodes, and a defect to be tested region is formed between any two adjacent electrodes. The electrodes are used to input or output electric signals, and the electron transmission layer is used to provide an electron transmission channel. By testing any two adjacent electrodes, an electric current can be generated in the electron transmission layer corresponding to the defect to be tested region, so as to test the current density in the region and determine the distribution of the current density. If there is a defect near the surface of the epitaxial wafer, the defect will capture the electrons in the transmission channel, so that the current density in the defect to be tested region is uneven. Therefore, the position of the surface defect of the epitaxial wafer and related information can be directly determined according to the distribution of the current density, the analysis cost of the surface defect is effectively reduced, and the accuracy of defect detection and analysis is improved.

[0016] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0018] Figure 1 is a schematic diagram of a cross-sectional structure of an epitaxial wafer for surface defect analysis according to an embodiment of the present application; Figure 2 is a schematic diagram of a top view structure of an epitaxial wafer for surface defect analysis according to an embodiment of the present application; Figure 3 is Figure 2 is a schematic diagram of an enlarged structure of the dashed line part in Figure 4 is Figure 3 is a schematic diagram of a top view structure of Figure 5 is a schematic diagram of a flow of a surface defect analysis method of an epitaxial wafer according to an embodiment of the present application; Figure 6 is a specific flow of step S120 in a surface defect analysis method of an epitaxial wafer according to an embodiment of the present application; Figure 7is a specific flowchart of step S140 in a surface defect analysis method of an epitaxial wafer provided by the embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to enable persons skilled in the art to better understand the scheme of the present application, the technical scheme in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative labor should belong to the protection scope of the present application.

[0020] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0021] The embodiment of the present application provides an epitaxial wafer for surface defect analysis. Figure 1 The embodiment of the present application provides a cross-sectional structure diagram of an epitaxial wafer for surface defect analysis. As shown in the figure, the epitaxial wafer for surface defect analysis comprises: Figure 1 The epitaxial wafer for surface defect analysis comprises: The epitaxial wafer 100 is arranged as a first conductive type and comprises a first surface 101; The electron transport layer 200 is located on the first surface 101; The electrically connected layer 300 is located on the side of the electron transport layer 200 away from the first surface 101, and comprises a plurality of electrodes 301 arranged in an array. The electrodes 301 are used for inputting or outputting electrical signals. A defect to be tested region 302 is formed between each adjacent two electrodes 301.

[0022] Exemplarily, the epitaxial wafer 100 can comprise a substrate and an epitaxial layer. In some embodiments of the present application, the epitaxial wafer 100 can also only comprise an epitaxial layer, which is not limited herein. Figure 1The epitaxial wafer 100 is shown to include only the epitaxial layer 10. The epitaxial layer 10 is a semiconductor layer formed on the basis of the substrate 10 by a one-time epitaxial process, which includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), and the like. In the embodiments of the present application, the epitaxial wafer 100 can be a doped silicon carbide layer having a first conductivity type. For example, for an epitaxial wafer used to prepare an N-type semiconductor device, the first conductivity type is N-type; for an epitaxial wafer used to prepare a P-type semiconductor device, the first conductivity type is P-type. In this embodiment, the conductivity type of the epitaxial wafer 100 is not limited.

[0023] The epitaxial wafer 100 is shown to include only the epitaxial layer 10. The epitaxial layer 10 is a semiconductor layer formed on the basis of the substrate 10 by a one-time epitaxial process, which includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), and the like. In the embodiments of the present application, the epitaxial wafer 100 can be a doped silicon carbide layer having a first conductivity type. For example, for an epitaxial wafer used to prepare an N-type semiconductor device, the first conductivity type is N-type; for an epitaxial wafer used to prepare a P-type semiconductor device, the first conductivity type is P-type. In this embodiment, the conductivity type of the epitaxial wafer 100 is not limited.

[0024] For the epitaxial wafer used for surface defect analysis, by inputting an electrical signal to one of the two adjacent electrodes 301 and outputting an electrical signal from the other, an electrical current can be generated in the electron transport layer 200 corresponding to the defect detection area 302 between the two adjacent electrodes 301, so that the corresponding current density distribution of the defect detection area 302 can be collected and determined. If there is a defect near the surface of the epitaxial wafer 100, the electron transport layer 200 corresponding to the defect will capture the electrons in the transmission channel, that is, the current will increase, so that the current density in the range of the defect detection area 302 corresponding to the electron transport layer 200 is uneven. Thus, according to the corresponding current density distribution in the defect detection area 302, the presence of surface defects in the defect detection area 302 and the location of the defects can be determined intuitively, and then the current test of the defect detection area 302 between each adjacent two electrodes 301 can be performed in turn to obtain the corresponding current density distribution, so that the location of the surface defect of the complete epitaxial wafer 100 and the information related to the defect can be determined. Compared with the analysis of the surface defects of the epitaxial wafer 100 by using the expensive analysis equipment in the related art, the cost of analyzing the surface defects of the epitaxial wafer 100 is effectively reduced, and the accuracy and intuitiveness of defect detection and analysis are improved.

[0025] The epitaxial wafer for surface defect analysis provided by the embodiment of the present application is provided with an electron transport layer 200 on the first surface 101 of the epitaxial wafer 100, and an electrical connection layer 300 is provided on the side of the electron transport layer 200 away from the first surface 101, the electrical connection layer 300 includes a plurality of electrodes 301, and a defect detection area 302 is formed between adjacent two electrodes 301. The electrode 301 is used to input an input end electrical signal or output an output end electrical signal, and the electron transport layer 302 is used to provide an electron transmission channel. By applying a test current to any adjacent two electrodes 301, an electrical current can be generated in the range of the electron transport layer 200 corresponding to the defect detection area 302 to test the current density in the area and determine the current density distribution. If there is a defect near the surface of the epitaxial wafer 100, the electron transport layer 200 corresponding to the defect will capture the electrons in the transmission channel, so that the current density in the defect detection area 302 is uneven. Thus, according to the current density distribution, the location of the surface defect of the epitaxial wafer and the related information can be determined intuitively, the analysis cost of the surface defect is effectively reduced, and the accuracy of defect detection and analysis is improved.

[0026] Based on the above embodiment, continue to refer to Figure 1 Optionally, the thickness of the electron transport layer 200 is in the range of 20-100 nm.

[0027] Specifically, the thickness of the electron transport layer 200 has a great influence on the electron transport after power-on. Therefore, the thickness of the electron transport layer 200 is preferably in the range of 20-100 nm. Preferably, the thickness of the electron transport layer 200 is 50 nm. If the thickness of the electron transport layer 200 is too thin, the electron transport layer 200 can not be prepared by normal process technology; if the thickness of the electron transport layer 200 is too thick, the electron transport layer 200 itself can have many defects, which can affect the uneven distribution of current density caused by the defects near the surface of the epitaxial wafer; and in the electron transport layer 200 with too thick thickness, the electrons can recombine, thereby reducing the current density in the electron transport layer 200, which in turn can reduce the accuracy of the surface defect analysis of the epitaxial wafer 100.

[0028] On the basis of the above-mentioned embodiments, optionally, the material of the electron transport layer 200 includes any one of zinc oxide, titanium dioxide or tin dioxide.

[0029] Specifically, the material of the electron transport layer 200 can be a wide-bandgap semiconductor oxide, which has the advantages of high electron mobility, good optical transparency and strong chemical stability, and can make the electron transport layer 200 better exhibit the influence of the defects near the surface of the epitaxial wafer on the current density distribution, thereby accurately and intuitively determining the position of the surface defects and the related position. Illustratively, the material of the electron transport layer 200 can include any one of zinc oxide (ZnO), titanium dioxide (TiO2) or tin dioxide (SnO2).

[0030] On the basis of the above-mentioned embodiments, Figure 2 is a top view structural schematic diagram of an epitaxial wafer for surface defect analysis provided by the embodiments of the present application, Figure 3 is Figure 2 is an enlarged structural schematic diagram of the dashed portion in Figure 4 is Figure 3 is a top view structural schematic diagram of Figures 1 to 4 Optionally, the projection of the electrode 301 on the first surface 101 is a rectangle extending along the first direction Y. In the second direction X, the area between the adjacent two electrodes 301 is the defect to-be-tested area 302. The first direction Y intersects the second direction X.

[0031] Specifically, the electrode 301 in the electrical connection layer 300 can be a long strip-shaped cube, and the projection on the first surface 101 is a rectangle. Illustratively, the first direction can be the X direction and the second direction can be the Y direction; or the first direction can also be the Y direction and the second direction can be the X direction, which is not limited herein. In the embodiments of the present application, the first direction is taken as the Y direction and the second direction is taken as the X direction as an example for illustration.Figure 2 The electrodes 301 extend in the first direction Y and are arranged in parallel at intervals along the second direction X, and a plurality of electrodes 301 can also be arranged at intervals in the first direction Y, that is, a multi-row and multi-column arrangement is formed.

[0032] Wherein, referring to Figure 3 and Figure 4 , which shows the case of a defect to be tested region 302 in the epitaxial wafer 100. For a region surrounded by two adjacent electrodes 301, for example: Figure 4 The region surrounded by the red solid line in is a defect to be tested region 302. Among them, one of the two adjacent electrodes 301 is an input electrode 311, and the other is an output electrode 312. Figure 4 , which shows the case of a surface defect 00 in the defect to be tested region 302. Since the defect to be tested region 302 with the defect 00 near the surface of the epitaxial wafer 100 will appear to be electrically leaked, an input electrical signal is input to the input electrode 311 to generate a current in the electron transport layer 200 in the defect to be tested region 302, which flows from the input electrode 311 to the output electrode 312, and an output electrical signal is output by the output electrode 312. By collecting the input electrical signal and the output electrical signal, the current between the input electrode 311 and the output electrode 312 can be determined, and the current density can be obtained by dividing the current by the area of the defect to be tested region 302, so as to determine the current density distribution of the defect to be tested region 302. In the case of the presence of the surface defect 00 in the epitaxial wafer 100, the current density distribution of the defect to be tested region 302 will appear to be uneven, resulting in a decrease in the current density, so as to determine the position and related type of the surface defect 00.

[0033] The embodiment of the present application also provides a surface defect analysis system. The surface defect analysis system comprises a current detection device and the epitaxial wafer for surface defect analysis provided by any of the above embodiments. The surface defect analysis system provided by the embodiment of the present application is used for surface defect detection and analysis of the epitaxial wafer for surface defect analysis provided by any of the above embodiments, and has similar analysis principles and beneficial effects as the epitaxial wafer for surface defect analysis, which will not be repeated here.

[0034] The embodiment of the present application also provides a surface defect analysis method of an epitaxial wafer. Figure 5 is a flow diagram of a surface defect analysis method of an epitaxial wafer provided by the embodiment of the present application. Referring to Figure 1 and Figure 5 , optionally, the surface defect analysis method of the epitaxial wafer specifically comprises the following steps: S110, providing an epitaxial wafer; the epitaxial wafer is set to a first conductive type and comprises a first surface.

[0035] Specifically, the epitaxial wafer 100 can include a substrate and an epitaxial layer, or can only include the epitaxial layer 10, which is not limited herein.

[0036] S120, forming an electron transport layer on the first surface.

[0037] Specifically, by forming the electron transport layer 200 with a certain thickness on the first surface 101 of the epitaxial wafer 100, a channel for transporting electrons can be formed.

[0038] S130, forming an electrical connection layer on the side of the electron transport layer away from the first surface; the electrical connection layer includes a plurality of electrodes arranged in an array, and a defect-to-be-tested region is formed between each adjacent two electrodes.

[0039] Specifically, a plurality of electrodes 301 are formed on the surface of the electron transport layer 200 by using a vapor deposition process, and the electrodes 301 are arranged in a certain array arrangement, so that a defect-to-be-tested region 302 is formed between each adjacent two electrodes, so as to divide the first surface 101 of the complete epitaxial wafer 100 into a plurality of defect-to-be-tested regions 302, so as to analyze the surface defects of the epitaxial wafer 100.

[0040] S140, energizing at least one group of adjacent two electrodes, and performing current testing on the defect-to-be-tested region to determine the type and position of defects existing in the defect-to-be-tested region.

[0041] Specifically, by energizing at least one group of adjacent two electrodes 301, an electrical signal is input from an input electrode and output from an output electrode, so as to form a current in the region of the electron transport layer 200 corresponding to the defect-to-be-tested region 302, so as to determine the position and related type information of the surface defects existing in the defect-to-be-tested region 302 through the distribution of the current density change, thereby effectively reducing the analysis cost of the surface defects of the epitaxial wafer 100, and facilitating to improve the accuracy and intuitiveness of the surface defect analysis of the epitaxial wafer.

[0042] The surface defect analysis method of the epitaxial wafer provided in the embodiments of the present application forms an electron transport layer on the first surface of the epitaxial wafer, and forms an electrical connection layer on the surface of the electron transport layer, the electrical connection layer includes a plurality of electrodes, and a defect-to-be-tested region is formed between each adjacent two electrodes. By energizing at least one group of adjacent two electrodes, a current is generated in the region of the electron transport layer corresponding to the defect-to-be-tested region, which can reflect the distribution of the current density in the region. Since the position of the defects existing on the surface of the epitaxial wafer is prone to leakage, the specific position and related type information of the surface defects existing in the corresponding defect-to-be-tested region of the epitaxial wafer can be determined through the distribution of the current density change in the corresponding region of the electron transport layer. In this way, the analysis cost of the surface defects of the epitaxial wafer can be effectively reduced, and the accuracy and intuitiveness of the surface defect analysis of the epitaxial wafer can be improved.

[0043] On the basis of the above embodiments, Figure 6 is a specific flowchart of step S120 in the method for analyzing surface defects of an epitaxial wafer provided by the embodiments. Referring to Figure 6 Optionally, the step of forming an electron transport layer on the first surface in step S120 specifically includes the following steps. S121, preparing a predetermined solution with a predetermined concentration.

[0044] Illustratively, taking ZnO as an example of the material of the electron transport layer, an ammonia zinc oxide solution with a certain predetermined concentration is prepared in advance as a raw material for standby.

[0045] S122, spin coating the predetermined solution on the first surface of the epitaxial wafer, and performing high-temperature annealing to form an electron transport layer.

[0046] Illustratively, the spin coating method can be used to spin coat the prepared ammonia zinc oxide solution on the first surface of the epitaxial wafer, and the epitaxial wafer after spin coating is annealed at high temperature to form a ZnO electron transport layer. In addition, in addition to the spin coating method, chemical solution deposition method, pyrolysis method or vacuum sputtering method can also be used to form the electron transport layer, which is not limited here.

[0047] On the basis of the above embodiments, Figure 7 is a specific flowchart of step S140 in the method for analyzing surface defects of an epitaxial wafer provided by the embodiments. Referring to Figure 7 Optionally, the step of passing current through at least one set of adjacent two electrodes in step S140 to perform current testing on the defect to be tested region to determine the defect type and position existing in the defect to be tested region specifically includes the following steps. S141, collecting input end electrical signals and output end electrical signals of the adjacent two electrodes during the current testing process.

[0048] Specifically, the current detection device is used, the output end thereof is electrically connected with the input end electrode of the adjacent two electrodes, and the input end thereof is electrically connected with the output end electrode of the adjacent two electrodes to input the corresponding current detection electrical signals to the electrodes. After the electrodes are powered on, current will be generated in the corresponding region of the electron transport layer, so that the input end electrical signals and the output end electrical signals are collected respectively.

[0049] S142, drawing a current density variation distribution map of the defect to be tested region according to the input end electrical signals and the output end electrical signals.

[0050] Specifically, the current density variation distribution map of the defect to be tested region can be drawn according to the collected input end electrical signals and output end electrical signals.

[0051] S143, determining the position of the defect and the type of the defect in the defect to be tested region according to the current density change distribution map.

[0052] Specifically, for the defect to be tested region without surface defects, the corresponding current density change distribution map shows uniform current density. For the defect to be tested region with surface defects, there is electric leakage at the position of the defect, which captures the electrons transmitted in the electron transport layer, so that the current density change distribution map of the defect to be tested region shows unevenness at the defect. In this way, the position of the surface defect and the related type information can be determined intuitively and accurately.

[0053] On the basis of the above embodiments, before the first surface forms the electron transport layer in step S120, the following steps are further included: The epitaxial wafer is subjected to surface defect characterization to determine the surface defect analysis result of the epitaxial wafer.

[0054] Specifically, when initially establishing the surface defect library, before the epitaxial wafer is subjected to surface defect analysis by using the current density test method, the epitaxial wafer can be first subjected to conventional surface defect characterization by using the analysis equipment, so as to determine a surface defect analysis result in advance by using the equipment detection method, as a data basis.

[0055] After step S142 of drawing the current density change distribution map of the defect to be tested region according to the input end electrical signal and the output end electrical signal, the following steps are further included: According to the surface defect analysis result and the current density change distribution map drawn in the current test process, an epitaxial wafer defect model is constructed; the epitaxial wafer defect model represents the mapping relationship between the surface defect type and the current density.

[0056] Specifically, the epitaxial wafer is further subjected to current density test, and the current density change distribution map of the corresponding defect to be tested region is drawn, which is then compared with the surface defect analysis result characterized in advance, so as to establish the corresponding mapping relationship between the defect type and the current density, and to construct the epitaxial wafer defect model, so that the defect position and the defect type of the epitaxial wafer surface can be determined directly by using the current density test method in the future.

[0057] The above specific embodiments do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An epitaxial wafer for surface defect analysis, characterized by, include: An epitaxial wafer, configured as a first conductivity type, and including a first surface; An electron transport layer is located on the first surface; An electrical connection layer, located on the side of the electron transport layer away from the first surface, includes multiple electrodes arranged in an array, which are used to input or output electrical signals; a defect test area is formed between each pair of adjacent electrodes.

2. The epiwafer for surface defect analysis according to claim 1, wherein, The thickness of the electron transport layer ranges from 20 to 100 nm.

3. The epiwafer for surface defect analysis of claim 1, wherein, The material of the electron transport layer includes any one of zinc oxide, titanium dioxide, or tin dioxide.

4. The epiwafer for surface defect analysis of claim 1, wherein, The electrode's orthographic projection onto the first surface is rectangular and extends along the first direction; In the second direction, the region between two adjacent electrodes is the defect test area; The first direction intersects with the second direction.

5. The epiwafer for surface defect analysis of claim 1, wherein, The electrode is made of aluminum.

6. A surface defect analysis system characterized by comprising: include: The current detection device and the epitaxial wafer for surface defect analysis as described in any one of claims 1-5.

7. A method for analyzing surface defects in epitaxial wafers, characterized in that, include: An epitaxial wafer is provided; the epitaxial wafer is configured with a first conductivity type and includes a first surface; An electron transport layer is formed on the first surface; An electrical connection layer is formed on the side of the electron transport layer away from the first surface; the electrical connection layer includes a plurality of electrodes arranged in an array, and a defect test area is formed between each pair of adjacent electrodes; At least one pair of adjacent electrodes are energized to perform a current test on the defect test area in order to determine the type and location of defects present in the defect test area.

8. The surface defect analysis method for epitaxial wafers according to claim 7, characterized in that, The formation of an electron transport layer on the first surface includes: Prepare a pre-set solution with a preset concentration; The preset solution is spin-coated onto the first surface of the epitaxial wafer and then subjected to high-temperature annealing to form the electron transport layer.

9. The surface defect analysis method for epitaxial wafers according to claim 7, characterized in that, The step of energizing at least one pair of adjacent electrodes to perform a current test on the defect test area to determine the type and location of defects present in the defect test area includes: During the current test, the input and output electrical signals of the two adjacent electrodes are collected respectively. Based on the input electrical signal and the output electrical signal, plot the current density variation distribution map of the defect test area; Based on the current density variation distribution map, the location and type of defects within the defect test area are determined.

10. The surface defect analysis method for epitaxial wafers according to claim 9, characterized in that, Before the electron transport layer is formed on the first surface, the following is also included: The surface defects of the epitaxial wafer are characterized to determine the surface defect analysis results of the epitaxial wafer; After plotting the current density variation distribution map of the defect test area based on the input terminal electrical signal and the output terminal electrical signal, the method further includes: Based on the surface defect analysis results and the current density variation distribution map plotted during the current testing process, an epitaxial wafer defect model is constructed; the epitaxial wafer defect model characterizes the mapping relationship between surface defect types and current densities.

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