A control circuit of a permanent magnet synchronous motor and an identification method thereof

Abstract

The application discloses a control circuit of a permanent magnet synchronous motor and a recognition method thereof. A pulse generation circuit provides a first driving signal. A comparison circuit compares a first current with a first reference current and outputs a first level when the first current is greater than or equal to the first reference current. A pulse capture circuit acquires a first time of the first driving signal. A conversion circuit collects a first voltage of a bus of an inverter circuit. The pulse generation circuit provides a second driving signal. The comparison circuit compares the first current with a second reference current and outputs the first level when the first current is greater than or equal to the second reference current. The pulse capture circuit acquires a second time of the second driving signal. The conversion circuit collects a second voltage of the bus of the inverter circuit. A processor obtains a first inductance and a first resistance according to the first voltage, the second voltage, the first reference current, the second reference current, the first time and the second time. The detection duration can be reduced, and the detection efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of motor technology, and in particular to a control circuit and identification method for a permanent magnet synchronous motor. Background Technology

[0002] With the gradual promotion and application of permanent magnet synchronous motors, permanent magnet synchronous motors are a widely used type of motor. They have advantages such as high efficiency, good dynamic response performance, and low noise, and are widely used in electric vehicles, robots, or other equipment that requires high efficiency.

[0003] Existing technologies require two different testing methods to detect the resistance and inductance of permanent magnet synchronous motors, which involves first detecting the resistance and then the inductance. This process is time-consuming and complex. Summary of the Invention

[0004] This application mainly provides a control circuit and identification method for a permanent magnet synchronous motor, which can solve the technical problems of long detection time and complex detection process.

[0005] This application provides a control circuit for a permanent magnet synchronous motor. The permanent magnet synchronous motor is connected to an inverter circuit and has a first phase, a second phase, and a third phase. The control circuit includes a processor, a pulse generating circuit, a pulse capturing circuit, a comparator circuit, and a conversion circuit. The processor is connected to the pulse generating circuit, the pulse capturing circuit, the comparator circuit, and the conversion circuit. The comparator circuit is connected to the pulse generating circuit and the conversion circuit. The pulse capturing circuit is connected to the pulse generating circuit. The comparator circuit is used to receive a first current between the first phase and the second phase, a second current between the second phase and the third phase, or a third current between the third phase and the first phase.

[0006] The pulse generating circuit provides a first drive signal to the power transistors corresponding to the first phase and the second phase. The comparison circuit is used to compare the first current with the first reference current and output a first level when the first current is greater than or equal to the first reference current. The pulse generator is used to stop outputting the first drive signal according to the first level. The pulse capturing circuit acquires the first time of the first drive signal. The conversion circuit is used to acquire the first voltage of the bus of the inverter circuit according to the first level.

[0007] The pulse generating circuit provides a second drive signal to the power transistors corresponding to the first phase and the second phase. The comparison circuit is used to compare the first current with the second reference current and output the first level when the first current is greater than or equal to the second reference current. The pulse generator is used to stop outputting the second drive signal according to the first level. The pulse capturing circuit acquires the second time of the second drive signal. The conversion circuit is used to acquire the second voltage of the bus of the inverter circuit according to the first level.

[0008] The processor is configured to obtain a first inductance and a first resistance between the first phase and the second phase based on the first voltage, the second voltage, the first reference current, the second reference current, the first time, and the second time; the second reference current is greater than the first reference current.

[0009] The pulse generating circuit provides the first drive signal to the power transistor corresponding to the second phase and the third phase. The comparison circuit is used to compare the second current with the first reference current and output the first level when the second current is greater than or equal to the first reference current. The pulse generator is used to stop outputting the first drive signal according to the first level. The pulse capturing circuit acquires the third time of the first drive signal. The conversion circuit is used to acquire the third voltage of the bus of the inverter circuit according to the first level.

[0010] The pulse generating circuit provides the second drive signal to the power transistor corresponding to the second phase and the third phase. The comparison circuit is used to compare the second current with the second reference current and output the first level when the second current is greater than or equal to the second reference current. The pulse generator is used to stop outputting the second drive signal according to the first level. The pulse capturing circuit acquires the fourth time of the second drive signal. The conversion circuit is used to acquire the fourth voltage of the bus of the inverter circuit according to the first level.

[0011] The processor is used to obtain a second inductance and a second resistance between the second phase and the third phase based on the third voltage, the fourth voltage, the first reference current, the second reference current, the third time, and the fourth time.

[0012] The pulse generating circuit provides the first drive signal to the power transistor corresponding to the third phase and the first phase. The comparison circuit compares the third current with the first reference current and outputs the first level when the third current is greater than or equal to the first reference current. The pulse generator stops outputting the first drive signal according to the first level. The pulse capturing circuit acquires the fifth time of the first drive signal. The conversion circuit acquires the fifth voltage of the bus of the inverter circuit according to the first level.

[0013] The pulse generating circuit provides the second drive signal to the power transistor corresponding to the third phase and the first phase. The comparison circuit is used to compare the third current with the second reference current and output the first level when the third current is greater than or equal to the second reference current. The pulse generator is used to stop outputting the second drive signal according to the first level. The pulse capturing circuit acquires the sixth time of the second drive signal. The conversion circuit is used to acquire the sixth voltage of the bus of the inverter circuit according to the first level.

[0014] The processor is used to obtain a third inductance and a third resistance between the third phase and the first phase based on the fifth voltage, the sixth voltage, the first reference current, the second reference current, the fifth time, and the sixth time.

[0015] Wherein, the first inductor satisfies the following formula:

[0016] ;

[0017] Where L1 is the first inductor, V1 is the first voltage, V2 is the second voltage, I1 is the first reference current, I2 is the second reference current, T1 is the first time, and T2 is the second time; the first resistor satisfies the following formula:

[0018] ;

[0019] Wherein, R1 is the first resistor; the second inductor satisfies the following formula:

[0020] ;

[0021] Wherein, L2 is the second inductor, V3 is the third voltage, V4 is the fourth voltage, T3 is the third time, and T4 is the fourth time; the second resistor satisfies the following formula:

[0022] ;

[0023] Wherein, R2 is the second resistor; the third inductor satisfies the following formula:

[0024] ;

[0025] Wherein, L3 is the third inductor, V5 is the fifth voltage, V6 is the sixth voltage, T5 is the fifth time, and T6 is the sixth time; the third resistor satisfies the following formula:

[0026] ;

[0027] R3 is the third resistor.

[0028] The processor is used to obtain the quadrature-axis inductance and direct-axis inductance of the permanent magnet synchronous motor based on the first inductor, the second inductor, and the third inductor.

[0029] The quadrature-axis inductance of the permanent magnet synchronous motor satisfies the following formula:

[0030] ;

[0031] Wherein, Lq is the quadrature axis inductance, L1 is the first inductance, L2 is the second inductance, and L3 is the third inductance;

[0032] The direct-axis inductance satisfies the following formula:

[0033] ;

[0034] Ld is the direct-axis inductance shown.

[0035] The processor is configured to obtain the first stator resistance of the first phase, the second stator resistance of the second phase, and the third stator resistance of the third phase based on the first resistor, the second resistor, and the third resistor.

[0036] The first stator resistance of the first phase satisfies the following formula:

[0037] ;

[0038] RU is the first stator resistance of the first phase, R1 is the first resistor, R2 is the second resistor, and R3 is the third resistor; the second stator resistance of the second phase satisfies the following formula:

[0039] ;

[0040] RV is the second stator resistance of the second phase; the third stator resistance of the third phase satisfies the following formula:

[0041] ;

[0042] RW is the third stator resistance of the third phase.

[0043] The inverter circuit includes a first power transistor, a second power transistor, a third power transistor, a fourth power transistor, a fifth power transistor, a sixth power transistor, and a capacitor. A first bus of the inverter circuit is connected to one end of the capacitor, the first end of the first power transistor, the first end of the third power transistor, and the first end of the fifth power transistor. A second bus of the inverter circuit is connected to the other end of the capacitor, the second end of the second power transistor, the second end of the fourth power transistor, and the second end of the sixth power transistor. A first phase is connected to the second end of the first power transistor and the first end of the second power transistor. A second phase is connected to the second end of the third power transistor and the first end of the fourth power transistor. A third phase is connected to the second end of the fifth power transistor and the first end of the sixth power transistor. The control terminals of the first power transistor, the second power transistor, the third power transistor, the fourth power transistor, the fifth power transistor, and the sixth power transistor are all connected to the pulse generating circuit.

[0044] When the pulse generating circuit provides a first drive signal or a second drive signal to the power transistors corresponding to the first phase and the second phase, the first power transistor and the fourth power transistor are turned on.

[0045] When the pulse generating circuit provides the first drive signal or the second drive signal to the power transistor corresponding to the second phase and the third phase, the third power transistor and the sixth power transistor are turned on.

[0046] When the pulse generating circuit provides the first drive signal or the second drive signal to the power transistor corresponding to the third phase and the first phase, the fifth power transistor and the second power transistor are turned on.

[0047] This application also provides a method for identifying a permanent magnet synchronous motor, applied to the aforementioned control circuit, the identification method comprising:

[0048] The pulse generating circuit provides a first drive signal to the power transistors corresponding to the first phase and the second phase, and the comparison circuit is used to compare the first current with the first reference current, and outputs a first level when the first current is greater than or equal to the first reference current.

[0049] The pulse generator is used to stop outputting the first drive signal according to the first level, the pulse capture circuit is used to obtain the first time of the first drive signal, and the conversion circuit is used to collect the first voltage of the bus of the inverter circuit according to the first level.

[0050] The pulse generating circuit provides a second drive signal to the power transistors corresponding to the first phase and the second phase. The comparison circuit is used to compare the first current with the second reference current and output the first level when the first current is greater than or equal to the second reference current.

[0051] The pulse generator is used to stop outputting the second drive signal according to the first level, the pulse capture circuit is used to obtain the second time of the second drive signal, and the conversion circuit is used to collect the second voltage of the bus of the inverter circuit according to the first level.

[0052] The processor is configured to obtain a first inductance and a first resistance between the first phase and the second phase based on the first voltage, the second voltage, the first reference current, the second reference current, the first time, and the second time; the second reference current is greater than the first reference current.

[0053] The beneficial effects of this application are as follows: This application provides a first drive signal to the power transistors corresponding to the first phase and the second phase through a pulse generation circuit; the processor is used to compare the first current with the first reference current and output a first level when the first current is greater than or equal to the first reference current; the pulse generator is used to stop outputting the first drive signal according to the first level; the pulse capture circuit acquires the first time of the first drive signal; and the conversion circuit is used to acquire the first voltage of the inverter circuit bus according to the first level. The pulse generation circuit also provides a second drive signal to the power transistors corresponding to the first phase and the second phase; the processor is used to compare the first current with the second reference current and output a first level when the first current is greater than or equal to the second reference current; the pulse generator is used to stop outputting the second drive signal according to the first level; the pulse capture circuit acquires the second time of the second drive signal; and the conversion circuit acquires the second voltage of the inverter circuit bus according to the first level. The processor is used to obtain the first inductance and the first resistance between the first phase and the second phase based on the first voltage, the second voltage, the first reference current, the second reference current, the first time, and the second time. The second reference current is greater than the first reference current. By setting up a processor, pulse generation circuit, pulse capture circuit, comparison circuit, and conversion circuit, the power transistors of the first and second phases are detected twice to obtain the first voltage, second voltage, first reference current, second reference current, first time, and second time. The processor obtains the first inductance and first resistance based on the first voltage, second voltage, first reference current, second reference current, first time, and second time. By using the same detection method twice, the detection time can be reduced, the detection efficiency can be improved, the calculation can be simplified, and the efficiency can be increased. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0055] Figure 1 This is a circuit diagram of one embodiment of the permanent magnet synchronous motor and inverter circuit provided in this application;

[0056] Figure 2 This is a circuit diagram of one embodiment of the control circuit provided in this application;

[0057] Figure 3 This is a flowchart illustrating an embodiment of the identification method for permanent magnet synchronous motors provided in this application. Detailed Implementation

[0058] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0060] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly indicating the number, specific order, or primary and secondary relationship of the indicated technical features.

[0061] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0062] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a connection between two components or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0063] Please see Figure 1 and Figure 2 As shown, Figure 1 This is a circuit diagram of one embodiment of the permanent magnet synchronous motor and inverter circuit provided in this application; Figure 2This is a circuit diagram of one embodiment of the control circuit provided in this application. The permanent magnet synchronous motor 100 of this embodiment can be applied to electric vehicles or robots, etc. The permanent magnet synchronous motor 100 is connected to the inverter circuit 200. The permanent magnet synchronous motor 100 has a first phase, a second phase and a third phase. For example, the first phase can be the U phase of the permanent magnet synchronous motor 100, the second phase can be the V phase of the permanent magnet synchronous motor 100, and the third phase can be the W phase of the permanent magnet synchronous motor 100.

[0064] The control circuit 300 in this embodiment includes a processor 10, a pulse generation circuit 20, a pulse capture circuit 30, a comparison circuit 40, and a conversion circuit 50. The conversion circuit 50 can be an analog-to-digital converter, the comparison circuit 40 can be a comparator, the pulse generation circuit 20 can be a pulse generator, and the pulse capture circuit 30 can be a pulse capture device.

[0065] In some embodiments, the processor 10 can be a microcontroller unit (MCU), and both the pulse generation circuit 20 and the pulse capture circuit 30 can be disposed within the processor 10, that is, the processor 10 integrates the pulse generation circuit 20 and the pulse capture circuit 30, which will not be described in detail here.

[0066] The processor 10 is connected to the pulse generation circuit 20, the pulse capture circuit 30, the comparison circuit 40, and the conversion circuit 50, respectively. The comparison circuit 40 is connected to the pulse generation circuit 20 and the conversion circuit 50, respectively. The pulse capture circuit 30 is connected to the pulse generation circuit 20.

[0067] The comparator circuit 40 is used to receive a first current between the first phase and the second phase, a second current between the second phase and the third phase, or a third current between the third phase and the first phase. For example, the first current between the first phase and the second phase is the inductor current between the U phase and the V phase of the permanent magnet synchronous motor 100; the second current between the second phase and the third phase is the inductor current between the V phase and the W phase of the permanent magnet synchronous motor 100; and the third current between the third phase and the first phase is the inductor current between the W phase and the U phase of the permanent magnet synchronous motor 100.

[0068] In some embodiments, the control circuit 300 further includes a plurality of current sensors (not shown), and the comparison circuit 40 receives a first current, a second current, or a third current through the current sensors. The current sensors can be current sensors in the prior art, which will not be described in detail here.

[0069] The pulse generating circuit 20 is connected to the power transistors of the inverter circuit 200. The pulse generating circuit 20 provides a first drive signal to the power transistors corresponding to the first and second phases. At this time, the comparator circuit 40 receives a first current between the first and second phases and compares this first current with a first reference current I1. It outputs a first level when the first current is greater than or equal to the first reference current I1. For example, the comparator circuit 40 outputs a second level when the first current is less than the first reference current I1 and outputs a first level when the first current is greater than or equal to the first reference current I1. The first level is high, and the second level is low; that is, when the first current is less than the first reference current I1, the pulse generating circuit 20 continuously provides the first drive signal to the power transistors corresponding to the first and second phases.

[0070] The pulse generating circuit 20 and the conversion circuit 50 receive a first level from the comparator circuit 40. The pulse generating circuit 20 stops outputting the first drive signal based on the first level, for example, by disconnecting the power transistors corresponding to the first and second phases. At this time, the pulse capturing circuit 30 acquires the first time T1 of the first drive signal. For example, the pulse capturing circuit 30 starts timing at the rising edge of the captured first drive signal and stops timing at the falling edge of the captured first drive signal, thereby acquiring the first time T1 of the first drive signal. The conversion circuit 50 acquires the first voltage V1 of the bus of the inverter circuit 200 based on the first level; that is, the conversion circuit 50 acquires the first voltage V1 of the bus of the inverter circuit 200 when it receives the first level.

[0071] The pulse generating circuit 20 provides a second drive signal to the power transistors corresponding to the first and second phases. At this time, the comparator circuit 40 receives a first current between the first and second phases and compares this first current with a second reference current I2. It outputs a first level when the first current is greater than or equal to the second reference current I2. For example, the comparator circuit 40 outputs a second level when the first current is less than the second reference current I2 and outputs a first level when the first current is greater than or equal to the second reference current I2. The first level is high, and the second level is low. That is, when the first current is less than the second reference current I2, the pulse generating circuit 20 continuously provides the second drive signal to the power transistors corresponding to the first and second phases.

[0072] The pulse generating circuit 20 and the conversion circuit 50 receive a first level from the comparator circuit 40. The pulse generating circuit 20 stops outputting the second drive signal based on the first level, for example, by disconnecting the power transistors corresponding to the first and second phases. At this time, the pulse capturing circuit 30 acquires the second time T2 of the second drive signal. For example, the pulse capturing circuit 30 starts timing at the rising edge of the captured second drive signal and stops timing at the falling edge of the captured second drive signal, thereby acquiring the second time T2 of the second drive signal. The conversion circuit 50 acquires the second voltage V2 of the inverter circuit 200 bus based on the first level; that is, the conversion circuit 50 acquires the second voltage V2 of the inverter circuit 200 bus when it receives the first level.

[0073] The processor 10 is used to acquire a first voltage V1, a second voltage V2, a first reference current I1, a second reference current I2, a first time T1, and a second time T2, and to obtain a first inductance L1 and a first resistance R1 between the first phase and the second phase based on the first voltage V1, the second voltage V2, the first reference current I1, the second reference current I2, the first time T1, and the second time T2; the second reference current I2 is greater than the first reference current I1.

[0074] In some embodiments, the nameplate of the permanent magnet synchronous motor 100 has a rated current, where the first reference current I1 can be 30% of the rated current and the second reference current I2 can be 60% of the rated current. In other embodiments, the first reference current I1 can be other proportions of the rated current and the second reference current I2 can be other proportions of the rated current, for example, the first reference current I1 can be 25% of the rated current and the second reference current I2 can be 55% of the rated current, which will not be elaborated further here.

[0075] This embodiment, by setting up a processor 10, a pulse generation circuit 20, a pulse capture circuit 30, a comparison circuit 40, and a conversion circuit 50, enables two detections of the power transistors corresponding to the first and second phases, obtaining a first voltage V1, a second voltage V2, a first reference current I1, a second reference current I2, a first time T1, and a second time T2. The processor 10 obtains the first inductor L1 and the first resistor R1 based on the first voltage V1, the second voltage V2, the first reference current I1, the second reference current I2, the first time T1, and the second time T2. By using the same detection method twice, the detection time can be reduced, the detection efficiency can be improved, the calculation can be simplified, and the efficiency can be increased.

[0076] In this embodiment, the pulse generating circuit 20 provides a first drive signal to the power transistors corresponding to the second and third phases. At this time, the comparator circuit 40 receives a second current between the second and third phases and compares this second current with a first reference current I1. It then outputs a first level when the second current is greater than or equal to the first reference current I1. For example, the comparator circuit 40 outputs a second level when the second current is less than the first reference current I1 and outputs a first level when the second current is greater than or equal to the first reference current I1. The first level is high, and the second level is low. That is, when the second current is less than the first reference current I1, the pulse generating circuit 20 continuously provides the first drive signal to the power transistors corresponding to the second and third phases.

[0077] The pulse generating circuit 20 and the conversion circuit 50 receive a first level from the comparator circuit 40. The pulse generating circuit 20 stops outputting the first drive signal based on the first level, for example, by turning off the power transistors corresponding to the second and third phases. At this time, the pulse capturing circuit 30 acquires the third time T3 of the first drive signal. For example, the pulse capturing circuit 30 starts timing at the rising edge of the captured first drive signal and stops timing at the falling edge of the captured first drive signal, thereby acquiring the third time T3 of the first drive signal. The conversion circuit 50 acquires the third voltage V3 of the bus of the inverter circuit 200 based on the first level; that is, the conversion circuit 50 acquires the third voltage V3 of the bus of the inverter circuit 200 when it receives the first level.

[0078] The pulse generating circuit 20 provides a second drive signal to the power transistors corresponding to the second and third phases. At this time, the comparator circuit 40 receives a second current between the second and third phases and compares this second current with a second reference current I2. It outputs a first level when the second current is greater than or equal to the second reference current I2. For example, the comparator circuit 40 outputs a second level when the second current is less than the second reference current I2 and outputs a first level when the second current is greater than or equal to the second reference current I2. The first level is high, and the second level is low. That is, when the second current is less than the second reference current I2, the pulse generating circuit 20 continuously provides the second drive signal to the power transistors corresponding to the second and third phases.

[0079] The pulse generating circuit 20 and the conversion circuit 50 receive a first level from the comparator circuit 40. The pulse generating circuit 20 stops outputting the second drive signal based on the first level, for example, by turning off the power transistors corresponding to the second and third phases. At this time, the pulse capturing circuit 30 acquires the fourth time T4 of the second drive signal. For example, the pulse capturing circuit 30 starts timing at the rising edge of the captured second drive signal and stops timing at the falling edge of the captured second drive signal, thereby acquiring the fourth time T4 of the second drive signal. The conversion circuit 50 acquires the fourth voltage V4 of the inverter circuit 200 bus based on the first level; that is, the conversion circuit 50 acquires the fourth voltage V4 of the inverter circuit 200 bus when it receives the first level.

[0080] The processor 10 is used to acquire the third voltage V3, the fourth voltage V4, the first reference current I1, the second reference current I2, the third time T3, and the fourth time T4, and to obtain the second inductance L2 and the second resistance R2 between the second phase and the third phase based on the third voltage V3, the fourth voltage V4, the first reference current I1, the second reference current I2, the third time T3, and the fourth time T4.

[0081] This embodiment, by setting up a processor 10, a pulse generation circuit 20, a pulse capture circuit 30, a comparison circuit 40, and a conversion circuit 50, enables the power transistors of the second and third phases to be detected twice, obtaining the third voltage V3, the fourth voltage V4, the first reference current I1, the second reference current I2, the third time T3, and the fourth time T4. The processor 10 obtains the second inductor L2 and the second resistor R2 based on the third voltage V3, the fourth voltage V4, the first reference current I1, the second reference current I2, the third time T3, and the fourth time T4. By using the same detection method twice, the detection time can be reduced, the detection efficiency can be improved, the calculation can be simplified, and the efficiency can be increased.

[0082] In this embodiment, the pulse generating circuit 20 provides a first drive signal to the power transistor corresponding to the third phase and the first phase. At this time, the comparator circuit 40 receives a third current between the third phase and the first phase, compares the third current with the first reference current I1, and outputs a first level when the third current is greater than or equal to the first reference current I1. For example, the comparator circuit 40 outputs a second level when the third current is less than the first reference current I1, and outputs a first level when the third current is greater than or equal to the first reference current I1. The first level is a high level, and the second level is a low level; that is, when the third current is less than the first reference current I1, the pulse generating circuit 20 continuously provides the first drive signal to the power transistor corresponding to the third phase and the first phase.

[0083] The pulse generating circuit 20 and the conversion circuit 50 receive a first level from the comparator circuit 40. The pulse generating circuit 20 stops outputting the first drive signal based on the first level, for example, by turning off the power transistor corresponding to the third phase and the first phase. At this time, the pulse capturing circuit 30 acquires the fifth time T5 of the first drive signal. For example, the pulse capturing circuit 30 starts timing at the rising edge of the captured first drive signal and stops timing at the falling edge of the captured first drive signal, thereby acquiring the fifth time T5 of the first drive signal. The conversion circuit 50 acquires the fifth voltage V5 of the bus of the inverter circuit 200 based on the first level; that is, the conversion circuit 50 acquires the fifth voltage V5 of the bus of the inverter circuit 200 when it receives the first level.

[0084] The pulse generating circuit 20 provides a second drive signal to the power transistors corresponding to the third phase and the first phase. At this time, the comparator circuit 40 receives a third current between the third phase and the first phase, compares this third current with a second reference current I2, and outputs a first level when the third current is greater than or equal to the second reference current I2. For example, the comparator circuit 40 outputs a second level when the third current is less than the second reference current I2, and outputs a first level when the third current is greater than or equal to the second reference current I2. The first level is high, and the second level is low; that is, when the third current is less than the second reference current I2, the pulse generating circuit 20 continuously provides the second drive signal to the power transistors corresponding to the third phase and the first phase.

[0085] The pulse generating circuit 20 and the conversion circuit 50 receive a first level from the comparator circuit 40. The pulse generating circuit 20 stops outputting the second drive signal based on the first level, for example, by turning off the power transistor corresponding to the third phase and the first phase. At this time, the pulse capturing circuit 30 acquires the sixth time T6 of the second drive signal. For example, the pulse capturing circuit 30 starts timing at the rising edge of the captured second drive signal and stops timing at the falling edge of the captured second drive signal, thereby acquiring the sixth time T6 of the second drive signal. The conversion circuit 50 acquires the sixth voltage V6 of the inverter circuit 200 bus based on the first level; that is, the conversion circuit 50 acquires the sixth voltage V6 of the inverter circuit 200 bus when it receives the first level.

[0086] The processor 10 is used to acquire the fifth voltage V5, the sixth voltage V6, the first reference current I1, the second reference current I2, the fifth time T5, and the sixth time T6, and to obtain the third inductance L3 and the third resistance R3 between the third phase and the first phase based on the fifth voltage V5, the sixth voltage V6, the first reference current I1, the second reference current I2, the fifth time T5, and the sixth time T6.

[0087] This embodiment, by setting up a processor 10, a pulse generation circuit 20, a pulse capture circuit 30, a comparison circuit 40, and a conversion circuit 50, enables two detections of the power transistors corresponding to the third phase and the first phase, obtaining the fifth voltage V5, the sixth voltage V6, the first reference current I1, the second reference current I2, the fifth time T5, and the sixth time T6. The processor 10 obtains the third inductor L3 and the third resistor R3 based on the fifth voltage V5, the sixth voltage V6, the first reference current I1, the second reference current I2, the fifth time T5, and the sixth time T6. By using the same detection method twice, the detection time can be reduced, the detection efficiency can be improved, the calculation can be simplified, and the efficiency can be increased.

[0088] The first inductor L1 in this embodiment satisfies the following formula:

[0089] ;

[0090] ;

[0091] Combining the two formulas above, we get:

[0092] ;

[0093] Where L1 is the first inductor, V1 is the first voltage, V2 is the second voltage, I1 is the first reference current, I2 is the second reference current, T1 is the first time, and T2 is the second time.

[0094] In this embodiment, the first resistor R1 satisfies the following formula:

[0095] ;

[0096] Where R1 is the first resistor. The second inductor L2 satisfies the following formula:

[0097] ;

[0098] Where L2 is the second inductor, V3 is the third voltage, V4 is the fourth voltage, T3 is the third time, and T4 is the fourth time.

[0099] The second resistor R2 satisfies the following formula:

[0100] ;

[0101] Where R2 is the second resistor. The third inductor L3 satisfies the following formula:

[0102] ;

[0103] Where L3 is the third inductor, V5 is the fifth voltage, V6 is the sixth voltage, T5 is the fifth time interval, and T6 is the sixth time interval. The third resistor R3 satisfies the following formula:

[0104] ;

[0105] R3 is the third resistor.

[0106] Specifically, the first inductor L1 is the inductance between the U phase and V phase of the permanent magnet synchronous motor 100, and the first resistor R1 is the resistance between the U phase and V phase of the permanent magnet synchronous motor 100; the second inductor L2 is the inductance between the V phase and W phase of the permanent magnet synchronous motor 100, and the second resistor R2 is the resistance between the V phase and W phase of the permanent magnet synchronous motor 100; the third inductor L3 is the inductance between the W phase and U phase of the permanent magnet synchronous motor 100, and the third resistor R3 is the resistance between the W phase and U phase of the permanent magnet synchronous motor 100.

[0107] The processor 10 in this embodiment is used to obtain the quadrature axis inductance Lq and direct axis inductance Ld of the permanent magnet synchronous motor 100 based on the first inductance L1, the second inductance L2 and the third inductance L3.

[0108] The quadrature-axis inductance Lq of the permanent magnet synchronous motor 100 satisfies the following formula:

[0109] ;

[0110] Where Lq is the quadrature axis inductance, L1 is the first inductance, L2 is the second inductance, and L3 is the third inductance.

[0111] The direct-axis inductance Ld of the permanent magnet synchronous motor 100 satisfies the following formula:

[0112] ;

[0113] Ld is the direct-axis inductance shown.

[0114] The processor 10 in this embodiment is used to obtain the quadrature axis inductance Lq and direct axis inductance Ld of the permanent magnet synchronous motor 100 based on the first inductance L1, the second inductance L2 and the third inductance L3. The operation is simple and efficient, and it can obtain the key parameters of the permanent magnet synchronous motor 100 (quadrature axis inductance Lq and direct axis inductance Ld).

[0115] The processor 10 in this embodiment is used to obtain the first stator resistance RU of the first phase, the second stator resistance RV of the second phase, and the third stator resistance RW of the third phase based on the first resistor R1, the second resistor R2, and the third resistor R3.

[0116] The first stator resistance RU of the first phase satisfies the following formula:

[0117] ;

[0118] RU is the first stator resistance of the first phase, R1 is the first resistor, R2 is the second resistor, and R3 is the third resistor. The second stator resistance RV of the second phase satisfies the following formula:

[0119] ;

[0120] RV is the second stator resistance of the second phase. The third stator resistance RW of the third phase satisfies the following formula:

[0121] ;

[0122] RW is the third stator resistor of the third phase.

[0123] This embodiment is used to obtain the first stator resistance RU of the first phase, the second stator resistance RV of the second phase, and the third stator resistance RW of the third phase based on the first resistor R1, the second resistor R2, and the third resistor R3. The calculation is simple, the efficiency is improved, and the key parameters of the permanent magnet synchronous motor 100 (the first stator resistance RU of the first phase, the second stator resistance RV of the second phase, and the third stator resistance RW of the third phase) can be obtained.

[0124] Please continue reading Figure 1 and Figure 2 As shown, the inverter circuit 200 of this embodiment includes a first power transistor M1, a second power transistor M2, a third power transistor M3, a fourth power transistor M4, a fifth power transistor M5, a sixth power transistor M6, and a capacitor C.

[0125] The first bus 201 of the inverter circuit 200 is connected to one end of the capacitor C, the first end of the first power transistor M1, the first end of the third power transistor M3 and the first end of the fifth power transistor M5, respectively. The second bus 202 of the inverter circuit 200 is connected to the other end of the capacitor C, the second end of the second power transistor M2, the second end of the fourth power transistor M4 and the second end of the sixth power transistor M6, respectively.

[0126] The first phase (U phase) of the permanent magnet synchronous motor 100 is connected to the second end of the first power transistor M1 and the first end of the second power transistor M2, respectively. The second phase (V phase) of the permanent magnet synchronous motor 100 is connected to the second end of the third power transistor M3 and the first end of the fourth power transistor M4, respectively. The third phase (W phase) of the permanent magnet synchronous motor 100 is connected to the second end of the fifth power transistor M5 and the first end of the sixth power transistor M6, respectively.

[0127] The control terminals of the first power transistor M1, the second power transistor M2, the third power transistor M3, the fourth power transistor M4, the fifth power transistor M5, and the sixth power transistor M6 are all connected to the pulse generating circuit 20. The pulse generating circuit 20 is used to control the first power transistor M1, the second power transistor M2, the third power transistor M3, the fourth power transistor M4, the fifth power transistor M5, and the sixth power transistor M6 to be turned on or off.

[0128] Specifically, when the pulse generating circuit 20 provides a first drive signal or a second drive signal to the power transistors corresponding to the first and second phases, the first power transistor M1 and the fourth power transistor M4 are turned on, while the second power transistor M2, the third power transistor M3, the fifth power transistor M5, and the sixth power transistor M6 are all turned off. When the pulse generating circuit 20 stops providing the first drive signal and the second drive signal to the power transistors corresponding to the first and second phases, the first power transistor M1, the second power transistor M2, the third power transistor M3, the fourth power transistor M4, the fifth power transistor M5, and the sixth power transistor M6 are all turned off.

[0129] When the pulse generating circuit 20 provides the first drive signal or the second drive signal to the power transistors corresponding to the second and third phases, the third power transistor M3 and the sixth power transistor M6 are turned on, and the first power transistor M1, the second power transistor M2, the fourth power transistor M4 and the fifth power transistor M5 are all turned off.

[0130] When the pulse generating circuit 20 provides the first drive signal or the second drive signal to the power transistors corresponding to the third phase and the first phase, the fifth power transistor M5 and the second power transistor M2 are turned on, and the first power transistor M1, the third power transistor M3, the fourth power transistor M4 and the sixth power transistor M6 are all turned off.

[0131] The inverter circuit 200 of this embodiment includes a first power transistor M1, a second power transistor M2, a third power transistor M3, a fourth power transistor M4, a fifth power transistor M5, a sixth power transistor M6, and a capacitor C. The pulse generation circuit 20 outputs a first drive signal or a second drive signal to control the corresponding power transistor to conduct, thereby realizing detection and improving efficiency.

[0132] Please see Figure 3 As shown, Figure 3 This is a flowchart illustrating an embodiment of the identification method for a permanent magnet synchronous motor provided in this application. The identification method of this embodiment is applied to the control circuit 300 disclosed in the above embodiment. The identification method of this embodiment includes the following steps.

[0133] Step S101: The pulse generation circuit 20 provides a first drive signal to the power transistors corresponding to the first phase and the second phase. The comparison circuit 40 compares the first current with the first reference current I1 and outputs a first level when the first current is greater than or equal to the first reference current I1.

[0134] The pulse generating circuit 20 provides a first drive signal to the power transistors corresponding to the first and second phases. At this time, the comparator circuit 40 receives a first current between the first and second phases, compares the first current with a first reference current I1, and outputs a first level when the first current is greater than or equal to the first reference current I1. For example, the comparator circuit 40 is used to output a second level when the first current is less than the first reference current I1, and output a first level when the first current is greater than or equal to the first reference current I1. The first level is a high level, and the second level is a low level; that is, when the first current is less than the first reference current I1, the pulse generating circuit 20 continuously provides a first drive signal to the power transistors corresponding to the first and second phases.

[0135] Step S102: The pulse generation circuit 20 stops outputting the first drive signal according to the first level, the pulse capture circuit 30 obtains the first time T1 of the first drive signal, and the conversion circuit 50 collects the first voltage V1 of the bus of the inverter circuit 200 according to the first level.

[0136] The pulse generating circuit 20 and the conversion circuit 50 receive a first level signal from the comparator circuit 40. The pulse generating circuit 20 stops outputting the first drive signal based on the first level signal, for example, by disconnecting the power transistors corresponding to the first and second phases. At this time, the pulse capturing circuit 30 acquires the first time T1 of the first drive signal. For example, the pulse capturing circuit 30 starts timing at the rising edge of the captured first drive signal and stops timing at the falling edge of the captured first drive signal, thereby acquiring the first time T1 of the first drive signal. The conversion circuit 50 acquires the first voltage V1 of the inverter circuit 200 bus based on the first level signal; that is, the conversion circuit 50 acquires the first voltage V1 of the inverter circuit 200 bus upon receiving the first level signal.

[0137] Step S103: The pulse generation circuit 20 provides a second drive signal to the power transistors corresponding to the first and second phases. The comparison circuit 40 compares the first current with the second reference current I2 and outputs a first level when the first current is greater than or equal to the second reference current I2.

[0138] The pulse generating circuit 20 provides a second drive signal to the power transistors corresponding to the first and second phases. Meanwhile, the comparator circuit 40 receives the first current between the first and second phases, compares it with a second reference current I2, and outputs a first level when the first current is greater than or equal to the second reference current I2. For example, the comparator circuit 40 outputs a second level when the first current is less than the second reference current I2, and outputs a first level when the first current is greater than or equal to the second reference current I2. The first level is high, and the second level is low; that is, when the first current is less than the second reference current I2, the pulse generating circuit 20 continuously provides the second drive signal to the power transistors corresponding to the first and second phases.

[0139] Step S104: The pulse generation circuit 20 stops outputting the second drive signal according to the first level, the pulse capture circuit 30 obtains the second time T2 of the second drive signal, and the conversion circuit 50 collects the second voltage V2 of the inverter circuit bus according to the first level.

[0140] The pulse generating circuit 20 receives a first level signal from the comparator circuit 40 via the pulse generating circuit 20 and the conversion circuit 50. Based on this first level, the pulse generating circuit 20 stops outputting the second drive signal, for example, by disconnecting the power transistors corresponding to the first and second phases. At this time, the pulse capturing circuit 30 acquires the second time T2 of the second drive signal. For example, the pulse capturing circuit 30 starts timing at the rising edge of the captured second drive signal and stops timing at the falling edge, thus acquiring the second time T2 of the second drive signal. The conversion circuit 50 acquires the second voltage V2 of the inverter circuit 200 bus based on the first level; that is, the conversion circuit 50 acquires the second voltage V2 of the inverter circuit 200 bus upon receiving the first level.

[0141] Step S105: The processor 10 acquires the first voltage V1, the second voltage V2, the first reference current I1, the second reference current I2, the first time T1, and the second time T2. Based on the first voltage V1, the second voltage V2, the first reference current I1, the second reference current I2, the first time T1, and the second time T2, the processor 10 obtains the first inductance L1 and the first resistance R1 between the first phase and the second phase. The second reference current I2 is greater than the first reference current I1.

[0142] In some embodiments, the pulse generating circuit 20 provides a first drive signal to the power transistors corresponding to the second and third phases; the comparator circuit 40 receives a second current between the second and third phases, compares the second current with a first reference current I1, and outputs a first level when the second current is greater than or equal to the first reference current I1. For example, the comparator circuit 40 is used to output a second level when the second current is less than the first reference current I1, and to output a first level when the second current is greater than or equal to the first reference current I1, wherein the first level is a high level and the second level is a low level; that is, when the second current is less than the first reference current I1, the pulse generating circuit 20 continuously provides the first drive signal to the power transistors corresponding to the second and third phases.

[0143] The pulse generating circuit 20 and the conversion circuit 50 receive a first level signal from the comparator circuit 40. The pulse generating circuit 20 stops outputting the first drive signal based on the first level signal, for example, by disconnecting the power transistors corresponding to the second and third phases. At this time, the pulse capturing circuit 30 acquires the third time T3 of the first drive signal. For example, the pulse capturing circuit 30 starts timing at the rising edge of the captured first drive signal and stops timing at the falling edge of the captured first drive signal, thus acquiring the third time T3 of the first drive signal. The conversion circuit 50 acquires the third voltage V3 of the inverter circuit 200 bus based on the first level signal; that is, the conversion circuit 50 acquires the third voltage V3 of the inverter circuit 200 bus when it receives the first level signal.

[0144] The pulse generating circuit 20 provides a second drive signal to the power transistors corresponding to the second and third phases. Meanwhile, the comparator circuit 40 receives a second current between the second and third phases, compares this second current with a second reference current I2, and outputs a first level when the second current is greater than or equal to the second reference current I2. For example, the comparator circuit 40 outputs a second level when the second current is less than the second reference current I2, and outputs a first level when the second current is greater than or equal to the second reference current I2. The first level is high, and the second level is low; that is, when the second current is less than the second reference current I2, the pulse generating circuit 20 continuously provides a second drive signal to the power transistors corresponding to the second and third phases.

[0145] The pulse generating circuit 20 and the conversion circuit 50 receive a first level from the comparator circuit 40. The pulse generating circuit 20 stops outputting the second drive signal based on the first level, for example, by disconnecting the power transistors corresponding to the second and third phases. At this time, the pulse capturing circuit 30 acquires the fourth time T4 of the second drive signal. For example, the pulse capturing circuit 30 starts timing at the rising edge of the captured second drive signal and stops timing at the falling edge of the captured second drive signal, thus acquiring the fourth time T4 of the second drive signal. The conversion circuit 50 acquires the fourth voltage V4 of the inverter circuit 200 bus based on the first level; that is, the conversion circuit 50 acquires the fourth voltage V4 of the inverter circuit 200 bus when it receives the first level.

[0146] The processor 10 acquires the third voltage V3, the fourth voltage V4, the first reference current I1, the second reference current I2, the third time T3, and the fourth time T4. Based on the third voltage V3, the fourth voltage V4, the first reference current I1, the second reference current I2, the third time T3, and the fourth time T4, it obtains the second inductance L2 and the second resistance R2 between the second phase and the third phase.

[0147] In some embodiments, the pulse generating circuit 20 provides a first drive signal to the power transistor corresponding to the third phase and the first phase. At this time, the comparator circuit 40 receives a third current between the third phase and the first phase, compares this third current with a first reference current I1, and outputs a first level when the third current is greater than or equal to the first reference current I1. For example, the comparator circuit 40 is used to output a second level when the third current is less than the first reference current I1, and to output a first level when the third current is greater than or equal to the first reference current I1. The first level is high, and the second level is low; that is, when the third current is less than the first reference current I1, the pulse generating circuit 20 continuously provides the first drive signal to the power transistor corresponding to the third phase and the first phase.

[0148] The pulse generating circuit 20 and the conversion circuit 50 receive a first level signal from the comparator circuit 40. The pulse generating circuit 20 stops outputting the first drive signal based on the first level signal, for example, by disconnecting the power transistors corresponding to the third and first phases. At this time, the pulse capturing circuit 30 acquires the fifth time T5 of the first drive signal. For example, the pulse capturing circuit 30 starts timing at the rising edge of the captured first drive signal and stops timing at the falling edge of the captured first drive signal, thus acquiring the fifth time T5 of the first drive signal. The conversion circuit 50 acquires the fifth voltage V5 of the inverter circuit 200 bus based on the first level signal; that is, the conversion circuit 50 acquires the fifth voltage V5 of the inverter circuit 200 bus when it receives the first level signal.

[0149] The pulse generating circuit 20 provides a second drive signal to the power transistors corresponding to the third phase and the first phase. Meanwhile, the comparator circuit 40 receives a third current between the third phase and the first phase, compares this third current with a second reference current I2, and outputs a first level when the third current is greater than or equal to the second reference current I2. For example, the comparator circuit 40 outputs a second level when the third current is less than the second reference current I2, and outputs a first level when the third current is greater than or equal to the second reference current I2. The first level is high, and the second level is low; that is, when the third current is less than the second reference current I2, the pulse generating circuit 20 continuously provides the second drive signal to the power transistors corresponding to the third phase and the first phase.

[0150] The pulse generating circuit 20 receives a first level signal from the comparator circuit 40 via the pulse generating circuit 20 and the conversion circuit 50. Based on this first level, the pulse generating circuit 20 stops outputting the second drive signal, for example, by disconnecting the power transistor corresponding to the third phase and the first phase. At this time, the pulse capturing circuit 30 acquires the sixth time T6 of the second drive signal. For example, the pulse capturing circuit 30 starts timing at the rising edge of the captured second drive signal and stops timing at the falling edge, thus acquiring the sixth time T6 of the second drive signal. The conversion circuit 50 acquires the sixth voltage V6 of the inverter circuit 200 bus based on the first level; that is, the conversion circuit 50 acquires the sixth voltage V6 of the inverter circuit 200 bus upon receiving the first level.

[0151] The processor 10 acquires the fifth voltage V5, the sixth voltage V6, the first reference current I1, the second reference current I2, the fifth time T5, and the sixth time T6. Based on the fifth voltage V5, the sixth voltage V6, the first reference current I1, the second reference current I2, the fifth time T5, and the sixth time T6, it obtains the third inductor L3 and the third resistor R3 between the third phase and the first phase.

[0152] In some embodiments, the processor 10 obtains the quadrature-axis inductance Lq and direct-axis inductance Ld of the permanent magnet synchronous motor 100 based on the first inductance L1, the second inductance L2 and the third inductance L3.

[0153] In some embodiments, the processor 10 obtains the first stator resistance RU of the first phase, the second stator resistance RV of the second phase, and the third stator resistance RW of the third phase based on the first resistor R1, the second resistor R2, and the third resistor R3.

[0154] In summary, this application, by setting up a processor 10, a pulse generation circuit 20, a pulse capture circuit 30, a comparison circuit 40, and a conversion circuit 50, enables two detections of the power transistors corresponding to the first and second phases, obtaining a first voltage V1, a second voltage V2, a first reference current I1, a second reference current I2, a first time T1, and a second time T2. The processor 10 obtains the first inductor L1 and the first resistor R1 based on the first voltage V1, the second voltage V2, the first reference current I1, the second reference current I2, the first time T1, and the second time T2. By using the same detection method twice, the detection time can be reduced, the detection efficiency can be improved, the calculation can be simplified, and the efficiency can be increased.

[0155] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A control circuit for a permanent magnet synchronous motor, characterized in that, The permanent magnet synchronous motor is connected to the inverter circuit. The permanent magnet synchronous motor has a first phase, a second phase, and a third phase. The control circuit includes a processor, a pulse generating circuit, a pulse capturing circuit, a comparator circuit, and a conversion circuit. The processor is connected to the pulse generating circuit, the pulse capturing circuit, the comparator circuit, and the conversion circuit. The comparator circuit is connected to the pulse generating circuit and the conversion circuit. The pulse capturing circuit is connected to the pulse generating circuit. The comparator circuit is used to receive a first current between the first phase and the second phase, a second current between the second phase and the third phase, or a third current between the third phase and the first phase. The pulse generating circuit provides a first drive signal to the power transistors corresponding to the first phase and the second phase. The comparison circuit is used to compare the first current with the first reference current and output a first level when the first current is greater than or equal to the first reference current. The pulse generator is used to stop outputting the first drive signal according to the first level. The pulse capturing circuit acquires the first time of the first drive signal. The conversion circuit is used to acquire the first voltage of the bus of the inverter circuit according to the first level. The pulse generating circuit provides a second drive signal to the power transistors corresponding to the first phase and the second phase. The comparison circuit is used to compare the first current with the second reference current and output the first level when the first current is greater than or equal to the second reference current. The pulse generator is used to stop outputting the second drive signal according to the first level. The pulse capturing circuit acquires the second time of the second drive signal. The conversion circuit is used to acquire the second voltage of the bus of the inverter circuit according to the first level. The processor is configured to obtain a first inductance and a first resistance between the first phase and the second phase based on the first voltage, the second voltage, the first reference current, the second reference current, the first time, and the second time; the second reference current is greater than the first reference current; Wherein, the first inductor satisfies the following formula: ； Where L1 is the first inductor, V1 is the first voltage, V2 is the second voltage, I1 is the first reference current, I2 is the second reference current, T1 is the first time, and T2 is the second time; the first resistor satisfies the following formula: ； Wherein, R1 is the first resistor.

2. The control circuit according to claim 1, characterized in that, The pulse generating circuit provides the first drive signal to the power transistor corresponding to the second phase and the third phase. The comparison circuit is used to compare the second current with the first reference current and output the first level when the second current is greater than or equal to the first reference current. The pulse generator is used to stop outputting the first drive signal according to the first level. The pulse capturing circuit obtains the third time of the first drive signal. The conversion circuit is used to collect the third voltage of the bus of the inverter circuit according to the first level. The pulse generating circuit provides the second drive signal to the power transistor corresponding to the second phase and the third phase. The comparison circuit is used to compare the second current with the second reference current and output the first level when the second current is greater than or equal to the second reference current. The pulse generator is used to stop outputting the second drive signal according to the first level. The pulse capturing circuit acquires the fourth time of the second drive signal. The conversion circuit is used to acquire the fourth voltage of the bus of the inverter circuit according to the first level. The processor is used to obtain a second inductance and a second resistance between the second phase and the third phase based on the third voltage, the fourth voltage, the first reference current, the second reference current, the third time, and the fourth time.

3. The control circuit according to claim 2, characterized in that, The pulse generating circuit provides the first drive signal to the power transistor corresponding to the third phase and the first phase. The comparison circuit is used to compare the third current with the first reference current and output the first level when the third current is greater than or equal to the first reference current. The pulse generator is used to stop outputting the first drive signal according to the first level. The pulse capturing circuit acquires the fifth time of the first drive signal. The conversion circuit is used to acquire the fifth voltage of the bus of the inverter circuit according to the first level. The pulse generating circuit provides the second drive signal to the power transistor corresponding to the third phase and the first phase. The comparison circuit is used to compare the third current with the second reference current and output the first level when the third current is greater than or equal to the second reference current. The pulse generator is used to stop outputting the second drive signal according to the first level. The pulse capturing circuit acquires the sixth time of the second drive signal. The conversion circuit is used to acquire the sixth voltage of the bus of the inverter circuit according to the first level. The processor is used to obtain a third inductance and a third resistance between the third phase and the first phase based on the fifth voltage, the sixth voltage, the first reference current, the second reference current, the fifth time, and the sixth time.

4. The control circuit according to claim 3, characterized in that, The second inductor satisfies the following formula: ; Wherein, L2 is the second inductor, V3 is the third voltage, V4 is the fourth voltage, T3 is the third time, and T4 is the fourth time; the second resistor satisfies the following formula: ； Wherein, R2 is the second resistor; the third inductor satisfies the following formula: ; Wherein, L3 is the third inductor, V5 is the fifth voltage, V6 is the sixth voltage, T5 is the fifth time, and T6 is the sixth time; the third resistor satisfies the following formula: ； R3 is the third resistor.

5. The control circuit according to claim 3, characterized in that, The processor is used to obtain the quadrature-axis inductance and direct-axis inductance of the permanent magnet synchronous motor based on the first inductor, the second inductor, and the third inductor.

6. The control circuit according to claim 5, characterized in that, The quadrature-axis inductance of the permanent magnet synchronous motor satisfies the following formula: ； Wherein, Lq is the quadrature axis inductance, L1 is the first inductance, L2 is the second inductance, and L3 is the third inductance; The direct-axis inductance satisfies the following formula: ； Ld is the direct-axis inductance shown.

7. The control circuit according to claim 3, characterized in that, The processor is used to obtain the first stator resistance of the first phase, the second stator resistance of the second phase, and the third stator resistance of the third phase based on the first resistor, the second resistor, and the third resistor.

8. The control circuit according to claim 7, characterized in that, The first stator resistance of the first phase satisfies the following formula: ； RU is the first stator resistance of the first phase, R1 is the first resistor, R2 is the second resistor, and R3 is the third resistor; the second stator resistance of the second phase satisfies the following formula: ； RV is the second stator resistance of the second phase; the third stator resistance of the third phase satisfies the following formula: ； RW is the third stator resistance of the third phase.

9. The control circuit according to any one of claims 1-8, characterized in that, The inverter circuit includes a first power transistor, a second power transistor, a third power transistor, a fourth power transistor, a fifth power transistor, a sixth power transistor, and a capacitor. The first bus of the inverter circuit is connected to one end of the capacitor, the first end of the first power transistor, the first end of the third power transistor, and the first end of the fifth power transistor. The second bus of the inverter circuit is connected to the other end of the capacitor, the second end of the second power transistor, the second end of the fourth power transistor, and the second end of the sixth power transistor. The first phase is connected to the second end of the first power transistor and the first end of the second power transistor. The second phase is connected to the second end of the third power transistor and the first end of the fourth power transistor. The third phase is connected to the second end of the fifth power transistor and the first end of the sixth power transistor. The control terminals of the first power transistor, the second power transistor, the third power transistor, the fourth power transistor, the fifth power transistor, and the sixth power transistor are all connected to the pulse generating circuit. When the pulse generating circuit provides a first drive signal or a second drive signal to the power transistors corresponding to the first phase and the second phase, the first power transistor and the fourth power transistor are turned on. When the pulse generating circuit provides the first drive signal or the second drive signal to the power transistor corresponding to the second phase and the third phase, the third power transistor and the sixth power transistor are turned on. When the pulse generating circuit provides the first drive signal or the second drive signal to the power transistor corresponding to the third phase and the first phase, the fifth power transistor and the second power transistor are turned on.

10. A method for identifying a permanent magnet synchronous motor, characterized in that, Applied to the control circuit as described in any one of claims 1-9, the identification method includes: The pulse generating circuit provides a first drive signal to the power transistors corresponding to the first phase and the second phase, and the comparison circuit is used to compare the first current with the first reference current, and outputs a first level when the first current is greater than or equal to the first reference current. The pulse generator is used to stop outputting the first drive signal according to the first level, the pulse capture circuit is used to obtain the first time of the first drive signal, and the conversion circuit is used to collect the first voltage of the bus of the inverter circuit according to the first level. The pulse generating circuit provides a second drive signal to the power transistors corresponding to the first phase and the second phase. The comparison circuit is used to compare the first current with the second reference current and output the first level when the first current is greater than or equal to the second reference current. The pulse generator is used to stop outputting the second drive signal according to the first level, the pulse capture circuit is used to obtain the second time of the second drive signal, and the conversion circuit is used to collect the second voltage of the bus of the inverter circuit according to the first level. The processor is configured to obtain a first inductance and a first resistance between the first phase and the second phase based on the first voltage, the second voltage, the first reference current, the second reference current, the first time, and the second time; the second reference current is greater than the first reference current.

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