Subthreshold reference source and voltage stabilization cooperation system for passive chip

Abstract

The invention discloses a subthreshold reference source and voltage stabilization cooperation system for a passive chip, and relates to the field of integrated circuit power management. According to the system, a reference source module is injected into a resistor through sub-threshold current, and reference current is obtained through feedback locking of a current mirror; the derivation module obtains bias current through mirror image and obtains reference voltage through a load network; the voltage-stabilizing feedback module is used for serially connecting linear region transistors to obtain feedback voltage; the error amplifier compares reference voltage with the feedback voltage to drive the power tube to generate output voltage; the parameter code module is used for collecting three electric quantities at two temperature points to generate coupling parameters, generating trimming codes and writing the trimming codes into nonvolatile storage; and the digital trimming module is used for adjusting the compensation branch to calibrate the reference current recharge derivation module according to the trimming code. Low power consumption, controllable output consistency and small-area on-chip voltage stabilization are realized through cooperation of a subthreshold reference source and voltage stabilization feedback, two-temperature-point parameter code calibration and active feedback sampling.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit power management, specifically to a subthreshold reference source and voltage regulator co-system for passive chips. Background Technology

[0002] Passive chips typically rely on radio frequency energy harvesting and rectification to obtain their operating voltage. The power supply amplitude fluctuates significantly with changes in coupling distance, incident power, and load conditions, and the available power is limited. To ensure the stable operation of the analog front-end, digital logic, and memory units, the chip needs to provide a stable reference current and reference voltage, and regulate the rectified operating voltage to form a reusable bias and power supply foundation.

[0003] Existing reference circuits often employ bandgap references or their variations to obtain temperature-stable reference values. However, such solutions typically have requirements regarding supply voltage margin, startup conditions, and quiescent power consumption, making them difficult to adapt to the low-voltage, low-power operating constraints of passive chips. While using subthreshold devices to construct low-power reference sources can reduce quiescent current, the absolute value of the output is susceptible to process variations, device threshold drift, and layout mismatch. Furthermore, zero-point drift and slope drift under temperature changes are difficult to suppress simultaneously, limiting inter-chip consistency and mass production manufacturability. If the reference output is directly used as the bias or reference input for subsequent stages, its deviation will be propagated along the bias link and voltage regulation loop, leading to increased system-level output dispersion.

[0004] On-chip voltage regulation is typically achieved using low-dropout regulators. Conventional low-dropout regulators often use a resistor divider network to generate a feedback voltage, which is compared with a reference voltage to drive the power transistor, forming a closed-loop regulation. To meet low ripple and low noise requirements, the divider resistors are often chosen with large resistance values ​​to reduce quiescent current. However, large resistor values ​​significantly increase on-chip area, and their temperature coefficient and process variations can introduce output voltage deviations. To reduce resistor area, some solutions use the on-resistance of linear transistors to replace part of the divider resistors. However, the on-resistance varies with temperature, voltage, and device parameters, limiting the stability and repeatability of the feedback ratio and placing higher demands on the bias of the error amplifier and the stability of the reference source.

[0005] Furthermore, reference sources and regulators are often designed as independent functional units in a system: the error amplifier bias current is generated by an independent bias source, the reference voltage is provided by an independent reference source, and the feedback network parameters depend on the inherent characteristics of the device and process. This separate design makes it difficult to form a unified calibration loop during the factory calibration stage, leading to the superposition of absolute value errors of the reference source, bias current errors, and feedback network drift. This is especially prone to output instability or parameter discrepancies in the boundary operating range of passive power supplies. Therefore, there is an urgent need for a low-power reference source and on-chip voltage regulator co-operation solution for passive chips to adapt to low voltage, low power consumption, and small area constraints, and to improve batch consistency and temperature adaptability. Summary of the Invention

[0006] Based on the shortcomings of the prior art described above, the purpose of this invention is to provide a subthreshold reference source and voltage regulation co-system for passive chips to solve the above-mentioned technical problems.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a subthreshold reference source and voltage regulator co-system for passive chips, comprising: Reference source module: A reference current is generated by injecting current into the resistor through a subthreshold transistor, and the node is locked by feedback through a current mirror. Derived module: Obtains bias current from reference current through current mirroring, and generates reference voltage from reference current through load network; The voltage regulation feedback module: The feedback voltage is obtained by forming an active feedback network through the series connection of linear region transistors. The non-inverting terminal of the error amplifier is connected to the reference voltage, and the inverting terminal is connected to the feedback voltage, which drives the power transistor to obtain the output voltage. Parameter code module: Collect reference current, reference voltage and output voltage at two temperature points at the factory, generate temperature drift coupling parameters, and generate adjustment codes based on temperature drift coupling parameters and target values ​​and write them into non-volatile storage; Digital trimming module: The trimming code controls the trimming resistor array switch to change the compensation branch resistance calibration reference current, and the calibrated reference current is input to the derived module.

[0008] The present invention is further configured such that the reference source module includes a self-biasing branch, a resistor branch, a subthreshold current branch, and a current mirror feedback branch: The bias voltage is output from the self-biasing branch and input to the control terminal of the transistor in the subthreshold current branch, so that the transistor is in the operating range where the gate-source voltage is lower than the threshold voltage. The subthreshold current branch outputs the drain current, and the drain current is input to the on-chip resistor of the resistor branch. The on-chip resistor has a positive temperature coefficient, while the drain current has a negative temperature coefficient. The on-chip resistor forms a reference node voltage across its terminals. The reference node voltage is input to the sampling terminal of the current mirror feedback branch, the current mirror feedback branch outputs the feedback current and sends it back to the reference node, and the reference current is drawn out from the output terminal of the current mirror feedback branch.

[0009] The present invention is further configured such that the current mirror feedback branch adopts a common-source, common-gate current mirror structure: The current mirror feedback branch consists of a sampling mirror path and an output mirror path. The sampling mirror path is equipped with a first mirror transistor, and the output mirror path is equipped with a second mirror transistor. The gates of the first mirror transistor and the second mirror transistor are connected. The sampling mirror path is connected in series with the first cascode transistor, and the output mirror path is connected in series with the second cascode transistor. The control terminals of the first and second cascode transistors receive the cascaded bias voltage output from the bias branch. The drain of the first mirror transistor is connected to the sampling terminal of the reference node and is also connected to the gate of the first mirror transistor. The drain of the second mirror transistor is led out as the reference current output terminal.

[0010] The present invention is further configured such that the derived module includes a current mirror unit and a load network: The current mirror unit is configured with an input branch, which receives the reference current output from the reference source module. The current mirror unit is configured with a bias branch, which outputs a bias current from the reference current mirror. The bias current output terminal is connected to the bias input terminal of the error amplifier of the voltage regulation feedback module. The current mirror unit sets up a reference branch, which outputs a reference current through a mirror of the reference current. The reference current is input to the load network, and the output of the load network forms a reference voltage output. The reference voltage output is connected to the reference input of the error amplifier of the voltage regulation feedback module.

[0011] The present invention is further configured such that the current mirror unit adopts a common-source, common-gate current mirror structure: The current mirror unit includes an input branch, a first bias branch, a second bias branch, and a reference branch. The input branch is connected to the reference current input terminal. The input branch, the first bias branch, the second bias branch, and the reference branch are respectively equipped with mirror transistors and cascaded transistors. The control terminal of the mirror transistor in the input branch is connected to the control terminals of the mirror transistors in the first bias branch, the second bias branch, and the reference branch. The control terminal of the cascaded transistor receives the cascaded bias voltage. The input branch mirror transistor is set to a size ratio with the first bias branch mirror transistor, the second bias branch mirror transistor, and the reference branch mirror transistor. The first bias branch outputs a first tail current biased to the input terminal of the error amplifier tail current source, the second bias branch outputs a second tail current biased to the input terminal of the error amplifier tail current source, and the reference branch outputs a reference current to the input terminal of the load network.

[0012] The present invention is further configured such that the voltage regulation feedback module includes an error amplifier, a power regulation transistor, and an active feedback network: The error amplifier is configured with a reference input, a feedback input, a bias input, and a drive output. The reference input is connected to the reference voltage output of the derived module, the bias input is connected to the bias current output of the derived module, and the drive output is connected to the control terminal of the power adjustment transistor. The first terminal of the power regulator is connected to the working voltage input terminal, and the second terminal is connected to the output voltage output terminal. The active feedback network connects the output voltage terminal to the ground terminal, and the feedback voltage output terminal is connected to the feedback input terminal of the error amplifier.

[0013] The present invention is further configured such that the voltage regulation feedback module further includes: The error amplifier is composed of transistors operating in the subthreshold region. The error amplifier is equipped with a first tail current source and a second tail current source. The currents of the first tail current source and the second tail current source are set by the bias current received at the bias input terminal. The active feedback network consists of three transistors operating in the linear region connected in series. The three transistors are connected in sequence to the output voltage terminal and the ground terminal. The connection point between the second and third transistors serves as the feedback voltage output terminal. The voltage regulation feedback module is equipped with a filter transistor and a filter capacitor. The first terminal of the filter transistor is connected to the working voltage input terminal and the second terminal is connected to ground. The first terminal of the filter capacitor is connected to the working voltage input terminal and the second terminal is connected to ground.

[0014] The present invention is further configured such that the parameter code module includes a temperature acquisition unit, a data organization unit, a parameter generation unit, a trimming code unit, and a storage and writing unit: The temperature acquisition unit establishes a first temperature point and a second temperature point during the factory manufacturing stage. The reference current, reference voltage and output voltage are collected at the first temperature point to form a first acquisition group, and the reference current, reference voltage and output voltage are collected at the second temperature point to form a second acquisition group. The data organization unit establishes a correlation between the first acquisition group and the second acquisition group according to signal type and temperature point identifier to form a temperature acquisition dataset; The parameter generation unit generates temperature drift coupling parameters from the temperature acquisition dataset according to preset parameter generation rules; The correction code unit generates correction codes based on temperature drift coupling parameters and preset target values; The storage write unit writes the modifier code to non-volatile memory.

[0015] The present invention is further configured such that the temperature drift coupling parameter is generated based on the temperature acquisition dataset, including: Record the reference current, reference voltage, and output voltage reference values ​​at the first temperature point, and record the corresponding values ​​at the second temperature point. The drift amount is obtained by subtracting the first temperature point value from the second temperature point value for the reference current, reference voltage, and output voltage in sequence. The drift amount is divided by the corresponding first temperature point reference value to obtain the drift ratio. The absolute value of the drift ratio is taken. The absolute value of the result of subtracting the reference voltage drift ratio from the output voltage drift ratio is used to obtain the voltage coupling deviation, and the absolute value of the result of subtracting the reference current drift ratio from the output voltage drift ratio is used to obtain the current coupling deviation. The temperature drift coupling parameter is determined by taking the larger of the voltage coupling deviation and the current coupling deviation. The temperature drift coupling parameter is written into the parameter record and the code determination unit is called to generate the adjustment code.

[0016] The present invention is further configured such that the digital trimming module includes a non-volatile memory readout unit, a code allocation unit, and a trimming resistor array: The non-volatile memory read unit reads the four-bit trimming code written by the parameter code module and outputs a four-bit switch control signal. The code allocation unit generates the first control line to the fourth control line based on the four-position switch control signal; The adjustment resistor array is configured with fixed resistors and first, second, third and fourth branches. The fixed resistors are connected in series to the compensation branch of the reference source module. The first to fourth branches are respectively configured with adjustment resistor strings and switching transistor strings. The first to fourth control lines are connected to the corresponding switch transistor control terminals. The conduction state of the switch transistor determines the access state of the first to fourth branches. The equivalent resistance of the compensation branch is updated according to the access state. The reference source module outputs the adjusted reference current and then inputs it into the derived module.

[0017] This invention provides a subthreshold reference source and voltage regulator co-system for passive chips. The system comprises: a reference source module that generates a reference current by injecting current into a resistor via a subthreshold transistor, with the node locked by a current mirror feedback; a derivative module that obtains a bias current from the reference current via a current mirror, and generates a reference voltage through a load network; a voltage regulator feedback module that extracts a feedback voltage by forming an active feedback network using a series of linear transistors, connecting the non-inverting input of an error amplifier to the reference voltage and the inverting input to the feedback voltage, driving a power transistor to obtain the output voltage; a parameter code module that collects the reference current, reference voltage, and output voltage at two factory temperature points, generates temperature drift coupling parameters, and generates a trimming code based on the temperature drift coupling parameters and a target value, writing it into non-volatile memory; and a digital trimming module that controls a trimming resistor array switch to change the compensation branch resistance to calibrate the reference current, with the calibrated reference current input to the derivative module. The beneficial effects include: 1. Low-power collaborative power supply: The reference source module generates a reference current in the subthreshold region, the derived module mirrors the bias current and generates a reference voltage, and the voltage regulation feedback module sets the operating point of the error amplifier with the bias current and uses the reference voltage as the reference input to form a power supply link shared by the reference and the voltage regulation, reducing the demand for independent bias and reference branches and adapting to the energy-constrained working conditions of passive chips. 2. Output consistency can be calibrated: The parameter code module collects the reference current, reference voltage and output voltage at two temperature points at the factory, generates temperature drift coupling parameters and generates adjustment codes based on these parameters, which are then written into non-volatile storage; the digital adjustment module adjusts the compensation branch resistance according to the adjustment codes to calibrate the reference current, and the calibration results are fed back to the derived and regulated links to achieve batch consistency control and temperature drift constraint. 3. Small area feedback implementation: The voltage regulation feedback module uses a linear region transistor connected in series to form an active feedback network to extract the feedback voltage, replacing the traditional large-value resistor voltage divider; together with the reference voltage and bias current derived from the reference source, the operating point of the feedback network is maintained, reducing the on-chip resistor area occupation and maintaining the structural integrity of the closed-loop voltage regulation, meeting the high integration requirements of passive chips.

[0018] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 The flowchart illustrates a subthreshold reference source and voltage regulator co-system for a passive chip, as an exemplary embodiment of the present invention. Detailed Implementation

[0020] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0021] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0022] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0023] Example 1: A subthreshold reference source and voltage regulator co-system for passive chips, such as Figure 1 As shown, it includes: Reference source module: A reference current is generated by injecting current into the resistor through a subthreshold transistor, and the node is locked by feedback through a current mirror. Derived module: Obtains bias current from reference current through current mirroring, and generates reference voltage from reference current through load network; The voltage regulation feedback module: The feedback voltage is obtained by forming an active feedback network through the series connection of linear region transistors. The non-inverting terminal of the error amplifier is connected to the reference voltage, and the inverting terminal is connected to the feedback voltage, which drives the power transistor to obtain the output voltage. Parameter code module: Collect reference current, reference voltage and output voltage at two temperature points at the factory, generate temperature drift coupling parameters, and generate adjustment codes based on temperature drift coupling parameters and target values ​​and write them into non-volatile storage; Digital trimming module: The trimming code controls the trimming resistor array switch to change the compensation branch resistance calibration reference current, and the calibrated reference current is input to the derived module.

[0024] The present invention is further configured such that the reference source module includes a self-biasing branch, a resistor branch, a subthreshold current branch, and a current mirror feedback branch: The self-biased branch outputs a bias voltage, which is then input to the control terminal of the transistor in the subthreshold current branch, ensuring that the transistor operates within the range where its gate-source voltage is below the threshold voltage. Specifically, after power-on, the self-biased branch enters a bootstrap state, first forming a stable bias voltage output, which serves as the input to the control terminal of the subsequent subthreshold current branch transistor. Simultaneously, the self-biased branch derives a cascaded bias voltage output from the bias voltage, which serves as the input to the control terminal of the common-source common-gate transistor in the current mirror feedback branch. The setting of the bias voltage follows the constraint logic to ensure subthreshold operation, while the setting of the cascaded bias voltage follows the constraint logic to ensure consistent voltage margins in the mirror path. Both use the steady-state output of the self-biased branch as input to complete convergence confirmation. The subthreshold current branch outputs drain current, which is input to the on-chip resistor in the resistance branch. The on-chip resistor has a positive temperature coefficient, while the drain current has a negative temperature coefficient. A reference node voltage is formed across the on-chip resistor. Specifically, the transistor control terminal of the subthreshold current branch receives the bias voltage output in step one. The transistor enters the operating range where the gate-source voltage is lower than the threshold voltage, and the branch outputs drain current as the current output. The drain current setting adopts target current window constraint logic: constrained by a preset reference current target range, the subthreshold conduction degree is first determined by the bias voltage, and then the drain current is stably locked into the target window through subsequent negative feedback. The resistance branch uses an on-chip resistor with a positive temperature coefficient. After the drain current flows through the on-chip resistor, a voltage drop is formed, and the reference node voltage is output across the on-chip resistor. The processing idea is to construct temperature complementary primitives: the resistance changes positively with increasing temperature, and the subthreshold drain current changes negatively with increasing temperature. The two form complementary changes in the voltage domain. The reference node voltage serves as the sampling input for the subsequent current mirror feedback branch, providing a controllable quantity for negative feedback locking. The reference node voltage is input to the sampling terminal of the current mirror feedback branch, the current mirror feedback branch outputs the feedback current and sends it back to the reference node, and the reference current is drawn out from the output terminal of the current mirror feedback branch.

[0025] The present invention is further configured such that the current mirror feedback branch adopts a common-source, common-gate current mirror structure: The current mirror feedback branch consists of a sampling mirror path and an output mirror path. The sampling mirror path uses a first mirror transistor, and the output mirror path uses a second mirror transistor. The gates of the first and second mirror transistors are connected. Specifically, the current mirror feedback branch uses a sampling mirror path. The drain of the first mirror transistor in the sampling mirror path is connected to the sampling terminal of the reference node, and the drain and gate of the first mirror transistor are connected to form a sampling control point, allowing the reference node voltage to be directly converted into a gate control quantity of the first mirror transistor. A first cascode transistor is connected in series in the sampling mirror path. The control terminal of the first cascode transistor receives the cascaded bias voltage output from step one, enabling the current path of the sampling mirror path to obtain a more stable voltage distribution under the cascaded bias constraint, thus ensuring the consistency of the sampling control quantity during power supply fluctuations. The sampling mirror path is connected in series with a first cascode transistor, and the output mirror path is connected in series with a second cascode transistor. The control terminals of the first and second cascode transistors receive the cascaded bias voltage output from the bias branch. Specifically, the current mirror feedback branch sets up the output mirror path, and the gate of the second mirror transistor in the output mirror path is connected to the gate of the first mirror transistor, so that the output mirror path inherits the mirror control quantity. The output mirror path is connected in series with the second cascode transistor, and the control terminal of the second cascode transistor receives the cascaded bias voltage from step one, so that the current output of the output mirror path maintains high consistency. The drain of the second mirror transistor is led out as the reference current output terminal to form an externally callable reference current. The key process logic is mirror consistency confirmation: with the control quantity of the sampling mirror path as the reference, the output mirror path outputs a stable current under the cascaded bias constraint to avoid mirror deviation caused by the difference in path voltage. The drain of the first mirror transistor is connected to the sampling terminal of the reference node and to the gate of the first mirror transistor. The drain of the second mirror transistor is led out as the reference current output terminal. Specifically, the feedback current output from the sampling mirror path is fed back to the reference node, so that the reference node voltage automatically adjusts with the change of feedback current, thereby forming a closed-loop constraint on the subthreshold drain current in step two, realizing negative feedback locking of reference node voltage—mirror control quantity—feedback current—reference node voltage. Steady-state confirmation adopts node voltage convergence criterion and output current convergence criterion: the reference node voltage is stable within a preset allowable fluctuation range, and the reference current output terminal is stable within a preset current window. When both conditions are met, the reference source module is determined to enter the working state.

[0026] The present invention is further configured such that the derived module includes a current mirror unit and a load network: The current mirror unit is configured with an input branch, which receives the reference current output from the reference source module. The current mirror unit is configured with a bias branch, which outputs a bias current from the reference current mirror. The bias current output terminal is connected to the bias input terminal of the error amplifier of the voltage regulation feedback module. The current mirror unit sets up a reference branch, which outputs a reference current through a mirror of the reference current. The reference current is input to the load network, and the output of the load network forms a reference voltage output. The reference voltage output is connected to the reference input of the error amplifier of the voltage regulation feedback module.

[0027] The present invention is further configured such that the current mirror unit adopts a common-source, common-gate current mirror structure: The current mirror unit includes an input branch, a first bias branch, a second bias branch, and a reference branch. The input branch is connected to the reference current input terminal. Specifically, the input branch is connected to the reference current output terminal of the reference source module. The reference current is injected into the mirror transistor of the input branch. The mirror transistor of the input branch forms a sampling control point by connecting the drain and the gate, so that the gate control voltage corresponding to the reference current is established in the input branch. This gate control voltage is transmitted to the mirror transistor control terminals of the first bias branch, the second bias branch, and the reference branch through a gate common connection. The calculation logic adopts the mirror control quantity consistency constraint: the sampling control point of the input branch is used as the only control source to ensure that each output branch shares the same control quantity, avoiding the discrepancy introduced by multi-source bias. This method allows the derived module to complete multiple derivations by relying only on the reference current input, reducing the dependence on additional bias links. The input branch, first bias branch, second bias branch, and reference branch are each equipped with mirror transistors and cascaded transistors. The control terminals of the mirror transistors in the input branch are connected to the control terminals of the mirror transistors in the first bias branch, second bias branch, and reference branch. The control terminals of the cascaded transistors receive the cascaded bias voltage. Specifically, the input branch, first bias branch, second bias branch, and reference branch are each connected in series with cascaded transistors. The control terminals of the cascaded transistors uniformly receive the cascaded bias voltage provided by the reference source module, ensuring that the drain-source voltage of each branch's mirror transistor is within a controlled range. The calculation logic employs a drain-source voltage window constraint: the voltage margin of each branch is limited by the cascaded bias voltage, ensuring that the mirroring accuracy is primarily determined by the device size ratio, thus mitigating the impact of operating voltage fluctuations on the mirroring results. The input branch mirror transistor is configured with a size ratio relationship with the first bias branch mirror transistor, the second bias branch mirror transistor, and the reference branch mirror transistor. The first bias branch outputs a first tail current biased to the input terminal of the error amplifier tail current source. The second bias branch outputs a second tail current biased to the input terminal of the error amplifier tail current source. The reference branch outputs a reference current to the input terminal of the load network. Specifically, the control terminal of the first bias branch mirror transistor receives the gate control voltage, the branch output terminal forms the first tail current bias, and the output terminal is connected to the first tail current source input terminal of the error amplifier in the voltage regulation feedback module. The calculation logic uses the target tail current to inversely deduce the size ratio: first, the target range of the first tail current bias is determined by the static operating point of the error amplifier; then, using the reference current as a reference, the ratio of the target tail current to the reference current is used to determine the size ratio of the first bias branch mirror transistor relative to the input branch mirror transistor; the size ratio is expressed and fixed in the layout implementation as the channel width-to-length ratio or the equivalent number of parallel cells; this process ensures that the error amplifier bias current is derived from the reference source and can be synchronously controlled with the reference current calibration result; the control terminal of the second bias branch mirror transistor receives the gate control voltage, the branch output terminal forms the second tail current bias, and the output terminal is connected to the input terminal of the second tail current source of the error amplifier. The calculation logic uses tail current distribution consistency constraints: based on the current distribution requirements of the differential input stage and the load stage of the error amplifier, the ratio of the first tail current bias to the second tail current bias is preset, and then this ratio is used to constrain the size ratio matching of the second bias branch and the first bias branch; in the layout, the same-direction adjacent placement and equal-proportional partitioning methods are used to maintain the consistency of the proportional relationship. This step ensures that the bias of both tail currents is derived from the same reference current, reducing the risk of operating point drift caused by bias inconsistency. The reference branch mirror transistor control terminal receives the gate control voltage, the reference branch output terminal forms the reference current, the reference current is input to the load network, and the load network output terminal forms the reference voltage output terminal, which is connected to the non-inverting input terminal of the error amplifier in the voltage regulation feedback module. The calculation logic uses the target reference voltage to deduce the load network parameters: first, the target range of the reference voltage required for the non-inverting input terminal of the error amplifier is determined by the voltage regulation output target; then, the size ratio of the reference branch relative to the input branch is selected to obtain the target range of the reference current; subsequently, the equivalent conduction parameters of the load network are selected according to the current-voltage characteristics of the load network, so that when the reference current is within the target range, the output voltage of the load network falls within the target range of the reference voltage; the load network parameters are implemented using a discrete unit combination method, making the subsequent layout verifiable and repeatable.

[0028] The present invention is further configured such that the voltage regulation feedback module includes an error amplifier, a power regulation transistor, and an active feedback network: The error amplifier is configured with a reference input, a feedback input, a bias input, and a drive output. The reference input is connected to the reference voltage output of the derived module, the bias input is connected to the bias current output of the derived module, and the drive output is connected to the control terminal of the power adjustment transistor. The first terminal of the power regulator is connected to the working voltage input terminal, and the second terminal is connected to the output voltage output terminal. The active feedback network connects the output voltage terminal to the ground terminal, and the feedback voltage output terminal is connected to the feedback input terminal of the error amplifier. The present invention is further configured such that the voltage regulation feedback module further includes: The error amplifier is composed of transistors operating in the subthreshold region. It has a first tail current source and a second tail current source, the currents of which are set by the bias current received at the bias input terminal. Specifically, the reference input terminal receives the reference voltage output from the derived module, the feedback input terminal receives the feedback voltage output from the subsequent active feedback network, the bias input terminal receives the bias current output from the derived module, and the drive output terminal serves as the control input for the subsequent power adjustment transistor. After the bias current reaches the error amplifier, the current level of the input stage tail current source is determined according to a preset bias allocation rule. The level selection uses an allowable window filtering logic: based on the continuous conduction condition of the error amplifier input pair and the available swing condition of the drive output terminal, several discrete tail current levels are preset. Each level is checked to see if it meets the constraints under the full range of inputs of the reference voltage and feedback voltage. Levels that meet the constraints are fixed as the working level, while those that do not are eliminated and replaced. This process outputs the steady-state bias state of the error amplifier, forming a closed-loop precondition of reference voltage + bias current + feedback voltage → drive output state. The active feedback network consists of three transistors operating in the linear region connected in series. These three transistors are sequentially connected to the output voltage terminal and ground. The connection point between the second and third transistors serves as the feedback voltage output terminal. Specifically, the first terminal of the power regulator is connected to the operating voltage input terminal, and the second terminal is connected to the output voltage output terminal. The control terminal receives the potential of the drive output terminal from step one. Changes in the control terminal potential alter the conduction level of the power regulator, causing the operating voltage input terminal to provide a controlled current to the output voltage output terminal. The power regulator parameter selection employs a load capacity range screening logic: the conduction capacity requirement is determined based on the preset maximum load current, minimum operating voltage, and target output voltage tolerance band. Several discrete size ranges are preset, and each range is checked to verify whether the output terminal remains adjustable under the minimum operating voltage condition. If it is not adjustable, the size range is increased for re-verification. Simultaneously, the control margin of the drive output terminal for that size range is verified. If the drive margin is insufficient, the error amplifier tail current range or the power transistor size range is adjusted back until both the conduction capacity constraint and the drive margin constraint are simultaneously satisfied and fixed. The voltage regulation feedback module includes filter transistors and filter capacitors. The first terminal of the filter transistor is connected to the operating voltage input, and the second terminal is connected to ground. Similarly, the first terminal of the filter capacitor is connected to the operating voltage input, and the second terminal is connected to ground. Specifically, the active feedback network connects the output voltage to ground. The network is formed by connecting transistors operating in the linear region in series. The midpoint of the series connection is used to output the feedback voltage and input it to the error amplifier's feedback input. The network parameters are selected using a two-level consistent criterion logic: the first level is the linear region constraint criterion, with several preset discrete size ranges. Each range is used to verify the network parameters within the output voltage variation range. The first layer is the voltage divider consistency criterion. It aims to ensure that the feedback voltage enters the allowable deviation band of the reference voltage under steady-state conditions. It verifies the consistency between the feedback voltage and the reference voltage after the closed loop stabilizes, step by step. If the condition is not met, it backtracks and adjusts the size of the active feedback network and rechecks. The closed-loop convergence determination adopts two conditions: deviation convergence and stability maintenance. The feedback voltage enters the allowable deviation band and is maintained within the preset time window. The output voltage enters the target tolerance band synchronously and is maintained within the time window. When these conditions are met, the output voltage is confirmed and output to the subsequent load.

[0029] The present invention is further configured such that the parameter code module includes a temperature acquisition unit, a data organization unit, a parameter generation unit, a trimming code unit, and a storage and writing unit: The temperature acquisition unit establishes a first temperature point and a second temperature point during the factory manufacturing process. At the first temperature point, it acquires reference current, reference voltage, and output voltage to form a first acquisition group. At the second temperature point, it acquires the same reference current, reference voltage, and output voltage to form a second acquisition group. Specifically, the first and second temperature points are established at the factory, with the temperature points assigned by the temperature control equipment and identified by a temperature point identifier. At the first temperature point, the reference current output by the reference source module, the reference voltage output by the derived module, and the output voltage output by the voltage regulation feedback module are acquired and recorded to form the first acquisition group. At the second temperature point, the same acquisition sequence is repeated to form the second acquisition group. The acquisition process employs a stable window sampling logic: before acquisition, each signal is checked to ensure its fluctuation amplitude within a preset time window does not exceed the allowable range; if this is met, the acquired value and timestamp are written; if not, sampling is delayed or repeated until the requirement is met. This step outputs two sets of original acquisition records with temperature point identifiers, providing a common input source for subsequent correlation and parameter generation. The data organization unit establishes a correlation between the first and second acquisition groups based on signal type and temperature point identifiers to form a temperature acquisition dataset. Specifically, the first and second acquisition groups are divided into three categories of records: reference current records, reference voltage records, and output voltage records. A key-value structure of temperature point identifier—signal type identifier—acquisition value—timestamp is established for each category of records. The three categories of records at the first temperature point are then paired one-to-one with the corresponding records at the second temperature point to form the temperature acquisition dataset. The data organization process employs a matching verification logic: pairing is performed based on signal type identifiers. After pairing, the temperature point identifiers are verified to be distinct and the acquisition order is consistent. If any condition is not met, the dataset is deemed unusable, and the process reverts to step one for re-acquisition. This step outputs a structured temperature acquisition dataset, allowing subsequent rule generation to be directly invoked without relying on additional inference. The parameter generation unit generates temperature drift coupling parameters from the temperature acquisition dataset according to preset parameter generation rules; The adjustment code unit generates adjustment codes based on the temperature drift coupling parameters and preset target values. Specifically, the adjustment code unit reads the temperature drift coupling parameters and preset target values, where the preset target values ​​include the target reference current window and the target temperature drift coupling upper limit. The adjustment code generation adopts a candidate code screening-optimization sorting logic: first, a candidate adjustment code set is established; for each candidate adjustment code, the corresponding compensation branch resistor connection state is called to obtain the candidate reference current state; codes that do not meet the target reference current window are filtered out from the candidate set; for the remaining candidate codes, they are sorted in ascending order of temperature drift coupling parameters, and the code with the best sorting and that meets the temperature drift coupling upper limit is selected as the adjustment code; if no candidate code meets the temperature drift coupling upper limit, the candidate code with the smallest temperature drift coupling parameter is selected as the rollback adjustment code and marked as a state requiring review. This step outputs the adjustment code and the code generation basis record to ensure that the temperature drift coupling parameters are actually used in subsequent steps and do not exist in isolation. The storage writing unit writes the trimming code into non-volatile memory. Specifically, the storage writing unit writes the trimming code determined in step four into non-volatile memory, and simultaneously writes the temperature point identifier, acquisition record reference key, and generation timestamp corresponding to the trimming code to form a write record. After writing, a post-write read verification process is executed: the trimming code is read from the non-volatile memory and compared bit by bit with the trimming code to be written. If any bit is inconsistent, a rewrite is performed and the number of rewrites is recorded. If the number of rewrites exceeds a preset number, it is marked as a write error and an error record is output. This step outputs the trimming code and the complete write verification record in the non-volatile memory, providing a definite input for the digital trimming module to subsequently read and control the trimming resistor array.

[0030] The present invention is further configured such that the temperature drift coupling parameter is generated based on the temperature acquisition dataset, including: Record the reference current, reference voltage, and output voltage values ​​at the first temperature point, and record the corresponding values ​​at the second temperature point. Specifically, read the first and second temperature point identifiers from the temperature acquisition dataset, retrieve the reference current, reference voltage, and output voltage values ​​at the first temperature point, and retrieve the corresponding values ​​at the second temperature point. Perform a consistency check on the two temperature point records, checking for identical signal type identifiers, distinct temperature point identifiers, and acquisition timestamp order that meets the preset acquisition order. If any check fails, mark the dataset as unusable and revert to the temperature acquisition stage for re-acquisition. The drift amount is calculated by subtracting the first temperature point value from the second temperature point value for the reference current, reference voltage, and output voltage. The drift amount is then divided by the corresponding first temperature point reference value to obtain the drift ratio, and the absolute value of the drift ratio is taken. Specifically, drift amount generation is performed separately for the three types of signals: reference current, reference voltage, and output voltage. The difference between the corresponding value at the second temperature point and the first temperature point reference value is used as the drift amount. Then, normalization processing is performed on each drift amount, and the normalization reference is selected from the corresponding first temperature point reference value to obtain the drift ratio. The drift ratio is then amplitude-enhanced, and the absolute value method is used to eliminate the influence of positive and negative directions on subsequent coupling judgment. The calculation process adopts a signal-by-signal serial processing logic: first, the drift amount and drift ratio of the reference current are completed, then the drift amount and drift ratio of the reference voltage are completed, and then the drift amount and drift ratio of the output voltage are completed. After processing each type of signal, it is written into an intermediate record for direct use in subsequent coupling deviation calculations. The absolute value of the difference between the output voltage drift ratio and the reference voltage drift ratio yields the voltage coupling deviation, and the absolute value of the difference between the output voltage drift ratio and the reference current drift ratio yields the current coupling deviation. Specifically, coupling deviation extraction is performed based on the three types of drift ratio records: the output voltage drift ratio is compared with the reference voltage drift ratio using a difference-amplification order to obtain the voltage coupling deviation; the output voltage drift ratio is also compared with the reference current drift ratio using a difference-amplification order to obtain the current coupling deviation. The calculation logic of this step adopts the same-scale comparison constraint: all three types of drift ratios have been normalized according to the reference value at the first temperature point, ensuring that the voltage coupling deviation and current coupling deviation can be directly compared on the same scale; if any drift ratio is missing or has not been amplitudeized, the deviation is determined to be uncalculated. The temperature drift coupling parameter is determined by taking the maximum of the voltage coupling deviation and the current coupling deviation. The temperature drift coupling parameter is written into the parameter record and called by the code determination unit to generate the adjustment code. Specifically, the maximum value selection is performed on the voltage coupling deviation and the current coupling deviation, and the maximum value is used as the temperature drift coupling parameter. The maximum value selection follows the strictest criterion logic, so that the temperature drift coupling parameter reflects the one with the more significant deviation between the two coupling paths. The temperature drift coupling parameter, together with the first temperature point identifier, the second temperature point identifier, the reference keys of the three types of drift ratio records, and the reference keys of the two types of coupling deviation records, is written into the parameter record, and a parameter record identifier is generated. The parameter record identifier is output to the adjustment code unit as the call entry point. The adjustment code unit reads the temperature drift coupling parameter based on this entry point and compares it with the preset target value to generate the adjustment code.

[0031] The present invention is further configured such that the digital trimming module includes a non-volatile memory readout unit, a code allocation unit, and a trimming resistor array: The non-volatile memory read unit reads the four-bit trimming code written by the parameter code module and outputs a four-bit switch control signal. Specifically, after powering on and entering the working state, the non-volatile memory read unit accesses the storage address of the trimming code written by the parameter code module and reads the four-bit trimming code bit by bit. The read process adopts a post-read verification logic: two consecutive reads are performed on the same address and the bit values ​​are compared for consistency. If the bit values ​​are consistent, the bit is latched as a valid bit value. If they are inconsistent, a reread is triggered and the number of rereads is recorded. When the number of rereads reaches a preset threshold, a read error flag is output and the previous valid bit value is retained. The four valid bit values ​​are combined to form a four-bit switch control signal and output to the code allocation unit. The code allocation unit generates the first to fourth control lines based on the four-bit switch control signals. Specifically, the code allocation unit receives the four-bit switch control signals, establishes a control line mapping table bit by bit, maps the first bit to the first control line, the second bit to the second control line, the third bit to the third control line, and the fourth bit to the fourth control line. The mapping process uses a bit order consistency criterion: the bit order of the mapping table is consistent with the bit order when writing to the non-volatile memory, and the control line output level meets the high / low level judgment threshold of the switch transistor control terminal. If any control line level is in an uncertain range, the corresponding bit is re-latched and the control line output is updated. The adjustment resistor array includes a fixed resistor and four branches: a first branch, a second branch, a third branch, and a fourth branch. The fixed resistor is connected in series with the compensation branch of the reference source module. The first to fourth branches are respectively configured with adjustment resistor strings and switching transistors connected in series. Specifically, the adjustment resistor array includes a fixed resistor and four branches. The fixed resistor is connected in series with the compensation branch of the reference source module. The first to fourth branches are respectively composed of adjustment resistor strings and switching transistors connected in series, forming a selectable series extension structure with the fixed resistor. The first to fourth control lines are respectively connected to the control terminals of the corresponding switching transistors, so that the conduction state of the switching transistors determines the access state of the corresponding branch. The calculation logic adopts the "discrete access state parsing" process: the bit value state of each of the four control lines is determined one by one, the branch with the bit value in the access state is marked as a valid branch, and the branch with the bit value in the disconnect state is marked as an invalid branch; the fixed resistor and the adjustment resistor series of all valid branches are summarized in series to form the equivalent resistance state of the compensation branch, and the equivalent resistance state is written into the adjustment state record. The adjustment state record includes the adjustment code, the valid branch set identifier and the equivalent resistance state identifier. The first to fourth control lines are connected to the corresponding switching transistor control terminals. The conduction state of the switching transistors determines the access state of the first to fourth branches. The equivalent resistance of the compensation branch is updated according to the access state. The reference source module outputs the adjusted reference current, which is then input to the derived module. Specifically, after the equivalent resistance of the compensation branch is updated, the feedback locking point of the reference source module converges again under the new compensation branch resistance condition, and the output terminal forms the adjusted reference current. The adjusted reference current is sent as an input to the derived module, so that the bias current and reference voltage of the derived module are updated synchronously with the adjusted reference current. The calculation process uses a convergence criterion for confirmation: monitoring the fluctuation amplitude of the reference current at the output terminal of the reference source module within a preset time window. When the fluctuation amplitude meets the allowable range, the convergence is confirmed to be complete and the adjustment state record is released as valid; if it does not meet the allowable range, the current branch access state is maintained and the convergence waiting window is extended. When the preset waiting upper limit is exceeded, an adjustment abnormality flag is output and the latched adjustment code and branch state are maintained.

[0032] It should be noted that the specific operation methods of each module and unit in the subthreshold reference source and voltage regulator co-operation system for passive chips provided in the above embodiments have been described in detail in the system embodiments and will not be repeated here. In practical applications, the subthreshold reference source and voltage regulator co-operation system for passive chips provided in the above embodiments can be assigned to different functional modules as needed, that is, the internal structure of the system can be divided into different functional modules to complete all or part of the functions described above, and this is not a limitation.

[0033] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A subthreshold reference source and voltage regulator co-system for passive chips, characterized in that, include: Reference source module: A reference current is generated by injecting current into the resistor through a subthreshold transistor, and the node is locked by feedback through a current mirror. Derived module: Obtains bias current from reference current through current mirroring, and generates reference voltage from reference current through load network; The voltage regulation feedback module: The feedback voltage is obtained by forming an active feedback network through the series connection of linear region transistors. The non-inverting terminal of the error amplifier is connected to the reference voltage, and the inverting terminal is connected to the feedback voltage, which drives the power transistor to obtain the output voltage. Parameter code module: Collect reference current, reference voltage and output voltage at two temperature points at the factory, generate temperature drift coupling parameters, and generate adjustment codes based on temperature drift coupling parameters and target values ​​and write them into non-volatile storage; Digital trimming module: The trimming code controls the trimming resistor array switch to change the compensation branch resistance calibration reference current, and the calibrated reference current is input to the derived module.

2. The subthreshold reference source and voltage regulator co-system for passive chips according to claim 1, characterized in that, The reference source module includes a self-biasing branch, a resistor branch, a subthreshold current branch, and a current mirror feedback branch: The bias voltage is output from the self-biasing branch and input to the control terminal of the transistor in the subthreshold current branch, so that the transistor is in the operating range where the gate-source voltage is lower than the threshold voltage. The subthreshold current branch outputs the drain current, and the drain current is input to the on-chip resistor of the resistor branch. The on-chip resistor has a positive temperature coefficient, while the drain current has a negative temperature coefficient. The on-chip resistor forms a reference node voltage across its terminals. The reference node voltage is input to the sampling terminal of the current mirror feedback branch, the current mirror feedback branch outputs the feedback current and sends it back to the reference node, and the reference current is drawn out from the output terminal of the current mirror feedback branch.

3. The subthreshold reference source and voltage regulator co-system for passive chips according to claim 2, characterized in that, The current mirror feedback branch adopts a common-source, common-gate current mirror structure: The current mirror feedback branch consists of a sampling mirror path and an output mirror path. The sampling mirror path is equipped with a first mirror transistor, and the output mirror path is equipped with a second mirror transistor. The gates of the first mirror transistor and the second mirror transistor are connected. The sampling mirror path is connected in series with the first cascode transistor, and the output mirror path is connected in series with the second cascode transistor. The control terminals of the first and second cascode transistors receive the cascaded bias voltage output from the bias branch. The drain of the first mirror transistor is connected to the sampling terminal of the reference node and is also connected to the gate of the first mirror transistor. The drain of the second mirror transistor is led out as the reference current output terminal.

4. The subthreshold reference source and voltage regulator co-system for passive chips according to claim 1, characterized in that, The derived module includes a current mirror unit and a load network: The current mirror unit is configured with an input branch, which receives the reference current output from the reference source module. The current mirror unit is configured with a bias branch, which outputs a bias current from the reference current mirror. The bias current output terminal is connected to the bias input terminal of the error amplifier of the voltage regulation feedback module. The current mirror unit sets up a reference branch, which outputs a reference current through a mirror of the reference current. The reference current is input to the load network, and the output of the load network forms a reference voltage output. The reference voltage output is connected to the reference input of the error amplifier of the voltage regulation feedback module.

5. A subthreshold reference source and voltage regulator co-system for passive chips according to claim 4, characterized in that, The current mirror unit adopts a common-source, common-gate current mirror structure: The current mirror unit includes an input branch, a first bias branch, a second bias branch, and a reference branch. The input branch is connected to the reference current input terminal. The input branch, the first bias branch, the second bias branch, and the reference branch are respectively equipped with mirror transistors and cascaded transistors. The control terminal of the mirror transistor in the input branch is connected to the control terminals of the mirror transistors in the first bias branch, the second bias branch, and the reference branch. The control terminal of the cascaded transistor receives the cascaded bias voltage. The input branch mirror transistor is set to a size ratio with the first bias branch mirror transistor, the second bias branch mirror transistor, and the reference branch mirror transistor. The first bias branch outputs a first tail current biased to the input terminal of the error amplifier tail current source, the second bias branch outputs a second tail current biased to the input terminal of the error amplifier tail current source, and the reference branch outputs a reference current to the input terminal of the load network.

6. The subthreshold reference source and voltage regulator co-system for passive chips according to claim 1, characterized in that, The voltage regulation feedback module includes an error amplifier, a power regulation transistor, and an active feedback network. The error amplifier is configured with a reference input, a feedback input, a bias input, and a drive output. The reference input is connected to the reference voltage output of the derived module, the bias input is connected to the bias current output of the derived module, and the drive output is connected to the control terminal of the power adjustment transistor. The first terminal of the power regulator is connected to the working voltage input terminal, and the second terminal is connected to the output voltage output terminal. The active feedback network connects the output voltage terminal to the ground terminal, and the feedback voltage output terminal is connected to the feedback input terminal of the error amplifier.

7. A subthreshold reference source and voltage regulator co-system for passive chips according to claim 6, characterized in that, The voltage regulation feedback module also includes: The error amplifier is composed of transistors operating in the subthreshold region. The error amplifier is equipped with a first tail current source and a second tail current source. The currents of the first tail current source and the second tail current source are set by the bias current received at the bias input terminal. The active feedback network consists of three transistors operating in the linear region connected in series. The three transistors are connected in sequence to the output voltage terminal and the ground terminal. The connection point between the second and third transistors serves as the feedback voltage output terminal. The voltage regulation feedback module is equipped with a filter transistor and a filter capacitor. The first terminal of the filter transistor is connected to the working voltage input terminal and the second terminal is connected to ground. The first terminal of the filter capacitor is connected to the working voltage input terminal and the second terminal is connected to ground.

8. A subthreshold reference source and voltage regulator co-system for passive chips according to claim 1, characterized in that, The parameter code module includes a temperature acquisition unit, a data organization unit, a parameter generation unit, a trimming code unit, and a storage and writing unit. The temperature acquisition unit establishes a first temperature point and a second temperature point during the factory manufacturing stage. The reference current, reference voltage and output voltage are collected at the first temperature point to form a first acquisition group, and the reference current, reference voltage and output voltage are collected at the second temperature point to form a second acquisition group. The data organization unit establishes a correlation between the first acquisition group and the second acquisition group according to signal type and temperature point identifier to form a temperature acquisition dataset; The parameter generation unit generates temperature drift coupling parameters from the temperature acquisition dataset according to preset parameter generation rules; The correction code unit generates correction codes based on temperature drift coupling parameters and preset target values; The storage write unit writes the modifier code to non-volatile memory.

9. A subthreshold reference source and voltage regulator co-system for passive chips according to claim 8, characterized in that, Temperature drift coupling parameters are generated based on the temperature acquisition dataset and include: Record the reference current, reference voltage, and output voltage reference values ​​at the first temperature point, and record the corresponding values ​​at the second temperature point. The drift amount is obtained by subtracting the first temperature point value from the second temperature point value for the reference current, reference voltage, and output voltage in sequence. The drift amount is divided by the corresponding first temperature point reference value to obtain the drift ratio. The absolute value of the drift ratio is taken. The absolute value of the result of subtracting the reference voltage drift ratio from the output voltage drift ratio is used to obtain the voltage coupling deviation, and the absolute value of the result of subtracting the reference current drift ratio from the output voltage drift ratio is used to obtain the current coupling deviation. The temperature drift coupling parameter is determined by taking the larger of the voltage coupling deviation and the current coupling deviation. The temperature drift coupling parameter is written into the parameter record and the code determination unit is called to generate the adjustment code.

10. A subthreshold reference source and voltage regulator co-system for passive chips according to claim 1, characterized in that, The digital trimming module includes a non-volatile memory readout unit, a code allocation unit, and a trimming resistor array. The non-volatile memory read unit reads the four-bit trimming code written by the parameter code module and outputs a four-bit switch control signal. The code allocation unit generates the first control line to the fourth control line based on the four-position switch control signal; The adjustment resistor array is configured with fixed resistors and first, second, third and fourth branches. The fixed resistors are connected in series to the compensation branch of the reference source module. The first to fourth branches are respectively configured with adjustment resistor strings and switching transistor strings. The first to fourth control lines are connected to the corresponding switch transistor control terminals. The conduction state of the switch transistor determines the access state of the first to fourth branches. The equivalent resistance of the compensation branch is updated according to the access state. The reference source module outputs the adjusted reference current and then inputs it into the derived module.

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